TLK4211EARGTT

TLK4211EA www.ti.com SLLS655 – NOVEMBER 2005 4.25 Gbps Cable and PC Board Equalizer FEATURES APPLICATIONS • • • • • • • • • • • • • Multi-Rate Operation Up To 4.25 Gbps Compensates Up To 12 dB Loss At 2.1 GHz Suitable To Receive 4.25-Gbps Data Over Up To 30 Inches (0,76 Meters) Of FR4 PC Boards Suitable To Receive 4.25-Gbps Data Over Up To 30 Feet (9,1 Meters) Of CX4 Cable Ultra-Low Power Consumption Input Offset Cancellation High Input Dynamic Range Output Disable Output Polarity Select CML Data Outputs Single 3.3-V Supply Surface Mount Small Footprint 3 mm × 3 mm 16-Pin QFN Package • • • 1.0625 Gbps, 2.125 Gbps, and 4.25 Gbps Fibre Channel Systems High Speed Links In Communication and Data Systems Backplane Interconnect Rack-to-Rack Interconnect DESCRIPTION The TLK4211EA is a versatile high-speed limiting equalizer for applications in digital high-speed links with data rates up to 4.25 Gbps. This device provides a high frequency boost of 12 dB at 2.1 GHz as well as sufficient gain to ensure a fully differential output swing for input signals as low as 200 mVp-p (at the input of the interconnect line). The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal swings as high as 2000 mVp-p. The TLK4211EA is available in a small footprint 3 mm × 3 mm 16-pin QFN package. It requires a single 3.3-V supply. This power efficient equalizer is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated TLK4211EA www.ti.com SLLS655 – NOVEMBER 2005 BLOCK DIAGRAM A simplified block diagram of the TLK4211EA is shown in Figure 1. This compact, low-power 4.25-Gbps equalizer consists of a high-speed data path with offset cancellation circuitry, a bandgap voltage reference, and bias current generation block. The equalizer requires a single 3.3-V supply voltage. All circuit parts are described in detail in below. COC2 COC1 Bandgap Voltage Reference and Bias Current Generation VCC OUTPOL Offset Cancellation GND VCC DIN+ + + + + DIN− − − − − Gain Stage Gain Stage Fixed Equilizer Stage Gain Stage DOUT+ DOUT− CML Output Buffer Stage DISABLE B0052-02 Figure 1. Simplified Block Diagram of the TLK4211EA HIGH-SPEED DATA PATH The high-speed data signal with frequency dependent loss is applied to the data path by means of the input signal pins DIN+/DIN–. The data path consists of the fixed equalizer input stage with 100-Ω differential on-chip line termination, three gain stages, which provide the required gain to ensure a limited output signal, and a CML output stage. The equalized and amplified data output signal is available at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCC. The output stage also includes a data polarity switching function, which is controlled by the OUTPOL input, and a disable function controlled by the signal applied to the DISABLE input pin. An offset cancellation compensates inevitable internal offset voltages and thus ensures proper operation even for small input data signals. The low frequency cutoff is as low as 10 kHz with the built-in filter capacitor. For applications which require even lower cutoff frequencies, an additional external filter capacitor may be connected to the COC1/COC2 pins. BANDGAP VOLTAGE AND BIAS GENERATION The TLK4211EA equalizer is supplied by a single 3.3-V ±10% supply voltage connected to the VCC pins. This voltage is referred to ground (GND). An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other internally required voltages and bias currents are derived. PACKAGE The TLK4211EA is available in a small footprint 3 mm × 3 mm, 16-pin QFN package with a lead pitch of 0,5 mm. The pin out is shown below in Figure 2. 2 TLK4211EA www.ti.com SLLS655 – NOVEMBER 2005 VCC 1 DIN+ 2 COC2 COC1 16 15 14 NC GND RGT PACKAGE (TOP VIEW) 13 12 VCC 11 DOUT+ 10 DOUT− EP 9 5 6 7 8 GND 4 NC VCC DISABLE 3 NC DIN− OUTPOL P0019-02 Figure 2. Pin Out of TLK4211EA in a 3 mm × 3 mm 16-Pin QFN Package TERMINAL FUNCTIONS TERMINAL NAME NO. TYPE DESCRIPTION 3.3-V ±10% supply voltage VCC 1, 4 , 12 Supply DIN+ 2 Analog in Non-inverted data input. On-chip 100-Ω terminated to DIN– DIN– 3 Analog in Inverted data input. On-chip 100-Ω terminated to DIN+ NC DISABLE 5, 7, 13 Not connected 6 CMOS in 8, 16 Supply OUTPOL 9 CMOS in Output data signal polarity select (internally pulled up): Setting to high-level or leaving pin open selects normal polarity. Low-level selects inverted polarity. DOUT– 10 CML out Inverted data output. On-chip 50-Ω back-terminated to VCC. DOUT+ 11 CML out Non-inverted data output. On-chip 50-Ω back-terminated to VCC. COC1 14 Analog Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15). COC2 15 Analog Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15). EP EP GND Disables CML output stage when set to high level Circuit ground. Exposed die pad (EP) must be grounded. 3 TLK4211EA www.ti.com SLLS655 – NOVEMBER 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE / UNIT VCC Supply voltage (2) VDIN+, VDIN– Voltage at DIN+, DIN– (2) –0.3 V to 4 V 0.5 V to 4 V COC2 (2) VDISABLE, VOUTPOL, VDOUT+, VDOUT–, VCOC1, VCOC2 Voltage at DISABLE, OUTPOL, DOUT+, DOUT–, COC1, VCOC,DIFF Differential voltage between COC1 and COC2 VDIN,DIFF Differential voltage between DIN+ and DIN– IDIN+, IDIN–, IDOUT+, IDOUT– Continuous current at inputs and outputs ESD ESD rating at all pins TJ(max) Maximum junction temperature TSTG Storage temperature range –65°C to 85°C TA Characterized free-air operating temperature range –40°C to 85°C TL Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) –0.3 V to 4 V ±1 V ±2.5 V – 25 mA to 25 mA 2.5 kV (HBM) 125°C 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 3 3.3 3.6 V 85 °C VCC Supply voltage TA Operating free-air temperature –40 CMOS input high voltage 2.1 UNIT V CMOS input low voltage 0.6 V DC ELECTRICAL CHARACTERISTICS over recommended operating conditions, typical operating condition is at VCC = 3.3 V and TA = 25°C(unless otherwise noted) PARAMETER TEST CONDITIONS VCC Supply voltage ICC Supply current DISABLE = low, including CML output current RIN Data input resistance Differential ROUT Data output resistance Single-ended to VCC MIN TYP MAX 3 3.3 3.6 UNIT V 30 38 mA 100 Ω 50 Ω AC ELECTRICAL CHARACTERISTICS over recommended operating conditions, typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted) PARAMETER Low frequency –3 dB bandwidth TYP MAX COC = open TEST CONDITIONS 10 50 COC = 0.22 µF 0.8 Data rate 4.25 VIN,MIN Data input sensitivity (1) BER < 10–12, voltage at the input of the interconnect line VIN,MAX Data input overload Voltage at the input of the interconnect line High frequency boost f = 2.1 GHz Differential data output voltage swing DISABLE = high VOD (1) 4 MIN DISABLE = low kHz Gbps 200 250 2000 mVp-p mVp-p 12 580 UNIT dB 0.25 10 780 1200 mVp-p The given differential input signal swing is measured at the input of the interconnect line. The high frequency components of the signal at the output of the interconnect line (which is connected the input pins DIN+/DIN– of the TLK4211EA) may be attenuated by 0 dB up to 12 dB at 2.1 GHz dependent of the interconnect line length. TLK4211EA www.ti.com SLLS655 – NOVEMBER 2005 AC ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions, typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted) PARAMETER DJ RJ TEST CONDITIONS MIN TYP No board or cable 20 12 inches of 7 mils wide microstrip interconnect line on standard FR4 30 Deterministic jitter, 4.25 Gbps, K28.5 pattern, 24 inches of 7 mils wide microstrip interconnect line on VIN = 200 mVpp standard FR4 (differential voltage at the 36 inches of 7 mils wide microstrip interconnect line on cable input) standard FR4 MAX 30 UNIT psp-p 30 30 feet CX4 cable 20 Deterministic jitter, 3.3 Gbps, K28.5 pattern, VIN = 200 mVpp (differential voltage at the cable input) No board or cable 20 48 inches of 7 mils wide microstrip interconnect line on standard FR4 25 30 feet CX4 cable 20 Random jitter Input = 200 mVp-p, 36 inches of 7 mils wide stripline interconnect line on standard FR4 (voltage at the input of the interconnect line) 4.5 250 psp-p psRMS Latency From DIN± to DOUT± tr Output rise time 20% to 80%, without microstrip line loss at input 55 85 ps tf Output fall time 20% to 80%, without microstrip line loss at input 55 85 ps TDIS Disable response time 20 ps ns 5 TLK4211EA www.ti.com SLLS655 – NOVEMBER 2005 APPLICATION INFORMATION Figure 3 shows the TLK4211EA connected with an ac-coupled interface to the data signal source via a microstrip interconnect line. The output load is ac-coupled as well. The ac coupling capacitors C1 through C4 in the input and output data signal lines are the only required external components. In addition, if a low cutoff frequency is required, as an option, an external filter capacitor COC may be used. DIN− DIN+ COC1 NC DOUT+ TLK4211EA 16-Pin QFN DIN− NC VCC DOUT− OUTPOL VCC C3 C4 DOUT+ DOUT− OUTPOL GND C2 VCC NC DIN+ VCC C1 DISABLE 0 Inch to 30 Inches Stripline on FR4 COC2 GND COC Optional DISABLE S0072-02 Figure 3. Basic Application Circuit With AC Coupled I/Os 6 TLK4211EA www.ti.com SLLS655 – NOVEMBER 2005 TYPICAL CHARACTERISTICS Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted). DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT 4.25 GBPS USING A K28.5 PATTERN No Stripline Output Voltage 250mV/Div Output Voltage 250mV/Div Input Voltage 75mV/Div Input Voltage 75mV/Div No Stripline Time − 100 ps/Div 12 Inches x 7 mil Stripline 12 Inches x 7 mil Stripline Output Voltage 250mV/Div Output Voltage 250mV/Div Input Voltage 75mV/Div Input Voltage 75mV/Div Time − 1 ns/Div Time − 100 ps/Div 24 Inches x 7 mil Stripline 24 Inches x 7 mil Stripline Output Voltage 250mV/Div Output Voltage 250mV/Div Input Voltage 75mV/Div Input Voltage 75mV/Div Time − 1 ns/Div Time − 100 ps/Div 36 Inches x 7 mil Stripline 36 Inches x 7 mil Stripline Output Voltage 250mV/Div Output Voltage 250mV/Div Input Voltage 75mV/Div Input Voltage 75mV/Div Time − 1 ns/Div Time − 1 ns/Div Time − 100 ps/Div G001 Figure 4. Equalizer Input and Output Signals With Different Interconnect Lines Patterns 7 TLK4211EA www.ti.com SLLS655 – NOVEMBER 2005 TYPICAL CHARACTERISTICS (continued) Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted). DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT 3.3 GBPS USING A K28.5 PATTERN No Stripline Input Voltage 75mV/Div Output Voltage 250mV/Div Output Voltage 250mV/Div Input Voltage 75mV/Div No Stripline Time − 100 ps/Div 24 Inches x 7 mil Stripline 24 Inches x 7 mil Stripline Output Voltage 250mV/Div Output Voltage 250mV/Div Input Voltage 75mV/Div Input Voltage 75mV/Div Time − 1 ns/Div Time − 100 ps/Div 48 Inches x 7 mil Stripline Output Voltage 250mV/Div Output Voltage 250mV/Div Input Voltage 75mV/Div Input Voltage 75mV/Div Time − 1 ns/Div 48 Inches x 7 mil Stripline Time − 1 ns/Div Time − 100 ps/Div Figure 5. Equalizer Input and Output Signals With Different Interconnect Lines and Data 8 G002 TLK4211EA www.ti.com SLLS655 – NOVEMBER 2005 TYPICAL CHARACTERISTICS (continued) Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted). TRANSFER CHARACTERISTIC OF STRIPLINE INTERCONNECT LINES RANDOM JITTER vs INPUT AMPLITUDE 0 10 12” Stripline 9 8 −15 Random Jitter − psRMS Differential Stripline Attenuation − dB −5 −10 −20 −25 24” Stripline −30 −35 36” Stripline −40 7 6 5 36” Stripline 4 3 −45 48” Stripline 2 −50 1 −55 0” Stripline −60 0 1 2 3 4 5 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 6 f − Frequency − GHz VID − Differential Input Voltage − VP−P G004 Figure 6. Figure 7. DETERMINISTIC JITTER 4.25 GBPS vs INPUT AMPLITUDE (K28.5 PATTERN) DETERMINISTIC JITTER 4.25 GBPS vs STRIPLINE INTERCONNECT LINE LENGTH 50 50 45 45 Deterministic Jitter Including PWD − psP−P Deterministic Jitter Including PWD − psP−P G003 40 35 30 0” Stripline 25 20 36” Stripline 15 10 5 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VID − Differential Input Voltage − VP−P Figure 8. 40 35 30 215 − 1 PRBS 25 20 15 K28.5 10 5 0 0 5 10 15 20 25 30 35 40 45 50 Stripline Length − Inches G005 G006 Figure 9. 9 TLK4211EA www.ti.com SLLS655 – NOVEMBER 2005 TYPICAL CHARACTERISTICS (continued) Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted). DIFFERENTIAL INPUT RETURN GAIN vs FREQUENCY DIFFERENTIAL OUTPUT RETURN GAIN vs FREQUENCY 0 −5 −5 −10 −10 −15 −15 −20 −20 −25 −25 S22 − dB S11 − dB 0 −30 −35 −30 −35 −40 −40 −45 −45 −50 −50 −55 −55 −60 −60 0 1 2 3 4 5 6 0 f − Frequency − GHz 1 2 3 10 5 6 f − Frequency − GHz G007 Figure 10. 4 G008 Figure 11. PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) (4/5) TLK4211EARGTR OBSOLETE QFN RGT 16 TBD Call TI Call TI -40 to 85 TLK4211EARGTRG4 OBSOLETE QFN RGT 16 TBD Call TI Call TI -40 to 85 TLK4211EARGTT NRND QFN RGT 16 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 250 Device Marking 421E 421E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLK4211EARGTT Package Package Pins Type Drawing QFN RGT 16 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 12.4 Pack Materials-Page 1 3.3 B0 (mm) K0 (mm) P1 (mm) 3.3 1.1 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLK4211EARGTT QFN RGT 16 250 338.1 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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