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TLV197-Q1, TLV2197-Q1, TLV4197-Q1
SBOS935B – APRIL 2020 – REVISED JULY 2020
TLVx197-Q1 Automotive, High-Voltage, Precision, Rail-to-Rail In, Rail-to-Rail Out Op Amp
1 Features
3 Description
•
The TLV197-Q1, TLV2197-Q1 and TLV4197-Q1
(TLVx197-Q1) family of devices are part of a new
generation, of low-cost, 36-V, automotive-qualified,
operational amplifiers. The TLVx197-Q1 family uses a
method of package-level trim for offset and offset
temperature drift implemented during the final steps
of manufacturing after the plastic molding process.
This method minimizes the influence of inherent input
transistor mismatch, as well as errors induced during
package molding.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Low offset voltage: ±500 µV (maximum)
Low noise: 5.5 nV/√Hz at 1 kHz
High common-mode rejection: 140 dB
Low bias current: ±5 pA
Rail-to-rail input and output
Wide bandwidth: 10-MHz GBW
High slew rate: 20 V/µs
Low quiescent current: 1 mA per amplifier
Wide supply: ±2.25 V to ±18 V, 4.5 V to 36 V
EMI/RFI filtered inputs
Differential input-voltage range to supply rail
High capacitive load drive capability: 1 nF
Industry-standard package:
– Single channel in very small 8-pin VSSOP
– Dual channel in 8-pin VSSOP
– Quad channel in 14-pin TSSOP
Good dc precision and ac performance including railto-rail input/output, an optimized cost structure, and
AEC-Q100 grade 1 qualification, make this family an
excellent choice for low-side current-sensing and
signal-conditioning applications in the automotive
space.
More unique features, such as a differential inputvoltage range to the supply rail, a high output current
(±65 mA), a heavy capacitive load drive of up to 1 nF,
and a high slew rate (20 V/µs), make these devices a
robust, high-performance operational amplifier family
for high-voltage automotive applications.
The TLVx197-Q1 family of op amps is available in
standard packages and is specified from –40°C to
+125°C.
2 Applications
•
•
•
•
Inverter and motor control
DC/DC converter
On-board (OBC) and wireless charger
Battery management system (BMS)
Device Information
PART NUMBER
TLV197-Q1
TLV2197-Q1
TLV4197-Q1
1.
PACKAGE
BODY SIZE (NOM)
VSSOP (8)
3.00 mm × 3.00 mm
TSSOP (14)
5.00 mm x 4.40 mm
For all available packages, see the package option addendum
at the end of the data sheet.
TLVx197-Q1 Detect Voltages in Automotive Applications
VBUS
VREF
TLVx197-Q1
+
ADC
±
GND
GND
`
VREF
TLVx197-Q1
+
ADC
±
GND
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV197-Q1, TLV2197-Q1, TLV4197-Q1
SBOS935B – APRIL 2020 – REVISED JULY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information: TLV197-Q1 ............................. 7
Thermal Information: TLV2197-Q1 ........................... 7
Thermal Information: TLV4197-Q1 ........................... 7
Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8
V to 36 V) ................................................................... 8
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS =
4.5 V to 8 V)............................................................. 10
6.9 Typical Characteristics ............................................ 12
7
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
7.3 Feature Description................................................. 19
7.4 Device Functional Modes........................................ 25
8
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Applications ................................................ 26
9 Power Supply Recommendations...................... 29
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Examples................................................... 30
11 Device and Documentation Support ................. 31
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
32
32
32
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2020) to Revision B
•
Page
Changed TLV197-Q1 and TLV2197-Q1 from advance information (preview) to production data (active) ............................ 1
Changes from Original (April 2020) to Revision A
•
2
Page
Changed to correct device names in titles for all Thermal Information tables ....................................................................... 7
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TLV197-Q1, TLV2197-Q1, TLV4197-Q1
www.ti.com
SBOS935B – APRIL 2020 – REVISED JULY 2020
5 Pin Configuration and Functions
TLV197-Q1 DGK Package
8-Pin VSSOP
Top View
Pin Functions: TLV197-Q1
PIN
NAME
I/O
NO.
DESCRIPTION
+IN
3
I
Noninverting input
–IN
2
I
Inverting input
NC
1, 5, 8
—
No internal connection (can be left floating)
OUT
6
O
Output
V+
7
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
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3
TLV197-Q1, TLV2197-Q1, TLV4197-Q1
SBOS935B – APRIL 2020 – REVISED JULY 2020
www.ti.com
TLV2197-Q1 DGK Package
8-Pin VSSOP
Top View
Pin Functions: TLV2197-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
4
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SBOS935B – APRIL 2020 – REVISED JULY 2020
TLV4197-Q1 PW Package
14-Pin TSSOP
Top View
Pin Functions: TLV4197-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input, channel A
–IN B
5
I
Noninverting input, channel B
+IN C
10
I
Noninverting input, channel C
+IN D
12
I
Noninverting input, channel D
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
–IN C
9
I
Inverting input, channel C
–IN D
13
I
Inverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V+
4
—
Positive (highest) power supply
V–
11
—
Negative (lowest) power supply
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5
TLV197-Q1, TLV2197-Q1, TLV4197-Q1
SBOS935B – APRIL 2020 – REVISED JULY 2020
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
VS
Supply voltage
Voltage
±20
(V–) – 0.5
(V+) + 0.5
Current
TA
Operating temperature
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
V
(V+) – (V–) +
0.2
Differential
±10
Output short circuit (2)
UNIT
40
Dual-supply, VS = (V+) – (V–)
Common-mode
+IN, –IN
MAX
Single-supply, VS = (V+)
Continuous
Continuous
–55
150
150
–65
mA
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 2
±2000
V
Charge Device Model (CDM), per AEC Q100-011
CDM ESD Classification Level C5
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Supply voltage
TA
Operating temperature
6
Single-supply, VS = (V+)
Dual-supply, VS = (V+) – (V–)
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NOM
MAX
4.5
36
±2.25
±18
–40
125
UNIT
V
°C
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Product Folder Links: TLV197-Q1 TLV2197-Q1 TLV4197-Q1
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SBOS935B – APRIL 2020 – REVISED JULY 2020
6.4 Thermal Information: TLV197-Q1
TLV197-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
180.4
°C/W
RθJC(top)
RθJB
Junction-to-case(top) thermal resistance
67.9
°C/W
Junction-to-board thermal resistance
102.1
°C/W
ψJT
Junction-to-top characterization parameter
10.4
°C/W
ψJB
Junction-to-board characterization parameter
100.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
(1)
For more information about traditional and new thermal metrics, see the Semiconductorand IC Package Thermal Metrics application
report.
6.5 Thermal Information: TLV2197-Q1
TLV2197-Q1
THERMAL METRIC
(1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
158
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
48.6
°C/W
RθJB
Junction-to-board thermal resistance
78.7
°C/W
ψJT
Junction-to-top characterization parameter
3.9
°C/W
ψJB
Junction-to-board characterization parameter
77.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
(1)
For more information about traditional and new thermal metrics, see the Semiconductorand IC Package Thermal Metrics application
report.
6.6 Thermal Information: TLV4197-Q1
TLV4197-Q1
THERMAL METRIC
(1)
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
108.1
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
26.3
°C/W
RθJB
Junction-to-board thermal resistance
54.4
°C/W
ψJT
Junction-to-top characterization parameter
1.4
°C/W
ψJB
Junction-to-board characterization parameter
53.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
(1)
For more information about traditional and new thermal metrics, see the Semiconductorand IC Package Thermal Metrics application
report.
Copyright © 2020, Texas Instruments Incorporated
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7
TLV197-Q1, TLV2197-Q1, TLV4197-Q1
SBOS935B – APRIL 2020 – REVISED JULY 2020
www.ti.com
6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
±5
±500
dVOS/dT
Input offset voltage drift
TA = –40°C to +125°C
±1
±5
µV/°C
µV
PSRR
Power-supply rejection
ratio
TA = –40°C to +125°C
±0.3
±1.0
µV/V
±5
±20
pA
±5
nA
±20
pA
±2
nA
INPUT BIAS CURRENT
IB
IOS
Input bias current
Input offset current
TA = –40°C to +125°C
±2
TA = –40°C to +125°C
NOISE
En
Input voltage noise
en
Input voltage noise
density
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 0.1 Hz to 10 Hz
1.3
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 0.1 Hz to 10 Hz
4
(V–) – 0.1 V < VCM < (V+) – 3 V
(V+) – 1.5 V < VCM < (V+) + 0.1 V
in
Input current noise
density
f = 100 Hz
µVPP
10.5
f = 1 kHz
5.5
f = 100 Hz
32
f = 1 kHz
nV/√Hz
12.5
f = 1 kHz
1.5
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) – 3 V
CMRR
Common-mode
rejection ratio
(V–) < VCM < (V+) – 3 V
(V+) – 1.5 V < VCM < (V+)
TA = –40°C to +125°C
TA = –40°C to +125°C
(V+) + 0.1
120
140
114
126
100
120
86
100
V
dB
INPUT IMPEDANCE
ZID
Differential
ZIC
Common-mode
8
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100 || 1.6
MΩ || pF
1 || 6.4
1013Ω ||
pF
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Product Folder Links: TLV197-Q1 TLV2197-Q1 TLV4197-Q1
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SBOS935B – APRIL 2020 – REVISED JULY 2020
Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
120
134
114
126
126
140
120
134
MAX
UNIT
OPEN-LOOP GAIN
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
AOL
Open-loop voltage gain
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
TA = –40°C to +125°C
dB
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
TA = –40°C to +125°C
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
SR
Slew rate
ts
Settling time
G = 1, 10-V step
To 0.01%
To 0.001%
ts
Settling time
tOR
Overload recovery time
VIN × G = VS
THD+N
Total harmonic
distortion + noise
G = 1, f = 1 kHz, VO = 3.5 VRMS
Crosstalk
G = 1, 10-V step
10
MHz
20
V/µs
1.4
G = 1, 5-V step
0.9
G = 1, 10-V step
2.1
µs
G = 1, 5-V step
1.8
µs
0.2
µs
0.00008%
TLV4197-Q1 at dc
150
dB
TLV4197-Q1, f = 100 kHz
130
dB
OUTPUT
No load
Positive rail
VO
Voltage output swing
from rail
15
95
110
RL = 2 kΩ
430
500
5
15
RL = 10 kΩ
95
110
RL = 2 kΩ
430
500
No load
Negative rail
ISC
5
RL = 10 kΩ
Short-circuit current
±65
mV
mA
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A
1
TA = –40°C to +125°C
1.2
1.5
mA
TEMPERATURE
Thermal protection
140
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°C
9
TLV197-Q1, TLV2197-Q1, TLV4197-Q1
SBOS935B – APRIL 2020 – REVISED JULY 2020
www.ti.com
6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VCM = (V+) – 3 V
±5
±500
dVOS/dT
Input offset voltage drift
VCM = (V+) – 1.5 V
±1
±5
PSRR
Power-supply rejection
ratio
TA = –40°C to +125°C
±2
µV
µV/°C
µV/V
INPUT BIAS CURRENT
IB
IOS
Input bias current
Input offset current
±5
TA = –40°C to +125°C
±2
TA = –40°C to +125°C
±20
pA
±5
nA
±20
pA
±2
nA
NOISE
En
Input voltage noise
en
Input voltage noise
density
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 0.1 Hz to 10 Hz
1.3
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 0.1 Hz to 10 Hz
4
(V–) – 0.1 V < VCM < (V+) – 3 V
(V+) – 1.5 V < VCM < (V+) + 0.1 V
in
Input current noise
density
f = 100 Hz
µVPP
10.5
f = 1 kHz
5.5
f = 100 Hz
32
f = 1 kHz
nV/√Hz
12.5
f = 1 kHz
1.5
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) – 3 V
CMRR
Common-mode
rejection ratio
(V–) < VCM < (V+) – 3 V
(V+) – 1.5 V < VCM < (V+)
TA = –40°C to +125°C
TA = –40°C to +125°C
(V+) + 0.1
94
110
90
104
100
120
84
100
V
dB
INPUT IMPEDANCE
ZID
Differential
ZIC
Common-mode
10
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100 || 1.6
MΩ || pF
1 || 6.4
1013Ω ||
pF
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SBOS935B – APRIL 2020 – REVISED JULY 2020
Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) (continued)
at TA = +25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
110
120
100
114
110
126
110
120
dB
10
MHz
20
V/µs
1
µs
OPEN-LOOP GAIN
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
AOL
Open-loop voltage gain
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RL = 2 kΩ
TA = –40°C to +125°C
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
AOL
Open-loop voltage gain
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RL = 10 kΩ
TA = –40°C to +125°C
dB
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
SR
Slew rate
G = 1, 5-V step
ts
Settling time
To 0.01%
tOR
Overload recovery time
VIN × G = VS
0.2
µs
TLV4197-Q1 at dc
150
dB
TLV4197-Q1, f = 100 kHz
130
dB
Crosstalk
VS = ±3V, G = 1, 5-V step
OUTPUT
No load
Positive rail
VO
Voltage output swing
from rail
15
95
110
RL = 2 kΩ
430
500
5
15
RL = 10 kΩ
95
110
RL = 2 kΩ
430
500
No load
Negative rail
ISC
5
RL = 10 kΩ
Short-circuit current
±65
mV
mA
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A
1
TA = –40°C to +125°C
1.2
1.5
mA
TEMPERATURE
Thermal protection
140
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°C
11
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6.9 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
100
50
75
VCM = +18.1 V
50
Offset Voltage (V)
Offset Voltage (V)
25
0
VCM = –18.1 V
VCM = –18.1 V
25
0
–25
P-Channel
N-Channel
–50
–25
–75
Transition
–50
–20
–15
–10
–5
0
5
10
15
–100
12.5
20
Common-Mode Voltage (V)
14.5
15.5
16.5
Figure 1. Offset Voltage vs Common-Mode Voltage
18.5
Figure 2. Offset Voltage vs Common-Mode Voltage
50
5 Typical Units Shown
10 Typical Units Shown
40
150
30
Offset Voltage (µV)
100
50
0
–50
VCM = +2.35 V
VCM = –2.35 V
–100
20
10
0
–10
–20
–30
–150
Transition
P-Channel
–200
–2.5 –2.0 –1.5 –1.0 –0.5 0.0 0.5
–40
N-Channel
1.0
1.5
2.0
–50
2.5
0.0
2.0
4.0
6.0
Common-Mode Voltage (V)
8.0
10.0 12.0 14.0 16.0 18.0 20.0
Power Supply Voltage (V)
VS = ±2.25 V
VS = ±2.25 V to ±18 V
Figure 3. Offset Voltage vs Common-Mode Voltage
140.0
Figure 4. Offset Voltage vs Power Supply
180
60.0
135
40.0
G = -100
G = +1
G = -1
G = -10
120.0
Phase
60.0
90
40.0
20.0
Phase (°)
80.0
45
Gain (dB)
Open-Loop Gain
100.0
Gain (dB)
17.5
Common-Mode Voltage (V)
200
Offset Voltage (µV)
13.5
C001
20.0
0.0
0.0
–20.0
1
10
100
1k
10k 100k
Frequency (Hz)
1M
0
10M 100M
±20.0
1000
10k
100k
Frequency (Hz)
1M
10M
C003
CLOAD = 15 pF
Figure 5. Open-Loop Gain and Phase vs Frequency
12
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Figure 6. Closed-Loop Gain and Phase vs Frequency
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Typical Characteristics (continued)
20
6000
15
5000
Input Bias Current (pA)
Input Bias Current (pA)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
IB–
10
5
0
IB+
–5
–10
IB+
IB Ios
4000
3000
2000
1000
Ios
0
–15
±1000
–20
18.0
9.0
0.0
9.0
±75
18.0
Common-Mode Voltage (V)
Figure 7. Input Bias Current vs Common-Mode Voltage
0
25
50
75
100
125
150
175
C001
Figure 8. Input Bias Current vs Temperature
160.0
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
Out pu Voltage Swing (V)
±25
Temperature (ƒC)
(V–) + 5
(V–) + 4
+125°C
(V–) + 3
(V–) + 2
– 40°C
(V–) + 1
(V–)
(V–) – 1
140.0
120.0
100.0
80.0
60.0
+PSRR
40.0
CMRR
20.0
-PSRR
0.0
0
10
20
30
40
50
60
70
Output Current (mA)
80
1
10
100
1k
10k
100k
Frequency (Hz)
C001
Figure 9. Output Voltage Swing vs Output Current
(Maximum Supply)
1M
C012
Figure 10. CMRR and PSRR vs Frequency
10
1
Power-Supply Rejection Ratio (µV/V)
Common-Mode Rejection Ratio (µV/V)
±50
C001
8
6
4
VS = ±2.25 V, VCM = V+ - 3 V
2
0
±2
VS = ±18 V, VCM = 0 V
±4
±6
±8
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
±10
±75
±50
±25
0
25
50
75
100
Temperature (ƒC)
Figure 11. CMRR vs Temperature
Copyright © 2020, Texas Instruments Incorporated
125
150
–75
–50 –25
0
25
50
75
100
125
Temperature (°C)
C001
150
C001
Figure 12. PSRR vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Noise (400 nV/div)
Voltage Noise Density (nV/√Hz)
1000
VCM = V+ – 100 mV
N-Channel Input
100
10
Peak-to-Peak Noise = VRMS × 6.6 = 1.30 µVpp
VCM = 0 V
P-Channel Input
1
0.1
Time (1 s/div)
1
10
Total Harmonic Distortion + Noise (%)
G = –1 V/V, RL = 10 kΩ
–80
G = –1 V/V, RL = 2 kΩ
0.001
–100
0.0001
–120
0.00001
100
1k
0.01
–80
0.001
–100
0.0001
10k
G = +1
G = +1
G = –1
G = –1
–120
V/V, RL = 10 kΩ
V/V, RL = 2 kΩ
V/V, RL = 10 kΩ
V/V, RL = 2 kΩ
0.1
–140
1
10
Output Amplitude (VRMS)
f = 1 kHz, BW = 80 kHz
VOUT = 3.5 VRMS, BW = 80 kHz
Figure 15. THD+N Ratio vs Frequency
Figure 16. THD+N vs Output Amplitude
1.2
1.2
Quiescent Current (mA)
Quiescent Current (mA)
C002
–60
Frequency (Hz)
1.1
1.0
0.9
0.8
1.1
VS = ±18 V
1
VS = ±2.25 V
0.9
0.8
0
14
100k
0.1
0.00001
0.01
–140
10
10k
Total Harmonic Distortion + Noise (dB)
G = +1 V/V, RL = 2 kΩ
Total Harmonic Distortion + Noise (dB)
–60
G = +1 V/V, RL = 10 kΩ
0.01
1k
Figure 14. Input Voltage Noise Spectral Density
vs Frequency
Total Harmonic Distortion + Noise (%)
Figure 13. 0.1-Hz to 10-Hz Noise
0.1
100
Frequency (Hz)
C001
4
8
12
16
20
24
28
32
36
75
50
25
0
25
50
75
100
125
150
Supply Voltage (V)
Temperature (°C)
Figure 17. Quiescent Current vs Supply Voltage
Figure 18. Quiescent Current vs Temperature
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C001
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
3.0
Output Impedance ( )
2.0
Open-Loop Gain (µV/V)
10k
VS = 4.5 V
VS = 36 V
1.0
0.0
–1.0
1k
100
–2.0
10
–3.0
–75
–50
–25
0
25
50
75
100
125
0
150
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Temperature (°C)
C016
RL = 10 kΩ
Figure 19. Open-Loop Gain vs Temperature
Figure 20. Open-Loop Output Impedance vs Frequency
50
50
+ 18 V
45
45
-
+ 18 V
-
+
35
TLV197-Q1
+
VIN
-
30
40
RISO
Overshoot (%)
Overshoot (%)
40
CL
-18 V
25
35
RISO
TLV197-Q1
+
VIN
+
RL
30
25
20
20
RISO = 00Ω
15
RISO = 2525
Ω
15
10
RISO = 50 Ω
10
RISO = 0 Ω0
RISO = 25
25 Ω
RISO = 50
50 Ω
5
5
0
0
10p
100p
CL
-18 V
-
10p
1n
100p
1n
Capacitive Load (F)
Capacitive Load (F)
G=1
RI = 1 kΩ, RF = 1 kΩ, G = –1
Figure 21. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 22. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
VOUT
+ 18 V
TLV197-Q1
VOUT
20 mV/div
5 V/div
+
+
VIN
-
- 18 V
+ 18 V
TLV197-Q1
+
VIN
+
-18 V
RL
CL
-
VIN
Time (200 ns/div)
RI = 1 kΩ, RF = 10 kΩ, G = –10
Figure 23. Positive Overload Recovery
Copyright © 2020, Texas Instruments Incorporated
Time (100 ns/div)
CL = 10 pF, G = 1
Figure 24. Small-Signal Step Response (100 mV)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
+ 18 V
-
+
TLV197-Q1
+
VIN
CL
- 18 V
2 V/div
20 mV/div
-
+ 18 V
-
+
TLV197-Q1
+
VIN
-
Time (120 ns/div)
Time (300 ns/div)
RL = 1 kΩ, CL = 10 pF, G = –1
RL = 1 kΩ, CL = 10 pF, G = –1
Figure 25. Small-Signal Step Response (100 mV)
Figure 26. Large-Signal Step Response
4
Output Delta from Final Value (mV)
Output Delta from Final Value (mV)
4
3
2
1
0
–1
0.01% Settling = ±1 mV
–2
–3
Step Applied at t = 0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
3
2
1
0
0.01% Settling = ±500 μV
–1
–2
–3
Step Applied at t = 0
–4
–4
0
2
0.2
0.6
1
G=1
G=1
1.2
1.4
1.6
1.8
Figure 28. Settling Time (5-V Positive Step)
30
Maximum output voltage without
slew-rate induced distortion.
VS = ±15 V
ISC, Source
25
Output Voltage (VPP)
ISC, Sink
60
0.8
Time (μs)
Figure 27. Settling Time (10-V Positive Step)
Short-Circuit Current (mA)
0.4
Time (μs)
80
40
20
20
15
VS = ±5 V
10
VS = ±2.25 V
5
0
0
–75
–50 –25
0
25
50
Temperature (°C)
75
100
125
150
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10k
100k
1M
Frequency (Hz)
C001
Figure 29. Short-Circuit Current vs Temperature
16
CL
-18 V
10M
C033
Figure 30. Maximum Output Voltage vs Frequency
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SBOS935B – APRIL 2020 – REVISED JULY 2020
Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Output Voltage (1 V/div)
Output Voltage (5 V/div)
Overdrive = 100 mV
tpLH = 0.97 s
VOUT Voltage
VOUT Voltage
tpLH = 1.1 s
Overdrive = 100 mV
Time (200 ns/div)
Time (200 ns/div)
C025
C026
Figure 31. Propagation Delay Rising Edge
Figure 32. Propagation Delay Falling Edge
-80
Crosstalk (db)
-100
-120
-140
-160
-180
1k
10k
100k
1M
Frequency (Hz)
Figure 33. Crosstalk vs Frequency
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7 Detailed Description
7.1 Overview
The TLVx197-Q1 family of e-trim™ operational amplifiers uses a method of package-level trim for offset and
offset temperature drift implemented during the final steps of manufacturing after the plastic molding process.
This method minimizes the influence of inherent input transistor mismatch, as well as errors induced during
package molding. The trim communication occurs on the output pin of the standard pinout, and after the trim
points are set, further communication to the trim structure is permanently disabled. The Functional Block
Diagram shows the simplified diagram of the TLVx197-Q1 e-trim operational amplifier.
Unlike previous e-trim op amps, the TLVx197-Q1 uses a patented two-temperature trim architecture to achieve a
low offset voltage of 500 µV (maximum), and low voltage offset drift of 5 µV/°C (maximum) over the full specified
temperature range. This level of precision performance at wide supply voltages makes these amplifiers useful for
high-impedance industrial sensors, filters, and high-voltage data acquisition.
7.2 Functional Block Diagram
+
NCH Input
Stage
±
IN+
36-V
Differential
Front End
Slew
Boost
+
High Capacitive
Load
Compensation
Output
Stage
VOUT
±
IN±
+
PCH Input
Stage
±
e-WULPŒ
Package Level Trim
18
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SBOS935B – APRIL 2020 – REVISED JULY 2020
7.3 Feature Description
7.3.1 Input Protection Circuitry
The TLVx197-Q1 use a unique input architecture to eliminate the need for input protection diodes, but still
provide robust input protection under transient conditions. Conventional input diode protection schemes shown in
Figure 34 can be activated by fast transient step responses, and can introduce signal distortion and settling time
delays because of alternate current paths, as shown in Figure 35. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes, cause an increase in input current, and result in extended settling time.
TLV197-Q1 Provides Full 36V Differential Input Range
Conventional Input Protection
Limits Differential Input Range
V+
V+
+
VIN+
+
VIN+
VOUT
±
VIN
VOUT
~0.7 V
TLVx197-Q1
36 V
±
VIN
V
V
Figure 34. TLVx197-Q1 Input Protection Does Not Limit Differential Input Capability
Vn = +10 V
RFILT
+10 V
1
Ron_mux
Sn
1
D
+10 V
CFILT
2
~±9.3 V
CS
CD
Vn+1 = ±10 V RFILT
±10 V
Ron_mux
Sn+1
Vin±
2
~0.7 V
CFILT
CS
Vout
Idiode_transient
±10 V
Input Low Pass Filter
Vin+
Buffer Amplifier
Simplified Mux Model
Figure 35. Back-to-Back Diodes Create Settling Issues
The TLVx197-Q1 family of operational amplifiers provides a true high-impedance differential input capability for
high-voltage applications. This patented input protection architecture does not introduce additional signal
distortion or delayed settling time, and makes the device an excellent choice for multichannel, high-switched,
input applications. The TLVx197-Q1 tolerates a maximum differential swing (voltage between inverting and
noninverting pins of the op amp) of up to 36 V, thus making the device great for use as a comparator or in
applications with fast-ramping input signals such as multiplexed data-acquisition systems; see Figure 41.
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Feature Description (continued)
7.3.2 EMI Rejection
The TLVx197-Q1 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLVx197-Q1 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 36 shows the results of this testing on the TLVx197-Q1. Table 1 shows the EMIRR IN+ values for the
TLVx197-Q1 at particular frequencies commonly encountered in real-world applications. Applications listed in
Table 1 may be centered on or operated near the particular frequency shown. Detailed information can also be
found in the EMI Rejection Ratio of Operational Amplifiers application report, available for download from
www.ti.com.
160.0
140.0
PRF = -10 dBm
VSUPPLY = ±18 V
VCM = 0 V
EMIRR IN+ (dB)
120.0
100.0
80.0
60.0
40.0
20.0
0.0
10M
100M
1G
Frequency (Hz)
10G
C017
Figure 36. EMIRR Testing
Table 1. TLVx197-Q1 EMIRR IN+ For Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications
44.1 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation, GPS
(to 1.6 GHz), GSM, aeronautical mobile, UHF applications
52.8 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
61.0 dB
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
69.5 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
88.7 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
105.5 dB
5 GHz
20
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7.3.3 Phase Reversal Protection
The TLVx197-Q1 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond the respective linear common-mode range. This condition is most often encountered in
noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the
output to reverse into the opposite rail. The TLVx197-Q1 is a rail-to-rail input op amp; therefore, the commonmode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the
output limits into the appropriate rail.
7.3.4 Thermal Protection
CAUTION
The absolute maximum junction temperature of the TLVx197-Q1 is 150°C. Exceeding
this temperature causes damage to the device.
VOUT
The internal power dissipation of any amplifier causes the internal (junction) temperature of the amplifier to rise.
This phenomenon is called self heating. The TLVx197-Q1 has a thermal protection feature that prevents damage
from self heating. The protection works by monitoring the temperature of the device and turning off the op amp
output drive for temperatures greater than 140°C. Figure 37 shows an application example for the TLVx197-Q1
that has significant self heating (159°C) because of the power dissipation (0.81 W). Thermal calculations indicate
that for an ambient temperature of 65°C, the device junction temperature must reach 187°C. The actual device,
however, turns off the output drive to maintain a safe junction temperature. Figure 37 shows how the circuit
behaves during thermal protection. During normal operation, the device acts as a buffer, so the output is 3 V.
When self heating causes the device junction temperature to exceed 140°C, the thermal protection forces the
output to a high-impedance state, and the output is pulled to ground through resistor RL.
30 V
TA = 65°C
PD = 0.81W
R JA = 116°C/W
TJ = 116°C/W × 0.81W + 65°C
TJ = 159°C (expected)
3V
Normal
Operation
0V
Output
High-Z
±
150°C
TLVx197-Q1
IOUT = 30 mA
+
±
RL
100 Ÿ
VIN
3V
+
3V
±
140°C
Temperature
+
Figure 37. Thermal Protection
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7.3.5 Capacitive Load and Stability
The TLVx197-Q1 features a patented output stage capable of driving large capacitive loads, and in a unity-gain
configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the
amplifier to drive greater capacitive loads.
The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider
when establishing whether an amplifier is stable in operation.
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10Ω to 20-Ω) resistor, RISO, in series with the output, as shown in Figure 38. This resistor significantly reduces
ringing and maintains dc performance for purely capacitive loads. However, if a resistive load is in parallel with
the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at
low output levels. A high capacitive load drive makes the TLVx197-Q1 a great choice for applications such as
reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 38 uses an isolation
resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased
phase margin, and the results using the TLVx197-Q1 are summarized in Table 2. For additional information on
techniques to optimize and design using this circuit, reference design TIPD128, Capacitive Load Drive Verified
Reference Design Using an Isolation Resistor, details complete design goals, simulation, and test results.
+Vs
Vout
Riso
+
Vin
Cload
+
±
-Vs
Figure 38. Extending Capacitive Load Drive With the TLVx197-Q1
Table 2. TLVx197-Q1 Capacitive Load Drive Using Isolation Resistor Comparison of Calculated and
Measured Results
PARAMETER
VALUE
Capacitive Load
100 pF
1000 pF
0.01 µF
0.1 µF
1 µF
Phase Margin
45°
60°
45°
60°
45°
60°
45°
60°
45°
60°
RISO (Ω)
47
360
24
100
20
51
6.2
15.8
2
4.7
Measured
Overshoot (%)
23.2 8.6
10.4
22.5
9
22.1
8.7
23.1
8.6
21
8.6
Calculated PM
45.1°
58.1°
45.8°
59.7°
46.1°
60.1°
45.2°
60.2°
47.2°
60.2°
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results,
see TI Precision Design TIDU032, Capacitive Load Drive Solution using an Isolation Resistor .
22
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SBOS935B – APRIL 2020 – REVISED JULY 2020
7.3.6 Common-Mode Voltage Range
The TLVx197-Q1 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 39. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 3 V to 100 mV greater than the positive supply. The P-channel pair is
active for inputs from 100 mV less than the negative supply to approximately (V+) – 1.5 V. There is a small
transition region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are on. This transition region can
vary modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and
THD performance may be degraded compared to operation outside this region.
+Vsupply
IS1
VIN±
PCH1
PCH2
NCH3
NCH4
VIN+
e-trimTM
FUSE BANK
VOS TRIM
VOS DRIFT TRIM
±Vsupply
Figure 39. Rail-to-Rail Input Stage
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The TLVx197-Q1 uses a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, and causes the variance in the
transition region of the input stages to appear exaggerated relative to offset over the full common-mode range.
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7.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 40 shows an illustration of the ESD circuits contained in the TLVx197-Q1 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
+
±
RF
+VS
VDD
TLVx197-Q1
R1
RS
IN±
100
IN+
100
±
+
Power Supply
ESD Cell
VIN
RL
+
±
VSS
+
±
±VS
TVS
Figure 40. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns); whereas, an EOS
event is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-ofcircuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to the
PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
24
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7.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLVx197-Q1 is approximately 200 ns.
7.4 Device Functional Modes
The TLVx197-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the TLVx197-Q1 is 36 V (±18 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLVx197-Q1 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer true rail-to-rail input and output, low offset voltage and offset voltage drift, as well as
10-MHz bandwidth and high capacitive load drive. These features make the TLVx197-Q1 a robust, highperformance operational amplifier for high-voltage automotive applications.
8.2 Typical Applications
8.2.1 16-Bit Precision Multiplexed Data-Acquisition System
Figure 41 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in
sensor based applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This
TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the
TLVx197-Q1 and TLV140 to achieve excellent dynamic performance and linearity with the ADS8864.
1
2
3
4
Very Low Output Impedance
Input-Filter Bandwidth
High-Impedance Inputs
No Differential Input Clamps
Fast Settling-Time Requirements
Attenuate High-Voltage Input Signal
Fast-Settling Time Requirements
Stability of the Input Driver
Attenuate ADC Kickback Noise
VREF Output: Value and Accuracy
Low Temp and Long-Term Drift
Voltage
Reference
CH0+
TLVx197-Q1
±20-V,
10-kHz
Sine Wave
+
RC Filter
Buffer
RC Filter
Reference Driver
+
CH0-
TLVx197-Q1
Gain
Network
TLVx197-Q1
Gain
Network
+
4:2
Mux
REFP
+
TLVx197-Q1
CH3+
TLVx197-Q1
+
VINP
+
Antialiasing
Filter
SAR
ADC
+
VINM
TLVx197-Q1
CH3-
n
16 Bits
400 kSPS
High-Voltage Level Translation
VCM
High-Voltage Multiplexed Input
CONV
Gain
Network
±20-V,
10-kHz
Sine Wave
TLVx197-Q1
Gain
Network
REF3240
Voltage
Divider
OPA350
VCM Generation Circuit
Counter
n
5
Fast logic transition
Shmidtt
Trigger
Delay
Digital Counter For Multiplexer
Figure 41. TLVx197-Q1 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for HighVoltage Inputs With Lowest Distortion
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Typical Applications (continued)
8.2.1.1 Design Requirements
The primary objective is to design a ±20 V, differential 4-channel multiplexed data acquisition system with lowest
distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10 kHz full-scale pure sine-wave input.
The design requirements for this block design are:
• System supply voltage: ±15 V
• ADC supply voltage: 3.3 V
• ADC sampling rate: 400 kSPS
• ADC reference voltage (REFP): 4.096 V
• System input signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
8.2.1.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for
highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 41. The circuit
is a multichannel data acquisition signal chain consisting of an input low-pass filter, multiplexer (mux), mux output
buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast
sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design
considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input
analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each
analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit
resolution and lowest distortion system. Figure 41 includes the most important specifications for each individual
analog block.
This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input
stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design
is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding
helps in the decision of an appropriate input filter and selection of a mux to meet the system settling
requirements. The next important step is the design of the attenuating analog front-end (AFE) used to level
translate the high-voltage input signal to a low-voltage ADC input when maintaining amplifier stability. The next
step is to design a digital interface to switch the mux input channels with minimum delay. The final design
challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference voltage
with low offset, drift, and noise contributions.
8.2.1.3 Application Curve
Integral Nonlinearity Error (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–20
–15
–10
–5
0
5
10
15
20
ADC Differential Input (V)
Figure 42. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TIPD151, 16Bit, 400 kSPS 4-Channell, Multiplexed Data Acquisition Ref erence Design for High Voltage Inputs, Low Distortion.
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8.2.2 Slew-Rate Limit for Input Protection
In control systems for motors, abrupt changes in voltages or currents can cause mechanical damages. By
controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down at
a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one additional
op amp provides slew-rate control for a given analog gain stage. The unique input protection and high output
current and slew rate of the TLVx197-Q1 make these devices an optimal amplifier to achieve slew-rate control for
both dual- and single-supply systems.Figure 43 shows the TLVx197-Q1 in a slew-rate limit design.
Op Amp Gain Stage
Slew Rate Limiter
C1
470 nF
R1
1.69 NŸ
VEE
VEE
R2
1.6 0Ÿ
+
±
VIN
TLVx197-Q1
+ V+
VOUT
TLVx197-Q1
V+
VCC
RL
10 NŸ
VCC
Figure 43. Slew-Rate Limiter Uses One Op Amp
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see TIPD140, Single
Op-Amp Slew Rate Limiter Reference Design.
8.2.3 Precision Reference Buffer
The TLVx197-Q1 feature high output-current-drive capability and low input offset voltage, making the device an
excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the
10-µF ceramic capacitor shown in Figure 44, RISO, a 37.4-Ω isolation resistor, provides separation of two
feedback paths for optimal stability. Feedback path number one is through RF and is directly at the output (VOUT).
Feedback path number two is through RFx and CF and is connected at the output of the op amp. The optimized
stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz and still
provide a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability
components: RF, RFx, CF, and RISO.
RF
1 kŸ
CF
39 nF
RFx
10 kŸ
RISO
37.4 Ÿ
±
TLVx197-Q1
+ V+
VREF
2.5 V
VOUT
CL
10 µF
VCC
Figure 44. Precision Reference Buffer
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9 Power Supply Recommendations
The TLVx197-Q1 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see Absolute
Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole. and through
the individual op amp. Bypass capacitors are used to reduce the coupled noise by providing lowimpedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better
than in parallel with the noisy trace.
• Place the external components as close as possible to the device. As illustrated in Figure 46, keep RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• For best performance, clean the PCB following board assembly.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove
moisture introduced into the device packaging during the cleaning process. A low-temperature, postcleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Examples
+
VIN
VOUT
RG
RF
Figure 45. Schematic Representation
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
RF
VS+
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitors
Figure 46. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
• Texas Instruments, Capacitive Load Drive Solution using an Isolation Resistor reference design
11.3 Related Links
Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to order now.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV197-Q1
Click here
Click here
Click here
Click here
Click here
TLV2197-Q1
Click here
Click here
Click here
Click here
Click here
TLV4197-Q1
Click here
Click here
Click here
Click here
Click here
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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11.6 Trademarks
e-trim, E2E are trademarks of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV197QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
Q197
TLV2197QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2BD6
TLV4197QPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
T4197Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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