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TLV320DAC3203
SLOS756B – MAY 2012 – REVISED DECEMBER 2018
TLV320DAC3203 Ultra Low Power Stereo Audio Codec With Integrated Headphone
Amplifiers
1 Features
3 Description
•
•
•
•
•
•
•
•
•
The TLV320DAC3203 (sometimes referred to as the
DAC3203) is a flexible, low-power, low-voltage stereo
audio codec with programmable outputs, PowerTune
capabilities, fixed predefined and parameterizable
signal processing blocks, integrated PLL, integrated
LDO and flexible digital interfaces. Extensive registerbased control of power, input/output channel
configuration, gains, effects, pin-multiplexing and
clocks is included, allowing the device to be precisely
targeted to its application.
1
Stereo Audio DAC with 100dB SNR
4.1mW Stereo 48ksps Playback
PowerTune™
Extensive Signal Processing Options
Stereo Headphone Outputs
Low Power Analog Bypass Mode
Programmable PLL
Integrated LDO
4 mm × 4 mm VQFN and 2.7 mm × 2.7 mm
DSGBA Package
The device is available in the 4 mm × 4 mm VQFN
and 2.7 mm × 2.7 mm DSGBA package.
Device Information(1)
2 Applications
•
•
•
PART NUMBER
Mobile Handsets
Communication
Portable Computing
TLV320DAC3203
PACKAGE
BODY SIZE (NOM)
VQFN (24)
4.00 mm x 4.00 mm
DSBGA (25)
2.70 mm x 2.70 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
spacer
Simplified Block Diagram
INL
DRC
Vol. Ctrl
-6...+29dB
MFP3/SCLK
MFP4/MISO
Data Interface
Dig Mic
Interface
Left
DAC
Dig Mic
Signal
Proc.
HPL
1dB steps
DAC Signal Proc.
-6...+29dB
Right
DAC
HPR
1dB steps
DRC
Vol. Ctrl
INR
ALDO
LDOin
AVdd
SPI_Select
PLL
Interrupt Secondary
Ctrl
I2S IF
Primary
I2S Interface
IOVdd
Jack
detect
Pin Muxing / Clock Routing
Ref
Supplies
Reset
SPI / I2C
Control Block
DVdd
IOVss
DVss
AVss
Ref
Micbias
WCLK
BCLK
DIN/MFP1
DOUT/MFP2
MCLK
GPIO
(WCSP Only)
SDA/MOSI
SCL/SSZ
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV320DAC3203
SLOS756B – MAY 2012 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics, Bypass Outputs .............. 6
Electrical Characteristics, Microphone Interface...... 6
Electrical Characteristics, Audio Outputs................. 7
Electrical Characteristics, LDO ................................ 9
Electrical Characteristics, Misc. ............................... 9
Electrical Characteristics, Logic Levels................... 9
Typical Timing Characteristics — Audio Data Serial
Interface Timing (I2S) ............................................... 10
6.12 Typical DSP Timing Characteristics...................... 11
6.13 I2C Interface Timing .............................................. 12
6.14 SPI Interface Timing (See Figure 6) .................... 13
6.15 Typical Characteristics .......................................... 14
7
Detailed Description ............................................ 16
7.1
7.2
7.3
7.4
7.5
8
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Register Maps .........................................................
16
16
17
22
23
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Application ................................................. 26
9 Power Supply Recommendations...................... 27
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 28
11 Device and Documentation Support ................. 29
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
29
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2017) to Revision B
Page
•
Changed Description of pin 7 in the Pin Functions table ....................................................................................................... 4
•
Changed TYPE and Description of pin 8 in the Pin Functions table...................................................................................... 4
•
Changed pin 14 (ball E4) TYPE From: AVdd To: AVss in the Pin Functions table ............................................................... 4
•
Changed pin 21 (ball D1) TYPE From: DVdd To: DVss in the Pin Functions table............................................................... 4
•
Changed pin 23 (ball B1) TYPE From: IOVdd To: IOVss in the Pin Functions table............................................................. 4
•
Changed ball C4 TYPE From: I To: I/O in the Pin Functions table ........................................................................................ 4
Changes from Original (May 2012) to Revision A
Page
•
Changed Feature From: 4mm × 4mm QFN and 2.7mm × 2.7mm WCSP package To: 4 mm × 4 mm VQFN and 2.7
mm × 2.7 mm DSGBA Package............................................................................................................................................. 1
•
Added the Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal
Information table, Detailed Description section, Application and Implementation section, Device and Documentation
Support, and Mechanical, Packaging, and Orderable Information sections........................................................................... 1
•
Corrected the pin names of the RGE Package image ........................................................................................................... 3
2
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TLV320DAC3203
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SLOS756B – MAY 2012 – REVISED DECEMBER 2018
5 Pin Configuration and Functions
YZK Package
25 Pin DSBGA
Top View
B
IOVss
BCLK
WCLK
SDA/MOSI
DMCLK/MFP4
/MISO
A
MCLK
DIN/MFP1
DOUT/MFP2
SCL/SS
DMDIN/MFP3
/SCLK
Not to scale
SPI_ SELECT
HPR
19
GPIO/MFP5
MCLK
1
18
MICBIAS
BCLK
2
17
REF
WCLK
3
16
INR
DIN/MFP1
4
15
INL
DOUT/MFP2
5
14
AVss
DMDIN/MFP3
6
13
AVdd
12
IOVdd
HPL
RESET
RESET
DVdd
20
C
11
LDOin/
HVPDD
LDOin
HPL
DVss
AVdd
DVdd
MICBIAS
21
DVss
10
D
HPR
INL
DMCLK/MFP4
AVss
IOVss
INR
22
REF
23
SPI_ SELECT
9
E
8
5
SDA/MOSI
4
IOVdd
3
7
2
SCL/SS
1
24
RGE Package
24 Pin VQFN
Top View
Not to scale
Pin Functions
PIN
QFN PIN
WCSP
BALL
NAME
TYPE
DESCRIPTION
1
A1
MCLK
I
2
B2
BCLK
IO
Audio serial data bus (primary) bit clock
3
B3
WCLK
IO
Audio serial data bus (primary) word clock
4
A2
DIN/MFP1
I
Master Clock Input
Primary function
Audio serial data bus data input
Secondary function
Digital Microphone Input
General Purpose Input
5
A3
DOUT/MFP2
O
Primary
Audio serial data bus data output
Secondary
General Purpose Output
Clock Output
INT1 Output
INT2 Output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
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TLV320DAC3203
SLOS756B – MAY 2012 – REVISED DECEMBER 2018
www.ti.com
Pin Functions (continued)
PIN
QFN PIN
WCSP
BALL
NAME
TYPE
6
A5
DMDIN/
MFP3/
I
DESCRIPTION
Primary (SPI_Select = 1)
SPI serial clock
Secondary: (SPI_Select = 0)
Digital microphone input
Headset detect input
Audio serial data bus (secondary) bit clock input
Audio serial data bus (secondary) DAC/common word clock input
Audio serial data bus (secondary) ADC word clock input
Audio serial data bus (secondary) data input
General Purpose Input
7
A4
SCL/
SS
I
Multi-function digital input.
For (SPI_SELECT=0): Clock Pin for I2C control bus.
For (SPI_SELECT = 1): SPI chip selection pin.
8
B4
SDA/ MOSI
I/O
Multi-function digital pin.
For (SPI_SELECT=0): Data Pin for I2C control bus.
For (SPI_SELECT = 1): SPI data input.
9
B5
DMCLK/
MFP4
O
Primary (SPI_Select = 1)
Serial data output
Secondary (SPI_Select = 0) Multifunction pin #4 (MFP4) options are only available using I2C
Digital microphone clock output
General purpose output
CLKOUT output
INT1 output
INT2 output
Audio serial data bus (primary) ADC word clock output
Audio serial data bus (secondary) data output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
10
C5
HPR
O
11
D5
LDOin
Power
Right high-power output driver
12
D4
HPL
O
13
D3
AVdd
Power
Analog voltage supply 1.5V–1.95V
Input when A-LDO disabled,
Filtering output when A-LDO enabled
14
E4
AVss
Ground
Analog ground supply
15
E5
INL
I
Left Analog Bypass Input
16
E3
INR
I
Right Analog Bypass Input
LDO Input supply and Headphone Power supply 1.9V– 3.6V
Left high power output driver
17
E2
REF
O
Reference voltage output for filtering
18
D2
MICBIAS
O
Microphone bias voltage output
19
E1
SPI_ SELECT
I
Control mode select pin ( 1 = SPI, 0 = I2C )
20
C2
RESET
I
Reset (active low)
21
D1
DVss
Ground
Digital Ground and Chip-substrate
22
C1
DVdd
Power
Digital voltage supply 1.26V–1.95V
23
B1
IOVss
Ground
I/O ground supply
24
C3
IOVdd
Power
I/O voltage supply 1.1V – 3.6V
n/a
C4
GPIO/MFP5
I/O
Primary
General Purpose digital IO
Secondary
CLKOUT Output
INT1 Output
INT2 Output
Audio serial data bus ADC word clock output
Audio serial data bus (secondary) bit clock output
Audio serial data bus (secondary) word clock output
Digital microphone clock output
4
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SLOS756B – MAY 2012 – REVISED DECEMBER 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
AVdd to AVss
–0.3
2.2
V
DVdd to DVss
–0.3
2.2
V
IOVDD to IOVSS
–0.3
3.9
V
LDOIN to AVss
–0.3
3.9
V
Digital Input voltage
–0.3
IOVDD + 0.3
V
Analog input voltage
–0.3
AVdd + 0.3
V
Operating temperature range
–40
85
°C
Storage temperature range
–55
125
°C
105
°C
Junction temperature (TJ Max)
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human-body model (HBM), YZK, per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Human-body model (HBM), RGE, per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), YZK, per JEDEC specification JESD22-C101 (2)
Charged-device model (CDM), RGE, per JEDEC specification JESD22-C101
(1)
(2)
UNIT
V
±1000
(2)
V
±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. .
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
LDOIN (1)
Referenced to AVss (2)
AVdd
IOVDD
Power Supply Voltage Range
DVdd
PLL Input Frequency
MCLK
Master Clock Frequency
SCL
SCL Clock Frequency
HPL, HPR
1.5
Referenced to IOVSS (2)
Clock divider uses fractional divide
(D > 0), P=1, DVdd ≥ 1.65V (See table in SLAU434, Maximum
TLV320DAC3203 Clock Frequencies)
Clock divider uses integer divide
(D = 0), P=1, DVdd ≥ 1.65V (Refer to table in SLAU434,
Maximum TLV320DAC3203 Clock Frequencies)
MAX
UNIT
3.6
1.8
1.95
1.65
1.8
1.95
1.26
1.8
1.95
1.1
Referenced to DVss (2)
DVdd (3)
NOM
1.9
3.6
V
10
20
MHz
0.512
20
MHz
50
MHz
400
kHz
MCLK; Master Clock Frequency; DVdd ≥ 1.65V
Ω
Stereo headphone output load resistance
Single-ended configuration
14.4
16
Headphone output load resistance
Differential configuration
24.4
32
Ω
CLout
Digital output load capacitance
10
pF
Cref
Reference decoupling capacitor
1
µF
(1)
(2)
(3)
Minimum spec applies if LDO is used. Minimum is 1.5V if LDO is not enabled. Using the LDO below 1.9V degrades LDO performance.
All grounds on board are tied together, so they should not differ in voltage by more than 0.2V max, for any combination of ground
signals.
At DVdd values lower than 1.65V, the PLL does not function. Please see table in SLAU434, Maximum TLV320DAC3203 Clock
Frequencies for details on maximum clock frequencies.
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6.4 Thermal Information
TLV320DAC3203
THERMAL METRIC (1)
YZK (DSBGA)
RGE (VQFN)
25 PINS
24 PINS
UNIT
57.6
34.6
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
0.3
26.6
°C/W
RθJB
Junction-to-board thermal resistance
13.7
12.5
°C/W
ψJT
Junction-to-top characterization parameter
0.1
0.3
°C/W
ψJB
Junction-to-board characterization parameter
13.7
12.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
2.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5
Electrical Characteristics, Bypass Outputs
At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 1.8V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10μF on REF PIN, PLL
disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE
Load = 16Ω (single-ended), 50pF;
Input and Output CM = 0.9V;
Headphone Output on LDOIN Supply;
INL routed to HPL and INR routed to HPR;
Channel Gain = 0dB
Device Setup
Gain Error
Noise, A-weighted
THD
(1)
6.6
±0.4
(1)
Total Harmonic Distortion
Idle Channel, INL and INR ac-shorted to
ground
dB
3
446mVrms, 1-kHz input signal
μVRMS
–82
dB
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
Electrical Characteristics, Microphone Interface
At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 1.8V, AVdd LDO disabled, Cref = 10μF on REF PIN, PLL disabled unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MICROPHONE BIAS
Micbias Mode 0, Connect to AVdd or LDOin
CM = 0.9V,
LDOin = 3.3V,
no load
Bias voltage
CM = 0.75V,
LDOin = 3.3V
Output Noise
CM = 0.9V
Current Sourcing
Inline Resistance
6
1.25
V
Micbias Mode 1, Connect to LDOin
1.7
V
Micbias Mode 2, Connect to LDOin
2.5
V
Micbias Mode 3, Connect to AVdd
AVdd
V
Micbias Mode 3, Connect to LDOin
LDOin
V
Micbias Mode 0, Connect to AVdd or LDOin
1.04
V
Micbias Mode 1, Connect to AVdd or LDOin
1.42
V
Micbias Mode 2, Connect to LDOin
2.08
V
Micbias Mode 3, Connect to AVdd
AVdd
V
Micbias Mode 3, Connect to LDOin
LDOin
V
Micbias Mode 2, A-weighted, 20Hz to 20kHz
bandwidth, Current load = 0mA
Micbias Mode 2, Connect to LDOin
10
μVRMS
3
mA
Micbias Mode 3, Connect to AVdd
160
Micbias Mode 3, Connect to LDOin
110
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6.7
SLOS756B – MAY 2012 – REVISED DECEMBER 2018
Electrical Characteristics, Audio Outputs
At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 1.8V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μF on REF PIN,
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.5
VRMS
88
100
dB
99
dB
Audio DAC – Stereo Single-Ended Headphone Output
Load = 16Ω (single-ended), 50pF
Headphone Output on AVdd Supply,
Input & Output CM = 0.9V, DOSR = 128,
MCLK = 256* fs, Channel Gain = 0dB
word length = 16 bits;
Processing Block = PRB_P1
Power Tune = PTM_P3
Device Setup
Full scale output voltage (0dB)
SNR
Signal-to-noise ratio, A-weighted (1)
(2)
DR
Dynamic range, A-weighted
THD+N
Total Harmonic Distortion plus Noise
–3dB full-scale, 1-kHz input signal
–80
DAC Gain Error
0dB, 1kHz input full scale signal
±0.1
dB
DAC Mute Attenuation
Mute
127
dB
DAC channel separation
–1dB, 1kHz signal, between left and right HP
out
92
dB
100mVpp, 1kHz signal applied to AVdd
70
dB
100mVpp, 217Hz signal applied to AVdd
75
dB
RL=16Ω, Output Stage on AVdd = 1.8V
THDN < 1%, Input CM=0.9V,
Output CM=0.9V, Channel Gain = 2dB
13
RL= 16Ω Output Stage on LDOIN = 3.3V,
THDN < 1% Input CM = 0.9V,
Output CM = 1.65V, Channel Gain = 8dB
47
(1) (2)
All zeros fed to DAC input, modulator in
excited state
–60dB 1kHz input full-scale signal, Word
Length = 20 bits, Power Tune = PTM_P4
DAC PSRR
Power Delivered
–70
dB
mW
Audio DAC – Stereo Single-Ended Headphone Output
Load = 16Ω (single-ended), 50pF,
Headphone Output on AVdd Supply,
Input and Output CM = 0.75V; AVdd = 1.5V,
DOSR = 128, MCLK = 256 x fs,
Channel Gain = –2dB, word length = 20-bits;
Processing Block = PRB_P1,
Power Tune = PTM_P4
Device Setup
Full scale output voltage (0dB)
0.375
SNR
Signal-to-noise ratio, A-weighted (1)
DR
Dynamic range, A-weighted
THD+N
Total Harmonic Distortion plus Noise
(1)
(2)
(2)
(1) (2)
All zeros fed to DAC input, modulator in
excited state
VRMS
99
dB
-60dB 1 kHz input full-scale signal
98
dB
–3dB full-scale, 1-kHz input signal
–84
dB
Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values
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Electrical Characteristics, Audio Outputs (continued)
At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 1.8V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μF on REF PIN,
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio DAC – Mono Differential Headphone Output
Load = 32 Ω (differential), 50pF,
Headphone Output on LDOIN Supply
Input CM = 0.75V, Output CM = 1.5V,
AVdd=1.8V, LDOIN = 3.0V, DOSR = 128
MCLK = 256* fs, Channel (headphone driver)
Gain = 5dB for full scale output signal,
word length = 16-bits,
Processing Block = PRB_P1,
Power Tune = PTM_P3
Device Setup
Full scale output voltage (0dB)
SNR
Signal-to-noise ratio, A-weighted (1)
DR
Dynamic range, A-weighted
THD
Total Harmonic Distortion
(1) (2)
Power Delivered
8
(2)
1778
mVRMS
101
dB
–60dB 1kHz input full-scale signal
98
dB
–3dB full-scale, 1-kHz input signal
–82
dB
RL = 32Ω, Output Stage on LDOIN = 3.3V,
THDN < 1%, Input CM = 0.9V,
Output CM = 1.65V, Channel Gain = 8dB
125
mW
RL = 32Ω Output Stage on LDOIN = 3V,
THDN < 1% Input CM = 0.9V,
Output CM = 1.5V, Channel Gain = 8dB
103
mW
All zeros fed to DAC input, modulator in
excited state
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6.8
SLOS756B – MAY 2012 – REVISED DECEMBER 2018
Electrical Characteristics, LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW DROPOUT REGULATOR (AVdd)
Output Voltage
LDOMode = 1, LDOin > 1.95V,
IO = 15mA
1.63
LDOMode = 0, LDOin > 2.0V,
IO = 15mA
1.68
LDOMode = 2, LDOin > 2.05V,
IO = 15mA
1.73
Output Voltage Accuracy
±2%
Load Regulation
Load current range 0 to 50mA
Line Regulation
Input Supply Range 1.9V to 3.6V
Decoupling Capacitor
26
mV
3
mV
1
μF
Bias Current
6.9
V
50
μA
Electrical Characteristics, Misc.
At 25°C, AVdd, DVdd, IOVDD = 1.8V, LDO_in = 3.3V, AVdd LDO disabled, fs (Audio) = 48kHz, Cref = 10 μF on REF PIN,
PLL disabled unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE
Reference Voltage Settings
Reference Noise
CMMode = 0 (0.9V)
0.9
CMMode = 1 (0.75V)
0.75
CM=0.9V, A-weighted, 20Hz to 20kHz bandwidth,
Cref = 10μF
V
1
Decoupling Capacitor
1
Bias Current
μVRfcMS
10
μF
120
µA
Shutdown Current
Coarse AVdd supply turned off, LDO_select held at
ground, No external digital input is toggled
Device Setup
IDVdd
1.4
IAVdd
1
ILDOin
1
IIOVDD
1.6V
–0.3
V
IIL = 5μA, IOVDD < 1.2V
VOH
IOH = 2 TTL loads
VOL
0.3 × IOVDD
V
0.1 × IOVDD
V
0
V
0.8 × IOVDD
V
IOL = 2 TTL loads
Capacitive Load
(1)
UNIT
IIH = 5 μA, IOVDD > 1.6V
IIL = 5μA, 1.2V ≤ IOVDD < 1.6V
VIL
MAX
CMOS
0.1 × IOVDD
10
V
pF
Applies to all DI, DO, and DIO pins shown in .
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6.11 Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
All specifications at 25°C, DVdd = 1.8V
IOVDD=1.8V
MIN
IOVDD=3.3V
MAX
MIN
UNITS
MAX
I2S/LJF/RJF Timing in Master Mode (see Figure 1)
td(WS)
WCLK delay
30
20
ns
td (DO-WS)
WCLK to DOUT delay (For LJF Mode only)
50
25
ns
td (DO-BCLK)
BCLK to DOUT delay
25
ns
ts(DI)
DIN setup
8
8
ns
th(DI)
DIN hold
8
8
ns
tr
Rise time
24
12
ns
tf
Fall time
24
15
ns
50
I2S/LJF/RJF Timing in Slave Mode (see Figure 2)
tH (BCLK)
BCLK high period
35
35
ns
tL (BCLK)
BCLK low period
35
35
ns
ts (WS)
WCLK setup
8
8
ns
th (WS)
WCLK hold
8
8
ns
td (DO-WS)
WCLK to DOUT delay (For LJF mode only)
50
25
ns
td (DO-BCLK)
BCLK to DOUT delay
50
25
ns
ts(DI)
DIN setup
8
th(DI)
DIN hold
8
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
8
ns
8
ns
WCLK
td(WS)
BCLK
td(DO-BCLK)
td(DO-WS)
DOUT
tS(DI)
th(DI)
DIN
Figure 1. I2S/LJF/RJF Timing in Master Mode
WCLK
th(WS)
BCLK
tL(BCLK)
tH(BCLK)
ts(WS)
td(DO-WS)
td(DO-BCLK)
DOUT
ts(DI)
th(DI)
DIN
Figure 2. I2S/LJF/RJF Timing in Slave Mode
10
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6.12 Typical DSP Timing Characteristics
All specifications at 25°C, DVdd = 1.8V
IOVDD=1.8V
MIN
IOVDD=3.3V
MAX
MIN
UNITS
MAX
DSP Timing in Master Mode (see Figure 3)
td (WS)
WCLK delay
30
20
ns
td (DO-BCLK)
BCLK to DOUT delay
40
20
ns
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
Rise time
24
12
ns
tf
Fall time
24
12
ns
ns
ns
DSP Timing in Slave Mode (see Figure 4)
tH (BCLK)
BCLK high period
35
35
ns
tL (BCLK)
BCLK low period
35
35
ns
ts(WS)
WCLK setup
8
8
ns
th(WS)
WCLK hold
8
8
td (DO-BCLK)
BCLK to DOUT delay
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
40
ns
22
ns
ns
ns
WCLK
td(WS)
td(WS)
BCLK
td(DO-BCLK)
DOUT
th(DI)
ts(DI)
DIN
Figure 3. DSP Timing in Master Mode
WCLK
th(ws)
BCLK
tH(BCLK)
ts(ws)
th(ws)
th(ws)
tL(BCLK)
td(DO-BCLK)
DOUT
ts(DI)
th(DI)
DIN
Figure 4. DSP Timing in Slave Mode
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6.13 I2C Interface Timing
Standard-Mode
MIN
TYP
0
Fast-Mode
MAX
0
TYP
UNITS
MAX
fSCL
SCL clock frequency
tHD;STA
Hold time (repeated) START condition. After this period,
the first clock pulse is generated.
4.0
0.8
μs
tLOW
LOW period of the SCL clock
4.7
1.3
μs
tHIGH
HIGH period of the SCL clock
4.0
0.6
μs
tSU;STA
Setup time for a repeated START condition
4.7
tHD;DAT
Data hold time: For I2C bus devices
tSU;DAT
Data set-up time
tr
SDA and SCL Rise Time
1000
20+0.1Cb
300
ns
tf
SDA and SCL Fall Time
300
20+0.1Cb
300
ns
tSU;STO
Set-up time for STOP condition
4.0
0.8
μs
tBUF
Bus free time between a STOP and START condition
4.7
1.3
μs
Cb
Capacitive load for each bus line
0
100
MIN
400
0.8
3.45
250
0
μs
0.9
100
400
kHz
μs
ns
400
pF
Figure 5. I2C Interface Timing
12
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6.14 SPI Interface Timing (See Figure 6)
All specifications at 25°C, DVdd = 1.8V
IOVDD=1.8V
MIN
tsck
SCLK Period
tsckh
IOVDD=3.3V
TYP MAX
MIN
TYP
UNITS
MAX
100
50
ns
SCLK Pulse width High
50
25
ns
tsckl
SCLK Pulse width Low
50
25
ns
tlead
Enable Lead Time
30
20
ns
tlag
Enable Lag Time
30
20
ns
td;seqxfr
Sequential Transfer Delay
40
20
ns
ta
Slave DOUT access time
40
20
ns
tdis
Slave DOUT disable time
40
25
ns
tsu
DIN data setup time
15
th;DIN
DIN data hold time
15
tv;DOUT
DOUT data valid time
tr
tf
10
ns
10
ns
45
25
ns
SCLK Rise Time
4
4
ns
SCLK Fall Time
4
4
ns
SS
S
t
t Lead
t Lag
t
td
sck
SCLK
tf
t sckl
tr
t sckh
t v(DOUT)
t dis
MISO
MSB OUT
ta
MOSI
t su
BIT 6 . . . 1
LSB OUT
t h(DIN)
MSB IN
BIT 6 . . . 1
LSB IN
Figure 6. SPI Interface Timing Diagram
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6.15 Typical Characteristics
0
0
CM=0.9 V,
RL = 16 W
Load = 32 W BTL
CM=1.65 V,
RL = 32 W
-10
THD - Total Harmonic Distortion - dB
THD - Total Harmonic Distortion - dB
CM=0.9 V,
-10 RL = 32 W
-20
-30
CM=1.65 V,
RL = 16 W
-40
-50
-60
-70
-20
CM=1.5 V
-30
CM=1.65 V
-40
-50
-60
-70
-80
-80
-90
-90
0
20
40
60
80
Headphone Output Power - mW
100
0
Figure 7. Total Harmonic Distortion vs Headphone Output
Power
100
150
Headphone output Power - mW
200
Figure 8. Total Harmonic Distortion vs Headphone Output
Power
250
70
105
50
SNR
60
200
50
90
85
40
SINGLE ENDED
OUTPUT POWER
16W, -40dB THD
80
30
75
20
Dropout Voltage - mV
95
Output Power - mW
SNR - Signal-to-Noise Ratio - dB
100
70
150
100
50
10
65
60
0.75
0.9
1.5
1.25
Output Common Mode Setting - V
1.65
0
0
0
10
20
30
Load - mA
40
50
Figure 10. LDO Dropout Voltage vs Load Current
Figure 9. Headphone SNR and SE Output Power vs Output
Common Mode Setting
40
2.5
2.48
20
MicBIAS Voltage - mV
Change In Output Voltage - mV
30
10
0
-10
2.46
2.44
-20
2.42
-30
2.4
-40
0
10
20
Load - mA
30
40
Figure 11. LDO Load Response
14
50
0
0.5
1
1.5
2
MicBIAS Load - mA
2.5
3
Figure 12. MICBIAS Mode 2, CM = 0.9 V, LDOIN OP Stage vs
MICBIAS Load Current
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6.15.1 Typical Characteristics, FFT
20
0
DAC
0
-20
-20
-40
Power - dBr
Power - dBr
-40
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
0
5000
10000
f - Frequency - Hz
15000
20000
Figure 13. DAC to Headphone FFT at -3 dBFS
0
5000
10000
f - Frequency - Hz
15000
20000
Figure 14. Analog Bypass to Headphone FFT at -3 dB
Below 0.5 Vrms
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7 Detailed Description
7.1 Overview
Combined with the advanced PowerTune technology, the device can cover operations from 8kHz mono voice
playback to stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony
applications.
The playback path offers signal processing blocks for filtering and effects, true differential output signal, flexible
mixing of DAC and analog input signals as well as programmable volume controls. The TLV320DAC3203
contains two high-power output drivers which can be configured in multiple ways, including stereo and mono
BTL. The integrated PowerTune technology allows the device to be tuned to just the right power-performance
trade-off. Mobile applications frequently have multiple use cases requiring very low-power operation while being
used in a mobile environment. When used in a docked environment, power consumption typically is less of a
concern and lowest possible noise is more important. With PowerTune the TLV320DAC3203 can address both
cases.
The voltage supply range for the TLV320DAC3203 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To
ease system-level design, a low-dropout regulator (LDO) is integrated to generate the appropriate analog supply
from input voltages ranging from 1.8V to 3.6V. Digital I/O voltages are supported in the range of 1.1V–3.6V.
The required internal clock of the TLV320DAC3203 can be derived from multiple sources, including the MCLK,
BCLK, GPIO pins or the output of internal PLL, where the input to the PLL again can be derived from the MCLK,
BCLK or GPIO pins. Although using the internal, fractional PLL ensures the availability of a suitable clock signal,
it is not recommended for the lowest power settings. The PLL is highly programmable and can accept available
input clocks in the range of 512kHz to 50MHz.
7.2 Functional Block Diagram
INL
DRC
Vol. Ctrl
-6...+29dB
MFP3/SCLK
MFP4/MISO
Data Interface
Dig Mic
Interface
Left
DAC
Dig Mic
Signal
Proc.
HPL
1dB steps
DAC Signal Proc.
-6...+29dB
Right
DAC
HPR
1dB steps
DRC
Vol. Ctrl
INR
ALDO
LDOin
AVdd
SPI_Select
PLL
Interrupt Secondary
Ctrl
I2S IF
Primary
I2S Interface
IOVdd
Jack
detect
Pin Muxing / Clock Routing
Ref
Supplies
Reset
SPI / I2C
Control Block
DVdd
IOVss
DVss
AVss
Ref
Micbias
WCLK
BCLK
DIN/MFP1
DOUT/MFP2
MCLK
GPIO
(WCSP Only)
SDA/MOSI
SCL/SSZ
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7.3 Feature Description
7.3.1 Device Connections
7.3.1.1 Digital Pins
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a
default function, and also can be reprogrammed to cover alternative functions for various applications.
The fixed-function pins are Reset and the SPI_Select pin, which are HW control pins. Depending on the state of
SPI_Select, the two control-bus pins SCL/SS and SDA/MOSI are configured for either I2C or SPI protocol.
Other digital IO pins can be configured for various functions via register control. An overview of available
functionality is given in Multifunction Pins.
7.3.1.1.1 Multifunction Pins
Table 1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
Table 1. Multifunction Pin Assignments
Pin Function
A
1
2
3
4
5
6
7
8
MCLK
BCLK
WCLK
DIN
MFP1
DOUT
MFP2
MFP3/
SCLK
MFP4/
MISO
GPIO
MFP5
S (1)
S (2)
PLL Input
B
Codec Clock Input
C
I2S BCLK input
S
2
D
I S BCLK output
2
E
I S WCLK input
F
I2S WCLK output
(1)
,D
(4)
S
S (3)
E
(2)
S (3)
S,D
E (5)
E, D
E
2
G
I S ADC word clock input
H
I2S ADC WCLK out
E
E
I
I2S DIN
J
I2S DOUT
K
General Purpose Output I
K
General Purpose Output II
K
General Purpose Output III
L
General Purpose Input I
L
General Purpose Input II
L
General Purpose Input III
M
INT1 output
E
E
E
N
INT2 output
E
E
E
Q
Secondary I2S BCLK input
E
E
E, D
E, D
E
E
E
E
E
E
2
E
E
E
R
Secondary I S WCLK in
E
S
Secondary I2S DIN
E
T
Secondary I2S DOUT
U
Secondary I2S BCLK OUT
E
E
2
E
E
E
V
Secondary I S WCLK OUT
E
E
E
X
Aux Clock Output
E
E
E
(1)
(2)
(3)
(4)
(5)
S(1):
S(2):
(3)
The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.
The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.
S : The GPIO/MFP5 pin can drive the PLL and Codec Clock inputs simultaneously.
D: Default Function
E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/MFP5 has been
allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)
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7.3.1.2 Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are
powered down by default. The blocks can be powered up with fine granularity according to the application needs.
7.3.2 Analog Audio I/O
The analog I/O path of the TLV320DAC3203 offers a variety of options for signal conditioning and routing:
• 2 headphone amplifier outputs
• Analog gain setting
• Single ended and differential modes
7.3.2.1 Analog Low Power Bypass
The TLV320DAC3203 offers an analog-bypass mode. An analog signal can be routed from the analog input pin
to the output amplifier. Neither the digital-input processing blocks nor the DAC resources are required for such
operation; this supports low-power operation during analog-bypass mode.
In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs INL to the left
headphone amplifier (HPL) and INR to HPR.
7.3.2.2 Headphone Outputs
The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ω in singleended AC-coupled headphone configurations, or loads down to 32Ω in differential mode, where a speaker is
connected between HPL and HPR. In single-ended drive configuration these drivers can drive up to 15mW
power into each headphone channel while operating from 1.8V analog supplies. While running from the AVdd
supply, the output common-mode of the headphone driver is set by the common-mode setting of analog inputs to
allow maximum utilization of the analog supply range while simultaneously providing a higher output-voltage
swing. In cases when higher output-voltage swing is required, the headphone amplifiers can run directly from the
higher supply voltage on LDOIN input (up to 3.6V). To use the higher supply voltage for higher output signal
swing, the output common-mode can be adjusted to either 1.25V, 1.5V or 1.65V. When the common-mode
voltage is configured at 1.65V and LDOIN supply is 3.3V, the headphones can each deliver up to 40mW power
into a 16Ω load.
The headphone drivers are capable of driving a mixed combination of DAC signal and bypass from analog input
INL and INR. The analog input signals can be attenuated up to 72dB before routing. The level of the DAC signal
can be controlled using the digital volume control of the DAC. To control the output-voltage swing of headphone
drivers, the digital volume control provides a range of –6.0dB to +29.0dB (1) in steps of 1dB. These level controls
are not meant to be used as dynamic volume control, but more to set output levels during initial device
configuration. Refer to for recommendations for using headphone volume control for achieving 0dB gain through
the DAC channel with various configurations.
7.3.3 Digital Microphone Inteface
The TLV320DAC3203 includes a stereo decimation filter for digital microphone inputs. The stereo recording path
can be powered up one channel at a time, to support the case where only mono record capability is required.
The digital microphone input path of the TLV320DAC3203 features a large set of options for signal conditioning
as well as signal routing:
• Stereo decimation filters (PDM input)
• Fine gain adjustment of digital channels with 0.1dB step size
• Digital volume control with a range of -12 to +20dB
• Mute function
In addition to the standard set of stereo decimation filter features the TLV320DAC3203 also offers the following
special functions:
• Channel-to-channel phase adjustment
• Adaptive filter mode
(1)
18
If the device must be placed into 'mute' from the –6.0dB setting, set the device at a gain of –5.0dB first, then place the device into mute.
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7.3.3.1 ADC Processing Blocks — Overview
The TLV320DAC3203 includes a built-in digital decimation filter to process the oversampled data from the PDM
input to generate digital data at Nyquist sampling rate with high dynamic range. The decimation filter can be
chosen from three different types, depending on the required frequency response, group delay and sampling
rate.
7.3.3.1.1
Processing Blocks
The TLV320DAC3203 offers a range of processing blocks which implement various signal processing capabilities
along with decimation filtering. These processing blocks give users the choice of how much and what type of
signal processing they may use and which decimation filter is applied.
Table 2 gives an overview of the available processing blocks and their properties.
The signal processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
• Variable-tap FIR filter
The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first order IIR, BiQuad and FIR filters have fully user-programmable coefficients. The Resource Class Column
(RC) gives an approximate indication of power consumption.
Table 2. Processing Blocks
Processing
Blocks
Channel
Decimation
Filter
1st Order
IIR Available
Number
BiQuads
FIR
Required
AOSR Value
Resource
Class
PRB_R1 (1)
Stereo
A
Yes
0
No
128,64
6
PRB_R2
Stereo
A
Yes
5
No
128,64
8
PRB_R3
Stereo
A
Yes
0
25-Tap
128,64
8
PRB_R4
Right
A
Yes
0
No
128,64
3
PRB_R5
Right
A
Yes
5
No
128,64
4
PRB_R6
Right
A
Yes
0
25-Tap
128,64
4
PRB_R7
Stereo
B
Yes
0
No
64
3
PRB_R8
Stereo
B
Yes
3
No
64
4
PRB_R9
Stereo
B
Yes
0
20-Tap
64
4
PRB_R10
Right
B
Yes
0
No
64
2
PRB_R11
Right
B
Yes
3
No
64
2
PRB_R12
Right
B
Yes
0
20-Tap
64
2
PRB_R13
Stereo
C
Yes
0
No
32
3
PRB_R14
Stereo
C
Yes
5
No
32
4
PRB_R15
Stereo
C
Yes
0
25-Tap
32
4
PRB_R16
Right
C
Yes
0
No
32
2
PRB_R17
Right
C
Yes
5
No
32
2
PRB_R18
Right
C
Yes
0
25-Tap
32
2
(1)
Default
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For more detailed information see the TLV320DAC3203 Application Reference Guide
7.3.4 DAC
The TLV320DAC3203 includes a stereo audio DAC supporting data rates from 8kHz to 192kHz. Each channel of
the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation
filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide
enhanced performance at low sampling rates through increased oversampling and image filtering, thereby
keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed
within the audio band to beyond 20kHz. To handle multiple input rates and optimize performance, the
TLV320DAC3203 allows the system designer to program the oversampling rates over a wide range from 1 to
1024. The system designer can choose higher oversampling ratios for lower input data rates and lower
oversampling ratios for higher input data rates.
The TLV320DAC3203 DAC channel includes a built-in digital interpolation filter to generate oversampled data for
the sigma-delta modulator. The interpolation filter can be chosen from three different types depending on
required frequency response, group delay and sampling rate.
The DAC path of the TLV320DAC3203 features many options for signal conditioning and signal routing:
• Digital volume control with a range of -63.5 to +24dB
• Mute function
• Dynamic range compression (DRC)
In addition to the standard set of DAC features the TLV320DAC3203 also offers the following special features:
• Built in sine wave generation (beep generator)
• Digital auto mute
• Adaptive filter mode
7.3.4.1 DAC Processing Blocks — Overview
The TLV320DAC3203 implements signal processing capabilities and interpolation filtering via processing blocks.
These fixed processing blocks give users the choice of how much and what type of signal processing they may
use and which interpolation filter is applied.
Table 3 gives an overview over all available processing blocks of the DAC channel and their properties.
The signal processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
• 3D – Effect
• Beep Generator
The processing blocks are tuned for typical cases and can achieve high image rejection or low group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first-order IIR and biquad filters have fully user-programmable coefficients. The Resource Class Column (RC)
gives an approximate indication of power consumption.
Table 3. Overview – DAC Predefined Processing Blocks
(1)
20
Processing
Block No.
Interpolation
Filter
Channel
1st Order
IIR Available
Num. of
Biquads
DRC
3D
Beep
Generator
PRB_P1 (1)
A
PRB_P2
A
Stereo
No
Stereo
Yes
PRB_P3
PRB_P4
A
Stereo
A
Left
PRB_P5
A
PRB_P6
PRB_P7
PRB_P8
Resource
Class
3
No
No
No
8
6
Yes
No
No
12
Yes
6
No
No
No
10
No
3
No
No
No
4
Left
Yes
6
Yes
No
No
6
A
Left
Yes
6
No
No
No
6
B
Stereo
Yes
0
No
No
No
6
B
Stereo
No
4
Yes
No
No
8
Default
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Table 3. Overview – DAC Predefined Processing Blocks (continued)
Processing
Block No.
Interpolation
Filter
Channel
1st Order
IIR Available
Num. of
Biquads
DRC
3D
Beep
Generator
Resource
Class
PRB_P9
B
Stereo
No
4
No
No
No
8
PRB_P10
B
Stereo
Yes
6
Yes
No
No
10
PRB_P11
B
Stereo
Yes
6
No
No
No
8
PRB_P12
B
Left
Yes
0
No
No
No
3
PRB_P13
B
Left
No
4
Yes
No
No
4
PRB_P14
B
Left
No
4
No
No
No
4
PRB_P15
B
Left
Yes
6
Yes
No
No
6
PRB_P16
B
Left
Yes
6
No
No
No
4
PRB_P17
C
Stereo
Yes
0
No
No
No
3
PRB_P18
C
Stereo
Yes
4
Yes
No
No
6
PRB_P19
C
Stereo
Yes
4
No
No
No
4
PRB_P20
C
Left
Yes
0
No
No
No
2
PRB_P21
C
Left
Yes
4
Yes
No
No
3
PRB_P22
C
Left
Yes
4
No
No
No
2
PRB_P23
A
Stereo
No
2
No
Yes
No
8
PRB_P24
A
Stereo
Yes
5
Yes
Yes
No
12
PRB_P25
A
Stereo
Yes
5
Yes
Yes
Yes
12
For more detailed information see the TLV320DAC3203 Application Reference Guide.
7.3.5 Powertune
The TLV320DAC3203 features PowerTune, a mechanism to balance power-versus-performance trade-offs at the
time of device configuration. The device can be tuned to minimize power dissipation, to maximize performance,
or to an operating point between the two extremes to best fit the application.
For more detailed information see the TLV320DAC3203 Application Reference Guide.
7.3.6 Digital Audio I/O Interface
Audio data is transferred between the host processor and the TLV320DAC3203 via the digital audio data serial
interface, or audio bus. The audio bus on this device is very flexible, including left or right-justified data options,
support for I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation,
very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple
devices within a system directly.
The audio bus of the TLV320DAC3203 can be configured for left or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard PCM interfaces is supported within the TDM mode. These modes
are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Page 0, Register 27,
D(5:4). In addition, the word clock and bit clock can be independently configured in either Master or Slave mode,
for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a
frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock
corresponds to the DAC sampling frequency.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0,
Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate various wordlengths as well as to support the case when multiple TLV320DAC3203s may share the same audio bus.
The TLV320DAC3203 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in Page 0,
Register 28.
The TLV320DAC3203 also has the feature of inverting the polarity of the bit-clock used for transferring the audio
data as compared to the default clock polarity used. This feature can be used independently of the mode of
audio interface chosen. This can be configured via Page 0, Register 29, D(3).
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The TLV320DAC3203 includes the programmability to program at what bit clock in a frame does audio data
begin. This enables time-division multiplexing (TDM), enabling use of multiple codecs on a single audio bus.
When the audio serial data bus is powered down while configured in master mode, the pins associated with the
interface are put into a hi-Z output condition.
By default when the word-clocks and bit-clocks are generated by the TLV320DAC3203, these clocks are active
only when the DAC is powered up within the device. This is done to save power. However, it also supports a
feature when both the word clocks and bit-clocks can be active even when the DAC in the device is powered
down. This is useful when using the TDM mode with multiple codecs on the same bus, or when word-clock or bitclocks are used in the system as general-purpose clocks.
7.3.7 Clock Generation and PLL
The TLV320DAC3203 supports a wide range of options for generating clocks for the DAC as well as interface
and other control blocks. The clocks for the DAC require a source reference clock. This clock can be provided on
a variety of device pins such as MCLK, BCLK, or GPIO pins. The CODEC_CLKIN can then be routed through
highly-flexible clock dividers to generate the various clocks required for the DAC sections. In the event that the
desired audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO, the
TLV320DAC3203 also provides the option of using the on-chip PLL, which supports a wide range of fractional
multiplication values to generate the required clocks. Starting from CODEC_CLKIN the TLV320DAC3203
provides several programmable clock dividers to help achieve a variety of sampling rates for the DAC.
For more detailed information see the TLV320DAC3203 Application Reference Guide.
7.3.8 Control Interfaces
The TLV320DAC3203 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I2C, SPI_SELECT should be tied low.
Changing the state of SPI_SELECT during device operation is not recommended.
7.3.8.1 I2C Control
The TLV320DAC3203 supports the I2C control protocol, and will respond to the I2C address of 0011000. I2C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus
only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the
bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW.
This circuit prevents two devices from conflicting; if two devices drive the bus simultaneously, there is no driver
contention.
7.3.8.2 SPI Control
In the SPI control mode, the TLV320DAC3203 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO,
SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit
CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the
TLV320DAC3203) depend on a master to start and synchronize transmissions. A transmission begins when
initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the
control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on
the MISO pin to the master shift register.
For more detailed information see the TLV320DAC3203 Application Reference Guide.
7.4 Device Functional Modes
The following special functions are available to support advanced system requirements:
• Headset detection
• Interrupt generation
• Flexible pin multiplexing
For more detailed information see the TLV320DAC3203 Application Reference Guide.
22
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7.5 Register Maps
Table 4. Summary of Register Map
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
0
0x00
0x00
Page Select Register
0
1
0x00
0x01
Software Reset Register
0
2
0x00
0x02
Reserved Register
0
3
0x00
0x03
Reserved Register
0
4
0x00
0x04
Clock Setting Register 1, Multiplexers
0
5
0x00
0x05
Clock Setting Register 2, PLL P&R Values
0
6
0x00
0x06
Clock Setting Register 3, PLL J Values
0
7
0x00
0x07
Clock Setting Register 4, PLL D Values (MSB)
0
8
0x00
0x08
Clock Setting Register 5, PLL D Values (LSB)
0
9-10
0x00
0x09-0x0A
Reserved Register
0
11
0x00
0x0B
Clock Setting Register 6, NDAC Values
0
12
0x00
0x0C
Clock Setting Register 7, MDAC Values
0
13
0x00
0x0D
DAC OSR Setting Register 1, MSB Value
0
14
0x00
0x0E
DAC OSR Setting Register 2, LSB Value
0
15-17
0x00
0x0F-0x11
Reserved Register
0
18
0x00
0x12
Clock Setting Register 8, NADC Values
0
19
0x00
0x13
Clock Setting Register 9, MADC Values
0
20-24
0x00
0x14-0x18
Reserved Register
0
25
0x00
0x19
Clock Setting Register 10, Multiplexers
0
26
0x00
0x1A
Clock Setting Register 11, CLKOUT M divider value
0
27
0x00
0x1B
Audio Interface Setting Register 1
0
28
0x00
0x1C
Audio Interface Setting Register 2, Data offset setting
0
29
0x00
0x1D
Audio Interface Setting Register 3
0
30
0x00
0x1E
Clock Setting Register 12, BCLK N Divider
0
31
0x00
0x1F
Audio Interface Setting Register 4, Secondary Audio Interface
0
32
0x00
0x20
Audio Interface Setting Register 5
0
33
0x00
0x21
Audio Interface Setting Register 6
0
34
0x00
0x22
Digital Interface Misc. Setting Register
0
35-36
0x00
0x23-0x24
Reserved Register
0
37
0x00
0x25
DAC Flag Register 1
0
38
0x00
0x26
DAC Flag Register 2
0
39-41
0x00
0x27-0x29
Reserved Register
0
42
0x00
0x2A
Sticky Flag Register 1
0
43
0x00
0x2B
Interrupt Flag Register 1
0
44
0x00
0x2C
Sticky Flag Register 2
0
45
0x00
0x2D
Sticky Flag Register 3
0
46
0x00
0x2E
Interrupt Flag Register 2
0
47
0x00
0x2F
Interrupt Flag Register 3
0
48
0x00
0x30
INT1 Interrupt Control Register
0
49
0x00
0x31
INT2 Interrupt Control Register
0
50-51
0x00
0x32-0x33
Reserved Register
0
52
0x00
0x34
GPIO/MFP5 Control Register (YZK Package only)
0
53
0x00
0x35
MFP2 Function Control Register
0
54
0x00
0x36
DIN/MFP1 Function Control Register
0
55
0x00
0x37
MISO/MFP4 Function Control Register
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Register Maps (continued)
Table 4. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
0
56
0x00
0x38
SCLK/MFP3 Function Control Register
0
57-59
0x00
0x39-0x3B
Reserved Registers
0
60
0x00
0x3C
DAC Signal Processing Block Control Register
0
61-62
0x00
0x3D-0x3E
Reserved Register
0
63
0x00
0x3F
DAC Channel Setup Register 1
0
64
0x00
0x40
DAC Channel Setup Register 2
0
65
0x00
0x41
Left DAC Channel Digital Volume Control Register
0
66
0x00
0x42
Right DAC Channel Digital Volume Control Register
0
67
0x00
0x43
Headset Detection Configuration Register
0
68
0x00
0x44
DRC Control Register 1
0
69
0x00
0x45
DRC Control Register 2
0
70
0x00
0x46
DRC Control Register 3
0
71
0x00
0x47
Beep Generator Register 1
0
72
0x00
0x48
Beep Generator Register 2
0
73
0x00
0x49
Beep Generator Register 3
0
74
0x00
0x4A
Beep Generator Register 4
0
75
0x00
0x4B
Beep Generator Register 5
0
76
0x00
0x4C
Beep Generator Register 6
0
77
0x00
0x4D
Beep Generator Register 7
0
78
0x00
0x4E
Beep Generator Register 8
0
79
0x00
0x4F
Beep Generator Register 9
0
80-127
0x00
0x50-0x7F
Reserved Register
1
0
0x01
0x00
Page Select Register
1
1
0x01
0x01
Power Configuration Register
1
2
0x01
0x02
LDO Control Register
1
3
0x01
0x03
Playback Configuration Register 1
1
4
0x01
0x04
Playback Configuration Register 2
1
5-8
0x01
0x05-0x08
Reserved Register
1
9
0x01
0x09
Output Driver Power Control Register
1
10
0x01
0x0A
Common Mode Control Register
1
11
0x01
0x0B
Over Current Protection Configuration Register
1
12
0x01
0x0C
HPL Routing Selection Register
1
13
0x01
0x0D
HPR Routing Selection Register
1
14-15
0x01
0x0E-0x0F
Reserved Register
1
16
0x01
0x10
HPL Driver Gain Setting Register
1
17
0x01
0x11
HPR Driver Gain Setting Register
1
18-19
0x01
0x12-0x13
Reserved Register
1
20
0x01
0x14
Headphone Driver Startup Control Register
1
21
0x01
0x15
Reserved Register
1
22
0x01
0x16
INL to HPL Volume Control Register
1
23
0x01
0x17
INR to HPR Volume Control Register
1
24-50
0x01
0x18-0x32
Reserved Register
1
51
0x01
0x33
MICBIAS Configuration Register
1
52-57
0x01
0x34-0x39
Reserved Register
1
58
0x01
0x3A
Analog Input Settings
24
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Register Maps (continued)
Table 4. Summary of Register Map (continued)
Decimal
Hex
DESCRIPTION
PAGE NO.
REG. NO.
PAGE NO.
REG. NO.
1
59-62
0x01
0x3B-0x3E
Reserved Register
1
63
0x01
0x3F
DAC Analog Gain Control Flag Register
1
64-122
0x01
0x40-0x7A
Reserved Register
1
123
0x01
0x7B
Reference Power-up Configuration Register
1
124
0x01
0x7C
Reserved Register
1
125
0x01
0x7D
Offset Callibration Register
1
126-127
0x01
0x7E-0x7F
Reserved Register
8
0-127
0x08
0x00-0x7F
Reserved Register
9-16
0-127
0x09-0x10
0x00-0x7F
Reserved Register
26-34
0-127
0x1A-0x22
0x00-0x7F
Reserved Register
44
0
0x2C
0x00
Page Select Register
44
1
0x2C
0x01
DAC Adaptive Filter Configuration Register
44
2-7
0x2C
0x02-0x07
Reserved
44
8-127
0x2C
0x08-0x7F
DAC Coefficients Buffer-A C(0:29)
45-52
0
0x2D-0x34
0x00
Page Select Register
45-52
1-7
0x2D-0x34
0x01-0x07
Reserved.
45-52
8-127
0x2D-0x34
0x08-0x7F
DAC Coefficients Buffer-A C(30:255)
62-70
0
0x3E-0x46
0x00
Page Select Register
62-70
1-7
0x3E-0x46
0x01-0x07
Reserved.
62-70
8-127
0x3E-0x46
0x08-0x7F
DAC Coefficients Buffer-B C(0:255)
80-114
0-127
0x50-0x72
0x00-0x7F
Reserved Register
152-186
0-127
0x98-0xBA
0x00-0x7F
Reserved Register
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV320DAC3203 offers a wide range of configuration options. shows the basic functional blocks of the
device.
8.2 Typical Application
Host Processor
Reset
MCLK
BCLK
WCLK DIN/MFP1 DOUT/MFP2
SDA
SCL
47uF Headset_Spkr_R
HPR
GPIO
(WCSP Package Only)
Headset_Spkr_L
HPL
47uF Headset_Gnd
headset
speakers
jack
SPI_Select
TLV320DAC3203
0.1uF
1.8V
INR
Aux Input
eg. FM Tuner 0.1uF
LDOIN
INL
AVDD
0.1uF
1uF
Vmic
MICBIAS
VDD
CLK
DATA
L/R
GND
MFP3
DVDD
0.1uF
10uF
MFP4
IOVDD
Vmic
AVSS
DVSS
IOVSS
VDD
CLK
DATA
L/R
GND
REF
1 uF
Copyright © 2017, Texas Instruments Incorporated
Figure 15. Typical Circuit Configuration
8.2.1 Design Requirements
For this design example, us the parameters in Table 5.
Table 5. Design Parameters
26
PARAMETER
EXAMPLE VALUE
Audio input
Digital Audio (I2S), Analog Audio INx
Speaker
Single-Ended 16-Ω Differential 32-Ω
Internal LDO
Enabled
Control interface
I2C
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8.2.2 Detailed Design Procedure
In this application, the device is able to use both digital and analog inputs, routing this signal into the headphone
outputs.
The internal LDO is being used in this application. External 1.8-V supply is used to power LDOIN, DVDD and
IOVDD. AVDD is internally supplied by the LDO.
Decoupling capacitors should be used at all the supply lines. TI recommends using 0.1-µF and 10-µF capacitors
for a better system performance.
Decoupling series capacitors must be used at the analog input and headphone output. The headphone output
can be connected in single-ended mode with DC offset voltage while the decoupling series capacitor protects the
speaker form the DC voltage. In addition the headphone output can be connected in a mono differential mode.
All grounds are tied together; route analog and digital paths are separated to avoid interference.
8.2.3 Application Curves
0
0
CM=0.9 V,
RL = 16 W
Load = 32 W BTL
CM=1.65 V,
RL = 32 W
-10
THD - Total Harmonic Distortion - dB
THD - Total Harmonic Distortion - dB
CM=0.9 V,
-10 RL = 32 W
-20
-30
CM=1.65 V,
RL = 16 W
-40
-50
-60
-70
-20
CM=1.5 V
-30
CM=1.65 V
-40
-50
-60
-70
-80
-80
-90
-90
0
20
40
60
80
Headphone Output Power - mW
100
Figure 16. Total Harmonic Distortion vs Headphone Output
Power
0
50
100
150
Headphone output Power - mW
200
Figure 17. Total Harmonic Distortion vs Headphone Output
Power
9 Power Supply Recommendations
Device power consumption largely depends on PowerTune configuration. For information on device power
consumption, see the TLV320DAC3203 Application Reference Guide.
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10 Layout
10.1 Layout Guidelines
If the analog inputs are:
• Used, analog input traces must be routed symmetrically for true differential performance.
• Used, do not run analog input traces parallel to digital lines.
• Used, they must be AC-coupled.
• Not used, they must be grounded through a capacitor.
Use a ground plane with multiple vias for each terminal to create a low-impedance connection to GND for
minimum ground noise.
Use supply decoupling capacitors and place them as close as possible to the device.
10.2 Layout Example
Figure 18. Layout Example
28
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• TLV320DAC3203 Application Reference Guide
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerTune, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV320DAC3203IRGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
DAC
3203I
TLV320DAC3203IRGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
DAC
3203I
TLV320DAC3203IYZKR
ACTIVE
DSBGA
YZK
25
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
DAC3203I
TLV320DAC3203IYZKT
ACTIVE
DSBGA
YZK
25
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
DAC3203I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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