TLV4113CDR




      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 D D D D D D D D Operational Amplifier High Output Drive . . . >300 mA Rail-To-Rail Output Unity-Gain Bandwidth . . . 2.7 MHz Slew Rate . . . 1.5 V/µs Supply Current . . . 700 µA/Per Channel Supply Voltage Range . . . 2.5 V to 6 V Specified Temperature Range: − TA = 0°C to 70°C . . . Commercial Grade − TA = −40°C to 125°C . . . Industrial Grade Universal OpAmp EVM + − TLV4112 D, DGN, OR P PACKAGE (TOP VIEW) 1OUT 1IN − 1IN + GND description 1 8 2 7 3 6 4 5 VDD 2OUT 2IN − 2IN+ The TLV411x single supply operational amplifiers provide output currents in excess of 300 mA at 5 V. This enables standard pin-out amplifiers to be used as high current buffers or in coil driver applications. The TLV4110 and TLV4113 come with a shutdown feature. The TLV411x is available in the ultra small MSOP PowerPAD package, which offers the exceptional thermal impedance required for amplifiers delivering high current levels. All TLV411x devices are offered in PDIP, SOIC (single and dual) and MSOP PowerPAD (dual). FAMILY PACKAGE TABLE PACKAGE TYPES NUMBER OF CHANNELS MSOP PDIP SOIC TLV4110 1 8 8 8 Yes TLV4111 1 8 8 8 — TLV4112 2 8 8 8 — TLV4113 2 10 14 14 Yes DEVICE SHUTDOWN HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT Refer to the EVM Selection Guide (Lit# SLOU060) LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3.0 1.0 2.9 VOL − Low-Level Output Voltage − V V OH − High-Level Output Voltage − V UNIVERSAL EVM BOARD VDD = 3 V 2.8 2.7 TA = 125°C TA = −40°C 2.6 2.5 TA = 0°C 2.4 TA = 25°C 2.3 TA = 70°C 2.2 2.1 2.0 0 50 100 150 200 250 300 IOH − High-Level Output Current − mA VDD = 3 V 0.9 0.8 TA = 70°C 0.7 TA = 25°C TA = 0°C TA = −40°C TA = 125°C 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 50 100 150 200 250 300 IOL − Low-Level Output Current − mA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright  1999−2006, Texas Instruments Incorporated 
 
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 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 TLV4110 AND TLV4111 AVAILABLE OPTIONS PACKAGED DEVICES MSOP TA SMALL OUTLINE (D)†‡ 0°C to 70°C −40°C to 125°C SMALL OUTLINE (DGN)† SYMBOL PLASTIC DIP (P) TLV4110CD TLV4110CDGN xxTIAHL TLV4110CP TLV4111CD TLV4111CDGN xxTIAHN TLV4111CP TLV4110ID TLV4110IDGN xxTIAHM TLV4110IP TLV4111ID TLV4111IDGN xxTIAHO TLV4111IP † This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV4110CDR). ‡ In the SOIC package, the maximum RMS output power is thermally limited to 350 mW; 700 mW peaks can be driven, as long as the RMS value is less than 350 mW. TLV4112 AND TLV4113 AVAILABLE OPTIONS PACKAGED DEVICES MSOP TA SMALL OUTLINE (D)†‡ TLV4112CD 0°C to 70°C PLASTIC DIP (P) SMALL OUTLINE (DGN)† SYMBOL SMALL OUTLINE (DGQ)† SYMBOL TLV4112DGN xxTIAHP — — TLV4112CP TLV4113CD — — TLV4113CDGQ xxTIAHR TLV4113CN TLV4112ID TLV4112IDGN xxTIAHQ — — TLV4112IP −40°C to 125°C TLV4113ID — — TLV4113IDGQ xxTIAHS TLV4113IN † This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV4112CDR). ‡ In the SOIC package, the maximum RMS output power is thermally limited to 350 mW; 700 mW peaks can be driven, as long as the RMS value is less than 350 mW. TLV411x PACKAGE PIN OUTS TLV4110 D, DGN OR P PACKAGE (TOP VIEW) NC IN − IN + GND 1 8 2 7 3 6 4 5 TLV4111 D, DGN OR P PACKAGE (TOP VIEW) SHDN VDD OUT NC NC IN − IN + GND 1 8 2 7 3 6 4 5 NC VDD OUT NC 1 2 3 4 5 10 9 8 7 6 1OUT 1IN − 1IN + GND 8 2 7 3 6 4 5 (TOP VIEW) VDD+ 2OUT 2IN − 2IN+ 2SHDN 1OUT 1IN − 1IN+ GND NC 1SHDN NC NC − No internal connection 2 1 TLV4113 D OR N PACKAGE TLV4113 DGQ PACKAGE (TOP VIEW) 1OUT 1IN − 1IN+ GND 1SHDN TLV4112 D, DGN, OR P PACKAGE (TOP VIEW) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VDD 2OUT 2IN − 2IN+ NC 2SHDN NC VDD 2OUT 2IN − 2IN+ 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD Output current, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mA Continuous /RMS output current, IO (each output of amplifier): TJ ≤ 105°C . . . . . . . . . . . . . . . . . . . . 350 mA TJ ≤ 150°C . . . . . . . . . . . . . . . . . . . . 110 mA Peak output current, IO (each output of amplifier: TJ ≤ 105°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA TJ ≤ 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to GND. 2. To prevent permanent damage the die temperature must not exceed the maximum junction temperature. DISSIPATION RATING TABLE PACKAGE θJC (°C/W) θJA (°C/W) TA ≤ 25°C POWER RATING TA = 125°C POWER RATING D (8) 38.3 176 710 mW 142 mW D (14) 26.9 122.3 1022 mW 204.4 mW DGN (8)‡ DGQ (10)‡ 4.7 52.7 2.37 W 474.4 mW 4.7 52.3 2.39 W 478 mW P (8) 41 104 1200 mW 240.4 mW N (14) 32 78 1600 mW 320.5 mW ‡ See The Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report (literature number SLMA002), for more information on the PowerPAD package. The thermal data was measured on a PCB layout based on the information in the section entitled Texas Instruments Recommended Board for PowerPAD on page 33 of the before mentioned document. recommended operating conditions Supply voltage, VDD Common-mode input voltage range, VICR C-suffix Operating free-air temperature, TA I-suffix V(on) VDD = 3 V VDD = 5 V V(off) VDD = 3 V VDD = 5 V Shutdown turn-on/off voltage level§ MIN MAX 2.5 6 UNIT V 0 V 0 VDD−1.5 70 −40 125 °C 2.1 3.8 0.9 V 1.65 § Relative to GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 electrical characteristics at recommend operating conditions, VDD = 3 V and 5 V (unless otherwise noted) dc performance PARAMETER VIO Input offset voltage αVIO Offset voltage draft CMRR Common-mode rejection ratio TEST CONDITIONS MIN TYP MAX 175 3500 VIC = VDD/2, RL = 100 Ω, VO = VDD/2 , RS = 50 Ω 25°C 3 VDD = 3 V, RS = 50 Ω VIC = 0 to 2 V, 25°C 63 VDD = 5 V, RS = 50 Ω VIC = 0 to 4 V, 25°C 68 VDD = 3 V, VO(PP)=0 to 1V AVD TA† 25°C Large-signal differential voltage amplification VDD = 5 V, VO(PP)=0 to 3V Full range 4000 25°C 78 Full range 67 25°C 85 RL=10 kΩ Full range 75 25°C 88 Full range 75 25°C 90 Full range 85 RL=10 kΩ µV V µV/°C dB RL=100 Ω RL=100 Ω UNITS 84 100 dB 94 110 † Full range is 0°C to 70°C for C suffix and − 40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C. input characteristics PARAMETER IIO Input offset current TEST CONDITIONS VIC = VDD/2 TA† 25°C MIN Input bias current ri(d) Differential input resistance • DALLAS, TEXAS 75265 50 pA 100 Full range 25°C POST OFFICE BOX 655303 250 0.3 TLV411xC TLV411xI UNITS 50 CIC Common-mode input capacitance f = 100 Hz 25°C † Full range is 0°C to 70°C for C suffix and − 40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C. 4 25 Full range 25°C IIB MAX 0.3 TLV411xC TLV411xI VO = VDD/2, RS = 50 Ω TYP 500 1000 GΩ 5 pF 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 electrical characteristics at specified free-air temperature, VDD = 3 V and 5 V (unless otherwise noted) (continued) output characteristics PARAMETER TEST CONDITIONS IOH = −10 mA VDD = 3 V, VIC = VDD/2 IOH =−100 mA VOH IOH = −10 mA High-level output voltage VDD = 5 V, VIC = VDD/2 IOH = −100 mA IOH = −200 mA TA† 25°C MIN TYP 2.7 2.97 Full range 2.7 25°C 2.6 Full range 2.6 25°C 4.7 Full range 4.7 25°C 4.6 Full range 4.6 25°C 4.45 −40°C to 85°C 4.35 25°C VDD = 3 V and 5 V, VIC = VDD/2 VOL IOL = 10 mA Full range IOL = 100 mA Full range IO Output current‡ IOS Short-circuit output current‡ IOL = 200 mA Measured at 0.5 V from rail VDD = 3 V VDD = 5 V 4.96 4.76 V 4.6 0.1 0.1 0.33 0.4 0.55 25°C VDD = 5 V, VIC = VDD/2 UNITS V 2.73 0.03 25°C Low-level output voltage MAX 0.38 −40°C to 85°C V 0.6 0.7 ±220 25°C mA ±320 Sourcing 800 25°C Sinking mA 800 † Full range is 0°C to 70°C for C suffix and − 40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C. ‡ When driving output currents in excess of 200 mA, the MSOP PowerPAD package is required for thermal dissipation. power supply PARAMETER IDD PSRR TEST CONDITIONS Supply current (per channel) VO = VDD/2 Power supply rejection ratio (∆VDD / ∆VIO) TA 25°C MIN TYP MAX 700 1000 Full range VDD =2.7 to 3.3 V, VIC = VDD/2 V No load, VDD =4.5 to 5.5 V, VIC = VDD/2 V No load, 1500 25°C 70 Full range 65 25°C 70 UNITS µA A 82 79 dB Full range 65 † Full range is 0°C to 70°C for C suffix and − 40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 electrical characteristics at specified free-air temperature, VDD = 3 V and 5 V (unless otherwise noted) (continued) dynamic performance PARAMETER GBWP SR φM Gain bandwidth product Slew rate at unity gain Phase margin TEST CONDITIONS RL=100 Ω CL=10 pF Vo(pp) = 2 V, RL = 100 Ω, CL = 10 pF MIN TYP 25°C 0.8 1.57 Full range 0.55 25°C VDD = 5 V Full range CL = 10 pF 25°C 2.7 1 UNITS MHz V/ s V/µs 1.57 0.7 16 V(STEP)pp = 1 V, 0.1% AV = −1, 25°C CL = 10 pF, 0.01% RL = 100 Ω † Full range is 0°C to 70°C for C suffix and − 40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C. ts MAX 66 RL = 100 Ω, Gain margin VDD = 3 V TA† 25°C dB 0.7 µs Settling time 1.3 noise/distortion performance PARAMETER THD+N Total harmonic distortion plus noise TEST CONDITIONS VO(pp) = VDD/2 V, RL = 100 Ω, f = 100 Hz TA AV = 1 AV = 10 AV = 100 f = 100 Hz Vn Equivalent input noise voltage In Equivalent input noise current MIN TYP MAX UNITS 0.025 0.035 0.15 25°C 55 f = 10 kHz nV/√Hz 10 f = 1 kHz 0.31 fA/√Hz shutdown characteristics PARAMETER IDD(SHDN) TEST CONDITIONS Supply current in shutdown mode (per channel) (TLV4110, TLV4113) SHDN = 0 V TA† 25°C Full range MIN TYP MAX 3.4 10 15 UNITS µA A t(ON) Amplifier turn-on time‡ 1 RL = 100 Ω 25°C µs ‡ t(Off) Amplifier turn-off time 3.3 † Full range is 0°C to 70°C for C suffix and − 40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C. ‡ Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO CMRR Input offset voltage vs Common-mode input voltage Common-mode rejection ratio vs Frequency VOH VOL High-level output voltage vs High-level output current 4, 6 Low-level output voltage vs Low-level output current 5, 7 Zo IDD Output impedance vs Frequency Supply current vs Supply voltage 9 kSVR Power supply voltage rejection ratio vs Frequency 10 AVD Differential voltage amplification and phase vs Frequency 11 Gain-bandwidth product vs Supply voltage 12 vs Supply voltage 13 SR Vn Slew rate 1, 2 3 8 vs Temperature 14 Total harmonic distortion+noise vs Frequency 15 Equivalent input voltage noise vs Frequency 16 Phase margin vs Capacitive load 17 Voltage-follower signal pulse response 18, 19 Inverting large-signal pulse response 20, 21 Small-signal inverting pulse response Crosstalk 22 vs Frequency Shutdown forward and reverse isolation Shutdown supply current 24 vs Free-air temperature Shutdown supply current/output voltage POST OFFICE BOX 655303 23 25 26 • DALLAS, TEXAS 75265 7 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 6000 VDD = 3 V TA = 25°C 4000 V IO − Input Offset Voltage − µ V 2000 0 −2000 −4000 VDD = 5 V TA = 25°C 4000 2000 0 −2000 −4000 −6000 −0.2 0 −6000 −0.2 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 VICR − Common-Mode Input Voltage − V 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2 Figure 1 VOL − Low-Level Output Voltage − V 2.7 TA = 125°C TA = −40°C TA = 0°C TA = 25°C 2.3 TA = 70°C 2.2 2.1 2.0 0 50 100 150 200 250 0.8 TA = 70°C 0.7 TA = 25°C 0.6 TA = 0°C TA = −40°C 0.5 0.4 0.3 0.2 0.1 0.0 300 TA = 125°C 0 50 Z o − Output Impedance − Ω VOL − Low-Level Output Voltage − V 0.8 TA = 70°C TA = 25°C TA = 0°C TA = −40°C TA = 125°C 0.3 0.2 100 150 200 250 10 k 100 k 1M 10 M VDD = 5 V 4.9 4.8 TA = 125°C 4.7 4.6 TA = −40°C 4.5 TA = 0°C 4.4 TA = 25°C 4.3 TA = 70°C 4.2 4.1 4.0 300 0 50 100 150 200 250 300 IOH − High-Level Output Current − mA Figure 6 SUPPLY CURRENT vs SUPPLY VOLTAGE 1200 VDD = 3 & 5 V TA = 25°C AV = 1 VIN = VDD/2 V 10 A = 100 1 A = 10 TA = 125°C 1000 TA = 70°C 800 TA = 25°C 600 TA = 0°C TA = −40°C 400 200 0.1 A=1 0.0 0 50 100 150 200 250 IOL − Low-Level Output Current − mA Figure 7 8 1k HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 100 VDD = 5 V 0.4 40 100 OUTPUT IMPEDANCE vs FREQUENCY 1.0 0.5 50 Figure 5 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.6 60 IOL − Low-Level Output Current − mA Figure 4 0.7 70 5.0 VDD = 3 V 0.9 IOH − High-Level Output Current − mA 0.9 80 Figure 3 I DD − Supply Current − µ A V OH − High-Level Output Voltage − V 2.8 2.4 90 f − Frequency − Hz 1.0 VDD = 3 V 2.5 100 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3.0 2.6 VDD = 3 V TA = 25°C 110 Figure 2 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 2.9 120 VICR − Common-Mode Input Voltage − V V OH − High-Level Output Voltage − V V IO − Input Offset Voltage − µ V 6000 COMMON-MODE REJECTION RATIO vs FREQUENCY CMRR − Common-Mode Rejection Ratio − dB INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 300 0.10 100 1k 10k 100k 1M 10M f − Frequency − Hz Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 0 1 2 3 4 VDD − Supply Voltage − V Figure 9 5 6 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE vs FREQUENCY PSRR − Power Supply Rejection Ratio − V 100 VDD = 3 & 5 V RF = 1 kΩ RI = 100 Ω VIN = 0 V TA = 25°C 90 80 70 60 50 40 30 20 10 0 100 1k 10 k 100 k 1M 10 M 120 135 100 PHASE 80 90 60 40 0 −20 VDD = 3 & 5 V RL = 100 kΩ CL = 10 pF TA = 25°C −40 100 1k 10 k f − Frequency − Hz 3.0 1.50 2.5 2.0 TA = 25°C RL = 100 Ω CL = 10 pF f = 1 kHz AV =open loop 3 3.5 4 4.5 5 SR− 1.00 0.75 0.50 0.25 0.00 5.5 2.5 0.1 A = 10 A=1 0.01 10 k f − Frequency − Hz 100 k Hz A = 100 Figure 15 0.75 0.50 3 3.5 4 4.5 5 5.5 6 0.00 −40 −25 −10 5 160 140 Figure 14 PHASE MARGIN vs CAPACITIVE LOAD 100 VDD = 3 & 5 V TA = 25°C 90 VDD = 5 V 80 120 VDD = 3 V 100 80 60 40 70 RL = 100 RL = 600 RNULL = 20 60 50 RNULL = 20 40 30 RNULL = 0 20 20 0 10 20 35 50 65 80 95 110 125 TA − Temperature − °C EQUIVALENT INPUT VOLTAGE NOISE vs FREQUENCY V n − Equivalent Input Voltage Noise − nV/ THD+N −Total Harmonic Distortion + Noise VDD = 5 V RL = 100 Ω VO(PP) = VDD/2 AV = 1, 10, & 100 1k SR− 1.00 Figure 13 10 SR+ 1.25 VDD − Supply Voltage − V TOTAL HARMONIC DISTORTION+NOISE vs FREQUENCY 100 1.50 VDD = 3 & 5 V AV = 1 RL = 100 Ω CL = 10 pF 0.25 Figure 12 10 SR+ 1.25 VDD − Supply Voltage − V 1 1.75 Phase Margin − ° 2.5 −45 10 M 2.00 AV = 1 RL = 100 Ω CL = 10 pF SR − Slew Rate − V/ µ s 1.75 SR − Slew Rate − V/ µ s Gain-Bandwidth Product − MHz 2.00 3.5 0.0 1M SLEW RATE vs TEMPERATURE SLEW RATE vs SUPPLY VOLTAGE 4.0 0.5 100 k Figure 11 GAIN-BANDWIDTH PRODUCT vs SUPPLY VOLTAGE 1.0 0 f − Frequency − Hz Figure 10 1.5 45 GAIN 20 Phase Margin − ° A VD − Differential Voltage Amplification − dB POWER SUPPLY REJECTION RATIO vs FREQUENCY RNULL = 0 10 100 1k 10 k 100 k f − Frequency − Hz Figure 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 10 100 1k 10 k 100 k Capacitive Load − pF Figure 17 9 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS 4 VIN 2 1 VO 0 4 VDD = 5 V AV = 1 RL = 100 Ω CL = 10 pF TA = 25°C 3 2 1 0 −2 0 2 4 6 8 10 12 14 2.6 VIN 2.55 VDD = 5 V AV = 1 RL = 100 Ω CL = 10 pF TA = 25°C VIN = 100 mV 2.5 2.45 2.55 VO 2.5 2.45 2.4 −0.2 0.0 0.2 t − TIME − µs VDD = 5 V AV = −1 RL = 100 Ω CL = 50 pF TA = 25°C VIN = 2.5 V 5 VIN 4 3 2 VO 1 0 −1 0 1 2 3 4 5 6 7 8 V O − Output Voltage − V V I − Input Voltage − V V O − Output Voltage − V V I − Input Voltage − V 2 −2 1.0 1.2 −1 −2 5 VIN 4 3 2 VO 1 0 −1 0 1 2 3 4 2.54 −20 2.5 VDD = 5 V AV = −1 RL = 100 Ω CL = 50 pF TA = 25°C VIN = 2.5 V 2.46 2.42 2.54 VDD = 3 & 5 V RL = 100 Ω All Channels −40 −60 VIN = 4 VPP −80 2.5 VO 2.46 −100 VIN = 2 VPP 2.42 0 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 −120 10 t − TIME − µs 100 1k Figure 23 SHUTDOWN SUPPLY CURRENT vs FREE-AIR TEMPERATURE I DD − Shutdown Supply Current − µ A 16 VIN = 0.1 VPP −100 −120 VIN = 2.5 VPP −140 14 12 VDD = 3 and 5 V VIN = VDD/2, No Load 10 8 6 4 2 0 −160 10 100 1k 10 k 100 k 1M 10 M f − Frequency − Hz −40 −25 −10 5 20 35 50 65 80 95 110 125 TA − Free-Air Temperature − °C Figure 25 Figure 24 10 POST OFFICE BOX 655303 10 k f − Frequency − Hz Figure 22 VDD = 3 and 5 V, RL = 100 Ω, CL = 50 pF, AV = 1. TA = 25°C −80 8 CROSSTALK vs FREQUENCY VIN 0 −60 7 Figure 20 SHUTDOWN FORWARD AND REVERSE ISOLATION −40 6 0 Figure 21 −20 5 t − TIME − µs 2.58 t − TIME − µs Shutdown F/R Isolation − dB 1.4 VDD = 5 V AV = −1 RL = 100 Ω CL = 50 pF TA = 25°C VIN = 2.5 V 0 SMALL-SIGNAL INVERTING PULSE RESPONSE 3 0 0.8 2 1 Figure 19 INVERTING LARGE-SIGNAL PULSE RESPONSE −1 0.6 3 t − TIME − µs Figure 18 1 0.4 Crosstalk − dB 3 V O − Output Voltage − V V I − Input Voltage − V 5 INVERTING LARGE-SIGNAL PULSE RESPONSE VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE V O − Output Voltage − V V I − Input Voltage − V V O − Output Voltage − V V − Input Voltage − V I VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE • DALLAS, TEXAS 75265 100 k 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS SHDN − Shutdown Pulse − V SHUTDOWN SUPPLY CURRENT / OUTPUT VOLTAGE 4 3 2 1 SD 0 I DD(SD) − Shutdown Supply Current −µ A V O − Output Voltage − V 2 VDD = 3 V AV = 1 RL = 100 Ω CL = 10 pF VIN = VDD/2 TA = 25° C 1.5 1 0.5 VO 0 0 2 IDD(SD) 4 6 0 20 40 60 80 100 120 t − Time − µs Figure 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 APPLICATION INFORMATION shutdown function Two members of the TLV411x family (TLV4110/3) have a shutdown terminal for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to just nano amps per channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. In order to save power in shutdown mode, an external pullup resistor is required, therefore, to enable the amplifier the shutdown terminal must be pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. driving a capacitive load When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 1 nF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown in Figure 27. A maximum value of 20 Ω should work well for most applications. RF RG − Input RF RG RNULL Output + RL RNULL − Input Output + Snubber CLOAD RL CL C (a) (b) Figure 27. Driving a Capacitive Load offset voltage The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB− RG + − VI VO + RS IIB+ V OO +V IO ǒ ǒ ǓǓ 1) R R F G "I IB) R S ǒ ǒ ǓǓ 1) R R F "I G Figure 28. Output Offset Voltage Model 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IB– R F 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 APPLICATION INFORMATION Rnull _ + RL CL Figure 29 general power design considerations When driving heavy loads at high junction temperatures there is an increased probability of electromigration affecting the long term reliability of ICs. Therefore for this not to be an issue either: D The output current must be limited (at these high junction temperatures). or D The junction temperature must be limited. The maximum continuous output current at a die temperature 150°C will be 1/3 of the current at 105°C. The junction temperature will be dependent on the ambient temperature around the IC, thermal impedance from the die to the ambient and power dissipated within the IC. TJ = TA + θJA × PDIS Where: PDIS is the IC power dissipation and is equal to the output current multiplied by the voltage dropped across the output of the IC. θJA is the thermal impedance between the junction and the ambient temperature of the IC. TJ is the junction temperature. TA is the ambient temperature. Reducing one or more of these factors results in a reduced die temperature. The 8-pin SOIC (small outline integrated circuit) has a thermal impedance from junction to ambient of 176°C/W. For this reason it is recommended that the maximum power dissipation of the 8-pin SOIC package be limited to 350 mW, with peak dissipation of 700 mW as long as the RMS value is less than 350 mW. The use of the MSOP PowerPAD dramatically reduces the thermal impedance from junction to case. And with correct mounting, the reduced thermal impedance greatly increases the IC’s permissible power dissipation and output current handling capability. For example, the power dissipation of the PowerPAD is increased to above 1 W. Sinusoidal and pulse-width modulated output signals also increase the output current capability. The equivalent dc current is proportional to the square-root of the duty cycle: I DC(EQ) +I Cont Ǹ(duty cycle) CURRENT DUTY CYCLE AT PEAK RATED CURRENT EQUIVALENT DC CURRENT AS A PERCENTAGE OF PEAK 100 100 70 84 50 71 Note that with an operational amplifier, a duty cycle of 70% would often result in the op amp sourcing current 70% of the time and sinking current 30%, therefore, the equivalent dc current would still be 0.84 times the continuous current rating at a particular junction temperature. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 APPLICATION INFORMATION general PowerPAD design considerations The TLV411x is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 30(a) and Figure 30(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 30(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. Soldering the PowerPAD to the PCB is always recommended, even with applications that have low-power dissipation. This provides the necessary thermal and mechanical connection between the lead frame die pad and the PCB. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with mechanical methods of heatsinking. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 30. Views of Thermally-Enhanced DGN Package 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 APPLICATION INFORMATION Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. general PowerPAD design considerations (continued) 1. The thermal pad must be connected to the most negative supply voltage on the device, GND. 2. Prepare the PCB with a top side etch pattern as illustrated in the thermal land pattern mechanical drawings at the end of this document. There should be etch for the leads as well as etch for the thermal pad. 3. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 4. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the TLV411x IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 5. Connect all holes to the internal ground plane that is at the same voltage potential as the device GND pin. 6. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the TLV411x PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 8. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 9. With these preparatory steps in place, the TLV411x IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For a given θJA, the maximum power dissipation is shown in Figure 31 and is calculated by the following formula: P Where: D + ǒ T Ǔ –T MAX A q JA PD = Maximum power dissipation of TLV411x IC (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient air temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to case θCA = Thermal coefficient from case to ambient air (°C/W) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 APPLICATION INFORMATION general PowerPAD design considerations (continued) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 4 TJ = 150°C Maximum Power Dissipation − W 3.5 3 DGN Package Low-K Test PCB θJA = 52.7°C/W 2.5 PDIP Package Low-K Test PCB θJA = 104°C/W 2 SOIC Package Low-K Test PCB θJA = 176°C/W 1.0 1 0.5 0 −55 −40 −25 −10 5 20 35 50 65 80 95 110 125 TA − Free-Air Temperature − °C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 31. Maximum Power Dissipation vs Free-Air Temperature The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package. For the dual amplifier packages, the sum of the RMS output currents and voltages should be used to choose the proper package. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 



      

  
   
 
 SLOS289E − DECEMBER 1999 − REVISED SEPTEMBER 2006 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 3) and subcircuit in Figure 33 are generated using the TLV411x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): D Maximum positive output voltage swing D Unity-gain frequency D Maximum negative output voltage swing D Common-mode rejection ratio D Slew rate D Phase margin D Quiescent power dissipation D DC output resistance D Input bias current D AC output resistance D Open-loop voltage amplification D Short-circuit output current limit NOTE 3: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 3 99 VDD + egnd rd1 rd2 rss ro2 css fb rp − c1 7 11 12 + c2 vlim 1 + r2 9 6 IN+ − vc D D 8 + − vb ga 2 G G − IN− ro1 gcm ioff 53 S S OUT dp 91 10 iss GND 4 + dc − dlp ve + 54 vlp − 90 dln + hlim − 5 92 − vln + de * TLV4112_5V operational amplifier ”macromodel” subcircuit * updated using Model Editor release 9.1 on 01/18/00 at 15:50 Model Editor is an OrCAD product. * * connections: non−inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * || | | | .subckt TLV4112_5V 12345 * c1 11 12 2.2439E−12 c2 6 7 10.000E−12 css 10 99 454.55E−15 dc 5 53 dy de 54 5 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 + 33.395E6 −1E3 1E3 33E6 −33E6 ga 6 0 11 12 168.39E−6 gcm 0 6 10 99 168.39E−12 iss hlim ioff j1 J2 r2 rd1 rd2 ro1 ro2 rp rss vb vc ve vlim vlp vln .model .model .model .model .ends *$ 10 90 0 11 12 6 3 3 8 7 3 10 9 3 54 7 91 0 dx dy jx1 jx2 4 dc 13.800E−6 0 vlim 1K 6 dc 75E−9 2 10 jx1 1 10 jx2 9 100.00E3 11 5.9386E3 12 5.9386E3 5 10 99 10 4 3.3333E3 99 14.493E6 0 dc 0 53 dc .86795 4 dc .86795 8 dc 0 0 dc 300 92 dc 300 D(Is=800.00E−18) D(Is=800.00E−18 Rs=1m Cjo=10p) NJF(Is=150.00E−12 Beta=2.0547E−3 +Vto=−1) NJF(Is=150.00E−12 Beta=2.0547E−3 + Vto=−1) Figure 32. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TLV4110ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4110I TLV4110IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4110I TLV4110IDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHM TLV4110IDGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHM TLV4110IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4110I TLV4110IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4110I TLV4110IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TLV4110I TLV4110IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TLV4110I TLV4111CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 4111C TLV4111CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 4111C TLV4111CDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AHN TLV4111CDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AHN TLV4111ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4111I TLV4111IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4111I TLV4111IDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHO TLV4111IDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHO TLV4111IDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHO Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2013 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TLV4111IDGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHO TLV4111IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4111I TLV4111IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4111I TLV4112CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 4112C TLV4112CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 4112C TLV4112CDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AHP TLV4112CDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AHP TLV4112CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TLV4112C TLV4112CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TLV4112C TLV4112ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4112I TLV4112IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4112I TLV4112IDGN ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHQ TLV4112IDGNG4 ACTIVE MSOPPowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHQ TLV4112IDGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHQ TLV4112IDGNRG4 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHQ TLV4112IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4112I TLV4112IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4112I TLV4112IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TLV4112I Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2013 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty TLV4112IPE4 ACTIVE PDIP P 8 TLV4113CDGQG4 OBSOLETE MSOPPowerPAD DGQ 10 TLV4113CDGQR ACTIVE MSOPPowerPAD DGQ 10 TLV4113CDGQRG4 ACTIVE MSOPPowerPAD DGQ TLV4113ID ACTIVE SOIC TLV4113IDG4 ACTIVE TLV4113IDGQ 50 Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TLV4112I TBD Call TI Call TI 0 to 70 AHR 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AHR 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 AHR D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4113I SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 4113I ACTIVE MSOPPowerPAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHS TLV4113IDGQG4 ACTIVE MSOPPowerPAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHS TLV4113IDGQR ACTIVE MSOPPowerPAD DGQ 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHS TLV4113IDGQRG4 ACTIVE MSOPPowerPAD DGQ 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 AHS TLV4113IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TLV4113I TLV4113INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TLV4113I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV4113 : • Enhanced Product: TLV4113-EP NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV4110IDGNR Package Package Pins Type Drawing MSOPPower PAD SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV4110IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV4111IDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV4111IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV4112IDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV4112IDGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV4112IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV4113CDGQR MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV4113IDGQR MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV4110IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 TLV4110IDR SOIC D 8 2500 340.5 338.1 20.6 TLV4111IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 TLV4111IDR SOIC D 8 2500 340.5 338.1 20.6 TLV4112IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 TLV4112IDGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 TLV4112IDR SOIC D 8 2500 340.5 338.1 20.6 TLV4113CDGQR MSOP-PowerPAD DGQ 10 2500 358.0 335.0 35.0 TLV4113IDGQR MSOP-PowerPAD DGQ 10 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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