TLV5633CDWR

PW www.ti.com TLV5633C TLV5633I DW SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN FEATURES • • • • • • • DW OR PW PACKAGE (TOP VIEW) 12-Bit Voltage Output DAC Programmable Internal Reference Programmable Settling Time vs Power Consumption – 1 µs in Fast Mode – 3.5 µs in Slow Mode 8-Bit µController Compatible Interface Differential Nonlinearity . . . 4.75 V MIN TYP MAX UNIT 1.003 1.024 1.045 V 2.027 2.048 2.069 1 -1 V mA mA -48 dB REFERENCE PIN CONFIGURED AS INPUT (REF) PARAMETER VI Input voltage RI Input resistance CI Input capacitance Reference input bandwidth TEST CONDITIONS REF = 0.2 Vpp + 1.024 V dc REF = 1 Vpp + 2.048 V dc, AVDD = 5 V 50 kHz 100 kHz Reference feedthrough TYP MAX 0 10 kHz Harmonic distortion, reference input MIN REF = 1 Vpp at 1 kHz + 1.024 V dc UNIT AVDD-1.5 V 10 MΩ 5 pF Fast 900 Slow 500 Fast -87 Slow -77 Fast -74 Slow -61 Fast -66 dB -80 dB (1) kHz dB dB DIGITAL INPUTS IIH High-level digital input current VI = DVDD IIL Low-level digital input current VI = 0 V CI Input capacitance (1) 1 -1 µA µA 8 pF Reference feedthrough is measured at the DAC output with an input code = 0x000. OPERATING CHARACTERISTICS over recommended operating free-air temperature range, Vref = 2.048 V, and Vref = 1.024 V, (unless otherwise noted) ANALOG OUTPUT DYNAMIC PERFORMANCE PARAMETER TEST CONDITIONS ts(FS) Output settling time, full scale RL = 10 kΩ, CL = 100 pF (1) ts(CC) Output settling time, code to code RL = 10 kΩ, CL = 100 pF (2) SR Slew rate RL = 10 kΩ, CL = 100 pF (3) Glitch energy DIN = 0 to 1, fCLK = 100 kHz, CS = VDD SNR Signal-to-noise ratio SINAD Signal-to-noise + distortion THD Total harmonic distortion SFDR Spurious free dynamic range (1) (2) (3) fs = 480 kSPS, fB = 20 kHz, fout = 1 kHz, RL = 10 kΩ, CL = 100 pF TYP MAX Fast MIN 1 3 Slow 3.5 7 Fast 0.5 1.5 Slow 1 2 Fast 6 10 Slow 1.2 1.7 73 78 61 67 63 µs µs V/µs 5 -69 UNIT nV-S -62 dB 74 Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF or 0xFDF to 0x020 respectively. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one count. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. Submit Documentation Feedback 5 TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 DIGITAL INPUT TIMING REQUIREMENTS MIN NOM MAX tsu(CS-WE) Setup time, CS low before negative WE edge 15 ns tsu(D) Setup time, data ready before positive WE edge 10 ns tsu(A) Setup time, addresses ready before positive WE edge 20 ns th(DA) Hold time, data and addresses held valid after positive WE edge 5 ns tsu(WE-LD) Setup time, positive WE edge before LDAC low 5 ns twH(WE) Pulse duration, WE high 20 ns tw(LD) Pulse duration, LDAC low 23 ns PARAMETER MEASUREMENT INFORMATION D(0-7) X A(0,1) X Data X Address X tsu(D) tsu(A) CS th(DA) twH(WE) tsu(CS-WE) WE tsu(WE-LD) tw(LD) LDAC Figure 1. Timing Diagram D(0-7) X LSW A(0,1) X 0 X X MSW X 1 X CS WE LDAC Figure 2. Example of a Complete Write Cycle (MSW, LSW) Using LDAC for Update 6 UNIT Submit Documentation Feedback TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) D(0−7) X LSW X MSW X Control X A(0−1) X 0 X 1 X 3 X CS WE LDAC Figure 3. Example of a Complete Write Cycle (MSW, LSW, Control) Submit Documentation Feedback 7 TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS DNL - Differential Nonlinearity - LSB DIFFERENTIAL NONLINEARY ERROR 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 2560 3072 3584 4096 3072 3584 4096 Digital Code Figure 4. INTEGRAL NONLINEARTIY ERROR INL - Intergral Nonlinearity - LSB 3 2 1 0 -1 -2 -3 0 512 1024 1536 2048 2560 Digital Code Figure 5. MAXIMUM OUTPUT VOLTAGE vs LOAD CURRENT MAXIMUM OUTPUT VOLTAGE vs LOAD CURRENT 2.04 4.08 AVDD = 3 V, Vref = Int. 1 V, Input Code = 0xFFF 2.0395 4.079 VO - Output Voltage - V VO - Output Voltage - V 2.039 Fast Mode, Source 2.0385 Fast Mode, Source 4.0785 2.038 2.0375 4.078 4.0775 2.037 Slow Mode, Source 4.077 Slow Mode, Source 2.0365 4.0765 2.036 4.076 2.0355 4.0755 0 8 AVDD = 5 V, Vref = Int. 2 V, Input Code = 0xFFF 4.0795 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Load Current - mA 0 1.5 2 2.5 3 Load Current - mA Figure 6. Figure 7. Submit Documentation Feedback 0.5 1 3.5 4 4.5 TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) MINIMUM OUTPUT VOLTAGE vs LOAD CURRENT MINIMUM OUTPUT VOLTAGE vs LOAD CURRENT 0.25 0.25 Fast Mode, Sink Fast Mode, Sink VO - Output Voltage - V 0.2 0.15 0.1 Slow Mode, Sink 0.05 0 0 0.5 1 1.5 2 2.5 3 Load Current - mA 3.5 4 THD - Total Harmonic Distortion - dB Slow Mode, Sink 0 AVDD = 3 V, Vref = Int. 1 V, Input Code = 0x000 0 0.5 1 1.5 2 2.5 3 Load Current - mA 3.5 4 4.5 Figure 8. Figure 9. TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY AVDD = 5 V, REF = 1 V dc + 1 V pp Sinewave, Output Full Scale -20 -30 -40 -50 -60 Slow Mode -70 -80 Fast Mode -90 -100 100 0.1 4.5 0 -10 0.15 0.05 AVDD = 5 V, Vref = Int. 2 V, Input Code = 0x000 1000 10000 100000 THD+N - Total Harmonic Distortion and Noise - dB VO - Output Voltage - V 0.2 0 -10 AVDD = 5 V, REF = 1 V dc + 1 V pp Sinewave, Output Full Scale -20 -30 -40 -50 -60 Slow Mode -70 -80 Fast Mode -90 -100 100 1000 10000 100000 f - Frequency - Hz f - Frequency - Hz Figure 10. Figure 11. Submit Documentation Feedback 9 TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 TYPICAL CHARACTERISTICS (continued) POWER DOWN SUPPLY CURRENT vs TIME 1 0.9 I DD - Supply Current - mA 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 10 20 30 40 50 60 t - Time - µs Figure 12. 10 Submit Documentation Feedback 70 80 90 TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 APPLICATION INFORMATION GENERAL FUNCTION The TLV5633 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel interface, a speed and power down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: 2 REF CODE [V] 0 1000 Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power on reset initially puts the internal latches to a defined state (all bits zero). PARALLEL INTERFACE The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written to one of the DAC holding latches (MSW, LSW) or the control register depends on the address bits A1 and A0. LDAC low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be held low, if a separate update is not necessary. However, to control the DAC using the load feature, there should be approximately a 5 ns delay after the positive WE edge before driving LDAC low. Two more asynchronous inputs, SPD and PWR control the settling times and the power-down mode: SPD: Speed control 1 → fast mode 0 → slow mode PWR: Power control 1 → normal operation 0 → power down It is also possible to program the different modes (fast, slow, power down) and the DAC update latch using the control register. The following tables list the possible combinations of control signals and control bits. PIN BIT SPD SPD 0 0 Slow 0 1 Fast 1 0 Fast 1 1 Fast PIN BIT PWR PWD 0 0 Down 0 1 Down 1 0 Normal 1 1 Down PIN BIT LDAC RLDAC 0 0 Transparent 0 1 Transparent 1 0 Hold 1 1 Transparent Submit Documentation Feedback MODE POWER LATCH 11 TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 DATA FORMAT The TLV5633 writes data either to one of the DAC holding latches or to the control register depending on the address bits A1 and A0. ADDRESS BITS A1 A0 REGISTER 0 0 DAC LSW holding 0 1 DAC MSW holding 1 0 Reserved 1 1 Control The following table lists the meaning of the bits within the control register. D7 X X (1) (1) D6 X X (1) D5 X X (1) D4 REF1 0 (1) D3 REF0 0 (1) D2 RLDAC 0 (1) D1 PWR 0 (1) D0 SPD 0 (1) Default values: X = Don't Care SPD: Speed control bit 1 → fast mode 0 → slow mode PWR: Power control bit 1 → power down 0 → normal operation RLDAC: Load DAC latch 1 → latch transparent 0 → DAC latch controlled by LDAC pin REF1 and REF0 determine the reference source and the reference voltage. REFERENCE BITS REF1 REF0 REFERENCE 0 0 External 0 1 1.024 V 1 0 2.048 V 1 1 External If an external reference voltage is applied to the REF pin, external reference must be selected. LAYOUT CONSIDERATIONS To achieve the best performance, it is recommended to have separate power planes for GND, AVDD, and DVDD. Figure 13 shows how to lay out the power planes for the TLV5633. As a general rule, digital and analog signals should be separated as wide as possible. To avoid crosstalk, analog and digital traces must not be routed in parallel. The two positive power planes (AVDD and DVDD) should be connected together at one point with a ferrite bead. A 100-nF ceramic low series inductance capacitor between DVDD and GND and a 1-µF tantalum capacitor between AVDD and GND placed as close as possible to the supply pins are recommended for optimal performance. 12 Submit Documentation Feedback TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 DVDD AVDD Figure 13. TLV5633 Board Layout LINEARITY, OFFSET, AND AGAIN ERROR USING SINGLE END SUPPLIES When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14. Output Voltage 0V Negative Offset DAC Code Figure 14. Effect of Negative Offset (Single Supply) The offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full scale code and the lowest code that produces a positive output voltage. Submit Documentation Feedback 13 TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 TLV5633 INTERFACED to an Intel MCS®51 Controller The circuit in Figure 15 shows how to interface the TLV5633 to an Intel MCS®51 microcontroller. The address bus and the data bus of the controller are multiplexed on port 0 (non page mode) to save port pins. To separate the address bits and the data bits, the controller provides a dedicated signal, address latch enable (ALE), which is connected to a latch at port 0. An address decoder is required to generate the chip select signal for the TLV5633. In this example, a simple 3-to-8 decoder (74AC138) is used for the interface as shown in Figure 15. The DAC is memory mapped at addresses 0x8000/1/2/3 within the data memory address space and mirrored every 32 address locations (0x8020/1/2/3, 0x8040/1/2/3, etc.). In a typical microcontroller system, programmable logic should be used to generate the chip select signals for the entire system. The data pins and the WE pin of the TLV5633 can be connected directly to the multiplexed address and data bus and the WR signal of the controller. The application uses the TLV5633 device's internal reference at 2.048 V. The LDAC pin is connected to P3.5 and is used to update the DAC after both data bytes have been written. 8xC51 8 P2 A(15-8) 16 8 8 P0 AD(7-0) D(7-0) AD(7-0) 74AC138 74AC373 8 Q(7-0) A2 A3 A4 A 8 Y(7-0) CS(7-0) B C DVDD TLV5633 ALE LE OE A15 DVDD G1 G2A G2B 2 G2A A(1-0) SPD D(7-0) PWR CS OUT WE WR P3.5 LDAC To Other Devices Requiring Voltage Reference REF Figure 15. TLV5633 Interfaced to an Intel MCS®51 Controller 14 A(15-0) Submit Documentation Feedback RL TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 SOFTWARE In the following example, the code generates a waveform at 20 KSPS with 32 samples stored in a table within the program memory space of the microcontroller. The waveform data is located in the program memory space at segment SINTBL beginning with the MSW of the first 16-bit word (the 4 MSBs are ignored), followed by the LSW. Two bytes are required for each DAC word (the table is not shown in the code example). The program consists of two parts: • A main routine, which is executed after reset and which initializes the timer and the interrupt system of the microcontroller. • An interrupt service routine, which reads a new value from the waveform table and writes it to the DAC. ;-------------------------------------------------------------------------------------; File: WAVE.A51 ; Function: wave generation with TLV5633 ; Processors: 80C51 family (running at 12 MHz) ; Software: ASM51 assembler, Keil BL51 code-banking linker ;(C) 1999 Texas Instruments ;-------------------------------------------------------------------------------------;-------------------------------------------------------------------------------------; Program function declaration ;-------------------------------------------------------------------------------------NAME WAVE MAIN SEGMENT CODE ISR SEGMENT CODE WAVTBL SEGMENT CODE VAR1 SEGMENT DATA STACK SEGMENT IDATA ;-------------------------------------------------------------------------------------; Code start at address 0, jump to start ;-------------------------------------------------------------------------------------CSEG AT 0 LJMP start ; Execution starts at address 0 on power-up. ;-------------------------------------------------------------------------------------; Code in the timer0 interrupt vector ;-------------------------------------------------------------------------------------CSEG AT 0BH LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh ;-------------------------------------------------------------------------------------; Define program variables ;-------------------------------------------------------------------------------------RSEG VAR1 rolling_ptr: DS 1 ;-------------------------------------------------------------------------------------; Interrupt service routine for timer 0 interrupts ;-------------------------------------------------------------------------------------RSEG ISR TIMER0ISR: PUSH PSW PUSH ACC ; The signal to be output on the dac is stored in a table ; as 32 samples of msb, lsb pairs (64 bytes). ; The pointer, rolling_ptr, rolls round the table of samples ; incrementing by 2 bytes (1 sample) on each interrupt ; (at the end of this routine). MOV DPTR, #wavetable ; set DPTR to the start of the table MOV R0, #001H ; R0 selects DAC MSW MOV A,rolling_ptr ; ACC loaded with the pointer into the wave table MOVC A,@A+DPTR ; get msb from the table MOVX @R0, A ; write DAC MSW MOV R0, #000H ; R0 selects DAC LSW MOV A,rolling_ptr ; move rolling pointer back in to ACC INC A ; increment ACC holding the rolling pointer MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC MOVX @R0, A ; write DAC LSW MOV A,rolling_ptr ; load ACC with rolling pointer again INC A ; increment the ACC twice, to get next sample INC A ANL A,#003FH ; wrap back round to 0 if >64 MOV rolling_ptr,A ; move value held in ACC back to the rolling pointer Submit Documentation Feedback 15 TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 CLR T1 ; set LDACB = 0 (update DAC) SETB T1 ; set LDACB = 1 POP ACC POP PSW RETI ;-------------------------------------------------------------------------------------; Set up stack ;-------------------------------------------------------------------------------------RSEG STACK DS 10h ; 16 Byte Stack! ;-------------------------------------------------------------------------------------; Main Program ;-------------------------------------------------------------------------------------RSEG MAIN start: MOV SP,#STACK-1 ; first set Stack Pointer CLR A MOV rolling_ptr,A ; set rolling pointer to 0 MOV TMOD,#002H ; set timer 0 to mode 2 - auto-reload MOV TH0,#0CEH ; set timer 2 re-load value for 20 kHz interrupts MOV P2, #080H ; set A15 of address bus high to 'memory map' ; device up beyond used address space SETB T1 ; set LDACB = 1 (on P3.5) ; TLV5633 setup MOV R0, #003H ; R0 selects control register MOV A, #011H ; LOAD ACC with control register value: ; REF1=1, REF0=0 -> 2.048V internal reference ; RLDAC=0 -> use LDACB pin to control DAC ; PD=0 -> DAC enabled ; SPD=1 -> FAST mode ; write control word: MOVX @R0, A ; write DAC control word SETB ET0 ; enable timer 0 interrupts SETB EA ; enable all interrupts SETB TR0 ; start timer 0 always: SJMP always RET ;-------------------------------------------------------------------------------------; Table of 32 wave samples used as DAC data ;-------------------------------------------------------------------------------------RSEG WAVTBL wavetable: ;...insert 32 samples here... .END 16 Submit Documentation Feedback TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY Integral Nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Differential Nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1-LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Zero-Scale Error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. Gain Error (EG) Gain error is the error in slope of the DAC transfer function. Signal-To-Noise Ratio + Distortion (SINAD) Signal-to-noise ratio + distortion is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels. Submit Documentation Feedback 17 TLV5633C TLV5633I www.ti.com SLAS190C – MARCH 1999 – REVISED SEPTEMBER 2006 Revision history 18 Revision Date Description A 01/2001 Minor typographical changes. B 08/2003 Changed the High-level and Low-level digital input voltage in the Recommended Operating Conditins table. C 09/2006 Changed the positions of LSW and MSW in Figure 2 and Figure 3. Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TLV5633CDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLV5633C TLV5633CPW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TV5633 TLV5633IDW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5633I TLV5633IPW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TY5633 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of