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TLV62150, TLV62150A
SLVSB71E – FEBRUARY 2012 – REVISED SEPTEMBER 2016
TLV62150x 4-V to 17-V 1-A Step-Down Converter In 3x3 QFN Package
1 Features
3 Description
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The TLV62150x device is an easy-to-use
synchronous step-down DC-DC converter optimized
for applications with high power density. A high
switching frequency of typically 2.5 MHz allows the
use of small inductors and provides fast transient
response as well as high output voltage accuracy by
use of the DCS-Control™ topology.
1
DCS-Control™ Topology
Input Voltage Range: 4 V to 17 V
Up to 1-A Output Current
Adjustable Output Voltage from 0.9 to 5 V
Pin-Selectable Output Voltage (nominal, + 5%)
Programmable Soft Start and Tracking
Seamless Power Save Mode Transition
Quiescent Current of 19 µA (Typical)
Selectable Operating Frequency
Power Good Output
100% Duty Cycle Mode
Short Circuit Protection
Over Temperature Protection
For Improved Feature Set, see TPS62150
Pin to Pin compatible with TLV62130
Available in a 3-mm × 3-mm, VQFN-16 Package
2 Applications
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•
•
•
•
Standard 12-V Rail Supplies
POL Supplies from Single or Multiple Li-Ion
Batteries
Appliances, Building Automation
Mobile PC's, Tablets, Modems, Cameras
TV, Set-top Boxes, Audio
With their wide operating input voltage range of 4 V
to 17 V, the devices are ideally suited for systems
powered from either a Li-Ion or other batteries as well
as from 12 V intermediate power rails. It supports up
to 1-A continuous output current at output voltages
between 0.9 V and 5 V (with 100% duty cycle mode).
The output voltage startup ramp is controlled by the
soft-start pin, which allows operation as either a
standalone power supply or in tracking configurations.
Power sequencing is also possible by configuring the
Enable and open-drain Power Good pins.
In Power Save Mode, the devices draw quiescent
current of about 19 μA from VIN. Power Save Mode,
entered automatically and seamlessly if load is small,
maintains high efficiency over the entire load range.
In Shutdown Mode, the device is turned off and
shutdown current consumption is less than 2 μA.
The devices is packaged in a 16-pin VQFN package
measuring 3 mm × 3 mm (RGT).
Device Information(1)
PART NUMBER
TLV62150
PACKAGE
VQFN (16)
TLV62150A
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
Efficiency vs Output Current
1 / 2.2 µH
10uF
PVIN
SW
AVIN
VOS
EN
PG
90.0
100k
750k
TLV62150
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
100.0
3.3V / 1A
240k
22uF
Efficiency (%)
(4 .. 17)V
VIN=5V
80.0
70.0
60.0
50.0
40.0
0.0
VOUT=3.3V
fsw=1.25MHz
0.1
0.2
0.3
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
1.0
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV62150, TLV62150A
SLVSB71E – FEBRUARY 2012 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
5
6
7
Detailed Description .............................................. 8
8.1
8.2
8.3
8.4
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview ................................................................... 8
Functional Block Diagram ......................................... 8
Feature Description................................................... 9
Device Functional Modes........................................ 10
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
9.3 System Examples ................................................... 23
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 28
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 28
11.3 Thermal Considerations ........................................ 29
12 Device and Documentation Support ................. 30
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support......................................................
Related Links ........................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
30
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2015) to Revision E
Page
•
Added Pin to Pin compatibility to Features ........................................................................................................................... 1
•
Added items to Applications list ............................................................................................................................................. 1
•
Corrected temperatures in Thermal Information ................................................................................................................... 5
•
Added Power Good Pin Logic Tables 1 and 2 ...................................................................................................................... 9
•
Added Receiving Notification of Documentation Updates ................................................................................................... 30
Changes from Revision C (June 2015) to Revision D
•
Page
Changed Power Good Threshold Voltage, Falling (%VOUT) MAX spec from 93% to 94% ................................................... 6
Changes from Revision B (June 2013) to Revision C
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision A (February 2013) to Revision B
Page
•
Added new device version TLV62150A to data sheet ........................................................................................................... 1
•
Added text to Power Good section regarding the TLV62150A function................................................................................. 9
•
Added additional option to the footnote for Pin-Selectable Output Voltage (DEF) section. ................................................. 10
•
Added text to Frequency Selection (FSW) section regarding pin control............................................................................. 10
•
Added text to Tracking Function section for clarification. ..................................................................................................... 17
•
Changed schematic for Figure 38 ........................................................................................................................................ 24
2
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SLVSB71E – FEBRUARY 2012 – REVISED SEPTEMBER 2016
Changes from Original (February 2012) to Revision A
Page
•
Added text to Terminal Functions table to clarify Description for AGND, PGND, and Exposed Thermal Pad. ..................... 4
•
Added text to Power Save Mode Operation section for clarification. ................................................................................... 11
•
Changed text in the Layout Considerations section for clarification..................................................................................... 28
Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
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TLV62150, TLV62150A
SLVSB71E – FEBRUARY 2012 – REVISED SEPTEMBER 2016
www.ti.com
5 Device Comparison Table
PART NUMBER
OUTPUT VOLTAGE
POWER GOOD LOGIC LEVEL (EN=Low)
TLV62150
Adjustable
High Impedance
TLV62150A
Adjustable
Low
6 Pin Configuration and Functions
SW
3
PG
4
PGND
VOS
EN
13
Exposed
Thermal Pad
5
6
7
8
DEF
2
14
FSW
SW
15
AGND
1
16
FB
SW
PGND
RGT Package
16-Pin VQFN
Top View
12
PVIN
11
PVIN
10
AVIN
9
SS/TR
Pin Functions
PIN
NAME
(1)
NO.
I/O
DESCRIPTION
AGND
6
—
AVIN
10
I
Supply voltage for control circuitry. Connect to same source as PVIN.
DEF
8
I
Output Voltage Scaling (Low = nominal, High = nominal + 5%) (2)
EN
13
I
Enable input (High = enabled, Low = disabled) (2)
FB
5
I
Voltage feedback. Connect resistive voltage divider to this pin.
FSW
7
I
Switching Frequency Select (Low ≈ 2.5 MHz, High ≈ 1.25 MHz (3) for typical operation) (2)
SW
1,2,3
O
Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
output capacitor.
PG
4
O
Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires pullup resistor)
PGND
15,16
—
Power ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
PVIN
11,12
I
Supply voltage for power stage. Connect to same source as AVIN.
SS/TR
9
I
Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise
time. It can be used for tracking and sequencing.
VOS
14
I
Output voltage sense pin and connection for the control loop circuitry.
Exposed
Thermal Pad
—
—
(1)
(2)
(3)
4
Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane. See the Layout
Example. Must be soldered to achieve appropriate power dissipation and mechanical reliability.
For more information about connecting pins, see Detailed Description and Application and Implementation sections.
An internal pull-down resistor keeps logic level low, if pin is floating.
Connect FSW to VOUT or PG in this case.
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SLVSB71E – FEBRUARY 2012 – REVISED SEPTEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Pin voltage
(2)
(1)
MIN
MAX
UNIT
AVIN, PVIN
–0.3
20
V
EN, SS/TR
–0.3
VIN+0.3
SW
–0.3
VIN+0.3
V
DEF, FSW, FB, PG, VOS
–0.3
7
V
10
mA
Power Good sink
current
PG
Operating junction
temperature
TJ
–40
125
Storage temperature
Tstg
–65
150
(1)
(2)
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
VESD
(1)
(2)
(3)
Electrostatic discharge (1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (2)
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (3)
±500
UNIT
V
ESD testing is performed according to the respective JESD22 JEDEC standard.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Supply Voltage
MIX
MAX
4
17
V
°C
Temperature Range, TA
–40
85
Operating junction temperature, TJ
–40
125
UNIT
7.4 Thermal Information
TLV62150
THERMAL METRIC (1)
RGT [VQFN]
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
45
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
53.6
°C/W
RθJB
Junction-to-board thermal resistance
17.4
°C/W
ψJT
Junction-to-top characterization parameter
1.1
°C/W
ψJB
Junction-to-board characterization parameter
17.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: TLV62150 TLV62150A
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TLV62150, TLV62150A
SLVSB71E – FEBRUARY 2012 – REVISED SEPTEMBER 2016
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7.5 Electrical Characteristics
over operating free-air temperature range (TA = –40°C to 85°C), typical values at VIN = 12 V and TA = 25°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input Voltage Range (1)
IQ
Operating Quiescent Current
ISD
Shutdown Current
VUVLO
Undervoltage Lockout Threshold
4
(2)
17
V
EN=High, IOUT=0 mA, device not
switching
19
27
μA
EN=Low
1.5
4
μA
2.7
2.8
V
Falling Input Voltage (PWM mode
operation)
2.6
Hysteresis
TSD
200
Thermal Shutdown Temperature
mV
160
Thermal Shutdown Hysteresis
°C
20
CONTROL (EN, DEF, FSW, SS/TR, PG)
VH
High Level Input Threshold Voltage
(EN, DEF, FSW)
VL
Low Level Input Threshold Voltage
(EN, DEF, FSW)
ILKG
Input Leakage Current (EN, DEF,
FSW)
EN=VIN or GND; DEF, FSW=VOUT
or GND
VTH_PG
Power Good Threshold Voltage
Rising (%VOUT)
Falling (%VOUT)
0.9
V
0.3
V
0.01
1
μA
92%
95%
98%
87%
90%
94%
VOL_PG
Power Good Output Low
IPG=-2 mA
0.07
0.3
V
ILKG_PG
Input Leakage Current (PG)
VPG=1.8 V
1
400
nA
ISS/TR
SS/TR Pin Source Current
2.5
2.7
μA
2.3
POWER SWITCH
RDS(ON)
ILIMF
High-Side MOSFET ON-Resistance
VIN≥6 V
90
mΩ
Low-Side MOSFET ON-Resistance
VIN≥6 V
40
mΩ
High-Side MOSFET Forward
Current Limit (3)
VIN =12 V, TA=25°C
1.7
A
Input Leakage Current (FB)
VFB=0.8 V
Output Voltage Range
VIN ≥ VOUT
DEF (Output Voltage Programming)
DEF=0 (GND)
VOUT
DEF=1 (VOUT)
VOUT+5%
1.4
OUTPUT
ILKG_FB
VOUT
Initial Output Voltage Accuracy
Load Regulation
(5)
Line Regulation (5)
(1)
(2)
(3)
(4)
(5)
6
(4)
1
0.9
PWM mode operation, VIN ≥ VOUT
+1 V
780
800
100
nA
5
V
820
mV
VIN=12 V, VOUT=3.3 V, PWM mode
operation
0.05
%/A
4 V ≤ VIN ≤ 17 V, VOUT=3.3 V, IOUT=
1 A, PWM mode operation
0.02
%/V
The device is still functional down to Under Voltage Lockout (see parameter VUVLO).
Current into AVIN+PVIN pin.
This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit and Short
Circuit Protection).
This is the accuracy provided by the device itself (line and load regulation effects are not included).
Line and load regulation depend on external component selection and layout (see Figure 20 and Figure 21).
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50.0
5.0
45.0
4.5
40.0
4.0
Input Current (µA)
Input Current (µA)
7.6 Typical Characteristics
35.0
30.0
25°C
25.0
85°C
20.0
15.0
10.0
3.5
85°C
3.0
2.5
2.0
1.5
1.0
−40°C
5.0
0.0
3.0
6.0
−40°C
25°C
0.5
9.0
12.0
15.0
Input Voltage (V)
18.0
0.0
3.0
20.0
6.0
9.0
12.0
15.0
Input Voltage (V)
G001
Figure 1. Quiescent Current
18.0
20.0
G001
Figure 2. Shutdown Current
100
200
160
125°C
140
RDSon Low−Side (mW)
RDSon High−Side (mW)
180
85°C
120
25°C
100
80
−10°C
60
−40°C
40
80
125°C
85°C
60
25°C
40
−10°C
20
−40°C
20
0
0
3
6
9
12
Input Voltage (V)
15
Figure 3. High-Side Switch Resistance
18
20
0
0
3
6
9
12
Input Voltage (V)
15
18
20
Figure 4. Low-Side Switch Resistance
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TLV62150, TLV62150A
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8 Detailed Description
8.1 Overview
The TLV62150 synchronous switched-mode power converters are based on DCS-Control™ (Direct Control with
Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of
hysteretic, voltage mode and current mode control including an AC loop directly associated to the output voltage.
This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage.
It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate
response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The
internally compensated regulation network achieves fast and stable operation with small external components
and low ESR capacitors.
The DCS-Control™ topology supports Pulse Width Modulation (PWM) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.5 MHz or 1.25 MHz with a controlled frequency
variation depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to
sustain high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly
with the load current. Since DCS-Control™ supports both operation modes within one single building block, the
transition from PWM to Power Save Mode is seamless without effects on the output voltage.
An internal current limit supports nominal output currents of up to 1 A.
The TLV62150 offers both excellent DC voltage and superior load transient regulation, combined with very low
output voltage ripple, minimizing interference with RF circuits.
8.2 Functional Block Diagram
PG
Soft
start
Thermal
Shtdwn
UVLO
AVIN
PVIN PVIN
PG control
HS lim
comp
*
EN
SW
SS/TR
power
control
control logic
gate
drive
SW
*
DEF
SW
FSW*
comp
LS lim
VOS
FB
direct control
&
compensation
ramp
_
comparator
+
timer tON
error
amplifier
DCS - ControlTM
AGND
PGND PGND
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8.3 Feature Description
8.3.1 Enable / Shutdown (EN)
When Enable (EN) is set High, the device starts operation. Shutdown is forced if EN is pulled Low with a
shutdown current of typically 1.5 µA. During shutdown, the internal power MOSFETs as well as the entire control
circuitry are turned off. The EN signal must be set externally to High or Low. An internal pull-down resistor of
about 400 kΩ is connected and keeps EN logic low, if the pin is floating. It is disconnected if the pin is High.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.
8.3.2 Soft Start / Tracking (SS/TR)
The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from highimpedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50µs and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR
pin. See Figure 32 and Figure 33 for typical startup operation.
Using a very small capacitor (or leaving SS/TR pin un-connected) provides fastest startup behavior. There is no
theoretical limit for the longest startup time. The TLV62150 can start into a pre-biased output. During monotonic
pre-biased startup, the low-side MOSFET is not allowed to turn on until the device's internal ramp sets an output
voltage above the pre-bias voltage. If the device is set to shutdown (EN=GND), undervoltage lockout or thermal
shutdown, an internal resistor pulls the SS/TR pin down to ensure a proper low level. Returning from those states
causes a new startup sequence as set by the SS/TR connection.
A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage will follow this voltage
in both directions up and down (see Application and Implementation).
8.3.3 Power Good (PG)
The TLV62150 has a built in power good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an
open-drain output that requires a pull-up resistor (to any voltage below 7 V). It can sink 2 mA of current and
maintain it's specified logic low level. With TLV62150 it is high impedance when the device is turned off due to
EN, UVLO or thermal shutdown. TLV62150A features PG=Low in this case and can be used to actively
discharge Vout (see Figure 37). VIN must remain present for the PG pin to stay Low. See SLVA644 for
application details. If not used, the PG pin should be connected to GND but may be left floating.
space
Table 1. Power Good Pin Logic Table (TLV62150)
Device State
PG Logic Status
High Impedance
Enable (EN=High)
VFB ≥ VTH_PG
Low
√
VFB ≤ VTH_PG
√
√
Shutdown (EN=Low)
UVLO
0.7V < VIN < VUVLO
√
Thermal Shutdown
TJ > TSD
√
√
Power Supply Removal VIN < 0.7V
space
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Table 2. Power Good Pin Logic Table (TLV62150A)
Device State
PG Logic Status
High Impedance
Enable (EN=High)
VFB ≥ VTH_PG
Low
√
VFB ≤ VTH_PG
√
√
Shutdown (EN=Low)
UVLO
0.7 V < VIN < VUVLO
Thermal Shutdown
TJ > TSD
√
√
√
Power Supply Removal VIN < 0.7 V
space
8.3.4 Pin-Selectable Output Voltage (DEF)
The output voltage of the TLV62150 can be increased by 5% above the nominal voltage by setting the DEF pin
to High (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal voltage
allows adapting the power supply voltage to the variations of the application hardware. More detailed information
on voltage margining using TLV62150 can be found in SLVA489. A pull down resistor of about 400 kΩ is
internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating after initially
set to Low. The resistor is disconnected if the pin is set High.
8.3.5 Frequency Selection (FSW)
To get high power density with very small solution size, a high switching frequency allows the use of small
external components for the output filter. However switching losses increase with the switching frequency. If
efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz
typical) by pulling FSW to High. It is mandatory to start with FSW=Low to limit inrush current, which can be done
by connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage
ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typical). To get low ripple and full
output current at the lower switching frequency, it's recommended to use an inductor of at least 2.2 µH. The
switching frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is
internally connected to the pin, acting the same way as at the DEF Pin (see above).
8.3.6 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents misoperation of the device by switching off both the
power FETs. The undervoltage lockout threshold is set typically to 2.7 V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 200 mV.
8.3.7 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 160°C
(typical), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and
PG goes high impedance. When TJ decreases below the hysteresis amount, the converter resumes normal
operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shut down temperature.
8.4 Device Functional Modes
8.4.1 Pulse Width Modulation (PWM) Operation
The TLV62150 operates with pulse width modulation in continuous conduction mode (CCM) with a nominal
switching frequency of 2.5 MHz or 1.25 MHz, selectable with the FSW pin. The frequency variation in PWM is
controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output
current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device
enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). This happens if the output
current becomes smaller than half the inductor's ripple current.
(1)
10
Maximum allowed voltage is 7 V. Therefore, it's recommended to connect it to VOUT or PG, not VIN.
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Device Functional Modes (continued)
8.4.2 Power Save Mode Operation
The built in Power Save Mode of the TLV62150 is entered seamlessly, if the load current decreases. This
secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor
current is discontinuous.
In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in
both directions.
TLV62150 includes a fixed on-time circuitry. This on-time, in steady-state operation, can be estimated (for
FSW=Low) as:
spacing
t ON =
VOUT
´ 400 ns
VIN
(1)
For very small output voltages, an absolute minimum on-time of about 80 ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also the off-time can
reach its minimum value at high duty cycles. The output voltage remains regulated in such cases. Using tON, the
typical peak inductor current in Power Save Mode can be approximated by:
spacing
I LPSM(peak) =
(VIN - VOUT )
´ t ON
L
(2)
When VIN decreases to typically 15% above VOUT, the TLV62150 does not enter Power Save Mode, regardless
of the load current. The device maintains output regulation in PWM mode.
8.4.3 100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to
the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal
setpoint. This allows the conversion of small input to output voltage differences, for example, for longest
operation time of battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
spacing
spacing
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
spacing
(
VIN(min) = VOUT(min) + I OUT RDS(on) + RL
)
where
•
•
•
IOUT is the output current.
RDS(on) is the RDS(on) of the high-side FET.
RL is the DC resistance of the inductor used.
(3)
spacing
8.4.4 Current Limit and Short Circuit Protection
The TLV62150 devices are protected against heavy load and short circuit events. At heavy loads, the current
limit determines the maximum output current. If the current limit is reached, the high-side FET is turned off.
Avoiding shoot through current, then the low-side FET switches on to allow the inductor current to decrease. The
low-side current limit is typically 1.2 A. The high-side FET turns on again, only if the current in the low-side FET
has decreased below the low side current limit threshold.
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Device Functional Modes (continued)
The output current of the device is limited by the current limit (see Electrical Characteristics). Due to internal
propagation delay, the actual current can exceed the static current limit during that time. The dynamic current
limit can be calculated as follows:
spacing
Ipeak(typ) = I LIMF +
VL
´ tPD
L
where
•
•
•
•
ILIMF is the static current limit, specified in the Electrical Characteristics.
L is the inductor value.
VL is the voltage across the inductor (VIN - VOUT).
tPD is the internal propagation delay.
(4)
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high side switch the peak current can be calculated as follows:
spacing
Ipeak(typ) = I LIMF +
12
(VIN - VOUT )
L
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´ 30ns
(5)
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9 Application and Implementation
spacing
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
spacing
9.1 Application Information
The TLV62150 is a switched-mode step-down converter, able to convert a 4-V to 17-V input voltage into a 0.9-V
to 5-V output voltage, providing up to 1 A. It needs a minimum amount of external components. Apart from the
LC output filter and the input capacitor, the TLV62150 (TLV62150A) needs an additional resistive divider to set
the output voltage level.
9.2 Typical Application
Figure 5 shows an application for Point-of-Load Power Supply Using TLV62150.
spacing
1 / 2.2 µH
(4 .. 17)V
C1
10uF
PVIN
SW
AVIN
VOS
EN
VOUT / 1A
R3
100k
PG
R1
TLV62150
SS/TR
C5
3.3nF
C3
22uF
FB
DEF
AGND
FSW
PGND
R2
Figure 5. 1-A Step-Down Converter
spacing
9.2.1 Design Requirements
The following design guideline provides a component selection to operate the device within the recommended
operating conditions. Using the FSW pin, the design can be optimized for highest efficiency or smallest solution
size and lowest output voltage ripple. For highest efficiency set FSW=High and the device operates at the lower
switching frequency. For smallest solution size and lowest output voltage ripple set FSW=Low and the device
operates with higher switching frequency. The typical values for all measurements are VIN = 12 V, VOUT = 3.3 V
and T = 25°C, using the external components of Table 3.
9.2.2 Detailed Design Procedure
The component selection used for measurements is given as follows:
Table 3. List of Components
MANUFACTURER (1)
REFERENCE
DESCRIPTION
IC
17-V, 1-A Step-Down Converter, VQFN
L1
2.2 µH, 0.165 × 0.165 in
C1
10 µF, 25 V, Ceramic
Standard
C3
22 µF, 6.3 V, Ceramic
Standard
(1)
TLV62150RGT, Texas Instruments
XFL4020-222MEB, Coilcraft
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Typical Application (continued)
Table 3. List of Components (continued)
MANUFACTURER (1)
REFERENCE
DESCRIPTION
C5
3300 pF, 25 V, Ceramic
R1
depending on Vout
R2
depending on Vout
R3
100 kΩ, Chip, 0603, 1/16 W, 1%
Standard
9.2.2.1 Programming the Output Voltage
The output voltage of the TLV62150 (TLV62150A) is adjustable. It can be programmed for output voltages from
0.9 V to 5 V by using a resistive divider from VOUT to AGND. The voltage at the FB pin is regulated to 800 mV.
The value of the output voltage is set by the selection of the resistive divider from Equation 6. It is recommended
to choose resistor values which allow a current of at least 2 µA, meaning the value of R2 should not exceed 400
kΩ. Lower resistor values are recommended for highest accuracy and most robust design.
ö
æV
R1 = R 2 ç OUT - 1÷
è 0.8V ø
(6)
In case the FB pin gets opened, the device clamps the output voltage at the VOS pin internally to about 7.4 V.
9.2.2.2 External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the devices
control loop. The TLV62150 is optimized to work within a range of external components. The LC output filter's
inductance and capacitance have to be considered in conjunction, creating a double pole, responsible for the
corner frequency of the converter (see Output Filter and Loop Stability section). Table 4 can be used to simplify
the output filter component selection. Checked cells represent combinations that are proven for stability by
simulation and lab test. Further combinations should be checked for each individual application. See SLVA463
for details.
Table 4. L-C Output Filter Combinations (1)
4.7 µF
10 µF
22 µF
47 µF
100 µF
200 µF
√
√
√
√
2.2 µH
√
√ (2)
√
√
√
3.3 µH
√
√
√
√
400 µF
0.47 µH
1 µH
4.7 µH
(1)
(2)
The values in the table are nominal values. The effective capacitance was considered to vary by +20% and -50%.
This LC combination is the standard value and recommended for most applications.
spacing
The TLV62150 can be run with an inductor as low as 1 µH or 2.2 µH. FSW should be set Low in this case.
However, for applications running with the low frequency setting (FSW=High) or with low input voltages, 3.3 µH is
recommended.
9.2.2.2.1 Inductor Selection
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-toPSM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under
static load conditions.
spacing
IL(max) = IOUT(max) +
14
DIL(max)
2
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(7)
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VOUT
æ
ç 1- V
IN(max)
DI L(max) = VOUT ´ ç
ç L(min) ´ fSW
çç
è
ö
÷
÷
÷
÷÷
ø
where
•
•
•
•
IL(max) is the maximum inductor current.
ΔIL is the Peak to Peak Inductor Ripple Current.
L(min) is the minimum effective inductor value.
fSW is the actual PWM Switching Frequency.
(8)
spacing
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TLV62150 and are recommended for use:
Table 5. List of Inductors
(1)
(2)
Type
Inductance [µH]
Saturation Current
[A] (1)
Dimensions [L x B x
H] mm
MANUFACTURER (2)
XFL4020-222ME_
2.2 µH, ±20%
3.5
4 × 4 × 2.1
Coilcraft
XFL3012-222MEC
2.2 µH, ±20%
1.6
3 × 3 × 1.2
Coilcraft
XFL3012-332MEC
3.3 µH, ±20%
1.4
3 × 3 × 1.2
Coilcraft
VLS252012T-2R2M1R3
2.2 µH, ±20%
1.3
2.5 × 2 × 1.2
TDK
LPS3015-332
3.3 µH, ±20%
1.4
3 × 3 × 1.4
Coilcraft
744025003
3.3 µH, ±20%
1.5
2.8 × 2.8 × 2.8
Wuerth
PSI25201B-2R2MS
2.2 µH, ±20%
1.3
2 × 2.5 × 1.2
Cyntec
NR3015T-2R2M
2.2 µH, ±20%
1.5
3 × 3 × 1.5
Taiyo Yuden
Lower of IRMS at 40°C rise or ISAT at 30% drop.
See Third-Party Products Disclaimer
spacing
The inductor value also determines the load current at which Power Save Mode is entered:
1
I load(PSM) = DI L
2
(9)
Using Equation 8, this current level can be adjusted by changing the inductor value.
9.2.2.2.2 Capacitor Selection
9.2.2.2.2.1 Output Capacitor
The recommended value for the output capacitor is 22 µF. The architecture of the TLV62150 allows the use of
tiny ceramic output capacitors which have low equivalent series resistance (ESR). These capacitors provide low
output voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it's recommended to use X7R or X5R dielectric. Using a higher value can
have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see
SLVA463).
Note: In power save mode, the output voltage ripple depends on the output capacitance, Its ESR and the peak
inductor current. Using ceramic capacitors provides small ESR and low ripple.
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9.2.2.2.2.2 Input Capacitor
For most applications, 10 µF will be sufficient and is recommended, though a larger value reduces input current
ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter
from the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied
from the same input source, it's recommended to place a capacitance of 0.1 uF from AVIN to AGND, to avoid
potential noise coupling. An RC, low-pass filter from PVIN to AVIN may be used but is not required.
9.2.2.2.2.3 Soft-Start Capacitor
A capacitance connected between SS/TR pin and AGND allows a user programmable start-up slope of the
output voltage. A constant current source supports 2.5 µA to charge the external capacitance. The capacitor
required for a given soft-start ramp time for the output voltage is given by:
2.5mA
CSS = t SS ´
éF ù
1.25V ë û
where
•
•
CSS is the capacitance (F) required at the SS/TR pin.
tSS is the desired soft-start ramp time (s).
(10)
spacing
spacing
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
spacing
9.2.2.3 Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50 mV and 1.2 V, the
FB pin will track the SS/TR pin voltage as described in Equation 11 and shown in Figure 6.
spacing
VFB » 0.64 ´ VSS/TR
(11)
spacing
VSS/TR
[V]
1.2
0.8
0.4
0.2
0.4
0.6
VFB [V]
0.8
Figure 6. Voltage Tracking Relationship
16
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Once the SS/TR pin voltage reaches about 1.2 V, the internal voltage is clamped to the internal feedback voltage
and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior,
as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage,
the device does not sink current from the output. So, the resulting decrease of the output voltage may be slower
than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not
exceed the voltage rating of the SS/TR pin which is VIN+0.3 V.
If the input voltage drops into undervoltage lockout or even down to zero, the output voltage will go to zero,
independent of the tracking voltage. Figure 7 shows how to connect devices to get ratiometric and simultaneous
sequencing by using the tracking function.
spacing
VOUT1
PVIN
SW
AVIN
VOS
EN
PG
TLV62150
SS/TR
FB
DEF
AGND
FSW
PGND
PVIN
SW
AVIN
VOS
VOUT2
PG
EN
R1
TLV62150
SS/TR
R2
FB
DEF
AGND
FSW
PGND
Figure 7. Sequence for Ratiometric and Simultaneous Startup
The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower or the same as
VOUT1.
A sequential startup is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. Ratiometric start
up sequence happens if both supplies are sharing the same soft start capacitor. Equation 10 calculates the soft
start time, though the SS/TR current has to be doubled. Details about these and other tracking and sequencing
circuits are found in SLVA470.
Note: If the voltage at the FB pin is below its typical value of 0.8 V, the output voltage accuracy may have a
wider tolerance than specified.
9.2.2.4 Output Filter and Loop Stability
The TLV62150 is internally compensated to be stable with L-C filter combinations corresponding to a corner
frequency to be calculated with Equation 12:
1
f LC =
2p L ´ C
(12)
Proven nominal values for inductance and ceramic capacitance are given in Table 4 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which will be affected. More
information including a detailed L-C stability matrix can be found in SLVA463.
The TLV62150 includes an internal 25 pF feedforward capacitor, connected between the VOS and FB pins. This
capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors of the
feedback divider, per equation Equation 13 and Equation 14:
spacing
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fzero =
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1
2p ´ R1 ´ 25pF
(13)
æ 1
1
1 ö
´ç
+
÷
2π ´ 25pF è R1 R2 ø
(14)
spacing
fpole =
spacing
Though the TLV62150 is stable without the pole and zero being in a particular location, adjusting their location to
the specific needs of the application can provide better performance in Power Save mode and/or improved
transient response. An external feedforward capacitor can also be added. A more detailed discussion on the
optimization for stability versus transient response can be found in SLVA289 and SLVA466.
18
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9.2.3 Application Curves
VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
100
100
90
90
80
70
VIN = 12 V
VIN = 17 V
Efficiency (%)
Efficiency (%)
80
60
50
40
70
60
30
30
20
20
10
10
0
0.0001
0.001
0.01
Output Current (A)
0.1
0
1
100
100
90
90
80
80
70
VIN = 17 V
60
50
VIN = 12 V
40
20
10
0
1
Figure 10. Efficiency With 2.5 MHz, Vout = 5 V
100
90
90
70
VIN = 12 V
VIN = 17 V
Efficiency (%)
Efficiency (%)
16
17
IOUT = 10 mA
IOUT = 1 A
IOUT = 100 mA
7
8
9
10
11
12
13
14
Input Voltage (V)
15
16
17
80
80
VIN = 5 V
50
40
60
20
10
10
0.1
Figure 12. Efficiency With 1.25 MHz, Vout = 3.3 V
1
IOUT = 1 mA
IOUT = 10 mA
40
30
0.01
Output Current (A)
IOUT = 100 mA
50
20
0.001
IOUT = 1 A
70
30
0
0.0001
15
Figure 11. Efficiency With 2.5 MHz, Vout = 5 V
100
60
11
12
13
14
Input Voltage (V)
40
10
0.1
10
50 IOUT = 1 mA
30
0.01
Output Current (A)
9
60
20
0.001
8
70
30
0
0.0001
7
IOUT = 100 mA
Figure 9. Efficiency With 1.25 MHz, Vout = 5 V
Efficiency (%)
Efficiency (%)
Figure 8. Efficiency With 1.25 MHz, Vout = 5 V
IOUT = 1 A
IOUT = 10 mA
50 IOUT = 1 mA
40
0
4
5
6
7
8
9 10 11 12 13 14 15 16 17
Input Voltage (V)
Figure 13. Efficiency With 1.25 MHz, Vout = 3.3 V
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100
100
90
90
80
80
70
70
60
VIN = 12 V
50
Efficiency (%)
Efficiency (%)
VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
VIN = 17 V
VIN = 5 V
40
60
30
20
20
10
10
0.001
0.01
Output Current (A)
0.1
0
1
4
100
100.0
90
90.0
80
80.0
70
VIN = 12 V
50
VIN = 17 V
VIN = 5 V
40
20.0
10.0
0.0
1
100.0
90
90.0
80
80.0
70
70.0
VIN = 17 V
50
40
VIN = 5 V
20.0
10
10.0
0.0
0.1
Figure 18. Efficiency With 1.25 MHz, Vout = 0.9 V
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5
6
7
8
IOUT=10mA
IOUT=1mA
9 10 11 12 13 14 15 16 17
Input Voltage (V)
G001
1
IOUT=1A
IOUT=100mA
40.0
20
0.01
Output Current (A)
4
50.0
30.0
0.001
IOUT=100mA
VOUT=1.8V
L=2.2uH (XFL4020)
Cout=22uF
60.0
30
0
0.0001
20
Efficiency (%)
Efficiency (%)
100
VIN = 12 V
9 10 11 12 13 14 15 16 17
Input Voltage (V)
Figure 17. Efficiency With 1.25 MHz, Vout = 1.8 V
Figure 16. Efficiency With 1.25 MHz, Vout = 1.8 V
60
8
40.0
10
0.1
7
50.0
30.0
0.01
Output Current (A)
6
IOUT=1A
60.0
20
0.001
5
70.0
30
0
0.0001
IOUT = 1 A
Figure 15. Efficiency With 2.5 MHz, Vout = 3.3 V
Efficiency (%)
Efficiency (%)
Figure 14. Efficiency With 2.5 MHz, Vout = 3.3 V
60
IOUT = 1 mA
IOUT = 10 mA
40
30
0
0.0001
IOUT = 100 mA
50
IOUT=10mA
IOUT=1mA
VOUT=0.9V
L=2.2uH (XFL4020)
Cout=22uF
4
5
6
7
8
9 10 11 12 13 14 15 16 17
Input Voltage (V)
G001
Figure 19. Efficiency With 1.25 MHz, Vout=0.9 V
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VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
3.4
3.4
Output Voltage (V)
Output Voltage (V)
VIN = 17 V
3.35
3.3
VIN = 5 V
VIN = 12 V
3.25
3.2
0.0001
0.001
0.01
Output Current (A)
0.1
IOUT = 1 A
3.25
4
4
3.5
3.5
3
2.5
2
IOUT = 0.5 A
IOUT = 1 A
1.5
1
0.5
4
7
10
13
Input Voltage (V)
16
3
2.5
2
1.5
1
0.5
0
4
6
8
10
12
Input Voltage (V)
14
16
0
18
FSW=Low
0
0.2
0.8
1
Figure 23. Switching Frequency
3
0.05
2.5
Output Current (A)
0.04
0.03
VIN = 17 V
0.02
0.01
2
−40°C
0
0.1
0.2
0.3
25°C
1.5
1
85°C
0.5
VIN = 5 V
0
0.5
Output Current (A)
FSW=Low
Figure 22. Switching Frequency
Output Voltage Ripple (V)
IOUT = 100 mA
Figure 21. Output Voltage Accuracy (Line Regulation)
Switching Frequency (MHz)
Switching Frequency (MHz)
Figure 20. Output Voltage Accuracy (Load Regulation)
IOUT = 10 mA
3.3
3.2
1
IOUT = 1 mA
3.35
VIN = 12 V
0.4 0.5 0.6 0.7
Output Current (A)
0.8
Figure 24. Output Voltage Ripple
0.9
1
0
4
5
6
7
8
9 10 11 12 13 14 15 16 17
Input Voltage (V)
Figure 25. Maximum Output Current
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VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
100
100
90
VIN=17V
PSRR (dB)
PSRR (dB)
70
60
50
40
30
VIN=17V
60
50
40
30
20
20
VOUT=3.3V, IOUT=1A
L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF
10
10
100
1k
10k
Frequency (Hz)
VOUT=3.3V, IOUT=0.1A
L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF
10
100k
1M
0
10
100
G000
IOUT = 1 A
22
VIN=5V
80
VIN=12V
70
0
VIN=12V
90
VIN=5V
80
1k
10k
Frequency (Hz)
100k
1M
G000
IOUT = 0.1 A
Figure 26. Power Supply Rejection Ratio, FSW = 2.5 MHz
Figure 27. Power Supply Rejection Ratio, FSW = 2.5 MHz
Figure 28. PWM-PSM-Transition
(VIN = 12 V, VOUT = 3.3 V With 50 mV/div)
Figure 29. Load Transient Response
(IOUT= 0.5 to 1 to 0.5 A, VIN = 12 V, VOUT = 3.3 V)
Figure 30. Load Transient Response of Figure 29,
Rising Edge
Figure 31. Load Transient Response of Figure 29,
Falling Edge
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VIN = 12 V, VOUT = 3.3 V, TA = 25°C, (unless otherwise noted)
Figure 32. Startup Into 100 mA
Figure 33. Startup Into 1 A
Figure 34. Typical Operation In PWM Mode
(IOUT = 1 A)
Figure 35. Typical Operation in Power Save Mode
(IOUT = 10 mA)
9.3 System Examples
9.3.1 LED Power Supply
The TLV62150x can be used as a power supply for power LEDs. The FB pin can be easily set down to lower
values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid
excessive power loss. Since this pin provides 2.5 µA, the FB pin voltage can be adjusted by an external resistor
per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode
voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TLV62150.
Figure 36 shows an application circuit, tested with analog dimming:
spacing
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System Examples (continued)
(4 .. 17) V
2.2µH
10uF
PVIN
SW
AVIN
VOS
PG
EN
ADIM
22uF
TLV62150
FB
SS/TR
187k
DEF
AGND
FSW
PGND
0.3R
Figure 36. 1-A Single LED Power Supply
spacing
The resistor at SS/TR sets the FB voltage to a level of about 300 mV and is calculated from Equation 15.
spacing
VFB = 0.64 ´ 2.5mA ´ RSS/TR
(15)
spacing
The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage
accordingly. The minimum input voltage has to be rated according the forward voltage needed by the LED used.
More information is available in the Application Note SLVA451.
spacing
9.3.2 Active Output Discharge
The TLV62150A pulls the PG pin Low, when the device is shut down by EN, UVLO or thermal shutdown.
Connecting PG to Vout through a resistor can be used to discharge Vout in those cases (see Figure 37). The
discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability,
keep the maximum current into the PG pin less than 10 mA.
(4 .. 17)V
1 / 2.2 µH
PVIN
Vout / 1A
SW
TLV62150A
AVIN
10uF
3.3nF
VOS
EN
PG
SS/TR
FB
DEF
AGND
FSW
PGND
R3
R1
22uF
R2
Figure 37. Discharge Vout Through PG Pin with TLV62150A
9.3.3 Inverting Power Supply
The TLV62150 can be used as inverting power supply by rearranging external circuitry as shown in Figure 38. As
the former GND node now represents a voltage level below system ground, the voltage difference between VIN
and VOUT has to be limited for operation to the maximum supply voltage of 17 V (see Equation 16).
spacing
VIN + VOUT £ VIN max
(16)
spacing
24
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System Examples (continued)
10uF
2.2µH
(4 .. 12)V
PVIN
SW
AVIN
VOS
10uF
680k
PG
EN
TLV62150
22uF
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
130k
-5V
Figure 38. –5-V Inverting Power Supply
spacing
The transfer function of the inverting power supply configuration differs from the buck mode transfer function,
incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output
capacitance of at least 22 µF is recommended. A detailed design example is given in SLVA469.
spacing
9.3.4 Various Output Voltages
The following example circuits show how to configure the external circuitry to furnish different output voltages at
1 A.
spacing
spacing
1 / 2.2 µH
(5 .. 17)V
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
5V / 1A
680k
22uF
TLV62150
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
130k
Figure 39. 5-V/1-A Power Supply
spacing
spacing
1 / 2.2 µH
(4 .. 17)V
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
3.3V / 1A
750k
22uF
TLV62150
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
240k
Figure 40. 3.3-V/1-A Power Supply
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System Examples (continued)
spacing
spacing
1 / 2.2 µH
(4 .. 17)V
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
2.5V / 1A
510k
22uF
TLV62150
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
240k
Figure 41. 2.5-V/1-A Power Supply
spacing
spacing
1 / 2.2 µH
(4 .. 17)V
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
1.8V / 1A
300k
22uF
TLV62150
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
240k
Figure 42. 1.8-V/1-A Power Supply
spacing
spacing
spacing
spacing
1 / 2.2 µH
(4 .. 17)V
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
1.5V / 1A
130k
22uF
TLV62150
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
150k
Figure 43. 1.5-V/1-A Power Supply
spacing
spacing
26
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System Examples (continued)
1 / 2.2 µH
(4 .. 17)V
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
1.2V / 1A
75k
22uF
TLV62150
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
150k
Figure 44. 1.2-V/1-A Power Supply
spacing
spacing
1 / 2.2 µH
(4 .. 17)V
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
1V / 1A
51k
22uF
TLV62150
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
200k
Figure 45. 1-V/1-A Power Supply
spacing
10 Power Supply Recommendations
The TLV6215X are designed to operate from a 4-V to 17-V input voltage supply. The input power supply's output
current needs to be rated according to the output voltage and the output current of the power rail application.
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11 Layout
11.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TLV62150 demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity.
See Figure 46 for the recommended layout of the TLV62150, which is designed for common external ground
connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the
PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system
ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to VOUT at the output
capacitor. To avoid noise coupling into the VOS line, this connection should be separated from the VOUT power
line/plane as shown in Layout Example.
Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load
current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an
alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (e.g.
SW). As they carry information about the output voltage, they should be connected as close as possible to the
actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB
resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground
plane.
The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve
appropriate power dissipation.
The recommended layout is implemented on the EVM and shown in its Users Guide, SLAU416. Additionally, the
EVM Gerber data are available for download here, SLVC394.
11.2 Layout Example
AGND
C5
R1
FB
AGND
DEF
SS/TR
PG
AVIN
SW
PGND
SW
PGND
SW
PVIN
EN
PVIN
VOS
VIN
FSW
R2
C3
C1
L1
VOUT
GND
Figure 46. Layout Example Recommendation
28
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11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the Exposed Thermal Pad
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: thermal characteristics
application note (SZZA017), and (SPRA953).
The TLV62150 is designed for a maximum operating junction temperature (Tj) of 125°C. Therefore the maximum
output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by
the package and the surrounding PCB structures. Since the thermal resistance of the package is fixed,
increasing the size of the surrounding copper area and improving the thermal connection to the IC can reduce
the thermal resistance. To get an improved thermal behavior, it's recommended to use top layer metal to connect
the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for
improved thermal performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 6. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV62150
Click here
Click here
Click here
Click here
Click here
TLV62150A
Click here
Click here
Click here
Click here
Click here
12.3 Documentation Support
12.3.1 Related Documentation
For related documentation, see the following:
• TLV62130EVM-505 and TLV62150EVM-505 Evaluation Modules, SLAU416
• EVM Gerber data, SLVC394
• Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs, SZZA017
• Semiconductor and IC Package Thermal Metrics, SPRA953
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
DCS-Control, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
30
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12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV62150ARGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
VUOI
TLV62150ARGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
VUOI
TLV62150RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
VUCI
TLV62150RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
VUCI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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