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TLV6713
SBVS331B – JANUARY 2018 – REVISED JULY 2018
TLV6713 Micropower, 36-V Comparator With 400-mV Reference
1 Features
3 Description
•
•
•
The TLV6713 high voltage comparator operates over
a 1.8-V to 36-V range. The device has a precision
comparator with an internal 400-mV reference and an
open-drain output rated to 25 V for undervoltage
detection. Set the monitored voltage with the use of
external resistors.
1
•
•
•
•
•
High Supply Voltage Range: 1.8 V to 36 V
Adjustable Threshold: Down to 400 mV
High Threshold Accuracy:
– 0.25% (Typ)
– 0.75% Max Over Temperature
Low Quiescent Current: 7 µA (Typ)
Open-Drain Output
Internal Hysteresis: 5.5 mV (Typ)
Temperature Range: –40°C to +125°C
Package: Thin SOT-23-6
OUT is driven low when the voltage at the SENSE
pin drops below the negative threshold, and goes
high when the voltage returns above the positive
threshold. The comparator in the TLV6713 includes
built-in hysteresis for noise rejection, thereby
ensuring stable output operation without false
triggering.
2 Applications
•
•
•
•
•
•
•
•
The TLV6713 is available in a Thin SOT-23-6
package and is specified over the junction
temperature range of –40°C to +125°C.
Notebook PCs and Tablets
Smartphones
Digital Cameras
Video Game Controllers
Relays and Circuit Breakers
Portable Medical Devices
Door and Window Sensors
Portable- and Battery-Powered Products
Device Information
PART NUMBER
TLV6713
PACKAGE
SOT-23 (6)
(1)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Typical Application
VMON
0.01 F
VPULLUP
Up to 25 V
VDD
R1
RP
SENSE
OUT
R2
VIT
+
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV6713
SBVS331B – JANUARY 2018 – REVISED JULY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
Changes from Revision A (April 2018) to Revision B
•
Page
Changed Typical Application graphic pull-up resistor text from 36V to 25V .......................................................................... 1
Changes from Original (January 2018) to Revision A
•
Page
Changed Advance Information to Production Data ............................................................................................................... 1
5 Device Comparison Table
Table 1. TLV67xx Integrated Comparator Family
CONFIGURATION
OPERATING
VOLTAGE RANGE
THRESHOLD ACCURACY OVER
TEMPERATURE
TLV6700
Window
1.8 V to 18 V
1%
TLV6703
Non-Inverting Single Channel
1.8 V to 18 V
1%
TLV6710
Window
1.8 V to 36 V
0.75%
TLV6713
Non-Inverting Single Channel
1.8 V to 36 V
0.75%
PART NUMBER
2
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SBVS331B – JANUARY 2018 – REVISED JULY 2018
6 Pin Configuration and Functions
DDC Package
6-Pin SOT-23-Thin
Top View
OUT
1
6
GND
GND
2
5
VDD
SENSE
3
4
GND
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
2, 4, 6
—
Ground. Connect all three pins to ground.
OUT
1
O
Comparator open-drain output. This pin is driven low when the voltage at this comparator is
less than VIT–. The output goes high when the sense voltage rises above VIT+.
SENSE
3
I
Comparator input. This pin is connected to the voltage to be monitored with the use of an
external resistor divider. When the voltage at this pin drops below the threshold voltage VIT–,
OUT is driven low.
VDD
5
I
Supply-voltage input. Connect a 1.8-V to 36-V supply to VDD to power the device. It is good
analog design practice to place a 0.1-µF ceramic capacitor close to this pin.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating junction temperature range (unless otherwise noted)
Voltage
(2)
Current
(2)
MAX
–0.3
40
VOUT
–0.3
28
VSENSE
–0.3
7
Output pin current
Temperature
(1)
MIN
VDD
UNIT
V
40
mA
Operating junction, TJ
–40
125
Storage, Tstg
–40
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
VDD
Supply pin voltage
VSENSE
NOM
MAX
UNIT
1.8
36
V
Input pin voltage
0
1.7
V
VOUT
Output pin voltage
0
25
V
VPULLUP
Pullup voltage
0
25
V
IOUT
Output pin current
0
10
mA
TJ
Junction temperature
125
°C
–40
25
7.4 Thermal Information
TLV6713
THERMAL METRIC
(1)
DDC (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
201.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47.8
°C/W
RθJB
Junction-to-board thermal resistance
51.2
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
50.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to +125°C, 1.8 V ≤ VDD < 36 V, and pullup resistor RP = 100 kΩ (unless
otherwise noted). Typical values are at TJ = 25°C and VDD = 12 V.
PARAMETER
TEST CONDITIONS
MIN
V(POR)
Power-on reset voltage (1)
VOL ≤ 0.2 V
VIT–
SENSE pin negative input threshold voltage
VDD = 1.8 V to 36 V
397
VIT+
SENSE pin positive input threshold voltage
VDD = 1.8 V to 36 V
400
VHYS
SENSE pin hysteresis voltage
(HYS = VIT+ – VIT–)
2
VOL
Low-level output voltage
IIN
Input current (at SENSE pin)
ID(leak)
Open-drain leakage current
VDD = 1.8 V and 36 V, VOUT = 25 V
IDD
Supply current
VDD = 1.8 V – 36 V
UVLO
Undervoltage lockout (2)
VDD falling
(1)
(2)
TYP
MAX
UNIT
0.8
V
400
403
mV
405.5
413
mV
5.5
12
mV
VDD = 1.8 V, IOUT = 3 mA
130
250
VDD = 5 V, IOUT = 5 mA
150
250
mV
VDD = 1.8 V and 36 V, VSENSE = 6.5 V
–25
+1
+25
VDD = 1.8 V and 36 V, VSENSE = 0.1 V
–15
+1
+15
10
300
nA
8
11
µA
1.5
1.7
V
MAX
UNIT
1.3
nA
The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. If less than V(POR), the output is undetermined.
When VDD falls below UVLO, OUT is driven low. The output cannot be determined if less than V(POR).
7.6 Timing Requirements
MIN
NOM
tpd(HL)
High-to-low propagation delay (1)
VDD = 24 V, ±10-mV input overdrive,
RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV
tpd(LH)
Low-to-high propagation delay (1)
VDD = 24 V, ±10-mV input overdrive,
RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV
28.1
µs
td(start) (2)
Startup delay
VDD = 5 V
155
µs
tr
Output rise time
VDD = 12 V, 10-mV input overdrive,
RL = 100 kΩ, CL = 10 pF, VO = (0.1 to 0.9) × VDD
2.7
µs
tf
Output fall time
VDD = 12 V, 10-mV input overdrive,
RL = 100 kΩ, CL = 10 pF, VO = (0.9 to 0.1) × VDD
0.12
µs
(1)
(2)
9.9
µs
High-to-low and low-to-high refers to the transition at the input pin (SENSE).
During power on, VDD must exceed 1.8 V for at least 150 µs (typical) before the output state reflects the input condition.
VDD
V(POR)
VIT+
SENSE
V HYS
VIT±
OUT
t pd(LH)
t pd(HL)
t pd(LH)
t d(start)
Figure 1. Timing Diagram
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7.7 Typical Characteristics
10
10
9
9
8
8
Minimum Pulse Width (Ps)
Supply Current (PA)
at TJ = 25°C and VDD = 12 V (unless otherwise noted)
7
6
5
4
3
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
2
1
7
6
5
4
3
2
1
0
0
0
4
8
12
16
20
24
Supply Voltage (V)
28
32
36
0
5
10
15
20
25
30
Overdrive (%)
35
40
45
50
VDD = 24 V, minimum pulse duration required to trigger output
high-to-low transition, SENSE = negative spike below VIT–
Figure 3. Minimum Pulse Duration vs
Threshold Overdrive Voltage
Figure 2. Supply Current vs Supply Voltage
400
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
408.5
408
Negative-Going Input Threshold (mV)
Positive-Going Input Threshold (mV)
409
407.5
407
406.5
406
405.5
405
404.5
404
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
399.9
399.8
399.7
399.6
399.5
399.4
399.3
399.2
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
399.1
399
-40
110 125
Figure 4. SENSE Positive Input Threshold Voltage (VIT+) vs
Temperature
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
Figure 5. SENSE Negative Input Threshold Voltage (VIT–) vs
Temperature
3500
4500
4000
3000
3500
3000
2000
Count
Count
2500
1500
2500
2000
1500
1000
1000
500
500
VDD = 1.8 V
402
401
400
VIT- Threshold (mV)
VDD = 1.8 V
Figure 6. SENSE Positive Input Threshold Voltage (VIT+)
Distribution
6
399
398
408
VIT+ Threshold (mV)
407
406
405
0
404
0
Figure 7. SENSE Negative Input Threshold Voltage (VIT–)
Distribution
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Typical Characteristics (continued)
at TJ = 25°C and VDD = 12 V (unless otherwise noted)
3
VDD = 1.8 V
VDD = 36 V
Low-to-High Propagation Delay (µs)
High-to-Low Propagation Delay (µs)
12
10
8
6
4
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
2.5
2
1.5
1
0.5
VDD = 1.8V
VDD = 36 V
0
-40
110 125
-25
-10
5
Input step ±200 mV
80
95
110 125
Input step ±200 mV
Figure 8. Propagation Delay vs Temperature
(High-to-Low Transition at SENSE)
Figure 9. Propagation Delay vs Temperature
(Low-to-High Transition at SENSE)
0.6
0.6
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0.5
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0.5
0.4
VOL (V)
0.4
VOL (V)
20 35 50 65
Temperature (qC)
0.3
0.3
0.2
0.2
0.1
0.1
0
0
0
1
2
3
4
5
6
7
Output Sink Current (mA)
8
9
10
0
1
2
VDD = 1.8 V
3
4
5
6
7
Output Sink Current (mA)
8
9
10
VDD = 12 V
Figure 10. Output Voltage Low vs Output Sink Current
Figure 11. Output Voltage Low vs Output Sink Current
195
Startup Delay (Ps)
180
165
150
135
120
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
VDD = 5 V
Figure 12. Start-up Delay vs Temperature
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8 Detailed Description
8.1 Overview
The TLV6713 combines a comparator and a precision reference for undervoltage detection. The TLV6713
features a wide supply voltage range (1.8 V to 36 V) and a high-accuracy threshold voltage of 400 mV (0.75%
over temperature) with built-in hysteresis. The output is rated to 25 V and can sink up to 10 mA.
Set the input pin (SENSE) to monitor any voltage above 0.4 V by using an external resistor divider network.
SENSE has very low input leakage current, allowing the use of a large resistor divider without sacrificing system
accuracy. The relationship between the input and the output is shown in Table 2. Broad voltage thresholds are
supported that enable the device to be used in a wide array of applications.
Table 2. Truth Table
CONDITION
OUTPUT
SENSE > VIT+
OUT high
Output high impedance
OUTPUT STATE
SENSE < VIT–
OUT low
Output sinking
8.2 Functional Block Diagram
VDD
SENSE
OUT
VIT-
GND
8
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8.3 Feature Description
8.3.1 Input Pin (SENSE)
The TLV6713 combines a comparator with a precision reference voltage. The comparator has one external input
and one internal input connected to the internal reference. The falling threshold on SENSE is designed and
trimmed to be equal to the reference voltage (400 mV). This configuration optimizes the device accuracy. The
comparator also has built-in hysteresis that proves immunity to noise and ensures stable operation.
The comparator input swings from ground to 1.7 V (7 V absolute maximum), regardless of the device supply
voltage used. Although not required in most cases, it is good analog design practice to place a 1-nF to 10-nF
bypass capacitor at the comparator input for noisy applications to reduce sensitivity to transient voltage changes
on the monitored signal.
For the comparator, the output (OUT) is driven to logic low when the input SENSE voltage drops below VIT–.
When the voltage exceeds VIT+, OUT goes to a high-impedance state; see Figure 1.
8.3.2 Output Pin (OUT)
In a typical TLV6713 application, the output is connected to a GPIO input of the processor (such as a digital
signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or applicationspecific integrated circuit [ASIC]).
The TLV6713 provides an open-drain output (OUT) rated to 25 V, independant of supply voltage, and can sink
up to 40 mA.. A pullup resistor is required to hold the line high when the output goes to a high-impedance state.
Connect this pullup resistor to a voltage rail that meets the logic requirements of the downstream device. To
ensure the proper voltage level, give some consideration when choosing the pullup resistor value. The pullup
resistor value is determined by VOL, output capacitive loading, and the open-drain leakage current (ID(leak)). These
values are specified in the Electrical Characteristics table.
Table 2 and Input Pin (SENSE) describe how the output is asserted or high impedance. See Figure 1 for a timing
diagram that describes the relationship between threshold voltage and the respective output.
8.4 Device Functional Modes
8.4.1 Normal Operation (VDD > UVLO)
When the voltage on VDD is greater than 1.8 V for at least 155 µs, the OUT signal corresponds to the voltage on
SENSE, as listed in Table 2.
8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,
V(POR), the OUT signal is asserted regardless of the voltage on SENSE.
8.4.3 Power On Reset (VDD < V(POR))
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND
(V(POR)), OUT is in a high-impedance state.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLV6713 is used as a precision voltage supervisor in several different configurations. The monitored voltage
(VMON), VDD voltage, and output pullup voltage can be independent voltages or connected in any configuration.
The following sections show the connection configurations and the voltage limitations for each configuration.
9.1.1 Input and Output Configurations
Figure 13 and Figure 14 show examples of the various input and output configurations.
1.8 V to 25 V
0.01 F
RP
R1
VDD
SENSE
OUT
R2
GND
Figure 13. Monitoring the Same Voltage as VDD
10
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Application Information (continued)
1.8 V to 36 V
VMON
0.01 F
VPULLUP
0 V to 25 V
RP
VDD
R1
SENSE
OUT
R2
GND
NOTE: The input can monitor a voltage higher than VDD (maximum) with the use of an external resistor divider
network.
Figure 14. Monitoring a Voltage Other than VDD
9.1.2 Immunity to Input Pin Voltage Transients
The TLV6713 is immune to short voltage transient spikes on the input pin. Sensitivity to transients depends on
both transient duration and amplitude; see Figure 3, Minimum Pulse Duration vs Threshold Overdrive Voltage.
9.2 Typical Application
VMON
24 V
0.01 F
VPULLUP
3.3 V
+
±
2 MŸ
100 kŸ
VDD
SENSE
OUT
37.4 kŸ
GND
Figure 15. 24-V, 10% Comparator
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Typical Application (continued)
9.2.1 Design Requirements
This typical voltage detector application is designed to meet the parameters listed in Table 3:
Table 3. Design Parameters
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
Monitored voltage
24-V nominal, falling (VMON(UV))
threshold
10% nominal (21.6 V)
VMON(UV) = 21.8 V ±2.7%
Output logic voltage
3.3-V CMOS
3.3-V CMOS
Maximum current consumption
30 µA
24 µA
9.2.2 Detailed Design Procedure
9.2.2.1 Resistor Divider Selection
The resistor divider values and target threshold voltage can be calculated by using Equation 1 to determine
VMON(UV).
R1 ·
§
VMON(UV) = ¨ 1 +
u VITR2 ¹¸
©
where
•
•
R1 and R2 are the resistor values for the resistor divider on the SENSE pin
VMON(UV) is the target voltage at which an undervoltage condition is detected
(1)
Choose an RTOTAL ( = R1 + R2) so that the current through the divider is approximately 100 times higher than the
input current at the SENSE pin. Use resistors with high values to minimize current consumption (as a result of
low input bias current) without adding significant error to the resistive divider. For details on sizing input resistors,
refer to Optimizing Resistor Dividers at a Comparator Input, available for download from www.ti.com.
9.2.2.2 Pullup Resistor Selection
To ensure the proper logic-high voltage level (VHI), select a pullup resistor value where the pullup voltage divided
by the pullup resistor value does not exceed the sink-current capability of the device. Confirm this voltage level
by verifying that the pullup voltage minus the open-drain leakage current (ID(leak) ) multiplied by the resistor is
greater than the desired VHI. These values are specified in the Electrical Characteristics.
Use Equation 2 to calculate the value of the pullup resistor.
VHI Vpullup
Vpullup
d RP d
ID(leak)
IOUT
(2)
9.2.2.3 Input Supply Capacitor
Although an input capacitor is not required for stability, for good analog design practice, connect a 0.1-μF low
equivalent series resistance (ESR) capacitor across the VDD and GND pins. A higher-value capacitor may be
necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power
source.
12
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9.2.3 Application Curve
10
Minimum Pulse Width (Ps)
9
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
Overdrive (%)
35
40
45
50
Figure 16. 24-V Window Monitor Output Response
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10 Power Supply Recommendations
The TLV6713 has a 40-V absolute maximum rating on the VDD pin, with a recommended maximum operating
condition of 36 V. If the voltage supply that provides power to VDD is susceptible to any large voltage transient
that may exceed 40 V, or if the supply exhibits high voltage slew rates greater than 1 V/µs, then place an RC
filter between the supply and VDD to filter any high-frequency transient surges on the VDD pin. In these cases, a
100-Ω resistor and 0.01-µF capacitor are required, as shown in Figure 17.
100 Ÿ
0.01 F
+
±
VPULLUP
R1
VDD
SENSE
OUT
R2
GND
Figure 17. Using a RC Filter to Remove High-Frequency Disturbances on VDD
14
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Product Folder Links: TLV6713
TLV6713
www.ti.com
SBVS331B – JANUARY 2018 – REVISED JULY 2018
11 Layout
11.1 Layout Guidelines
•
•
•
Place R2 and R2 close to the device to minimize noise coupling into the SENSE node.
Place the VDD decoupling capacitor close to the device.
Avoid using long traces for the VDD supply node. The VDD capacitor (CVDD), along with parasitic inductance
from the supply to the capacitor, might form an LC tank and create ringing with peak voltages above the
maximum VDD voltage. If long traces are unavoidable, see Figure 17 for an example of filtering VDD.
11.2 Layout Example
Pull up
Voltage
RP1
Output
Flag
Monitored
Voltage
R1
1
6
2
5
3
4
CVDD
Input
Sup ply
R2
Figure 18. Recommended Layout
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Product Folder Links: TLV6713
15
TLV6713
SBVS331B – JANUARY 2018 – REVISED JULY 2018
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
The DIP Adapter Evaluation Module allows conversion of the SOT-23-6 package to a standard DIP-6 pinout for
ease of prototyping and bench evaluation.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Product Folder Links: TLV6713
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV6713DDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1II1
TLV6713DDCT
ACTIVE
SOT-23-THIN
DDC
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1II1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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