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TLV9001SIDBVR

TLV9001SIDBVR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOT23-6

  • 描述:

    IC CMOS 1 CIRCUIT SOT23-6

  • 数据手册
  • 价格&库存
TLV9001SIDBVR 数据手册
TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 TLV900x Low-Power, RRIO, 1-MHz Operational Amplifier for Cost-Sensitive Systems 1 Features • • • • • • • • • • • • Scalable CMOS amplifier for low-cost applications Rail-to-rail input and output Low input offset voltage: ±0.4 mV Unity-gain bandwidth: 1 MHz Low broadband noise: 27 nV/√Hz Low input bias current: 5 pA Low quiescent current: 60 µA/Ch Unity-gain stable Internal RFI and EMI filter Operational at supply voltages as low as 1.8 V Easier to stabilize with higher capacitive load due to resistive open-loop output impedance Extended temperature range: –40°C to 125°C The TLV900x devices include a shutdown mode (TLV9001S, TLV9002S, and TLV9004S) that allow the amplifiers to switch off into standby mode with typical current consumption less than 1 µA. Micro-size packages, such as SOT-553 and WSON, are offered for all channel variants (single, dual, and quad), along with industry-standard packages such as SOIC, MSOP, SOT-23, and TSSOP packages. Device Information PART NUMBER(1) TLV9001 2 Applications • • • • • • • • • • • • • Sensor signal conditioning Power modules Active filters Low-side current sensing Smoke detectors Motion detectors Wearable devices Large and small appliances EPOS Barcode scanners Personal electronics HVAC: heating, ventilating, and air conditioning Motor control: AC induction 3 Description The TLV900x family includes single (TLV9001), dual (TLV9002), and quad-channel (TLV9004) low-voltage (1.8 V to 5.5 V) operational amplifiers (op amps) with rail-to-rail input and output swing capabilities. These op amps provide a cost-effective solution for space-constrained applications such as smoke detectors, wearable electronics, and small appliances where low-voltage operation and high capacitive-load drive are required. The capacitive-load drive of the TLV900x family is 500 pF, and the resistive openloop output impedance makes stabilization easier with much higher capacitive loads. These op amps are designed specifically for low-voltage operation (1.8 V to 5.5 V) with performance specifications similar to the TLV600x devices. The robust design of the TLV900x family simplifies circuit design. The op amps feature unity-gain stability, an integrated RFI and EMI rejection filter, and no-phase reversal in overdrive conditions. TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S (1) (2) PACKAGE BODY SIZE (NOM) SOT-23 (5) 1.60 mm × 2.90 mm SC70 (5) 1.25 mm × 2.00 mm SOT-553 (5)(2) 1.65 mm × 1.20 mm X2SON (5) 0.80 mm × 0.80 mm SOT-23 (6) 1.60 mm × 2.90 mm SC70 (6) 1.25 mm × 2.00 mm SOIC (8) 3.91 mm × 4.90 mm WSON (8) 2.00 mm × 2.00 mm VSSOP (8) 3.00 mm × 3.00 mm SOT-23 (8) 1.60 mm × 2.90 mm TSSOP (8) 3.00 mm × 4.40 mm VSSOP (10) 3.00 mm × 3.00 mm X2QFN (10) 1.50 mm × 2.00 mm DSBGA (9) 1.00 mm × 1.00 mm SOIC (14) 8.65 mm × 3.91 mm SOT-23 (14) 4.20 mm × 2.00 mm TSSOP (14) 4.40 mm × 5.00 mm WQFN (16) 3.00 mm × 3.00 mm X2QFN (14) 2.00 mm × 2.00 mm WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Package is for preview only. Single-Pole, Low-Pass Filter An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................6 6 Pin Configuration and Functions...................................7 7 Specifications................................................................ 14 7.1 Absolute Maximum Ratings...................................... 14 7.2 ESD Ratings............................................................. 14 7.3 Recommended Operating Conditions.......................14 7.4 Thermal Information: TLV9001................................. 15 7.5 Thermal Information: TLV9001S............................... 15 7.6 Thermal Information: TLV9002................................. 15 7.7 Thermal Information: TLV9002S............................... 16 7.8 Thermal Information: TLV9004................................. 16 7.9 Thermal Information: TLV9004S............................... 16 7.10 Electrical Characteristics.........................................17 7.11 Typical Characteristics............................................ 19 8 Detailed Description......................................................25 8.1 Overview................................................................... 25 8.2 Functional Block Diagram......................................... 25 8.3 Feature Description...................................................26 8.4 Overload Recovery................................................... 27 8.5 Shutdown.................................................................. 27 8.6 Device Functional Modes..........................................27 9 Application and Implementation.................................. 28 9.1 Application Information............................................. 28 9.2 Typical Application.................................................... 28 10 Power Supply Recommendations..............................34 10.1 Input and ESD Protection....................................... 34 11 Layout........................................................................... 35 11.1 Layout Guidelines................................................... 35 11.2 Layout Example...................................................... 35 12 Device and Documentation Support..........................36 12.1 Documentation Support.......................................... 36 12.2 Receiving Notification of Documentation Updates..36 12.3 Support Resources................................................. 36 12.4 Trademarks............................................................. 36 12.5 Electrostatic Discharge Caution..............................36 12.6 Glossary..................................................................36 13 Mechanical, Packaging, and Orderable Information.................................................................... 37 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision Q (June 2021) to Revision R (November 2021) Page • Added SOT-23 (14) package to Device Information table.................................................................................. 1 • Added SOT-23 DYY package to Device Comparison Table .............................................................................. 6 • Added SOT-23 (14) package to Pin Configuration and Functions section ........................................................ 7 • Added DYY (SOT-23) package thermal information to the Thermal Information: TLV9004 table.................... 16 Changes from Revision P (April 2021) to Revision Q (June 2021) Page • Changed supply voltage (V+) – (V–) MAX from 6 V to 7 V in the Absolute Maximum Ratings table............... 14 Changes from Revision O (April 2020) to Revision P (April 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Added 9-pin DSBGA package to Device Information table................................................................................ 1 • Added 9-pin DSBGA package to Device Comparison Table ............................................................................. 6 • Added TLV9002S 9-pin DSBGA package to Pin Configuration and Functions section......................................7 • Added TLV9002S 9-pin DSBGA package to Thermal Information: TLV9002S ............................................... 16 • Deleted the Related Links section from the Device and Documentation Support section................................36 Changes from Revision N (January 2020) to Revision O (April 2020) Page • Deleted PREVIEW designation on TLV9001S ...................................................................................................1 • Deleted TLV9001SIDCK (6-pin SC70) package preview note ...........................................................................7 • Added DCK (SC70) data to the Thermal Information: TLV9001S table ...........................................................15 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Changes from Revision M (September 2019) to Revision N (January 2020) Page • Added 6-pin SC70 package to Device Information table.................................................................................... 1 • Added 6-pin SC70 package to Device Comparison Table .................................................................................6 • Added TLV9001SIDCK (6-Pin SC70) package pinout........................................................................................7 • Added TLV9001S 6-pin SC70 package to Pin Configuration and Functions section......................................... 7 • Added 6-pin SC70 pinout to Pin Functions: TLV9001S ..................................................................................... 7 • Added TLV9001S 6-pin SC70 package to Thermal Information: TLV9001S table........................................... 15 Changes from Revision L (May 2019) to Revision M (September 2019) Page • Deleted preview notations for SOT-23-8 (DDF) package................................................................................... 6 • Added link to Shutdown section in all SHDN pin function rows.......................................................................... 7 • Added EMI Rejection section to the Feature Description section.....................................................................26 • Changed the Shutdown section to add more clarity regarding internal pull-up resistor....................................27 Changes from Revision K (March 2019) to Revision L (May 2019) Page • Added SOT-23 (8) information to Device Information table................................................................................ 1 • Added SOT-23 DDF package to Device Comparison Table .............................................................................. 6 • Added SOT-23 (DDF) to Pin Configuration and Functions section.....................................................................7 • Added DDF (SOT-23) Thermal Information: TLV9002 table.............................................................................15 Changes from Revision J (January 2019) to Revision K (March 2019) Page • Changed TLV9002S ESD Ratings heading to include all TLV9002S packages............................................... 14 • Deleted preview notation from TLV9002SIRUG in Thermal Information table................................................. 16 Changes from Revision I (November 2018) to Revision J (January 2019) Page • Deleted preview notation for TLV9002SIRUGR..................................................................................................1 • Changed TLV9004 WQFN(14) package designator to X2QFN(14) package designator................................... 1 • Added RUG package to Device Comparison Table ...........................................................................................6 • Added DGS package to Device Comparison Table ........................................................................................... 6 • Added shutdown devices to Device Comparison Table .....................................................................................6 • Changed TLV9001 DRL package pinout drawing...............................................................................................7 • Changed TLV9001 DRL package pin functions..................................................................................................7 • Deleted package preview note from TLV9002SIRUGR (X2QFN) pinout drawing.............................................. 7 • Added TLV9004IRUC Thermal Information...................................................................................................... 16 • Changed legend of Closed-Loop Gain vs Frequency plot................................................................................ 19 Changes from Revision H (October 2018) to Revision I (November 2018) Page • Added TLV9002SIDGS to ESD Ratings table...................................................................................................14 Changes from Revision G (September 2018) to Revision H (October 2018) Page • Changed From: TLV9001 DCK Package To: TLV9001T DCK Package............................................................. 7 Changes from Revision F (August 2018) to Revision G (September 2018) Page • Added Device Comparison Table ...................................................................................................................... 6 • Changed pin names for all devices and all packages.........................................................................................7 • Changed pin names and I/O designation on some TLV9001 pins .....................................................................7 • Changed the pin number for V+ in the SOIC, TSSOP column of the Pin Functions: TLV9004 table................. 7 Changes from Revision E (July 2018) to Revision F (August 2018) Page • Added Scalabe CMOS Amplifier for Low-Cost Applications feature...................................................................1 • Deleted PREVIEW designation on TLV9002 and TLV9004 devices with the TSSOP package. ....................... 1 • Added TLV9001U DBV (SOT-23) pinout drawing to Pin Configuration and Functions section ......................... 7 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 3 TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 • www.ti.com Added SOT-23 U Pinout to Pin Functions section ............................................................................................. 7 Changes from Revision D (June 2018) to Revision E (July 2018) Page • Corrected typo in Description section ................................................................................................................ 1 • Added TLV9001 5-pin X2SON package to Device Information table ................................................................ 1 • Added TLV9001S 6-pin SOT-23 package to Device Information table...............................................................1 • Added TLV9004 14-pin and 16-pin WQFN packages to Device Information table ............................................1 • Added TLV9001 DPW (X2SON) pinout drawing to Pin Configuration and Functions section............................ 7 • Added TLV9001S 6-pin SOT-23 package to Pin Configuration and Functions section...................................... 7 • Added TLV9004 RTE pinout information to Pin Configuration and Functions section .......................................7 • Added DPW (X2SON) and DRL (SOT-553) packages to Thermal Information: TLV9001 table.......................15 • Added Thermal Information: TLV9001S table to Specifications section........................................................... 15 • Added RUG (X2QFN) package to Thermal Information: TLV9002 table.......................................................... 15 • Added RTE (WQFN) and RUC (WQFN) packages to Thermal Information: TLV9004 table............................ 16 Changes from Revision C (May 2018) to Revision D (June 2018) Page • Added shutdown text to Description section.......................................................................................................1 • Added TLV9002S and TLV9004S devices to Device Information table.............................................................. 1 • Added TLV9002S 10-pin X2QFN package to Device Information table............................................................. 1 • Added TLV9002S DGS package pinout information to Pin Configurations and Functions section.................... 7 • Added Thermal Information: TLV9001 table to Specifications section............................................................. 15 • Added Thermal Information: TLV9004 table to Specifications section............................................................. 16 • Added shutdown section to Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V table.................................................................................................................................................................. 17 • Added Shutdown section.................................................................................................................................. 27 Changes from Revision B (March 2018) to Revision C (May 2018) Page • Added TLV9002 16-pin TSSOP package to Device Information table............................................................... 1 • Added TLV9002 10-pin X2QFN package to Device Information table................................................................1 • Added TLV9002S DGS package pinout drawing in Pin Configurations and Functions section..........................7 • Added TLV9004 pinout diagram and pin configuration table to Pin Configuration and Functions section ........ 7 • Added TLV9004S pinout diagram and pin configuration table to Pin Configuration and Functions section ...... 7 • Changed TLV9002 D (SOIC) junction-to-ambient thermal resistance value from 147.4°C/W to 207.9°C/W... 15 • Changed TLV9002 D (SOIC) junction-to-case (top) thermal resistance from 94.3°C/W to 92.8°C/W..............15 • Changed TLV9002 D (SOIC) junction-to-board thermal resistance from 89.5°C/W to 129.7°C/W...................15 • Changed TLV9002 D (SOIC) junction-to-top characterization parameter from 47.3°C/W to 26°C/W.............. 15 • Changed TLV9002 D (SOIC) junction-to-board characterization parameter from 89°C/W to 127.9°C/W........ 15 • Added DGK (VSSOP) thermal information to Thermal Information: TLV9002 table ........................................15 • Added TLV9002 PW (TSSOP) thermal information to Thermal Information: TLV9002 table........................... 15 • Added PW (TSSOP) thermal information to Thermal Information: TLV9002 table ..........................................16 Changes from Revision A (December 2017) to Revision B (March 2018) Page • Added package preview notes to TLV9001 packages, TLV9004 packages, and TLV9002 8-pin VSSOP package in Device Information table ..................................................................................................................1 • Added package preview notes to TLV9001, TLV9004 and TLV9002 VSSOP package pinout drawings in Pin Configuration and Functions section ................................................................................................................. 7 • Deleted package preview note from TLV9002 DSG (WSON) pinout drawing in Pin Configurations and Functions section................................................................................................................................................7 • Deleted package preview note from TLV9002 RUG (X2QFN) pinout drawing in Pin Configurations and Functions section................................................................................................................................................7 • Added DSG (WSON) package thermal information to the Thermal Information: TLV9002 table..................... 15 • Deleted package preview note from DSG (WSON) package in Thermal Information: TLV9002 table............. 15 • Added D (SOIC) package thermal information to the Thermal Information: TLV9004 table.............................16 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Changes from Revision * (October 2017) to Revision A (December 2017) Page • Changed device status from Advance Information to Production Data/Mixed Status........................................ 1 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 5 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 5 Device Comparison Table DEVICE TLV9001 TLV9001S TLV9002 TLV9002S TLV9004 TLV9004S 6 NO. OF CH. 1 2 4 PACKAGE LEADS SC70 DCK SOIC D SOT-23 DBV SOT-23 DYY SOT-553 DRL TSSOP PW VSSOP DGK SOT-23 DDF WQFN RTE WSON DSG X2QFN RUC 5 — 5 6 — 6 — 8 — X2SON DPW X2QFN RUG VSSOP DGS DSBGA YCK — 5 — — — — — — — — — — — — — 5 — — — — — — — — — — 8 8 8 — — 8 — — — — — — — — — — — — — — — — 10 10 — 14 — 14 — 14 — 9 — 16 — 14 — — — — — — — — — — — — 16 — — — — — — Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 6 Pin Configuration and Functions OUT 1 V± 2 IN+ 3 5 V+ 4 IN± IN+ 1 V± 2 IN± 3 Not to scale 5 V+ 4 OUT Not to scale Figure 6-1. TLV9001 DBV, TLV9001T DCK Package 5-Pin SOT-23, SC70 Top View OUT Figure 6-2. TLV9001 DCK Package, TLV9001 DRL Package, TLV9001U DBV Package 5-Pin SC70, SOT-553, SOT-23 Top View 1 5 V+ 4 IN+ 3 V± IN± 2 Not to scale Figure 6-3. TLV9001 DPW Package 5-Pin X2SON Top View Table 6-1. Pin Functions: TLV9001 PIN SOT-23, SC70(T) SC70, SOT-23(U), SOT-553 X2SON IN– 4 3 2 IN+ 3 1 OUT 1 4 V– 2 2 3 V+ 5 5 5 NAME I/O DESCRIPTION I Inverting input 4 I Noninverting input 1 O Output I or — Negative (low) supply or ground (for single-supply operation) I Positive (high) supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 7 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 OUT 1 6 V+ V± 2 5 SHDN IN+ 3 4 IN± IN+ 1 6 V+ V± 2 5 SHDN IN± 3 4 OUT Not to scale Not to scale Figure 6-5. TLV9001S DCK Package 6-Pin SC70 Top View Figure 6-4. TLV9001S DBV Package 6-Pin SOT-23 Top View Table 6-2. Pin Functions: TLV9001S PIN NAME SOT-23 SC70 IN– 4 3 IN+ 3 OUT 1 SHDN I/O DESCRIPTION I Inverting input 1 I Noninverting input 4 O Output 5 5 I Shutdown: low = amp disabled, high = amp enabled. See Section 8.5 for more information. V– 2 2 I or — V+ 6 6 I OUT1 1 8 V+ IN1± 2 7 OUT2 IN1+ 3 6 IN2± V± 4 5 IN2+ Negative (low) supply or ground (for single-supply operation) Positive (high) supply OUT1 1 IN1± 2 IN1+ 3 V± 4 Thermal Pad 8 V+ 7 OUT2 6 IN2± 5 IN2+ Not to scale Figure 6-6. TLV9002 D, DGK, PW, DDF Package 8-Pin SOIC, VSSOP, TSSOP, SOT-23 Top View Not to scale A. Connect thermal pad to V–. Figure 6-7. TLV9002 DSG Package 8-Pin WSON With Exposed Thermal Pad Top View Table 6-3. Pin Functions: TLV9002 PIN NAME 8 NO. I/O DESCRIPTION IN1– 2 I Inverting input, channel 1 IN1+ 3 I Noninverting input, channel 1 IN2– 6 I Inverting input, channel 2 IN2+ 5 I Noninverting input, channel 2 OUT1 1 O Output, channel 1 OUT2 7 O Output, channel 2 V– 4 I or — V+ 8 I Negative (low) supply or ground (for single-supply operation) Positive (high) supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com IN1+ SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 1 10 V+ IN1± 2 9 OUT2 IN1+ 3 8 IN2± V± 4 7 IN2+ SHDN1 5 6 SHDN2 V± 1 9 IN1± SHDN1 2 8 OUT1 SHDN2 3 7 V+ IN2+ 4 6 OUT2 10 OUT1 Not to scale 5 Figure 6-8. TLV9002S DGS Package 10-Pin VSSOP Top View IN2± Not to scale Figure 6-9. TLV9002S RUG Package 10-Pin X2QFN Top View 1 2 3 C OUT1 V+ OUT2 B IN1– SHDN IN2– A IN1+ V– IN2+ Not to scale Figure 6-10. TLV9002S YCK Package 9-Pin DSBGA (WCSP) Bottom View Table 6-4. Pin Functions: TLV9002S PIN NAME VSSOP X2QFN DSBGA (WCSP) I/O DESCRIPTION IN1– 2 9 B1 I Inverting input, channel 1 IN1+ 3 10 A1 I Noninverting input, channel 1 IN2– 8 5 B3 I Inverting input, channel 2 IN2+ 7 4 A3 I Noninverting input, channel 2 OUT1 1 8 C1 O Output, channel 1 OUT2 9 6 C3 O Output, channel 2 SHDN1 5 2 — I Shutdown: low = amp disabled, high = amp enabled, channel 1. See Section 8.5 for more information. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 9 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Table 6-4. Pin Functions: TLV9002S (continued) PIN VSSOP X2QFN DSBGA (WCSP) I/O SHDN2 6 3 — I SHDN — — B2 V– 4 1 A2 I or — V+ 10 7 C2 I NAME 10 DESCRIPTION Shutdown: low = amp disabled, high = amp enabled, channel 1. See Section 8.5 for more information. Shutdown: low = both amplifiers disabled, high = both amplifiers enabled Negative (low) supply or ground (for single-supply operation) Positive (high) supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com 2 13 IN4± IN1+ 3 12 IN4+ V+ 4 11 V± IN2+ 5 10 IN3+ IN2± 6 9 IN3± OUT2 7 8 OUT3 IN1± 1 IN1+ 2 V+ OUT4 IN1± 12 IN4± 11 IN4+ 3 10 V± IN2+ 4 9 IN3+ IN2± 5 8 IN3± 13 OUT4 7 14 14 1 6 OUT1 OUT1 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 OUT2 OUT3 Not to scale Figure 6-11. TLV9004 D, DYY, PW Package 14-Pin SOIC, SOT-23 (14), TSSOP Top View Not to scale IN1+ 1 V+ 2 IN1± OUT1 OUT4 IN4± 16 15 14 13 Figure 6-12. TLV9004 RUC Package 14-Pin X2QFN Top View 12 IN4+ 11 V± 10 IN3+ 9 IN3± Thermal A. 6 7 8 NC OUT3 4 NC IN2± Pad 5 3 OUT2 IN2+ Not to scale Connect thermal pad to V–. Figure 6-13. TLV9004 RTE Package 16-Pin WQFN With Exposed Thermal Pad Top View Table 6-5. Pin Functions: TLV9004 PIN SOIC, SOT-23 (14), TSSOP WQFN X2QFN IN1– 2 16 1 I Inverting input, channel 1 IN1+ 3 1 2 I Noninverting input, channel 1 IN2– 6 4 5 I Inverting input, channel 2 IN2+ 5 3 4 I Noninverting input, channel 2 NAME I/O DESCRIPTION Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 11 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Table 6-5. Pin Functions: TLV9004 (continued) PIN NAME SOIC, SOT-23 (14), TSSOP WQFN X2QFN I/O DESCRIPTION IN3– 9 9 8 I Inverting input, channel 3 IN3+ 10 10 9 I Noninverting input, channel 3 IN4– 13 13 12 I Inverting input, channel 4 IN4+ 12 12 11 I Noninverting input, channel 4 NC — 6, 7 — — No internal connection OUT1 1 15 14 O Output, channel 1 OUT2 7 5 6 O Output, channel 2 OUT3 8 8 7 O Output, channel 3 OUT4 14 14 13 O Output, channel 4 V– 11 11 10 V+ 4 2 3 12 I or — Negative (low) supply or ground (for single-supply operation) I Positive (high) supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com IN1+ 1 V+ 2 IN1± OUT1 OUT4 IN4± 16 15 14 13 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 12 IN4+ 11 V± 10 IN3+ 9 IN3± Thermal A. 6 7 8 SHDN34 OUT3 4 SHDN12 IN2± Pad 5 3 OUT2 IN2+ Not to scale Connect thermal pad to V–. Figure 6-14. TLV9004S RTE Package 16-Pin WQFN With Exposed Thermal Pad Top View Table 6-6. Pin Functions: TLV9004S PIN NAME NO. I/O DESCRIPTION IN1+ 1 I Noninverting input IN1– 16 I Inverting input IN2+ 3 I Noninverting input IN2– 4 I Inverting input IN3+ 10 I Noninverting input IN3– 9 I Inverting input IN4+ 12 I Noninverting input IN4– 13 I Inverting input SHDN12 6 I Shutdown: low = amp disabled, high = amp enabled, channel 1 and 2. See Section 8.5 for more information. SHDN34 7 I Shutdown: low = amp disabled, high = amp enabled, channel 3 and 4. See Section 8.5 for more information. OUT1 15 O Output OUT2 5 O Output OUT3 8 O Output OUT4 14 O Output V– 11 I or — V+ 2 I Negative (low) supply or ground (for single-supply operation) Positive (high) supply Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 13 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 7 Specifications 7.1 Absolute Maximum Ratings over operating temperature range (unless otherwise noted)(1) MIN MAX Supply voltage (V+) – (V–) Voltage(2) Signal input pins Common-mode V (V+) + 0.5 V (V+) – (V–) + 0.2 V (V–) – 0.5 Differential Current(2) –10 Output short-circuit(3) –55 Junction, TJ Storage, Tstg (2) (3) 10 mA 150 °C 150 °C 150 °C Continuous Operating, TA (1) UNIT 7 –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less. Short-circuit to ground, one amplifier per package. 7.2 ESD Ratings TLV9002S PACKAGE V(ESD) Electrostatic discharge VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 UNIT V ALL OTHER PACKAGES V(ESD) (1) (2) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating temperature range (unless otherwise noted) MIN MAX UNIT VS Supply voltage 1.8 5.5 V TA Specified temperature –40 125 °C 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 7.4 Thermal Information: TLV9001 TLV9001 THERMAL RθJA METRIC(1) DBV (SOT-23) DCK (SC70) DPW (X2SON) DRL (SOT-553)(2) 5 PINS 5 PINS 5 PINS 5 PINS 232.9 239.6 470.0 TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance 153.8 148.5 211.9 TBD °C/W RθJB Junction-to-board thermal resistance 100.9 82.3 334.8 TBD °C/W ψJT Junction-to-top characterization parameter 77.2 54.5 29.8 TBD °C/W ψJB Junction-to-board characterization parameter 100.4 81.8 333.2 TBD °C/W (1) (2) Junction-to-ambient thermal resistance UNIT For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. This package option for TLV9001 is preview only. 7.5 Thermal Information: TLV9001S TLV9001S THERMAL METRIC(1) DBV (SOT-23) DCK (SC70) UNIT 6 PINS 6 PINS RθJA Junction-to-ambient thermal resistance 232.9 215.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 153.8 146.4 °C/W RθJB Junction-to-board thermal resistance 100.9 72.0 °C/W ψJT Junction-to-top characterization parameter 77.2 55.0 °C/W ψJB Junction-to-board characterization parameter 100.4 71.7 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. 7.6 Thermal Information: TLV9002 TLV9002 THERMAL METRIC(1) D (SOIC) DGK (VSSOP) DGS (VSSOP) DSG (WSON) PW (TSSOP) DDF (SOT-23) UNIT 8 PINS 8 PINS 10 PINS 8 PINS 8 PINS 8 PINS RθJA Junction-to-ambient thermal resistance 207.9 201.2 169.5 103.2 200.7 183.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 92.8 85.7 84.1 120.1 95.4 112.5 °C/W RθJB Junction-to-board thermal resistance 129.7 122.9 113 68.8 128.6 98.2 °C/W ψJT Junction-to-top characterization parameter 26 21.2 15.8 14.7 27.2 18.8 °C/W ψJB Junction-to-board characterization parameter 127.9 121.4 111.6 68.5 127.2 97.6 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 15 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 7.7 Thermal Information: TLV9002S TLV9002S THERMAL METRIC(1) DGS (VSSOP) RUG (X2QFN) YCK (DSBGA) 10 PINS 10 PINS 9 PINS UNIT RθJA Junction-to-ambient thermal resistance 169.5 194.2 101.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 84.1 90.3 0.9 °C/W RθJB Junction-to-board thermal resistance 113 122.2 33.8 °C/W ψJT Junction-to-top characterization parameter 15.8 3.5 0.5 °C/W ψJB Junction-to-board characterization parameter 111.6 118.8 33.8 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. 7.8 Thermal Information: TLV9004 TLV9004 THERMAL METRIC(1) D (SOIC) DYY (SOT-23) PW (TSSOP) RTE (WQFN) RUC (X2QFN) 14 PINS 14 PINS 14 PINS 16 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal resistance 102.1 154.3 148.3 66.4 205.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 56.8 86.8 68.1 69.3 72.5 °C/W RθJB Junction-to-board thermal resistance 58.5 67.9 92.7 41.7 150.2 °C/W ψJT Junction-to-top characterization parameter 20.5 10.1 16.9 5.7 3.0 °C/W ψJB Junction-to-board characterization parameter 58.1 67.5 91.8 41.5 149.6 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. 7.9 Thermal Information: TLV9004S TLV9004S THERMAL METRIC(1) RTE (WQFN) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 66.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 69.3 °C/W RθJB Junction-to-board thermal resistance 41.7 °C/W ψJT Junction-to-top characterization parameter 5.7 °C/W ψJB Junction-to-board characterization parameter 41.5 °C/W (1) 16 For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 7.10 Electrical Characteristics For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX ±0.4 ±1.6 UNIT OFFSET VOLTAGE VOS Input offset voltage VS = 5 V VS = 5 V, TA = –40°C to 125°C dVOS/dT VOS vs temperature TA = –40°C to 125°C PSRR VS = 1.8 to 5.5 V, VCM = (V–) Power-supply rejection ratio ±2 80 mV ±0.6 µV/°C 105 dB INPUT VOLTAGE RANGE VCM CMRR Common-mode voltage range Common-mode rejection ratio No phase reversal, rail-to-rail input (V–) – 0.1 (V+) + 0.1 VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V, TA = –40°C to 125°C 86 VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V, TA = –40°C to 125°C 95 VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V, TA = –40°C to 125°C V dB 63 77 VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V, TA = –40°C to 125°C 68 VS = 5 V ±5 pA ±2 pA ƒ = 0.1 Hz to 10 Hz, VS = 5 V 4.7 µVPP ƒ = 1 kHz, VS = 5 V 30 ƒ = 10 kHz, VS = 5 V 27 ƒ = 1 kHz, VS = 5 V 23 fA/√ Hz 1.5 pF 5 pF INPUT BIAS CURRENT IB Input bias current IOS Input offset current NOISE En Input voltage noise (peak-topeak) en Input voltage noise density in Input current noise density nV/√ Hz INPUT CAPACITANCE CID Differential CIC Common-mode OPEN-LOOP GAIN VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V, RL = 10 kΩ AOL Open-loop voltage gain 104 117 VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V, RL = 10 kΩ 100 VS = 1.8 V, (V–) + 0.1 V < VO < (V+) – 0.1 V, RL = 2 kΩ 115 VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2 kΩ 130 dB FREQUENCY RESPONSE GBW Gain-bandwidth product VS = 5 V φm Phase margin VS = 5.5 V, G = 1 SR Slew rate VS = 5 V tS Settling time tOR Overload recovery time VS = 5 V, VIN × gain > VS THD+N Total harmonic distortion + noise VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1, ƒ = 1 kHz, 80-kHz measurement BW VO Voltage output swing from supply rails VS = 5.5 V, RL = 10 kΩ 10 20 VS = 5.5 V, RL = 2 kΩ 35 55 ISC Short-circuit current VS = 5.5 V ZO Open-loop output impedance VS = 5 V, ƒ = 1 MHz To 0.1%, VS = 5 V, 2-V step, G = +1, CL = 100 pF To 0.01%, VS = 5 V, 2-V step, G = +1, CL = 100 pF 1 MHz 78 ° 2 V/µs 2.5 µs 3 0.85 µs 0.004% OUTPUT mV ±40 mA 1200 Ω Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 17 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 7.10 Electrical Characteristics (continued) For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VS Specified voltage range IQ Quiescent current per amplifier 1.8 (±0.9) 5.5 (±2.75) TLV9002, TLV9002S TLV9004, TLV9004S IO = 0 mA, VS = 5.5 V 60 75 TLV9001, TLV9001S IO = 0 mA, VS = 5.5 V 60 77 IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C V µA 85 SHUTDOWN(1) IQSD Quiescent current per amplifier VS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN = VS– ZSHDN Output impedance during shutdown VS = 1.8 V to 5.5 V, amplifier disabled High level voltage shutdown threshold (amplifier enabled) VS = 1.8 V to 5.5 V Low level voltage shutdown threshold (amplifier disabled) VS = 1.8 V to 5.5 V Amplifier enable time (full shutdown) VS = 1.8 V to 5.5 V, full shutdown; G = 1, VOUT = 0.9 × VS / 2, RL connected to V– 70 Amplifier enable time (partial shutdown) VS = 1.8 V to 5.5 V, partial shutdown; G = 1, VOUT = 0.9 × VS / 2, RL connected to V– 50 Amplifier disable time VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2, RL connected to V– tON tOFF SHDN pin input bias current (per pin) (1) 18 0.5 1.5 10 || 2 (V–) + 0.9 (V–) + 0.2 V VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) – 0.8 V VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V– + 0.8 V (V–) + 0.7 V µA GΩ || pF (V–) + 1.1 V V µs 4 40 150 µs nA Specified by design and characterization; not production tested. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 7.11 Typical Characteristics at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) 25 40 35 20 Population (%) Population (%) 30 25 20 15 10 15 10 5 5 0 0 -1200 -900 -600 -300 0 300 0 900 1200 1500 1800 600 0.2 0.6 0.8 1 1.2 1.4 1.6 1.8 D002 VS = 5 V, TA = –40°C to 125°C VS = 5 V Figure 7-2. Offset Voltage Drift Distribution Histogram 1000 2000 800 1500 600 1000 Offset Voltage (μV) 400 200 0 -200 -400 500 0 -500 -1000 -600 -1500 -800 -1000 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 -2000 -4 140 -3 -2 D003 Figure 7-3. Input Offset Voltage vs Temperature -1 0 1 2 Common-Mode Voltage (V) 3 4 D004 Figure 7-4. Offset Voltage vs Common-Mode 6 1000 800 IB I B+ IOS 4 600 2 400 IB and IOS (pA) Offset Voltage (PV) 2 Offset Voltage Drift (μV/°C) Figure 7-1. Offset Voltage Distribution Histogram Input Offset Voltage (µV) 0.4 D001 Offset Voltage (μV) 200 0 -200 -400 0 -2 -4 -6 -600 -8 -800 -1000 1.5 2 2.5 3 3.5 4 4.5 Supply Voltage (V) 5 5.5 Figure 7-5. Offset Voltage vs Supply Voltage 6 -10 -40 -20 0 D005 20 40 60 80 Temperature (qC) 100 120 140 D006 Figure 7-6. IB and IOS vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 19 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 7.11 Typical Characteristics (continued) at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) 160 3.5 IB 3 IB+ IOS 140 2.5 120 Gain (dB) IB and IOS (pA) 2 1.5 1 0.5 0 -0.5 -1 100 80 60 40 -1.5 20 -2 -2.5 -3 -2 -1 0 1 Common-Mode Voltage (V) 2 0 -40 3 0 20 120 100 120 140 D008 80 100 60 80 40 60 20 40 0 20 160 Phase (q) 100 Gain Phase 40 60 80 Temperature (qC) Figure 7-8. Open-Loop Gain vs Temperature Open-Loop Voltage Gain (dB) Gain (dB) -20 D007 Figure 7-7. IB and IOS vs Common-Mode Voltage -20 1k VS = 5.5 V VS = 1.8 V 140 120 100 80 60 40 20 0 10k 100k Frequency (Hz) 0 -3 1M -2 -1 0 1 Output Voltage (V) D009 2 3 D010 CL = 10 pF Figure 7-9. Open-Loop Gain and Phase vs Frequency Figure 7-10. Open-Loop Gain vs Output Voltage 80 3 Gain = 1 Gain = 1 Gain = 100 Gain = 1000 Gain = 10 70 60 2 1.5 Output Voltage (V) Gain (dB) 50 2.5 40 30 20 10 0 125°C 1 85°C 25°C -40°C 0.5 0 -0.5 -1 85°C -1.5 25°C -40°C 125°C -2 -10 -2.5 -20 100 -3 1k 10k 100k Frequency (Hz) 1M 0 5 10 D011 15 20 25 30 35 Output Current (mA) 40 45 50 D012 CL = 10 pF Figure 7-11. Closed-Loop Gain vs Frequency 20 Figure 7-12. Output Voltage vs Output Current (Claw) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 7.11 Typical Characteristics (continued) at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) 120 PSRR+ PSRR 100 Power Supply Rejection Ratio (dB) Power Supply Rejection Ratio (dB) 120 80 60 40 20 0 100 1k 10k Frequency (Hz) 100k 100 80 60 40 20 0 -40 1M -20 0 20 D013 40 60 80 Temperature (qC) 100 120 140 D014 VS = 1.8 V to 5.5 V Figure 7-14. DC PSRR vs Temperature Figure 7-13. PSRR vs Frequency 160 Common-Mode Rejection Ratio (dB) Common-Mode Rejection Ratio (dB) 120 100 80 60 40 20 0 100 1k 10k Frequency (Hz) 100k 140 120 100 80 60 40 20 0 -40 1M VS = 1.8 V VS = 5.5 V -20 0 D015 20 40 60 80 Temperature (qC) 100 120 140 D016 VCM = (V–) – 0.1 V to (V+) – 1.4 V Figure 7-16. DC CMRR vs Temperature Amplitude (1 PV/div) Input Voltage Noise Spectral Density (nV/—Hz) Figure 7-15. CMRR vs Frequency Time (1 s/div) 120 100 80 60 40 20 0 10 100 D017 Figure 7-17. 0.1-Hz to 10-Hz Integrated Voltage Noise 1k Frequency (Hz) 10k 100k D018 Figure 7-18. Input Voltage Noise Spectral Density Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 21 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 7.11 Typical Characteristics (continued) at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) 0 -50 G = +1, RL = 2 k: G = +1, RL = 10 k: -20 THD + N (dB) -60 THD + N (dB) G = 1, RL = 2 k: G = 1, RL = 10 k: -70 -80 -40 -60 -80 -90 RL = 2K RL = 10K -100 100 1k Frequency (Hz) VS = 5.5 V BW = 80 kHz -100 0.001 10k VCM = 2.5 V VOUT = 0.5 VRMS G=1 VS = 5.5 V G=1 70 70 60 60 50 40 30 20 1 2 D020 VCM = 2.5 V BW = 80 kHz ƒ = 1 kHz 50 40 30 20 10 10 0 1.5 2 2.5 3 3.5 4 Voltage Supply (V) 4.5 5 0 -40 5.5 1800 45 1600 40 1400 35 Overshoot (%) 50 1200 1000 800 100 120 140 D022 20 15 10 200 5 1M 40 60 80 Temperature (qC) 25 400 100k Frequency (Hz) 20 30 600 10k 0 Figure 7-22. Quiescent Current vs Temperature 2000 0 1k -20 D021 Figure 7-21. Quiescent Current vs Supply Voltage 10M Overshoot (+) Overshoot (–) 0 0 200 D023 G=1 Figure 7-23. Open-Loop Output Impedance vs Frequency 22 0.1 Amplitude (V RMS) Figure 7-20. THD + N vs Amplitude Quiescent Current (PA) Quiescent Current (PA) Figure 7-19. THD + N vs Frequency Open-Loop Output Impedance (:) 0.01 D019 400 600 Capacitance Load (pF) 800 1000 D024 VIN = 100 mVpp Figure 7-24. Small Signal Overshoot vs Capacitive Load Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 7.11 Typical Characteristics (continued) at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) 50 90 45 80 40 70 Phase Margin (q) Overshoot (%) 35 30 25 20 15 60 50 40 30 20 10 Overshoot (+) Overshoot (–) 5 10 0 0 0 200 G = –1 400 600 Capacitance Load (pF) 800 0 1000 200 D025 400 600 Capacitance Load (pF) 800 1000 D026 VIN = 100 mVpp Figure 7-26. Phase Margin vs Capacitive Load Figure 7-25. Small Signal Overshoot vs Capacitive Load Amplitude (1 V/div) VOUT VIN Amplitude (1 V/div) VOUT VIN Time (100 Ps/div) Time (20 Ps/div) D027 G=1 D028 VIN = 6.5 VPP G = –10 Figure 7-27. No Phase Reversal VIN = 600 mVPP Figure 7-28. Overload Recovery VOUT VIN Voltage (1 V/div) Voltage (20 mV/div) VOUT VIN Time (10 Ps/div) Time (10 Ps/div) D029 G=1 VIN = 100 mVPP CL = 10 pF Figure 7-29. Small-Signal Step Response D030 G=1 VIN = 4 VPP CL = 10 pF Figure 7-30. Large-Signal Step Response Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 23 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 7.11 Typical Characteristics (continued) Output Voltage (1 mV/div) Output Voltage (1 mV/div) at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted) Time (1 Ps/div) Time (1 μs/div) D032 D031 G=1 CL = 100 pF G=1 2-V step Figure 7-32. Large-Signal Settling Time (Positive) 80 6 Maximum Output Voltage (V) Short Circuit Current (mA) 40 20 0 -20 -40 -60 -80 -40 VS = 5.5 V VS = 1.8 V 5 4 3 2 1 Sinking Sourcing 0 -20 0 20 40 60 Temperature (qC) 80 100 1 120 100 1k 10k 100k Frequency (Hz) 1M 10M 100M D034 Figure 7-34. Maximum Output Voltage vs Frequency 0 120 -20 Channel Separation (dB) 140 100 80 60 40 -40 -60 -80 -100 -120 20 0 10M 10 D033 Figure 7-33. Short-Circuit Current vs Temperature EMIRR (dB) 2-V step Figure 7-31. Large-Signal Settling Time (Negative) 60 100M 1G Frequency (Hz) 10G -140 1k 10k D035 Figure 7-35. Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency 24 CL = 100 pF 100k Frequency (Hz) 1M 10M D036 Figure 7-36. Channel Separation Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 www.ti.com TLV9001, TLV9002, TLV9004 SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 8 Detailed Description 8.1 Overview The TLV900x is a family of low-power, rail-to-rail input and output op amps. These devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input common-mode voltage range includes both rails and allows the TLV900x family to be used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply applications, and makes them suitable for driving sampling analog-to-digital converters (ADCs). 8.2 Functional Block Diagram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 25 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 8.3 Feature Description 8.3.1 Operating Voltage The TLV900x family of op amps are for operation from 1.8 V to 5.5 V. In addition, many specifications such as input offset voltage, quiescent current, offset current, and short circuit current apply from –40°C to 125°C. Parameters that vary significantly with operating voltages or temperature are shown in Section 7.11. 8.3.2 Rail-to-Rail Input The input common-mode voltage range of the TLV900x family extends 100 mV beyond the supply rails for the full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a P-channel differential pair, as shown in Section 8.2. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which both pairs are on. This 100-mV transition region can vary up to 100 mV with process variation. Thus, the transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to (V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can degrade compared to device operation outside this region. 8.3.3 Rail-to-Rail Output Designed as a low-power, low-voltage operational amplifier, the TLV900x family delivers a robust output drive capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing capability. For resistive loads of 10 kΩ, the output swings to within 20 mV of either supply rail, regardless of the applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the rails. 8.3.4 EMI Rejection The TLV900x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the TLV900x benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 8-1 shows the results of this testing on the TLV900x. Table 8-1 shows the EMIRR IN+ values for the TLV900x at particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op amps and is available for download from www.ti.com. 140 120 EMIRR (dB) 100 80 60 40 20 0 10M 100M 1G Frequency (Hz) 10G D035 Figure 8-1. EMIRR Testing 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 Table 8-1. TLV900x EMIRR IN+ For Frequencies of Interest FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+ 400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications 59.5 dB 900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 68.9 dB 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 77.8 dB Bluetooth®, 2.4 GHz 802.11b, 802.11g, 802.11n, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) 78.0 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.8 dB 8.4 Overload Recovery Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated state to a linear state. The output devices of the operational amplifier enter a saturation region when the output voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return to the linear state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew time. The overload recovery time for the TLV900x family is approximately 850 ns. 8.5 Shutdown The TLV9001S, TLV9002S, and TLV9004S devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode. In this mode, the op amp typically consumes less than 1 µA. The SHDN pins are active low, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low. The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown feature lies around 620 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.2 V and V+. The shutdown pin circuitry includes a pull-up resistor, which will inherently pull the voltage of the pin to the positive supply rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or driven to a valid logic high. To disable the amplifier, the SHDN pins must be driven to a valid logic low. While we highly recommend that the shutdown pin be connected to a valid high or a low voltage or driven, we have included a pull-up resistor connected to VCC. The maximum voltage allowed at the SHDN pins is (V+) + 0.5 V. Exceeding this voltage level will damage the device. The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be used to greatly reduce the average current and extend battery life. The enable time is 70 µs for full shutdown of all channels; disable time is 4 µs. When disabled, the output assumes a high-impedance state. This architecture allows the TLV9002S and TLV9004S to operate as a gated amplifier (or to have the device output multiplexed onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to midsupply (VS / 2) is required. If using the TLV9001S, TLV9002S, or TLV9004S without a load, the resulting turnoff time significantly increases. 8.6 Device Functional Modes The TLV900x family has a single functional mode. The devices are powered on as long as the power-supply voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V). Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 27 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The TLV900x family of low-power, rail-to-rail input and output operational amplifiers is specifically designed for portable applications. The devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide range of general-purpose applications. The class AB output stage is capable of driving less than or equal to 10‑kΩ loads connected to any point between V+ and V–. The input common-mode voltage range includes both rails, and allows the TLV900x devices to be used in any single-supply application. 9.2 Typical Application 9.2.1 TLV900x Low-Side, Current Sensing Application Figure 9-1 shows the TLV900x configured in a low-side current sensing application. VBUS ILOAD ZLOAD 5V + TLV9002 RSHUNT 0.1 Ÿ VSHUNT í VOUT í + RF 57.6 NŸ RG 1.2 NŸ Figure 9-1. TLV900x in a Low-Side, Current-Sensing Application 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 9.2.1.1 Design Requirements The design requirements for this design are: • Load current: 0 A to 1 A • Output voltage: 4.9 V • Maximum shunt voltage: 100 mV 9.2.1.2 Detailed Design Procedure The transfer function of the circuit in Figure 9-1 is given in Equation 1. VOUT ILOAD u RSHUNT u Gain (1) The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is shown using Equation 2. RSHUNT VSHUNT _ MAX ILOAD _ MAX 100mV 1A 100m: (2) Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the TLV900x to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by the TLV900x to produce the necessary output voltage is calculated using Equation 3. Gain VOUT _ MAX VIN _ MAX VOUT _ MIN VIN _ MIN (3) Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4 sizes the resistors RF and RG, to set the gain of the TLV900x to 49 V/V. Gain 1 RF RG (4) Selecting RF as 57.6 kΩ and RG as 1.2 kΩ provides a combination that equals 49 V/V. Figure 9-2 shows the measured transfer function of the circuit shown in Figure 9-1. Notice that the gain is only a function of the feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors values are determined by the impedance levels that the designer wants to establish. The impedance level determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no optimal impedance selection that works for every system, you must choose an impedance that is ideal for your system parameters. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 29 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 9.2.1.3 Application Curve 5 Output (V) 4 3 2 1 0 0 0.2 0.4 0.6 0.8 ILOAD (A) 1 C219 Figure 9-2. Low-Side, Current-Sense Transfer Function 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 9.2.2 Single-Supply Photodiode Amplifier Photodiodes are used in many applications to convert light signals to electrical signals. The current through the photodiode is proportional to the photon energy absorbed, and is commonly in the range of a few hundred picoamps to a few tens of microamps. An amplifier in a transimpedance configuration is typically used to convert the low-level photodiode current to a voltage signal for processing in an MCU. The circuit shown in Figure 9-3 is an example of a single-supply photodiode amplifier circuit using the TLV9002. +3.3V R1 11.5 NŸ CF 10 pF R2 357 Ÿ RF 309 NŸ VREF 3.3 V ± VOUT TLV9002 VREF IIN 0-10 µA + CPD 47 pF RL 10 k Figure 9-3. Single-Supply Photodiode Amplifier Circuit Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 31 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 9.2.2.1 Design Requirements The design requirements for this design are: • • • • Supply voltage: 3.3 V Input: 0 µA to 10 µA Output: 0.1 V to 3.2 V Bandwidth: 50 kHz 9.2.2.2 Detailed Design Procedure The transfer function between the output voltage (VOUT), the input current, (IIN) and the reference voltage (VREF) is defined in Equation 5. VOUT IIN u RF VREF (5) § R u R2 · V u¨ 1 ¸ © R1 R2 ¹ (6) Where: VREF Set VREF to 100 mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio calculated in Equation 7. VREF V 0.1 V 3.3 V 0.0303 (7) The closest resistor ratio to meet this ratio sets R1 to 11.5 kΩ and R2 to 357 Ω. The required feedback resistance can be calculated based on the input current and desired output voltage. RF VOUT VREF IIN 3.2 V 0.1 V 10 PA 310 kV | 309 k: A (8) Calculate the value for the feedback capacitor based on RF and the desired –3-dB bandwidth, (f–3dB) using Equation 9. CF 1 2 u S u RF u f 3dB 1 2 u S u 309 k: u 50 kHz 10.3 pF | 10 pF (9) The minimum op amp bandwidth required for this application is based on the value of RF, CF, and the capacitance on the INx– pin of the TLV9002 which is equal to the sum of the photodiode shunt capacitance, (CPD) the common-mode input capacitance, (CCM) and the differential input capacitance (CD) as Equation 10 shows. CIN CPD CCM CD 47 pF 5 pF 1 pF 53 pF (10) The minimum op amp bandwidth is calculated in Equation 11. f BGW t CIN CF 2 u S u RF u CF2 t 324 kHz (11) The 1-MHz bandwidth of the TLV900x meets the minimum bandwidth requirement and remains stable in this application configuration. 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 9.2.2.3 Application Curves The measured current-to-voltage transfer function for the photodiode amplifier circuit is shown in Figure 9-4. The measured performance of the photodiode amplifier circuit is shown in Figure 9-5. 3 120 2.5 Output Voltage (V) Gain (dB) 100 80 2 1.5 1 60 0.5 40 10 0 100 1k 10k Frequency (Hz) 100k 1M 0 2E-6 D001 Figure 9-4. Photodiode Amplifier Circuit AC Gain Results 4E-6 6E-6 Input Current (A) 8E-6 1E-5 D002 Figure 9-5. Photodiode Amplifier Circuit DC Results Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 33 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 10 Power Supply Recommendations The TLV900x family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply from –40°C to 125°C. Section 7.11 presents parameters that may exhibit significant variance with regard to operating voltage or temperature. CAUTION Supply voltages larger than 6 V may permanently damage the device; see Section 7.1. Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.1. 10.1 Input and ESD Protection The TLV900x family incorporates internal ESD protection circuits on all pins. For input and output pins, this protection primarily consists of current-steering diodes connected between the input and power-supply pins. These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10 mA. Figure 10-1 shows how a series input resistor can be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in noise-sensitive applications. V+ IOVERLOAD 10-mA maximum Device VOUT VIN 5 kW Figure 10-1. Input Current Protection 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 11 Layout 11.1 Layout Guidelines For best operational performance of the device, use good printed circuit board (PCB) layout practices, including: • • • • • • • • Noise can propagate into analog circuitry through the power connections of the board and propagate to the power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a low-impedance path to ground. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply applications. Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the ground current. To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as opposed to running the traces in parallel with the noisy trace. Place the external components as close to the device as possible, as shown in Figure 11-2. Keeping RF and RG close to the inverting input minimizes parasitic capacitance. Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive part of the circuit. Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce leakage currents from nearby traces that are at different potentials. Cleaning the PCB following board assembly is recommended for best performance. Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. 11.2 Layout Example + VIN 1 + VIN 2 VOUT 1 RG VOUT 2 RG RF RF Figure 11-1. Schematic Representation Place components close to device and to each other to reduce parasitic errors . OUT 1 VS+ OUT1 Use low-ESR, ceramic bypass capacitor . Place as close to the device as possible . GND V+ RF OUT 2 GND IN1 ± OUT2 IN1 + IN2 ± RF RG VIN 1 GND RG V± Use low-ESR, ceramic bypass capacitor . Place as close to the device as possible . GND VS± IN2 + Ground (GND) plane on another layer VIN 2 Keep input traces short and run the input traces as far away from the supply lines as possible . Figure 11-2. Layout Example Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 35 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: • Texas Instruments, EMI Rejection Ratio of Operational Amplifiers 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. Bluetooth® is a registered trademark of Bluetooth SIG, Inc. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary 36 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 TLV9001, TLV9002, TLV9004 www.ti.com SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9001 TLV9002 TLV9004 37 PACKAGE OPTION ADDENDUM www.ti.com 18-Nov-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TLV9001IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1OGF TLV9001IDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 1BZ TLV9001IDPWR ACTIVE X2SON DPW 5 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 DF TLV9001SIDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1OJF TLV9001SIDCKR ACTIVE SC70 DCK 6 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 1F8 TLV9001TIDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 1D6 TLV9001UIDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1ODF TLV9002IDDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T902 TLV9002IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1GNX TLV9002IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1GNX TLV9002IDR ACTIVE SOIC D 8 2500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TL9002 TLV9002IDSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1GMH TLV9002IDSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1GMH TLV9002IPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 9002 TLV9002SIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1GDX TLV9002SIRUGR ACTIVE X2QFN RUG 10 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 ENF TLV9002SIYCKR ACTIVE DSBGA YCK 9 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 125 JK TLV9004IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV9004 TLV9004IDYYR ACTIVE SOT-23-THIN DYY 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TLV9004I TLV9004IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TLV9004 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Nov-2021 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TLV9004IRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T9004 TLV9004IRUCR ACTIVE QFN RUC 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1DC TLV9004SIRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T9004S (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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TLV9001SIDBVR
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