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TLV9061, TLV9062, TLV9064
SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
TLV906xS 10-MHz, RRIO, CMOS Operational Amplifiers for Cost-Sensitive Systems
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The TLV9061 (single), TLV9062 (dual), and TLV9064
(quad) are single-, dual-, and quad- low-voltage (1.8
V to 5.5 V) operational amplifiers (op amps) with railto-rail input- and output-swing capabilities. These
devices are highly cost-effective solutions for
applications where low-voltage operation, a small
footprint, and high capacitive load drive are required.
Although the capacitive load drive of the TLV906x is
100 pF, the resistive open-loop output impedance
makes stabilizing with higher capacitive loads
simpler. These op amps are designed specifically for
low-voltage operation (1.8 V to 5.5 V) with
performance specifications similar to the OPAx316
and TLVx316 devices.
1
•
•
Rail-to-rail input and output
Low input offset voltage: ±0.3 mV
Unity-gain bandwidth: 10 MHz
Low broadband noise: 10 nV/√Hz
Low input bias current: 0.5 pA
Low quiescent current: 538 µA
Unity-gain stable
Internal RFI and EMI filter
Operational at supply voltages as low as 1.8 V
Easier to stabilize with higher capacitive load due
to resistive open-loop output impedance
Shutdown version: TLV906xS
Extended temperature range: –40°C to 125°C
Device Information(1)
PART NUMBER
PACKAGE
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
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BODY SIZE (NOM)
SOT-23 (5)
E-bikes
Smoke detectors
HVAC: heating, ventilating, and air conditioning
Motor control: AC induction
Refrigerators
Wearable devices
Laptop computers
Washing machines
Sensor signal conditioning
Power modules
Barcode scanners
Active filters
Low-side current sensing
1.60 mm × 2.90 mm
SC70 (5)
TLV9061
1.25 mm × 2.00 mm
(2)
TLV9061S
TLV9062
TLV9062S
TLV9064
TLV9064S
SOT553 (5)
1.65 mm × 1.20 mm
X2SON (5)
0.80 mm × 0.80 mm
SOT-23 (6)
1.60 mm × 2.90 mm
SOIC (8)
3.91 mm × 4.90 mm
TSSOP (8)
3.00 mm × 4.40 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOT-23 (8)
1.60 mm × 2.90 mm
WSON (8)
2.00 mm × 2.00 mm
VSSOP (10)
3.00 mm × 3.00 mm
X2QFN (10)
1.50 mm × 2.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
4.40 mm × 5.00 mm
WQFN (16)
3.00 mm × 3.00 mm
X2QFN (14)
2.00 mm × 2.00 mm
WQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Package is for preview only.
Single-Pole, Low-Pass Filter
RG
RF
Small-Signal Overshoot vs Load Capacitance
60
50
R1
VIN
C1
f-3 dB =
(
RF
VOUT
= 1+
RG
VIN
((
1
1 + sR1C1
(
1
2pR1C1
Overshoot (%)
VOUT
40
30
20
10
Overshoot+
Overshoot-
0
0
50
100
150
200
Capacitive Load (pF)
250
300
C025
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLV9061, TLV9062, TLV9064
SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Description (continued)......................................... 5
Device Comparison Table..................................... 5
Pin Configuration and Functions ......................... 6
Specifications....................................................... 12
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
9
Absolute Maximum Ratings ....................................
ESD Ratings............................................................
Recommended Operating Conditions.....................
Thermal Information: TLV9061 ...............................
Thermal Information: TLV9061S .............................
Thermal Information: TLV9062 ...............................
Thermal Information: TLV9062S .............................
Thermal Information: TLV9064 ...............................
Thermal Information: TLV9064S .............................
Electrical Characteristics.......................................
Typical Characteristics ..........................................
12
12
12
13
13
13
14
14
14
15
17
Detailed Description ............................................ 23
9.1 Overview ................................................................. 23
9.2 Functional Block Diagram ....................................... 23
9.3 Feature Description................................................. 24
9.4 Device Functional Modes........................................ 25
10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
10.2 Typical Applications .............................................. 26
11 Power Supply Recommendations ..................... 28
11.1 Input and ESD Protection ..................................... 28
12 Layout................................................................... 29
12.1 Layout Guidelines ................................................. 29
12.2 Layout Example .................................................... 30
13 Device and Documentation Support ................. 31
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
31
14 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (May 2019) to Revision J
Page
•
Deleted TLV9062IDDFR (SOT-23 (8)) package preview notations throughout data sheet ................................................... 1
•
Added industry standard package names to Device Comparison Table .............................................................................. 5
•
Added note to packages with thermal pads, specifying that the thermal pads need to be connected to V–......................... 7
•
Added link to Shutdown Function section in SHDN pin function rows ................................................................................. 11
•
Added EMI Rejection section to the Feature Description section ........................................................................................ 24
•
Changed Shutdown Function section to add more clarification .......................................................................................... 25
Changes from Revision H (April 2019) to Revision I
•
Page
Added DDF (SOT-23) thermal information to replace TBDs ................................................................................................ 13
Changes from Revision G (December 2018) to Revision H
Page
•
Added SOT-23 (8) information to Device Information ........................................................................................................... 1
•
Added DDF package column to Device Comparison Table ................................................................................................... 5
•
Added DDF (SOT-23) package to Pin Functions ................................................................................................................... 7
•
Added DDF (SOT-23) package to Thermal Information....................................................................................................... 13
•
Added TLV9062 RUG (X2QFN) thermal information to replace TBDs ................................................................................ 14
2
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SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
Changes from Revision F (September 2018) to Revision G
Page
•
Changed TLV9064 RUC package name From WQFN (14) : To X2QFN (14) in Device Information table ........................... 1
•
Added TLV9064 RUC (X2QFN) pinout drawing to Pin Configuration and Functions section................................................ 9
•
Added RUC (X2QFN) package pinout information to Pin Functions: TLV9064 table ............................................................ 9
•
Added RUC (X2QFN) to Thermal Information: TLV9064 table ............................................................................................ 14
Changes from Revision E (July 2018) to Revision F
Page
•
Deleted Shutdown part numbers from datasheet header ..................................................................................................... 1
•
Deleted X2QFN (10) package from TLV9062 Device Information table ................................................................................ 1
•
Added references to shutdown part numbers in Description section .................................................................................... 5
•
Changed TLV906xS series to TLV906xS family throughout datasheet ................................................................................. 5
•
Added Shutdown devices to Device Comparison Table ....................................................................................................... 5
•
Changed pin namings for all pinout drawings to reflect updated nomenclature ................................................................... 6
•
Added TLV9061S Thermal Information Table ...................................................................................................................... 13
•
Added TLV9064S Thermal Information Table ...................................................................................................................... 14
•
Deleted Partial Shutdown Amplifer Enable Time ................................................................................................................. 16
•
Added clarification on selecting resistors for a current sensing application in the Typical Applications Section ................ 27
•
Changed wording of third bullet in Layout Guidelines .......................................................................................................... 29
Changes from Revision D (June 2018) to Revision E
Page
•
Added TLV9061S device to Device Information table............................................................................................................ 1
•
Added TLV9064S device to Device Information table............................................................................................................ 1
•
Added RUC and RUG packages to the Device Comparison table ........................................................................................ 5
•
Added TLV9061S DBV (SOT-23) pinout drawing to Pin Configuration and Functions section ............................................. 7
•
Added TLV9061S DBV (SOT-23) package pinout information to Pin Functions: TLV9061S table ....................................... 7
•
Added TLV9062S RUG (VSSOP) package pinout drawing to Pin Configuration and Functions section .............................. 8
•
Added TLV9062S RUG (VSSOP) package pinout information to Pin Functions: TLV9062S table ....................................... 8
•
Added TLV9064 RTE (WQFN) pinout drawing to Pin Configuration and Functions section ................................................ 9
•
Added TLV9064 RTE pinout information to Pin Functions: TLV9064 table ........................................................................... 9
•
Added TLV9064S RTE (WQFN) pinout drawing to Pin Configuration and Functions section ............................................ 11
Changes from Revision C (March 2018) to Revision D
Page
•
Added shutdown suffix to "TLV906x" to document title.......................................................................................................... 1
•
Added "Shutdown Version" bullet to Features list ................................................................................................................. 1
•
Added TLV9062S device to Device Information table............................................................................................................ 1
•
Added shutdown text to Description (continued) section ....................................................................................................... 5
•
Added "(VS = [V+] – [V–]) supply voltage parameter in Absolute Maximum Ratings table .................................................. 12
•
Added "input voltage range" and "output voltage range" parameters and values to Recommended Operating
Conditions table .................................................................................................................................................................... 12
•
Added shutdown pin recommended operating conditions in Recommended Operating Conditions table .......................... 12
•
Added "TA" symbol to "specified temperature" parameter to Recommended Operating Conditions table ......................... 12
•
Added Thermal Information: TLV9062S thermal table data ................................................................................................. 14
•
Added Thermal Information: TLV9062S thermal table data ................................................................................................. 14
•
Added shutdown section to Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V table...... 16
Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TLV9061 TLV9062 TLV9064
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TLV9061, TLV9062, TLV9064
SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
•
www.ti.com
Added Shutdown Function section ...................................................................................................................................... 25
Changes from Revision B (October 2017) to Revision C
Page
•
Changed device status from Production Data/Mixed Status to Production Data .................................................................. 1
•
Deleted package preview note from TLV9061 DPW (X2SON) package in Device Information table .................................. 1
•
Deleted package preview note from TLV9061 DPW (X2SON) package pinout drawing ...................................................... 6
•
Changed formatting of ESD Ratings table to show different results for all packages ......................................................... 12
•
Deleted package preview note from DPW (X2SON) package in Thermal Information: TLV9061 table ............................. 13
•
Deleted package preview note from DPW (X2SON) package in Thermal Information: TLV9061 table ............................. 13
Changes from Revision A (June 2017) to Revision B
Page
•
Added 8-pin PW package to Pin Configuration and Functions section ................................................................................. 7
•
Added DSG (WSON) package to Thermal Information table ............................................................................................... 13
•
Added PW (TSSOP) to TLV9062 Thermal Information table .............................................................................................. 13
•
Changed maximum input offset voltage value from ±1.6 mV to 2 mV ................................................................................. 15
•
Changed maximum input offset voltage value from ±1.5 to ±1.6 mV................................................................................... 15
•
Changed minimum common-mode rejection ratio input voltage range from 86 dB to 80 dB ............................................. 15
•
Changed typical input current noise density value from 10 to 23 fA/√Hz............................................................................. 15
•
Changed THD + N test conditions from VS = 5 V to VS = 5.5 V........................................................................................... 15
•
Added VCM = 2.5 V test condition to THD + N parameter in Electrical Characteristics table .............................................. 15
•
Added maximum output voltage swing value from 25 mV to 60 mV.................................................................................... 15
•
Changed maximum output voltage swing value from 15 mV to 20 mV .............................................................................. 15
Changes from Original (March 2017) to Revision A
•
4
Page
Changed device status from Advance Information to Production Data ................................................................................. 1
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SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
5 Description (continued)
The TLV906xS devices include a shutdown mode that allow the amplifiers to switch into standby mode with
typical current consumption less than 1 µA.
The TLV906xS family helps simplify system design, because the family is unity-gain stable, integrates the RFI
and EMI rejection filter, and provides no phase reversal in overdrive condition.
Micro size packages, such as X2SON and X2QFN, are offered for all the channel variants (single, dual and
quad), along with industry-standard packages, such as SOIC, MSOP, SOT-23, and TSSOP.
6 Device Comparison Table
PACKAGE LEADS
DEVICE
NO. OF
CHANNELS
TLV9061
SOIC
D
SOT-23
DBV
SC-70
DCK
VSSOP
DGK
VSSOP
DGS
X2SON
DPW
SOT-553
DRL
WSON
DSG
TSSOP
PW
SOT-23
DDF
WQFN
RTE
X2QFN
RUC
X2QFN
RUG
8
5
5
—
—
5
5
—
—
—
—
—
—
TLV9061S
—
6
—
—
—
—
—
—
—
—
—
—
—
TLV9062
8
—
—
8
10
—
—
8
8
8
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
10
14
—
—
—
—
—
—
—
14
—
16
14
—
—
—
—
—
—
—
—
—
—
—
16
—
—
1
2
TLV9062S
TLV9064
4
TLV9064S
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SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
www.ti.com
7 Pin Configuration and Functions
TLV9061 DBV, DRL Packages
5-Pin SOT-23, SOT-553
Top View
OUT
1
V±
5
TLV9061 DCK Package
5-Pin SC70
Top View
V+
IN+
1
V±
2
IN±
3
5
V+
4
OUT
2
IN+
3
4
IN±
Not to scale
Not to scale
TLV9061 DPW Package
5-Pin X2SON
Top View
OUT
1
5
V+
4
IN+
3
V±
IN±
2
Not to scale
Pin Functions: TLV9061
PIN
I/O
DESCRIPTION
SOT-23,
SOT-553
SC70
X2SON
IN–
4
3
2
I
Inverting input
IN+
3
1
4
I
Noninverting input
OUT
1
4
1
O
Output
V–
2
2
3
I or —
V+
5
5
5
I
NAME
6
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Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
Copyright © 2017–2019, Texas Instruments Incorporated
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SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
TLV9061S DBV Package
6-Pin SOT-23
Top View
OUT
1
6
V+
V±
2
5
SHDN
+IN
3
4
±IN
Not to scale
Pin Functions: TLV9061S
PIN
NAME
I/O
NO.
DESCRIPTION
IN–
4
I
Inverting input
IN+
3
I
Noninverting input
OUT
1
O
Output
SHDN
5
I
Shutdown: low = amp disabled, high = amp enabled. See Shutdown Function section for
more information.
V–
2
I or —
V+
6
I
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
TLV9062 D, DGK, PW, DDF Packages
8-Pin SOIC, VSSOP, TSSOP, SOT-23
Top View
TLV9062 DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
OUT1
1
8
V+
IN1±
2
7
OUT2
IN1+
3
6
IN2±
V±
4
5
IN2+
OUT1
1
IN1±
2
IN1+
3
V±
4
Thermal
Pad
8
V+
7
OUT2
6
IN2±
5
IN2+
Not to scale
Not to scale
(1)
Connect thermal pad to V–
Pin Functions: TLV9062
PIN
NAME
NO.
I/O
DESCRIPTION
IN1–
2
I
Inverting input, channel 1
IN1+
3
I
Noninverting input, channel 1
IN2–
6
I
Inverting input, channel 2
IN2+
5
I
Noninverting input, channel 2
OUT1
1
O
Output, channel 1
OUT2
7
O
Output, channel 2
V–
4
—
Negative (lowest) supply or ground (for single-supply operation)
V+
8
—
Positive (highest) supply
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TLV9062S DGS Package
10-Pin VSSOP
Top View
TLV9062S RUG Package
10-Pin X2QFN
Top View
10
V+
IN1±
2
9
OUT2
IN1+
3
8
IN2±
V±
4
7
IN2+
SHDN1
5
6
SHDN2
V±
1
9
IN1±
SHDN1
2
8
OUT1
SHDN2
3
7
V+
IN2+
4
6
OUT2
5
Not to scale
IN1+
1
10
OUT1
IN2±
Not to scale
Pin Functions: TLV9062S
PIN
NAME
I/O
DESCRIPTION
VSSOP
X2QFN
IN1–
2
9
I
Inverting input, channel 1
IN1+
3
10
I
Noninverting input, channel 1
IN2–
8
5
I
Inverting input, channel 2
IN2+
7
4
I
Noninverting input, channel 2
OUT1
1
8
O
Output, channel 1
OUT2
9
6
O
Output, channel 2
SHDN1
5
2
I
Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Shutdown
Function section for more information.
SHDN2
6
3
I
Shutdown: low = amp disabled, high = amp enabled. Channel 2. See Shutdown
Function section for more information.
V–
4
1
I or —
V+
10
7
I
8
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Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
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SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
TLV9064 D, PW Packages
14-Pin SOIC, TSSOP
Top View
13
IN4±
IN1+
3
12
IN4+
V+
4
11
V±
IN2+
5
10
IN3+
IN2±
6
9
IN3±
OUT2
7
8
OUT3
IN1±
1
IN1+
2
V+
12
IN4±
11
IN4+
3
10
V±
IN2+
4
9
IN3+
IN2±
5
8
IN3±
Not to scale
1
V+
2
IN1±
OUT1
OUT4
IN4±
16
15
14
13
12
IN4+
11
V±
10
IN3+
9
IN3±
OUT2
TLV9064 RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
IN1+
OUT4
2
13
IN1±
7
OUT4
OUT3
14
14
1
6
OUT1
OUT1
TLV9064 RUC Package
14-Pin X2QFN
Top View
Not to scale
Thermal
(1)
6
7
8
NC
OUT3
4
NC
IN2±
Pad
5
3
OUT2
IN2+
Not to scale
Connect thermal pad to V–
Pin Functions: TLV9064
PIN
I/O
DESCRIPTION
SOIC,
TSSOP
WQFN
X2QFN
IN1–
2
16
1
I
Inverting input, channel 1
IN1+
3
1
2
I
Noninverting input, channel 1
IN2–
6
4
5
I
Inverting input, channel 2
IN2+
5
3
4
I
Noninverting input, channel 2
IN3–
9
9
8
I
Inverting input, channel 3
IN3+
10
10
9
I
Noninverting input, channel 3
IN4–
13
13
12
I
Inverting input, channel 4
IN4+
12
12
11
I
Noninverting input, channel 4
NAME
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Pin Functions: TLV9064 (continued)
PIN
I/O
DESCRIPTION
SOIC,
TSSOP
WQFN
NC
—
6, 7
—
—
No internal connection
OUT1
1
15
14
O
Output, channel 1
OUT2
7
5
6
O
Output, channel 2
OUT3
8
8
7
O
Output, channel 3
OUT4
14
14
13
O
Output, channel 4
V–
11
11
10
I or —
V+
4
2
3
I
NAME
10
Submit Documentation Feedback
X2QFN
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
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SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
IN1+
1
V+
2
IN1±
OUT1
OUT4
IN4±
16
15
14
13
TLV9064S RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
12
IN4+
11
V±
10
IN3+
9
IN3±
Thermal
(1)
6
7
8
SHDN34
OUT3
4
SHDN12
IN2±
Pad
5
3
OUT2
IN2+
Not to scale
Connect thermal pad to V–
Pin Functions: TLV9064S
PIN
NAME
NO.
I/O
DESCRIPTION
IN1–
16
I
Inverting input, channel 1
IN1+
1
I
Noninverting input, channel 1
IN2–
4
I
Inverting input, channel 2
IN2+
3
I
Noninverting input, channel 2
IN3–
9
I
Inverting input, channel 3
IN3+
10
I
Noninverting input, channel 3
IN4–
13
I
Inverting input, channel 4
IN4+
12
I
Noninverting input, channel 4
OUT1
15
O
Output, channel 1
OUT2
5
O
Output, channel 2
OUT3
8
O
Output, channel 3
OUT4
14
O
Output, channel 4
SHDN12
6
I
Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Shutdown Function
section for more information.
SHDN34
7
I
Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Shutdown Function
section for more information.
V–
11
I or —
V+
2
I
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
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8 Specifications
8.1 Absolute Maximum Ratings
over operating ambient temperature (unless otherwise noted) (1)
Supply voltage [(V+) – (V–)]
Common-mode
Voltage (2)
Signal input pins
(V+) + 0.5
V
–10
10
Continuous
UNIT
V
mA
mA
–40
125
Junction, TJ
150
Storage, Tstg
(3)
V
(V+) – (V–) + 0.2
Specified, TA
(2)
6
(V–) – 0.5
Output short-circuit (3)
(1)
MAX
0
Differential
Current (2)
Temperature
MIN
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
Short-circuit to ground, one amplifier per package.
8.2 ESD Ratings
VALUE
UNIT
TLV9061 PACKAGES
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
V
ALL OTHER PACKAGES
V(ESD)
(1)
(2)
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
1.8
5.5
V
(V–) – 0.1
(V+) + 0.1
V
Output voltage range
V–
V+
V
High level input voltage at shutdown pin (amplifier enabled)
1.1
V+
V
VSHDN_IL
Low level input voltage at shutdown pin (amplifier disabled)
V–
0.2
V
TA
Specified temperature
–40
125
°C
VS
Supply voltage (VS = [V+] – [V–])
VI
Input voltage range
VO
VSHDN_IH
12
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UNIT
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8.4 Thermal Information: TLV9061
TLV9061
THERMAL METRIC (1)
DBV (SOT-23)
DCK (SC70)
DPW (X2SON)
5 PINS
UNIT
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
221.7
263.3
467
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
144.7
75.5
211.6
°C/W
RθJB
Junction-to-board thermal resistance
49.7
51
332.2
°C/W
ψJT
Junction-to-top characterization parameter
26.1
1
29.3
°C/W
ψJB
Junction-to-board characterization parameter
49
50.3
330.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
125
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
8.5 Thermal Information: TLV9061S
TLV9061S
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
216.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
155.1
°C/W
RθJB
Junction-to-board thermal resistance
96.2
°C/W
ψJT
Junction-to-top characterization parameter
80.3
°C/W
ψJB
Junction-to-board characterization parameter
95.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics.
8.6 Thermal Information: TLV9062
TLV9062
THERMAL METRIC
(1)
D (SOIC)
DGK (VSSOP)
DSG (WSON)
PW (TSSOP)
DDF (SOT-23)
8 PINS
8 PINS
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal
resistance
157.6
201.2
94.4
205.8
184.4
°C/W
RθJC(top)
Junction-to-case (top) thermal
resistance
104.6
85.7
116.5
106.7
112.8
°C/W
RθJB
Junction-to-board thermal
resistance
99.7
122.9
61.3
133.9
99.9
°C/W
ψJT
Junction-to-top
characterization parameter
55.6
21.2
13
34.4
18.7
°C/W
ψJB
Junction-to-board
characterization parameter
99.2
121.4
61.7
132.6
99.3
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
N/A
34.4
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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8.7 Thermal Information: TLV9062S
TLV9062S
THERMAL METRIC (1)
DGS (VSSOP)
RUG (X2QFN)
10 PINS
10 PINS
UNIT
170.4
197.2
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
84.9
93.3
°C/W
RθJB
Junction-to-board thermal resistance
113.5
123.8
°C/W
ψJT
Junction-to-top characterization parameter
16.4
3.7
°C/W
ψJB
Junction-to-board characterization parameter
112.3
120.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
8.8 Thermal Information: TLV9064
TLV9064
THERMAL METRIC (1)
RθJA
PW (TSSOP)
D (SOIC)
RTE (WQFN)
RUC (X2QFN)
14 PINS
14 PINS
16 PINS
14 PINS
135.8
106.9
65.1
205.5
°C/W
64
64
67.9
72.5
°C/W
Junction-to-ambient thermal resistance
RθJC(top) Junction-to-case (top) thermal resistance
UNIT
RθJB
Junction-to-board thermal resistance
79
63
40.4
150.2
°C/W
ψJT
Junction-to-top characterization parameter
15.7
25.9
5.5
3.0
°C/W
ψJB
Junction-to-board characterization parameter
78.4
62.7
40.2
149.6
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
N/A
23.8
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
8.9 Thermal Information: TLV9064S
TLV9064S
THERMAL METRIC (1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
65.1
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
67.9
°C/W
RθJB
Junction-to-board thermal resistance
40.4
°C/W
ψJT
Junction-to-top characterization parameter
5.5
°C/W
ψJB
Junction-to-board characterization parameter
40.2
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
23.8
°C/W
(1)
14
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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8.10 Electrical Characteristics
For VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.3
±1.6
UNIT
OFFSET VOLTAGE
VS = 5 V
VOS
Input offset voltage
dVOS/dT
Drift
VS = 5 V, TA = –40°C to 125°C
±0.53
PSRR
Power-supply rejection ratio
VS = 1.8 V – 5.5 V, VCM = (V–)
±7
Channel separation, DC
At DC
VS = 5 V, TA = –40°C to 125°C
mV
±2
µV/°C
±80
µV/V
100
dB
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
VS = 1.8 V to 5.5 V
(V–) – 0.1
(V+) + 0.1
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C
80
103
VS = 5.5 V, VCM = –0.1 V to 5.6 V,
TA = –40°C to 125°C
57
87
V
dB
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C
88
VS = 1.8 V, VCM = –0.1 V to 1.9 V,
TA = –40°C to 125°C
81
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
±0.5
pA
±0.05
pA
4.77
µVPP
NOISE
En
Input voltage noise (peak-topeak)
en
Input voltage noise density
in
Input current noise density
VS = 5 V, f = 0.1 Hz to 10 Hz
VS = 5 V, f = 10 kHz
10
VS = 5 V, f = 1 kHz
16
f = 1 kHz
23
fA/√Hz
nV/√Hz
INPUT CAPACITANCE
CID
Differential
2
pF
CIC
Common-mode
4
pF
OPEN-LOOP GAIN
VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
RL = 10 kΩ
AOL
Open-loop voltage gain
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ
100
104
130
dB
VS = 1.8 V, (V–) + 0.06 V < VO < (V+) – 0.06 V,
RL = 2 kΩ
100
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ
130
FREQUENCY RESPONSE
GBP
Gain bandwidth product
VS = 5 V, G = +1
10
φm
Phase margin
VS = 5 V, G = +1
55
MHz
°
SR
Slew rate
VS = 5 V, G = +1
6.5
V/µs
To 0.1%, VS = 5 V, 2-V step , G = +1, CL = 100 pF
0.5
tS
Settling time
To 0.01%, VS = 5 V, 2-V step,
G = +1, CL = 100 pF
tOR
Overload recovery time
VS = 5 V, VIN × gain > VS
THD + N
Total harmonic distortion +
noise (1)
VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1,
f = 1 kHz
µs
1
0.2
µs
0.0008%
OUTPUT
VO
Voltage output swing from supply VS = 5.5 V, RL = 10 kΩ
rails
VS = 5.5 V, RL = 2 kΩ
ISC
Short-circuit current
VS = 5 V
±50
mA
ZO
Open-loop output impedance
VS = 5 V, f = 10 MHz
100
Ω
(1)
20
60
mV
Third-order filter; bandwidth = 80 kHz at –3 dB.
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Electrical Characteristics (continued)
For VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
538
750
UNIT
POWER SUPPLY
IQ
Quiescent current per amplifier
VS = 5.5 V, IO = 0 mA
VS = 5.5 V, IO = 0 mA, TA = –40°C to 125°C
800
µA
SHUTDOWN
IQSD
Quiescent current per amplifier
VS = 1.8 V to 5.5 V, all amplifiers disabled,
SHDN = Low
ZSHDN
Output impedance during
shutdown
VS = 1.8 V to 5.5 V, amplifier disabled
High level voltage shutdown
threshold (amplifier enabled)
VS = 1.8 V to 5.5 V
Low level voltage shutdown
threshold (amplifier disabled)
VS = 1.8 V to 5.5 V
tON
Amplifier enable time
(shutdown) (2)
tOFF
VSHDN_THR
_HI
VSDHN_THR
_LO
(2)
16
0.5
1.5
10 || 8
(V–) + 0.9 V
(V–) + 0.2 V
µA
GΩ || pF
(V–) + 1.1 V
V
(V–) + 0.7 V
V
VS = 1.8 V to 5.5 V, full shutdown; G = 1,
VOUT = 0.9 × VS / 2, RL connected to V–
10
µs
Amplifier disable time (2)
VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2,
RL connected to V–
0.6
µs
SHDN pin input bias current (per
pin)
VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) – 0.8 V
130
VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V– + 0.8 V
40
pA
Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
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8.11 Typical Characteristics
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
35
50
30
40
Population (%)
Population (%)
25
20
15
30
20
10
Offset Voltage (µV)
2.8
2.4
2
1.6
1.2
0.8
0
0
1500
1250
1000
750
500
0
250
-250
-500
-750
-1000
-1250
-1500
0
0.4
10
5
Offset Voltage Drift (µV/C)
C001
C002
TA = –40°C to 125°C
Figure 2. Offset Voltage Drift Distribution
2500
400
2000
300
1500
Offset Voltage (µV)
Offset Voltage (µV)
Figure 1. Offset Voltage Production Distribution
500
200
100
0
±100
±200
1000
500
0
±500
±1000
±300
±1500
±400
±2000
±500
±2500
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
-4
-3
-2
-1
0
1
2
3
4
Input Common Mode Voltage (V)
C003
V+ = 2.75 V
Figure 3. Offset Voltage vs Temperature
C005
V– = –2.75 V
Figure 4. Offset Voltage vs Common-Mode Voltage
1000
120
180
500
0
±500
±1000
100
Phase
135
80
60
90
40
20
45
0
0
±20
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Supply Voltage (V)
5.5
100
1k
10k
100k
1M
10M
Frequency (Hz)
C004
VS = 1.8 V to 5.5 V
Figure 5. Offset Voltage vs Power Supply
Phase Margin (deg)
Open Loop Voltage Gain (dB)
Offset Voltage (µV)
Gain
C006
CL = 10 pF
Figure 6. Open-Loop Gain and Phase vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
40
VS = 5.5 V
Closed Lopp Voltage Gain (dB)
Open Loop Voltage Gain (µV/V)
20
VS = 1.8 V
16
12
8
4
30
20
10
0
±10
G=+1
±20
G=-1
±30
G=+10
0
±50
±25
0
25
50
75
100
±40
1000
125
Temperature (ƒC)
10k
100k
1M
10M
Frequency (Hz)
C022
C007
RL = 2 kΩ
Figure 8. Closed-Loop Gain vs Frequency
3
IBN
200
2
IBP
IOS
Output Voltage (V)
Input Bias Current and offset current (pA)
Figure 7. Open-Loop Gain vs Temperature
250
150
100
50
0
125ƒC
1
85ƒC
0
25ƒC
85ƒC
±1
-40ƒC
125ƒC
±2
±3
±50
±50
±25
0
25
50
75
100
10
125
Temperature (ƒC)
20
30
Figure 9. Input Bias Current vs Temperature
50
C009
V– = –2.75 V
55
CMRR
PSRR-
50
PSRR+
CMRR (µV/V)
80
60
40
20
45
40
35
0
1000
10k
100k
1M
Frequency (Hz)
10M
C011
30
±50
±25
0
25
50
75
Temperature (ƒC)
Figure 11. CMRR and PSRR vs Frequency
(Referred to Input)
18
60
Figure 10. Output Voltage Swing vs Output Current
120
100
40
Output Current (mA)
C008
V+ = 2.75 V
PSRR and CMRR (dB)
-40ƒC
25ƒC
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VS = 5.5 V
RL= 10 kΩ
VCM = –0.1 V to 5.6 V
100
125
C012
TA= –40°C to 125°C
Figure 12. CMRR vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
10
10
9
9
7
PSRR (µV/V)
CMRR (µV/V)
8
6
5
4
3
8
7
6
2
5
1
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
±50
0
±25
25
VCM = (V–) – 0.1 V to (V+) – 1.4 V
TA= –40°C to 125°C
RL= 10 kΩ
50
75
100
125
Temperature (ƒC)
C016
C013
VS = 1.8 V to 5.5 V
VS = 5.5 V
Figure 13. CMRR vs Temperature
Figure 14. PSRR vs Temperature
Time (1s/div)
C014
,QSXW 9ROWDJH 1RLVH 6SHFWUDO 'HQVLW\ Q9 ¥+]
Voltage (1µV/div)
120
100
80
60
40
20
0
10
100
1k
10k
100k
Frequency (Hz)
C015
VS = 1.8 V to 5.5 V
Figure 15. 0.1-Hz to 10-Hz Input Voltage Noise
Figure 16. Input Voltage Noise Spectral Density vs
Frequency
±90
±40
±95
THD + N (dB)
THD + N (dB)
±60
±100
±105
±110
±80
±100
±115
±120
100
1k
Frequency (Hz)
VS = 5.5 V
VOUT = 0.5 VRMS
±120
0.001
10k
VCM = 2.5 V
BW = 80 kHz
RL = 2 kΩ
G = +1
Figure 17. THD + N vs Frequency
0.01
0.1
1
Output Voltage Amplitude (VRMS)
C017
VS = 5.5 V
VCM = 2.5 V
RL = 2 kΩ
BW = 80 kHz
C018
G = +1
f = 1 kHz
Figure 18. THD + N vs Amplitude
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
600
±40
580
Quiescent current (µA)
THD + N (dB)
±60
±80
±100
560
540
520
500
±120
0.001
0.01
0.1
1
1.5
Output Voltage Amplitude (VRMS)
VS = 5.5 V
G = –1
VCM = 2.5 V
BW = 80 kHz
3
3.5
4
4.5
5.5
C020
Figure 20. Quiescent Current vs Supply Voltage
Open Loop Output Impedance (Ÿ)
200
700
600
500
400
300
200
100
160
120
80
40
0
0
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
10k
1M
10M
Frequency (Hz)
C024
Figure 22. Open-Loop Output Impedance vs Frequency
60
50
50
40
40
Overshoot (%)
60
30
20
10
100k
C021
Figure 21. Quiescent Current vs Temperature
30
20
10
Overshoot+
Overshoot(+)
Overshoot-
Overshoot(-)
0
0
0
50
100
150
200
Capacitive Load (pF)
V+ = 2.75 V
VOUT step = 100 mVp-p
V– = –2.75 V
RL = 10 kΩ
250
300
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0
50
100
G = +1 V/V
150
200
Capacitive Load (pF)
C025
Figure 23. Small-Signal Overshoot vs Load Capacitance
20
5
RL = 2 kΩ
f = 1 kHz
Figure 19. THD + N vs Amplitude
Quiescent Current (µA)
2.5
Supply Voltage (V)
800
Overshoot (%)
2
C019
V+ = 2.75 V
VOUT step = 100 mVp-p
V– = –2.75 V
RL = 10 kΩ
250
300
C026
G = –1 V/V
Figure 24. Small-Signal Overshoot vs Load Capacitance
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Typical Characteristics (continued)
Voltage (1V/div)
Voltage (2 V/V)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
INPUT
Input
OUTPUT
Output
Time (1 µs/div)
Time (200 µs/div)
C028
C036
V+ = 2.75 V
V+ = 2.75 V
V– = –2.75 V
V– = –2.75 V
G = –10 V/V
Figure 26. Overload Recovery
Figure 25. No Phase Reversal
Input
Voltage (1 V/div)
Voltage (20 mV/div)
Output
Input
Output
Time (1 µs/div)
Time (0.1µs/div)
C031
C030
V+ = 2.75 V
V– = –2.75 V
V+ = 2.75 V
G = 1 V/V
G = 1 V/V
CL = 100 pF
Figure 28. Large-Signal Step Response
Figure 27. Small-Signal Step Response
6
80
60
Maximum Output Voltage (V)
Short Circuit Current Limit (mA)
V– = –2.75 V
40
20
Sinking
0
Sourcing
±20
±40
±60
5
4
3
2
1
VS = 5.5 V
VS = 1.8 V
0
±80
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
1
10
RL = 10 kΩ
Figure 29. Short-Circuit Current vs Temperature
100
1k
10k
100k
1M
Frequency (Hz)
C034
10M
C035
CL = 10 pF
Figure 30. Maximum Output Voltage vs Frequency and
Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
0
120
±20
Channel Separation (dB)
140
EMIRR (dB)
100
80
60
40
20
±40
±60
±80
±100
±120
0
±140
10M
100M
1G
100
Frequency (Hz)
Figure 31. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
1M
10M
C038
V– = –2.75 V
200
Open Loop Voltage Gain (dB)
75
60
45
30
15
160
120
80
40
0
0
0
10
20
30
40
50
60
70
80
90
Capacitive Load (pF)
0
100
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Voltage (V)
C037
VS = 5.5 V
5.5
C023
VS = 5.5 V
Figure 33. Phase Margin vs Capacitive Load
Figure 34. Open Loop Voltage Gain vs Output Voltage
100
100
75
75
50
50
Output voltage (mV)
Output Voltage (mV)
100k
Figure 32. Channel Separation vs Frequency
90
25
0
±25
±50
25
0
-25
-50
-75
-100
±75
-125
-150
±100
0
0.3
0.6
Figure 35. Large Signal Settling Time (Positive)
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0.9
Settling time (µs)
22
10k
Frequency (Hz)
V+ = 2.75 V
PRF = –10 dBm
Phase Margin (degrees)
1k
C041
0.3
0.6
0.9
1.2
Settling time (µs)
C032
1.5
C033
Figure 36. Large Signal Settling Time (Negative)
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9 Detailed Description
9.1 Overview
The TLV906x devices are a family of low-power, rail-to-rail input and output op amps. These devices operate
from 1.8 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications.
The input common-mode voltage range includes both rails and allows the TLV906x series to be used in virtually
any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially
in low-supply applications. The high bandwidth enables this family to drive the sample-hold circuitry of analog-todigital converters (ADCs).
9.2 Functional Block Diagram
V+
Reference
Current
V
V
INÛ
IN+
V
BIAS1
Class AB
Control
Circuitry
V
O
V
BIAS2
VÛ
(Ground)
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9.3 Feature Description
9.3.1 Rail-to-Rail Input
The input common-mode voltage range of the TLV906x family extends 100 mV beyond the supply rails for the
full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage: an
N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block
Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 200 mV
above the positive supply, whereas the P-channel pair is active for inputs from 200 mV below the negative
supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in
which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the
transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift,
and THD can degrade compared to device operation outside this region.
9.3.2 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TLV906x series delivers a robust output drive
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 15 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
9.3.3 EMI Rejection
The TLV906x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV906x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 37 shows the results of this testing on the TLV906x. Table 1 shows the EMIRR IN+ values for the
TLV906x at particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of
Operational Amplifiers application report contains detailed information on the topic of EMIRR performance as it
relates to op amps and is available for download from www.ti.com.
140
120
EMIRR (dB)
100
80
60
40
20
0
10M
100M
1G
Frequency (Hz)
C041
Figure 37. EMIRR Testing
Table 1. TLV906x EMIRR IN+ For Frequencies of Interest
FREQUENCY
24
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
59.5 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
68.9 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
77.8 dB
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Feature Description (continued)
Table 1. TLV906x EMIRR IN+ For Frequencies of Interest (continued)
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
78.0 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
88.8 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
87.6 dB
5 GHz
9.3.4 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the TLV906x family is approximately 200 ns.
9.3.5 Shutdown Function
The TLV906xS devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode. In
this mode, the op amp typically consumes less than 1 µA. The SHDN pins are active-low, meaning that
shutdown mode is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown
feature lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has
been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.2 V and V+. The shutdown
pin must either be connected to a valid high or a low voltage or driven, and not left as an open circuit. There is
no internal pull-up to enable the amplifier.
The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled, and
quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may
be used to greatly reduce the average current and extend battery life. The enable time is 10 µs for full shutdown
of all channels; disable time is 6 µs. When disabled, the output assumes a high-impedance state. This
architecture allows the TLV906xS to be operated as a gated amplifier (or to have the device output multiplexed
onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to
midsupply (VS / 2) is required. If using the TLV906xS without a load, the resulting turnoff time is significantly
increased.
9.4 Device Functional Modes
The TLV906x family are operational when the power-supply voltage is between 1.8 V (±0.9 V) and 5.5 V
(±2.75 V). The TLV906xS devices feature a shutdown mode and are shut down when a valid logic low is applied
to the shutdown pin.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TLV906x family features 10-MHz bandwidth and 6.5-V/µs slew rate with only 538 µA of supply current per
channel, providing good AC-performance at very low power consumption. DC applications are well served with a
very low input noise voltage of 10 nV/√Hz at 10 kHz, low input bias current, and a typical input offset voltage of
0.3 mV.
10.2 Typical Applications
10.2.1 Typical Low-Side Current Sense Application
Figure 38 shows the TLV906x configured in a low-side current-sensing application.
VBUS
ILOAD
ZLOAD
5V
+
VOUT
TLV906x
VSHUNT
Rshunt
0.1
RF
165 k
RG
3.4 k
Figure 38. TLV906x in a Low-Side, Current-Sensing Application
10.2.1.1 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.95 V
• Maximum shunt voltage: 100 mV
26
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Typical Applications (continued)
10.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 38 is given in Equation 1.
VOUT ILOAD u RSHUNT u Gain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _ MAX 100mV
RSHUNT
100m:
ILOAD _ MAX
1A
(2)
Using Equation 2, RSHUNT equals 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the
TLV906x to produce an output voltage of approximately 0 V to 4.95 V. Equation 3 calculates the gain required for
the TLV906x to produce the required output voltage.
Gain
VOUT _ MAX
VIN _ MAX
VOUT _ MIN
VIN _ MIN
(3)
Using Equation 3, the required gain equals 49.5 V/V, which is set with the RF and RG resistors. Equation 4 sizes
the RF and RG, resistors to set the gain of the TLV906x to 49.5 V/V.
RF
Gain 1
RG
(4)
Selecting RF to equal 165 kΩ and RG to equal 3.4 kΩ provides a combination that equals approximately 49.5
V/V. Figure 39 shows the measured transfer function of the circuit shown in Figure 38. Notice that the gain is
only a function of the feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and
the actual resistor values are determined by the impedance levels that the designer wants to establish. The
impedance level determines the current drain, the effect that stray capacitance has, and a few other behaviors.
There is no optimal impedance selection that works for every system, you must choose an impedance that is
ideal for your system parameters.
10.2.1.3 Application Curve
5
Output (V)
4
3
2
1
0
0
0.2
0.4
0.6
0.8
ILOAD (A)
1
C219
Figure 39. Low-Side, Current-Sense, Transfer Function
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11 Power Supply Recommendations
The TLV906x series is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to 125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute
Maximum Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
11.1 Input and ESD Protection
The TLV906x series incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA, as shown in the Absolute Maximum Ratings table. Figure 40 shows how a series input resistor can be
added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier
input and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
Device
VOUT
VIN
5 kW
Figure 40. Input Current Protection
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12 Layout
12.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply
applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more
detailed information, see Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much
better as opposed to running the traces in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 42, keeping RF and
RG close to the inverting input minimizes parasitic capacitance on the inverting input.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low-temperature, postcleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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12.2 Layout Example
+
VIN 1
+
VIN 2
VOUT 1
RG
VOUT 2
RG
RF
RF
Figure 41. Schematic Representation for Figure 42
Place components
close to device and to
each other to reduce
parasitic errors .
OUT 1
VS+
OUT1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
V+
RF
OUT 2
GND
IN1 ±
OUT2
IN1 +
IN2 ±
RF
RG
VIN 1
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
GND
VS±
IN2 +
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible .
Ground (GND) plane on another layer
Figure 42. Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
Texas Instruments, TLVx313 Low-Power, Rail-to-Rail In/Out, 500-μV Typical Offset, 1-MHz Operational Amplifier
for Cost-Sensitive Systems
Texas Instruments, TLVx314 3-MHz, Low-Power, Internal EMI Filter, RRIO, Operational Amplifier
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
Texas Instruments, QFN/SON PCB Attachment
Texas Instruments, Quad Flatpack No-Lead Logic Packages
Texas Instruments, Circuit Board Layout Techniques
Texas Instruments, Single-Ended Input to Differential Output Conversion Circuit Reference Design
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV9061
Click here
Click here
Click here
Click here
Click here
TLV9062
Click here
Click here
Click here
Click here
Click here
TLV9064
Click here
Click here
Click here
Click here
Click here
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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10-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
(1)
TLV9061IDBVR
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1OAF
TLV9061IDCKR
ACTIVE
SC70
DCK
5
3000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
1CA
TLV9061IDPWR
ACTIVE
X2SON
DPW
5
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
CG
TLV9061SIDBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1OEF
TLV9062IDDFR
ACTIVE
SOT-23-THIN
DDF
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T062
TLV9062IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T062
TLV9062IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T062
TLV9062IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
TL9062
TLV9062IDSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T062
TLV9062IDSGT
ACTIVE
WSON
DSG
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T062
TLV9062IPWR
ACTIVE
TSSOP
PW
8
2000
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
TL9062
TLV9062SIDGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1TDX
TLV9062SIRUGR
ACTIVE
X2QFN
RUG
10
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
EOF
TLV9064IDR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TLV9064D
TLV9064IPWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
TLV9064
TLV9064IPWT
ACTIVE
TSSOP
PW
14
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
TLV9064
TLV9064IRTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T9064
TLV9064IRUCR
ACTIVE
QFN
RUC
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1DD
TLV9064SIRTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
T9064S
The marketing status values are defined as follows:
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2021
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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