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F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
F28M36x Concerto™ Microcontrollers
1 Device Overview
1.1
Features
1
• Master Subsystem — Arm® Cortex®-M3
– 125 MHz
– Embedded memory
– Up to 1MB of flash (ECC)
– Up to 128KB of RAM (ECC or parity)
– Up to 64KB of shared RAM
– 2KB of IPC Message RAM
– Five Universal Asynchronous
Receiver/Transmitters (UARTs)
– Four Synchronous Serial Interfaces (SSIs)
and a Serial Peripheral Interface (SPI)
– Two Inter-integrated Circuits (I2Cs)
– Universal Serial Bus On-the-Go (USB-OTG) +
PHY
– 10/100 ENET 1588 MII
– Two Controller Area Network, D_CAN, modules
(pin-bootable)
– 32-channel Micro Direct Memory Access
(µDMA)
– Dual security zones (128-bit password per zone)
– External Peripheral Interface (EPI)
– Micro Cyclic Redundancy Check (µCRC)
module
– Four general-purpose timers
– Two watchdog timer modules
– Three external interrupts
– Endianness: little endian
• Clocking
– On-chip crystal oscillator and external clock
input
– Dynamic Phase-Locked Loop (PLL) ratio
changes supported
• 1.2-V digital, 1.8-V analog, 3.3-V I/O design
• Interprocessor Communications (IPC)
– 32 handshaking channels
– Four channels generate IPC interrupts
– Can be used to coordinate transfer of data
through IPC Message RAMs
• Up to 142 individually programmable, multiplexed
General-Purpose Input/Output (GPIO) pins
– Glitch-free I/Os
• Control Subsystem — TMS320C28x 32-bit CPU
– 150 MHz
– C28x core hardware built-in self-test
– Embedded memory
– Up to 512KB of flash (ECC)
– Up to 36KB of RAM (ECC or parity)
– Up to 64KB of shared RAM
– 2KB of IPC Message RAM
– IEEE-754 single-precision Floating-Point Unit
(FPU)
– Viterbi, Complex Math, CRC Unit (VCU)
– Serial Communications Interface (SCI)
– SPI
– I2C
– 6-channel Direct Memory Access (DMA)
– 12 Enhanced Pulse Width Modulator (ePWM)
modules
– 24 outputs (16 high-resolution)
– Six 32-bit Enhanced Capture (eCAP) modules
– Three 32-bit Enhanced Quadrature Encoder
Pulse (eQEP) modules
– Multichannel Buffered Serial Port (McBSP)
– EPI
– One security zone (128-bit password)
– Three 32-bit timers
– Endianness: little endian
• Analog Subsystem
– Dual 12-bit Analog-to-Digital Converters (ADCs)
– Up to 2.88 MSPS
– Up to 24 channels
– Four Sample-and-Hold (S/H) circuits
– Up to six comparators with 10-bit Digital-toAnalog Converter (DAC)
• Package
– 289-ball ZWT New Fine Pitch Ball Grid Array
(nFBGA)
• Temperature options:
– T: –40ºC to 105ºC Junction
– S: –40ºC to 125ºC Junction
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
1.2
•
•
•
•
•
Applications
Automated sorting equipment
CNC control
Central inverter
String inverter
AC drive control module
1.3
www.ti.com
•
•
•
•
•
Servo drive control module
AC-input BLDC motor drive
DC-input BLDC motor drive
Industrial AC-DC
Three phase UPS
Description
The Concerto family is a multicore system-on-chip microcontroller unit (MCU) with independent
communication and real-time control subsystems. The F28M36x family of devices is the second series in
the Concerto family.
The communications subsystem is based on the industry-standard 32-bit Arm Cortex-M3 CPU and
features a wide variety of communication peripherals, including Ethernet 1588, USB OTG with PHY,
Controller Area Network (CAN), UART, SSI, I2C, and an external interface.
The real-time control subsystem is based on TI’s industry-leading proprietary 32-bit C28x floating-point
CPU and features the most flexible and high-precision control peripherals, including ePWMs with fault
protection, and encoders and captures—all as implemented by TI’s TMS320C2000™ Entry performance
MCUs and Premium performance MCUs. In addition, the C28-CPU has been enhanced with the addition
of the VCU instruction accelerator that implements efficient Viterbi, Complex Arithmetic, 16-bit FFTs, and
CRC algorithms.
A high-speed analog subsystem and supplementary RAM memory is shared, along with on-chip voltage
regulation and redundant clocking circuitry. Safety considerations also include Error Correction Code
(ECC), parity, and code secure memory, as well as documentation to assist with system-level industrial
safety certification.
Device Information (1)
PACKAGE
BODY SIZE
F28M36P63C2ZWT
PART NUMBER
nFBGA (289)
16.0 mm × 16.0 mm
F28M36P53C2ZWT
nFBGA (289)
16.0 mm × 16.0 mm
(1)
2
For more information on these devices, see Mechanical, Packaging, and Orderable Information.
Device Overview
Copyright © 2012–2020, Texas Instruments Incorporated
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F28M36H53B2, F28M36H33B2
www.ti.com
1.4
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Functional Block Diagram
1.8-V
VREG
GPIO_MUX1
1.2-V
VREG
SECURE
C1
RAM
8KB
(ECC)
SECURE
FLASH
WDOG (2)
uCRC
NMI WDOG
GP TIMER (4)
SSI (4)
2
UART (5)
I C (2)
EMAC
CAN (2)
EPI
USB+PHY (OTG)
BOOT
ROM
C9-C15
RAM
7 ´ 8KB
(parity)
C2-C8
SECURE
C0
RAM
8KB
(ECC)
1MB
(ECC)
64KB
RAM
7 ´ 8KB
(parity)
REGS
ONLY
APB BUS
AHB BUS
uDMA BUS
AIO_MUX1
12 PINS
12
ADC
INPUTS
ADC_1
MODULE
M3
BUS
MATRIX
M3
uDMA
6
COMP
INPUTS
ANALOG COMMON INTERFACE BUS
GPIO_MUX2
8 PINS
6
COMPARE
6
+ DAC
COMP
UNITS
OUT
PUTS
MPU
M3 CPU
NVIC
M3 SYSTEM BUS
C28 CPU/DMA
ACCESS TO EPI
CLOCKS
I-CODE BUS
D-CODE BUS
INTERPROC
COMM
FREQ
GASKET
RESETS
MEM32
TO AHB
BUS
BRIDGE
NMI
DEBUG
S0
S1
S2
S3
S4
S5
S6
S7
8KB
8KB
8KB
8KB
8KB
8KB
8KB
8KB
IPC
MTOC
MSG
RAM
(parity)
2KB
CTOM
MSG
RAM
(parity)
2KB
S0-S7 SHARED RAM (parity)
INTERPROC
COMM
SECURITY
12 PINS
AIO_MUX2
6
COMP
INPUTS
C28 DMA BUS
C28
VCU
C28
DMA
ADC_2
12
MODULE
ADC
INPUTS
C28 CPU
PIE
C28
FPU
C28 CPU BUS
ANALOG
SUBSYSTEM
16BIT
PF2
32BIT
PF1
32BIT
PF3
16/32
- BIT
PF0
TIMER (3)
McBSP
EPWM (12)
ECAP (6)
EQEP (3)
NMI WDOG
SPI
SCI
2
IC
XINT (3)
BOOT
ROM
64KB
SECURE
FLASH
512KB
(ECC)
GPIO_MUX1
136 PINS
SECURE
L1
RAM
8KB
(ECC)
L3
M1
RAM
8KB
(parity)
RAM
2KB
(ECC)
SECURE
L0
RAM
8KB
(ECC)
L2
M0
RAM
8KB
(parity)
RAM
2KB
(ECC)
Copyright © 2017, Texas Instruments Incorporated
Figure 1-1. Functional Block Diagram
Copyright © 2012–2020, Texas Instruments Incorporated
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Device Overview
3
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table of Contents
1
2
3
Device Overview ......................................... 1
6.5
Analog Subsystem ................................. 184
1.1
Features .............................................. 1
6.6
Master Subsystem NMIs ........................... 187
1.2
Applications ........................................... 2
6.7
Control Subsystem NMIs
1.3
Description ............................................ 2
1.4
Functional Block Diagram
6.8
6.9
Revision History ......................................... 5
Device Comparison ..................................... 6
Resets.............................................. 189
Internal Voltage Regulation and Power-On-Reset
Functionality........................................ 194
6.10
Input Clocks and PLLs ............................. 197
Related Products ..................................... 9
6.11
Master Subsystem Clocking ....................... 207
Terminal Configuration and Functions ............ 10
6.12
Control Subsystem Clocking ....................... 212
Pin Diagrams ........................................ 10
6.13
Analog Subsystem Clocking ....................... 215
Signal Descriptions .................................. 15
6.14
Shared Resources Clocking ....................... 215
Specifications ........................................... 42
6.15
Loss of Input Clock (NMI Watchdog Function) .... 215
6.16
GPIOs and Other Pins ............................. 217
3.1
4
4.1
4.2
5
........................
ESD Ratings – Commercial .........................
Recommended Operating Conditions ...............
Power Consumption Summary......................
Electrical Characteristics ............................
5.1
Absolute Maximum Ratings
5.2
5.3
5.4
5.5
5.6
42
42
43
44
....................
7
8
...................................
.............................
6.19 µCRC Module ......................................
Applications, Implementation, and Layout ......
7.1
TI Reference Design ...............................
Device and Documentation Support ..............
187
6.17
Emulation/JTAG
237
6.18
Code Security Module
240
242
244
244
245
8.1
Device and Development Support Tool
Nomenclature ...................................... 245
5.8
Thermal Design Considerations
50
8.2
Tools and Software ................................ 246
5.9
Timing and Switching Characteristics ............... 51
8.3
Documentation Support ............................ 247
5.10
Analog and Shared Peripherals ..................... 70
8.4
Related Links
106
8.5
Support Resources
127
8.6
160
8.7
....................
5.12 Control Subsystem Peripherals ....................
Detailed Description .................................
6.1
Memory Maps ......................................
6.2
Identification........................................
6.3
Master Subsystem .................................
6.4
Control Subsystem .................................
5.11
4
3
48
Thermal Resistance Characteristics for ZWT
Package (Revision 0 Silicon)........................ 49
Thermal Resistance Characteristics for ZWT
Package (Revision A Silicon) ....................... 49
5.7
6
...........................
..........................
Master Subsystem Peripherals
Table of Contents
161
8.8
248
249
249
249
249
173
Mechanical, Packaging, and Orderable
Information ............................................. 250
179
9.1
172
9
......................................
................................
Trademarks ........................................
Electrostatic Discharge Caution ...................
Glossary............................................
Packaging Information ............................. 250
Copyright © 2012–2020, Texas Instruments Incorporated
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F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
2 Revision History
Changes from December 15, 2017 to June 23, 2020 (from E Revision (December 2017) to F Revision)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Page
Global: Removed F28M36H53C2 and F28M36H33C2. ........................................................................ 1
Global: Replaced "emulator" with "JTAG debug probe". ....................................................................... 1
Section 1.1 (Features): Added "Three External Interrupts" feature. ........................................................... 1
Section 1.2 (Applications): Updated section. ..................................................................................... 2
Section 3.1 (Related Products): Updated section. ............................................................................... 9
Table 4-1 (Signal Descriptions): Updated DESCRIPTION of XRS, EMU0, and EMU1. ................................... 15
Section 5.2 (ESD Ratings – Commercial): Changed title from "ESD Ratings" to "ESD Ratings – Commercial". ..... 42
Section 5.2: Added ANSI/ESDA/JEDEC JS-002 to charged-device model (CDM). ........................................ 42
Section 5.9.1.1 (Power Management and Supervisory Circuit Solutions): Updated section. ............................. 52
Section 5.10.1.5 (ADC Electrical Data and Timing): Removed "Typical ADC Total Error" figure (was Figure 5-12
in SPRS825E)........................................................................................................................ 73
Table 5-38 (Electrical Characteristics of the Comparator/DAC): Changed "Comparator response time to PWM
Trip Zone (Async)" parameter to "Comparator response time to GPIO". .................................................... 76
Table 5-75 (SPI Master Mode External Timing (Clock Phase = 0)): Updated MIN value (for both BRR EVEN and
BRR ODD) for Parameter 23, td(SPC)M. .......................................................................................... 145
Table 5-76 (SPI Master Mode External Timing (Clock Phase = 1)): Updated MIN value (for both BRR EVEN and
BRR ODD) for Parameter 23, td(SPC)M. .......................................................................................... 147
Table 6-7 (Control Subsystem Flash, ECC, OTP, Boot ROM): Removed references to 256KB Flash from
0010 0000 to 0011 FFFF. Changed SIZE (BYTES) of EPI0 from 2G to 2M. Added footnote about Control
Subsystem having less address reach to EPI memory than the Master Subsystem. ................................... 165
Table 6-8 (Master Subsystem Flash, ECC, OTP, Boot ROM): Updated M ADDRESS range 0068 0480 to
0070 01FF. ......................................................................................................................... 166
Table 6-8: Removed references to 256KB Flash from 0022 0000 to 002D FFFF. ....................................... 166
Table 6-11 (Master Subsystem Analog and EPI): Added footnote about Control Subsystem having less address
reach to EPI memory than the Master Subsystem. ........................................................................... 171
Section 6.18 (Code Security Module): Updated section. .................................................................... 240
Section 7.1 (TI Reference Design): Changed section title from "TI Design or Reference Design" to "TI Reference
Design". Updated section. ....................................................................................................... 244
Section 8 (Device and Documentation Support): Changed "Community Resources" section to "Support
Resources" section. Updated section. .......................................................................................... 245
Section 8.2 (Tools and Software): Updated section. .......................................................................... 246
Section 8.3 (Documentation Support): Updated section. ..................................................................... 247
Section 8.4 (Related Links): Updated section. ................................................................................ 248
Copyright © 2012–2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2
Revision History
5
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
3 Device Comparison
Table 3-1 lists the features of the F28M36x devices.
Table 3-1. Device Comparison
TYPE(1)
FEATURE
P63C2
P53C2
H53B2
H33B2
Master Subsystem — Arm Cortex-M3
Speed (MHz)(2)
–
125
125
100
100
Flash (ECC) (KB)
–
1024
512
512
512
RAM (ECC) (KB)
–
16
16
16
16
RAM (Parity) (KB)
–
112
112
112
112
IPC Message RAM (Parity) (KB)
–
2
2
2
2
Security Zones
–
2
2
2
2
10/100 ENET 1588 MII
0
Yes
Yes
No
No
USB OTG FS
0
Yes
Yes
No
No
SSI/SPI
0
4
4
4
4
UART
0
5
5
5
5
I2C
0
2
2
2
2
CAN(3)
0
2
2
2
2
µDMA
0
32-ch
32-ch
32-ch
32-ch
EPI(4)
0
1
1
1
1
µCRC module
0
1
1
1
1
General-Purpose Timers
–
4
4
4
4
Watchdog Timer modules
–
2
2
2
2
150
150
150
150
Control Subsystem — C28x
Speed (MHz)(2)
FPU
Yes
VCU
Yes
Flash (ECC) (KB)
512
512
512
512
RAM (ECC) (KB)
20
20
20
20
RAM (Parity) (KB)
16
16
16
16
IPC Message RAM (Parity) (KB)
2
2
2
2
Security Zones
1
1
1
1
ePWM modules
2
12: 24 outputs
High-Resolution Pulse Width Modulator (HRPWM) outputs
2
16 outputs
eCAP modules/PWM outputs
0
6 (32-bit)
6
Device Comparison
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www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 3-1. Device Comparison (continued)
FEATURE
TYPE(1)
P63C2
P53C2
H53B2
H33B2
eQEP modules
0
3 (32-bit)
Fault Trip Zones
–
12 on any of 64 GPIO pins
McBSP/SPI
1
1
1
1
1
SCI
0
1
1
1
1
SPI
0
1
1
1
1
I2C
0
1
1
1
1
DMA
0
6-ch
6-ch
6-ch
6-ch
EPI(4)
0
1
1
1
1
32-Bit Timers
–
3
3
3
3
Shared
Shared RAM (Parity) (KB)
MSPS(5)
12-Bit ADC 1
Conversion Time(5)
Channels
3
Sample-and-Hold
MSPS(5)
12-Bit ADC 2
Conversion Time(5)
Channels
3
Sample-and-Hold
Comparators with Integrated DACs
0
Voltage Regulator
64
64
64
0
2.88
2.88
2.88
2.88
347 ns
347 ns
347 ns
347 ns
12
12
12
12
2
2
2
2
2.88
2.88
2.88
2.88
347 ns
347 ns
347 ns
347 ns
12
12
12
12
2
2
2
2
6
6
6
6
Yes – Uses 3.3-V Single Supply (3.3-V/1.2-V recommended for 125ºC)
Clocking
See Section 6.10
Additional Safety
Master Subsystem
Control Subsystem
Shared
2 Watchdogs, NMI Watchdog: CPU, Memory
NMI Watchdog: CPU, Memory
Critical Register and I/O Function Lock Protection; RAM Fetch Protection
Device Comparison
Copyright © 2012–2020, Texas Instruments Incorporated
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7
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 3-1. Device Comparison (continued)
TYPE(1)
FEATURE
P63C2
P53C2
H53B2
H33B2
Packaging
Package Type
Junction Temperature (TJ)
289-Ball ZWT New Fine Pitch Ball Grid Array
Yes
Yes
Yes
Yes
T: –40°C to 105°C
–
Yes
Yes
Yes
Yes
S: –40°C to 125°C
–
Yes
Yes
Yes
Yes
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the
basic functionality of the module. These device-specific differences are listed in the C2000 Real-Time Control Peripherals Reference Guide and in the peripheral reference guides.
(2) The maximum frequency at which the Cortex-M3 core can run is 125 MHz. The clock divider before the Cortex-M3 core can only take values of /1, /2, or /4. For this reason, when the
C28x is configured to run at the maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex-M3 is 75 MHz. If the Cortex-M3 is configured to run at 125 MHz, the
maximum frequency of the C28x is limited to 125 MHz. If the Cortex-M3 is configured to run at 100 MHz, the maximum frequency of the C28x is limited to 100 MHz.
(3) The CAN module uses the popular IP known as D_CAN. This document uses the names “CAN” and “D_CAN” interchangeably to reference this peripheral.
(4) Single EPI arbitrated between masters in Master and Control Subsystems.
(5) An integer divide ratio must be maintained between the C28x and ADC clock frequencies. All MSPS and Conversion Time values are based on the maximum C28x clock frequency.
Table 3-2. Possible Speed Combinations for Cortex-M3 and C28x Cores
Cortex-M3
75 MHz
125 MHz
100 MHz
C28x
150 MHz
125 MHz
100 MHz
8
Device Comparison
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F28M36H53B2, F28M36H33B2
www.ti.com
3.1
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Related Products
For information about other devices in this family of products, see the following link:
F28M35x Concerto™ Microcontrollers
The F28M3x series of microcontrollers brings together connectivity and control by combining an Arm
Cortex-M3 core with the C28x core on to one device. With F28M3x, applications such as solar inverters
and industrial control can keep the benefits of separating the communication and control portions while
maintaining a single-chip solution. In addition, F28M3x microcontrollers enable safety certifications in your
system through enhanced hardware and safety features.
TMS320F2838x Microcontrollers With Connectivity Manager
The TMS320F2838x is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced
closed-loop control applications. The F2838x supports a dual-core C28x architecture along with a new
Connectivity Manager that offloads critical communication tasks, significantly boosting system
performance. The integrated analog and control peripherals with advanced connectivity peripherals like
EtherCAT and Ethernet also let designers consolidate real-time control and real-time communications
architectures, reducing requirements for multicontroller systems.
Device Comparison
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Copyright © 2012–2020, Texas Instruments Incorporated
9
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagrams
Figure 4-1 illustrates the ball locations for the 289-ball ZWT new fine pitch ball grid array package and is
used in conjunction with Figure 4-2, Figure 4-3, Figure 4-4, and Figure 4-5 to locate signal names and ball
grid numbers.
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
5
3
1
2
4
7
6
9
8
11 13 15 17 19
10 12 14 16 18
Figure 4-1. 289-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View)
10
Terminal Configuration and Functions
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www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Figure 4-2 through Figure 4-5 show the terminal assignments on the 289-ball ZWT package in four
quadrants (A, B, C, and D). See Table 4-1 for the complete multiplexed signal names.
1
2
3
4
5
6
7
8
9
W
VSS
VSS
PK5_
GPIO77
PC1_
GPIO65
PD2_
GPIO18
PD3_
GPIO19
PC5_
GPIO69
PC4_
GPIO68
PE1_
GPIO25
W
V
VSS
PK6_
GPIO78
PK7_
GPIO79
PC0_
GPIO64
PC3_
GPIO67
PE3_
GPIO27
PH2_
GPIO50
PC6_
GPIO70
PC7_
GPIO71
V
U
PL0_
GPIO80
PL1_
GPIO81
PL2_
GPIO82
PK4_
GPIO76
PC2_
GPIO66
PE2_
GPIO26
PH3_
GPIO51
PH1_
GPIO49
PH5_
GPIO53
U
T
PL3_
GPIO83
PL5_
GPIO85
PL6_
GPIO86
VDDIO
VDDIO
VSS
VDDIO
VDDIO
VSS
T
PM0_
GPIO88
PM1_
GPIO89
PM2_
GPIO90
5
6
7
8
9
R
VSS
R
P
PM3_
GPIO91
PM4_
GPIO92
PM5_
GPIO93
PM6_
GPIO94
P
N
PM7_
GPIO95
PS7_
PS6_
GPIO135 GPIO134
PB4_
GPIO12
N
VDD12
VDDIO
VDDIO
N
M
PS5_
PS4_
PS3_
GPIO133 GPIO132 GPIO131
PB5_
GPIO13
M
VDD12
VSS
VSS
M
L
FLT2
PS2_
PS1_
GPIO130 GPIO129
VSS
L
VDDIO
VSS
VSS
L
K
FLT1
PR7_
PS0_
GPIO128 GPIO127
VSS
K
VDDIO
VSS
VSS
K
7
8
9
1
A.
2
3
4
See Table 4-1 for the complete multiplexed signal names.
Figure 4-2. 289-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant A]
Terminal Configuration and Functions
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10
11
12
13
14
15
16
17
18
19
W
PE0_
GPIO24
PG7_
GPIO47
PF6_
GPIO38
PG6_
GPIO46
PG2_
GPIO42
PG5_
GPIO45
PJ0_
GPIO56
PD7_
GPIO23
VSS
VSS
W
V
PH0_
GPIO48
PG0_
GPIO40
PJ2_
GPIO58
PJ1_
GPIO57
PJ5_
GPIO61
PJ4_
GPIO60
PJ6_
GPIO62
PD6_
GPIO22
PL7_
GPIO87
VSS
V
U
PH4_
GPIO52
PF5_
GPIO37
PG1_
GPIO41
VDDIO
PF4_
GPIO36
PJ3_
GPIO59
PD4_
GPIO20
PD5_
GPIO21
PL4_
GPIO84
PE5_
GPIO29
U
T
VDD12
VDD12
VDD12
VDDIO
VSS
VDDIO
VDDIO
PN7_
GPIO103
PE4_
GPIO28
TDO
T
10
11
12
13
14
15
R
VSS
PH6_
GPIO54
PN6_
GPIO102
EMU1
R
P
PF2_
GPIO34
PF3_
GPIO35
PH7_
GPIO55
EMU0
N
PK1_
GPIO73
PG3_
GPIO43
PR0_
GPIO120
TRST
M
PK2_
GPIO74
PR3_
PR1_
GPIO123 GPIO121
TMS
N
M
L
VDDIO
VDDIO
VDD12
VDD12
VSS
VSS
VSS
VDD12
VSS
VSS
VSS
VDDIO
VSS
VSS
VSS
VDDIO
VSS
PN0_
GPIO96
PK3_
GPIO75
TCK
VSS
PK0_
GPIO72
PR2_
GPIO122
TDI
17
18
19
K
K
10
A.
L
11
12
13
16
P
N
M
L
K
See Table 4-1 for the complete multiplexed signal names.
Figure 4-3. 289-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant B]
12
Terminal Configuration and Functions
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
10
11
12
13
J
VSS
VSS
VSS
VDDIO
J
H
VSS
VSS
VSS
VDDIO
G
VDDIO
VDDIO
VDDIO
VDDIO
17
18
19
VSS
PN1_
GPIO97
PN2_
GPIO98
X1
J
H
PJ7_
PN5_
GPIO63/
GPIO101
XCLKIN
VSSOSC
VSSOSC
H
G
PP1_
PP0_
GPIO105 GPIO104
PN3_
GPIO99
X2
G
F
PD0_
GPIO16
PD1_
GPIO17
F
E
VSS
PF1_
GPIO33
PP3_
VREG12EN
GPIO107
VDDIO
PF7_
GPIO39
PG4_
GPIO44
10
11
12
13
14
15
D
VSSA
VSSA
VDD18
VDD18
VSS
VDDIO
C
VDDA
VDDA
ADC1INA6 ADC1INA0 ADC1INB4 ADC1INB7
PQ0_
GPIO112
PN4_
PP2_
GPIO106 GPIO100
D
PP5_
PP4_
PP6_
GPIO110 GPIO109 GPIO108
C
PP7_
ADC2INA6 ADC1INA7 ADC1INA3 ADC1INA2 ADC1INB3 ADC1INB6 GPIO197 GPIO199(A)
GPIO111
A
ADC2INA7 ADC1INA4 ADC1VREFHI ADC1INB0 ADC1INB2 VREG18EN GPIO196 GPIO198
11
12
13
14
15
E
PF0_
GPIO32
B
10
A.
B.
16
16
17
VSS
B
VSS
VSS
A
18
19
All I/Os, except for GPIO199, are glitch-free during power up and power down. See Section 6.11.
See Table 4-1 for the complete multiplexed signal names.
Figure 4-4. 289-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant C]
Terminal Configuration and Functions
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1
J
2
3
PR5_
PR4_
PR6_
GPIO126 GPIO125 GPIO124
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4
7
8
9
VSS
J
VDDIO
VSS
VSS
J
H
PE7_
GPIO31
PE6_
GPIO30
PB7_
GPIO15
PB6_
GPIO14
H
VDDIO
VSS
VSS
H
G
PB3_
GPIO11
PB2_
GPIO10
PB1_
GPIO9
PB0_
GPIO8
G
VDDIO
VDDIO
VDDIO
G
F
PA7_
GPIO7
PA6_
GPIO6
PA5_
GPIO5
PA4_
GPIO4
F
E
PA3_
GPIO3
PA2_
GPIO2
PA1_
GPIO1
VSS
E
D
PA0_
GPIO0
PQ7_
GPIO119
PQ6_
GPIO118
C
XRS
PQ5_
GPIO117
PQ4_
GPIO116
B
VSS
GPIO195 GPIO194 GPIO193 ADC2INB7 ADC2INB4 ADC2INB2 ADC2INA2 ADC2INA3
A
VSS
1
A.
VSS
ARS
5
6
7
8
9
VDDIO
VDDIO
VSS
VDD18
VSSA
VSSA
D
PQ3_
GPIO115
PQ2_
GPIO114
PQ1_
GPIO113
VDD18
ADC2INA0
VDDA
C
GPIO192 ADC2INB6 ADC2INB3 ADC2INB0 ADC2VREFHI ADC2INA4
5
4
2
3
6
See Table 4-1 for the complete multiplexed signal names.
7
8
B
A
9
Figure 4-5. 289-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant D]
14
Terminal Configuration and Functions
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4.2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Signal Descriptions
Table 4-1 describes the signals.
Table 4-1. Signal Descriptions(1)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
DESCRIPTION
PU
or
PD(3)
OUTPUT
BUFFER
STRENGTH
ADC 1 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 1
ADC1VREFHI
A12
I
ADC1 External High Reference – used only when
in ADC external reference mode.
ADC1VREFLO
see VSSA
I
ADC1 External Low Reference – used only when
in ADC external reference mode.
C13
I
ADC1 Group A, Channel 0 input
I
ADC1 Group A, Channel 2 input
I
Comparator Input A1
ADC1INA0
ADC1INA2
COMPA1
B13
AIO2
ADC1INA3
I/O
B12
ADC1INA4
COMPA2
A11
AIO4
ADC1INA6
COMPA3
I
ADC1 Group A, Channel 3 input
I
ADC1 Group A, Channel 4 input
I
Comparator Input A2
I/O
C12
AIO6
ADC1 Group A, Channel 6 input
I
Comparator Input A3
B11
I
ADC1 Group A, Channel 7 input
ADC1INB0
A13
I
ADC1 Group B, Channel 0 input
I
ADC1 Group B, Channel 2 input
I
Comparator Input B1
COMPB1
A14
AIO10
ADC1INB3
I/O
B14
ADC1INB4
COMPB2
C14
AIO12
ADC1INB6
COMPB3
B15
AIO14
ADC1INB7
ADC1 Group B, Channel 3 input
I
ADC1 Group B, Channel 4 input
I
Comparator Input B2
C15
ADC1 Group B, Channel 6 input
I
Comparator Input B3
I
4 mA
Digital AIO12
I
I/O
4 mA
Digital AIO10
I
I/O
4 mA
Digital AIO6
ADC1INA7
ADC1INB2
4 mA
Digital AIO4
I
I/O
4 mA
Digital AIO2
4 mA
Digital AIO14
ADC1 Group B, Channel 7 input
ADC 2 Reference Inputs, Analog Comparator Inputs, DAC Inputs, AIO Group 2
ADC2VREFHI
A8
I
ADC2 External High Reference – used only when
in ADC external reference mode.
ADC2VREFLO
see VSSA
I
ADC2 External Low Reference – used only when
in ADC external reference mode.
C8
I
ADC2 Group A, Channel 0 input
I
ADC2 Group A, Channel 2 input
I
Comparator Input A4
ADC2INA0
ADC2INA2
COMPA4
B8
AIO18
ADC2INA3
I/O
B9
ADC2INA4
COMPA5
A9
AIO20
I
ADC2 Group A, Channel 3 input
I
ADC2 Group A, Channel 4 input
I
Comparator Input A5
I/O
4 mA
Digital AIO18
4 mA
Digital AIO20
Terminal Configuration and Functions
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
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Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
ADC2INA6
COMPA6
B10
AIO22
I/O/Z(2)
DESCRIPTION
I
ADC2 Group A, Channel 6 input
I
Comparator Input A6
I/O
Digital AIO22
A10
I
ADC2 Group A, Channel 7 input
ADC2INB0
A7
I
ADC2 Group B, Channel 0 input
I
ADC2 Group B, Channel 2 input
I
Comparator Input B4
COMPB4
B7
AIO26
I/O
ADC2INB3
A6
ADC2INB4
COMPB5
B6
AIO28
ADC2INB6
COMPB6
A5
AIO30
ADC2 Group B, Channel 3 input
I
ADC2 Group B, Channel 4 input
I
Comparator Input B5
B5
4 mA
Digital AIO28
I
ADC2 Group B, Channel 6 input
I
Comparator Input B6
I/O
ADC2INB7
4 mA
Digital AIO26
I
I/O
I
OUTPUT
BUFFER
STRENGTH
4 mA
ADC2INA7
ADC2INB2
PU
or
PD(3)
4 mA
Digital AIO30
ADC2 Group B, Channel 7 input
ADC Modules Analog Power and Ground
VDDA
C9
3.3-V Analog Module Power Pin. Tie with
a 2.2-µF capacitor (typical) close to the pin.
VDDA
C10
3.3-V Analog Module Power Pin. Tie with
a 2.2-µF capacitor (typical) close to the pin.
VDDA
C11
3.3-V Analog Module Power Pin. Tie with
a 2.2-µF capacitor (typical) close to the pin.
VSSA
D8
Analog ground for ADC1, ADC2, ADC1VREFLO,
ADC2VREFLO, COMP1–6, and DAC1–3
VSSA
D9
Analog ground for ADC1, ADC2, ADC1VREFLO,
ADC2VREFLO, COMP1–6, and DAC1–3
VSSA
D10
Analog ground for ADC1, ADC2, ADC1VREFLO,
ADC2VREFLO, COMP1–6, and DAC1–3
VSSA
D11
Analog ground for ADC1, ADC2, ADC1VREFLO,
ADC2VREFLO, COMP1–6, and DAC1–3
Analog Comparator Results (Digital) and GPIO Group 2 (C28x Access Only)
GPIO192
GPIO193
COMP1OUT
GPIO194
COMP6OUT
GPIO195
COMP2OUT
GPIO196
COMP3OUT
GPIO197
COMP4OUT
GPIO198
GPIO199(4)
COMP5OUT
16
A4
B4
B3
B2
A16
B16
A17
B17
Terminal Configuration and Functions
I/O
General-purpose input/output 192
I/O
General-purpose input/output 193
O
Compare result from Analog Comparator 1
I/O
General-purpose input/output 194
O
Compare result from Analog Comparator 6
I/O
General-purpose input/output 195
O
Compare result from Analog Comparator 2
I/O
General-purpose input/output 196
O
Compare result from Analog Comparator 3
I/O
General-purpose input/output 197
O
Compare result from Analog Comparator 4
I/O
General-purpose input/output 198
I/O
General-purpose input/output 199
O
Compare result from Analog Comparator 5
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
8 mA
PU
4 mA
PU
4 mA
PU
8 mA
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
DESCRIPTION
PU
or
PD(3)
OUTPUT
BUFFER
STRENGTH
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
GPIO Group 1 and Peripheral Signals
PA0_GPIO0
I/O/Z
M_U0RX
M_I2C1SCL
I
D1
I/OD
General-purpose input/output 0
UART-0 receive data
I2C-1 clock open-drain bidirectional port
M_U1RX
I
UART-1 receive data
C_EPWM1A
O
Enhanced PWM-1 output A
PA1_GPIO1
I/O/Z
M_U0TX
O
M_I2C1SDA
M_U1TX
I/OD
E3
General-purpose input/output 1
UART-0 transmit data
I2C-1 data open-drain bidirectional port
O
UART-1 data transmit
M_SSI1FSS
I/O
SSI-1 frame
C_EPWM1B
O
Enhanced PWM-1 output B
I/O
Enhanced Capture-6 input/output
C_ECAP6
PA2_GPIO2
I/O/Z
M_SSI0CLK
I/O
SSI-0 clock
O
EMAC MII transmit data bit 2
C_EPWM2A
O
Enhanced PWM-2 output A
PA3_GPIO3
I/O/Z
M_SSI0FSS
I/O
SSI-0 frame
M_MIITXD2
M_MIITXD1
M_SSI1CLK
E2
E1
C_EPWM2B
C_ECAP5
General-purpose input/output 2
General-purpose input/output 3
O
EMAC MII transmit data bit 1
I/O
SSI-1 clock
O
Enhanced PWM-2 output B
I/O
Enhanced Capture-5 input/output
PA4_GPIO4
I/O/Z
M_SSI0RX
I
SSI-0 receive data
O
EMAC MII transmit data bit 0
M_CAN0RX
I
CAN-0 receive data
C_EPWM3A
O
Enhanced PWM-3 output A
PA5_GPIO5
I/O/Z
M_MIITXD0
F4
General-purpose input/output 4
General-purpose input/output 5
M_SSI0TX
O
SSI-0 transmit data
M_MIIRXDV
I
EMAC MII receive data valid
O
CAN-0 transmit data
C_EPWM3B
O
Enhanced PWM-3 output B
C_MFSRA
I
McBSP-A receive frame sync
C_ECAP1
I/O
M_CAN0TX
F3
Enhanced Capture-1 input/output
PA6_GPIO6
I/O/Z
General-purpose input/output 6
M_I2C1SCL
I/OD
I2C-1 clock open-drain bidirectional port
M_CCP1
M_MIIRXCK
I/O
Capture/Compare/PWM-1
(General-purpose Timer)
I
EMAC MII receive clock
I
CAN-0 receive data
M_USB0EPEN
O
USB-0 external power enable
(optionally used in host mode)
C_EPWM4A
O
Enhanced PWM-4 output A
C_EPWMSYNCO
O
Enhanced PWM-4 external sync pulse
M_CAN0RX
F2
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
DESCRIPTION
PA7_GPIO7
I/O/Z
General-purpose input/output 7
M_I2C1SDA
I/OD
I2C-1 data open-drain bidirectional port
M_CCP4
I/O
I
EMAC MII receive error
M_CAN0TX
O
CAN-0 transmit data
I/O
Capture/Compare/PWM-3
(General-purpose Timer)
F1
I
USB-0 external power error state
(optionally used in the host mode)
M_MIIRXD1
I
EMAC MII receive data 1
C_EPWM4B
O
Enhanced PWM-4 output B
C_MCLKRA
I
McBSP-A receive clock
M_USB0PFLT
C_ECAP2
I/O
PB0_GPIO8
I/O/Z
M_U1RX
I
UART-1 data receive data
M_SSI2TX
O
SSI-2 transmit data
M_CAN1TX
O
CAN-1 transmit data
M_U4TX
O
UART-4 transmit data
C_EPWM5A
O
Enhanced PWM-5 output A
C_ADCSOCAO
O
ADC start-of-conversion A
PB1_GPIO9
I/O/Z
Capture/Compare/PWM-2
(General-purpose Timer)
I/O
Capture/Compare/PWM-1
(General-purpose Timer)
M_U1TX
O
UART-1 transmit data
M_SSI2RX
I
SSI-2 receive data
C_EPWM5B
O
Enhanced PWM-5 output B
C_ECAP3
I/O
Enhanced Capture-3 input/output
PB2_GPIO10
I/O/Z
General-purpose input/output 10
M_I2C0SCL
I/OD
I2C-0 clock open-drain bidirectional port
M_CCP1
G3
M_CCP3
I/O
Capture/Compare/PWM-3
(General-purpose Timer)
M_CCP0
I/O
Capture/Compare/PWM-0
(General-purpose Timer)
O
USB-0 external power enable
(optionally used in the host mode)
M_SSI2CLK
I/O
SSI-2 clock
M_CAN1RX
I
CAN-1 receive data
M_U4RX
I
UART-4 receive data
C_EPWM6A
O
Enhanced PWM-6 output A
C_ADCSOCBO
O
ADC start-of-conversion B
M_USB0EPEN
18
G2
Terminal Configuration and Functions
PU
4 mA
PU
4 mA
PU
4 mA
General-purpose input/output 9
I/O
M_CCP2
4 mA
General-purpose input/output 8
Capture/Compare/PWM-0
(General-purpose Timer)
G4
PU
Enhanced Capture-1 input/output
I/O
M_CCP0
OUTPUT
BUFFER
STRENGTH
Capture/Compare/PWM-4
(General-purpose Timer)
M_MIIRXER
M_CCP3
PU
or
PD(3)
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
DESCRIPTION
PB3_GPIO11
I/O/Z
General-purpose input/output 11
M_I2C0SDA
I/OD
I2C-0 data open-drain bidirectional port
M_USB0PFLT
M_SSI2FSS
I
G1
M_U1RX
I/O
SSI-2 frame
UART-1 receive data
C_EPWM6B
O
Enhanced PWM-6 output B
C_ECAP4
I/O
Enhanced Capture-4 input/output
I/O/Z
General-purpose input/output 12
M_U2RX
I
UART-2 receive data
M_CAN0RX
I
CAN-0 receive data
M_U1RX
I
UART-1 receive data
M_EPI0S23
N4
I/O
EPI-0 signal 23
M_CAN1TX
O
CAN-1 transmit data
M_SSI1TX
O
SSI-1 transmit data
C_EPWM7A
O
Enhanced PWM-7 output A
PB5_GPIO13
I/O/Z
I/O
Capture/Compare/PWM-5
(General-purpose Timer)
M_CCP6
I/O
Capture/Compare/PWM-6
(General-purpose Timer)
M_CCP0
I/O
Capture/Compare/PWM-0
(General-purpose Timer)
O
CAN-0 transmit data
I/O
Capture/Compare/PWM-2
(General-purpose Timer)
M_U1TX
O
UART-1 transmit data
M_EPI0S22
I/O
EPI-0 signal 22
M_CAN1RX
I
CAN-1 receive data
M_SSI1RX
I
SSI-1 receive data
C_EPWM7B
O
Enhanced PWM-7 output B
PB6_GPIO14
I/O/Z
M4
M_CCP2
I/O
Capture/Compare/PWM-1
(General-purpose Timer)
M_CCP7
I/O
Capture/Compare/PWM-7
(General-purpose Timer)
M_CCP5
I/O
Capture/Compare/PWM-5
(General-purpose Timer)
I/O
EPI-0 signal 37
H4
M_MIICRS
I
M_I2C0SDA
I/OD
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
General-purpose input/output 14
M_CCP1
M_EPI0S37(5)
PU
General-purpose input/output 13
M_CCP5
M_CAN0TX
OUTPUT
BUFFER
STRENGTH
USB-0 external power error state
(optionally used in the host mode)
I
PB4_GPIO12
PU
or
PD(3)
EMAC MII carrier sense
I2C-0 data open-drain bidirectional port
M_U1TX
O
UART-1 transmit data
M_SSI1CLK
I/O
SSI-1 clock
C_EPWM8A
O
Enhanced PWM-8 output A
Terminal Configuration and Functions
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
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Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
PB7_GPIO15
I/O/Z
M_EXTNMI
M_MIIRXD1
M_EPI0S36(5)
M_I2C0SCL
I/O/Z(2)
H3
M_U1RX
DESCRIPTION
Cortex-M3 external nonmaskable interrupt
I
EMAC MII receive data 1
I/OD
I
EPI-0 signal 36
I2C-0 clock open-drain bidirectional port
I/O
SSI-1 frame
C_EPWM8B
O
Enhanced PWM-8 output B
PD0_GPIO16
I/O/Z
I
CAN-0 receive data
M_U2RX
I
UART-2 receive data
M_U1RX
I
UART-1 receive data
M_CCP6
I/O
I
EMAC MII receive data valid
I
EMAC MII receive data 2
M_SSI0TX
O
SSI-0 transmit data
M_CAN1TX
O
CAN-1 transmit data
M_USB0EPEN
O
USB-0 external power enable
(optionally used in the host mode)
C_SPISIMOA
I/O
SPI-A slave in, master out
PD1_GPIO17
I/O/Z
O
CAN-0 transmit data
M_U2TX
O
UART-2 transmit data
M_U1TX
O
UART-1 transmit data
M_CCP7
I/O
Capture/Compare/PWM-7
(General-purpose Timer)
O
EMAC MII transmit error
I/O
Capture/Compare/PWM-2
(General-purpose Timer)
M_MIICOL
I
EMAC MII collision detect
M_SSI0RX
I
SSI-0 receive data
M_CAN1RX
I
CAN-1 receive data
M_USB0PFLT
I
USB-0 external power error state
(optionally used in the host mode)
C_SPISOMIA
I/O
PD2_GPIO18
I/O/Z
M_CCP2
M_CCP6
I/O
Capture/Compare/PWM-6
(General-purpose Timer)
I/O
Capture/Compare/PWM-5
(General-purpose Timer)
M_EPI0S20
I/O
EPI-0 signal 20
M_SSI0CLK
I/O
SSI-0 clock
M_U1TX
O
UART-1 transmit data
M_CAN0RX
I
CAN-0 receive data
C_SPICLKA
I/O
20
Terminal Configuration and Functions
4 mA
PU
4 mA
General-purpose input/output 18
I
W5
PU
SPI-A master in, slave out
M_U1RX
M_CCP5
4 mA
General-purpose input/output 17
M_CAN0TX
F19
PU
Capture/Compare/PWM-6
(General-purpose Timer)
M_MIIRXD2
M_MIITXER
4 mA
General-purpose input/output 16
M_CAN0RX
F16
PU
UART-1 receive data
M_SSI1FSS
M_MIIRXDV
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 15
I
I/O
PU
or
PD(3)
UART-1 receive data
SPI-A clock
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
PD3_GPIO19
I/O/Z
DESCRIPTION
O
UART-1 transmit data
M_CCP7
I/O
Capture/Compare/PWM-7
(General-purpose Timer)
I/O
Capture/Compare/PWM-0
(General-purpose Timer)
M_EPI0S21
I/O
EPI-0 signal 21
M_SSI0FSS
I/O
SSI-0 frame
W6
M_U1RX
I
UART-1 receive data
M_CAN0TX
O
CAN-0 transmit data
C_SPISTEA
I/O
SPI-A slave transmit enable
PD4_GPIO20
I/O/Z
I/O
Capture/Compare/PWM-0
(General-purpose Timer)
M_CCP3
I/O
Capture/Compare/PWM-3
(General-purpose Timer)
O
EMAC MII transmit data 3
M_EPI0S19
I/O
EPI-0 signal 19
M_U3TX
O
UART-3 transmit data
M_CAN1TX
O
CAN-1 transmit data
C_EQEP1A
I
Enhanced QEP-1 input A
C_MDXA
O
McBSP-A transmit data
U16
PD5_GPIO21
I/O/Z
I/O
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP4
I/O
Capture/Compare/PWM-4
(General-purpose Timer)
O
EMAC MII transmit data 2
I
UART-2 receive data
M_U2RX
U17
M_EPI0S28
I/O
I
UART-3 receive data
M_CAN1RX
I
CAN-1 receive data
C_EQEP1B
I
Enhanced QEP-1 input B
I
McBSP-A receive data
PD6_GPIO22
I/O/Z
O
EMAC MII transmit data 1
M_U2TX
O
UART-2 transmit data
I/O
EPI-0 signal 29
M_I2C1SDA
V17
I/OD
4 mA
PU
6 mA
PU
6 mA
General-purpose input/output 22
M_MIITXD1
M_EPI0S29
PU
EPI-0 signal 28
M_U3RX
C_MDRA
4 mA
General-purpose input/output 21
M_CCP2
M_MIITXD2
PU
General-purpose input/output 20
M_CCP0
M_MIITXD3
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 19
M_U1TX
M_CCP0
PU
or
PD(3)
I2C-0 data open-drain bidirectional port
M_U1TX
O
UART-1 transmit data
C_EQEP1S
I/O
Enhanced QEP-1 strobe
C_MCLKXA
O
McBSP-A transmit clock
Terminal Configuration and Functions
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F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
PD7_GPIO23
I/O/Z(2)
I/O/Z
DESCRIPTION
Capture/Compare/PWM-1
(General-purpose Timer)
M_MIITXD0
O
EMAC MII transmit data 0
M_EPI0S30
I/O
EPI-0 signal 30
W17
M_I2C1SCL
I/OD
M_U1RX
I
Enhanced QEP-1 index
C_MFSXA
O
McBSP-A transmit frame sync
PE0_GPIO24
I/O/Z
M_SSI1CLK
I/O
SSI-1 clock
M_CCP3
I/O
Capture/Compare/PWM-3
(General-purpose Timer)
M_EPI0S8
I/O
EPI-0 signal 8
USB-0 external power error state
(optionally used in the host mode)
M_SSI3TX
O
SSI-3 transmit data
M_CAN0RX
I
CAN-1 receive data
M_SSI1TX
O
SSI-1 transmit data
C_ECAP1
I/O
Enhanced Capture-1 input/output
I
I/O/Z
M_SSI1FSS
I/O
SSI-1 frame
M_CCP2
I/O
Capture/Compare/PWM-2
(General-purpose Timer)
M_CCP6
I/O
Capture/Compare/PWM-6
(General-purpose Timer)
I/O
EPI-0 signal 9
W9
I
SSI-3 receive data
M_CAN0TX
O
CAN-1 transmit data
M_SSI1RX
O
SSI-1 receive data
C_ECAP2
I/O
Enhanced Capture-2 input/output
I
PE2_GPIO26
I/O/Z
M_CCP4
I/O
M_SSI1RX
I
M_CCP2
M_EPI0S24
U6
M_SSI3CLK
M_U2RX
4 mA
Capture/Compare/PWM-4
(General-purpose Timer)
SSI-1 receive data
Capture/Compare/PWM-2
(General-purpose Timer)
I/O
EPI-0 signal 24
I/O
SSI-3 clock
UART-2 receive data
I/O
SSI-1 clock
C_ECAP3
I/O
Enhanced Capture-3 input/output
C_EQEP2I
I/O
Enhanced QEP-2 index
Terminal Configuration and Functions
PU
General-purpose input/output 26
M_SSI1CLK
22
4 mA
Enhanced QEP-2 input B
I/O
I
PU
General-purpose input/output 25
M_SSI3RX
C_EQEP2B
4 mA
Enhanced QEP-2 input A
PE1_GPIO25
M_EPI0S9
PU
General-purpose input/output 24
I
C_EQEP2A
6 mA
UART-1 receive data
I/O
W10
PU
I2C-1 clock open-drain bidirectional port
C_EQEP1I
M_USB0PFLT
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 23
I/O
M_CCP1
PU
or
PD(3)
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www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
PE3_GPIO27
I/O/Z
DESCRIPTION
I/O
Capture/Compare/PWM-1
(General-purpose Timer)
M_SSI1TX
O
SSI-1 transmit data
M_CCP7
I/O
Capture/Compare/PWM-7
(General-purpose Timer)
I/O
EPI-0 signal 25
M_SSI3FSS
I/O
SSI-3 frame
M_U2TX
O
UART-2 transmit data
M_SSI1FSS
I/O
SSI-1 frame
C_ECAP4
I/O
Enhanced Capture-4 input/output
C_EQEP2S
I/O
Enhanced QEP-2 strobe
V6
PE4_GPIO28
I/O/Z
I/O
Capture/Compare/PWM-3
(General-purpose Timer)
M_U2TX
O
UART-2 transmit data
M_CCP2
I/O
Capture/Compare/PWM-2
(General-purpose Timer)
I
EMAC MII receive data 0
T18
M_EPI0S34(5)
I/O
M_U0RX
I
EPI-0 signal 38
M_USB0EPEN
O
USB-0 external power enable
(optionally used in the host mode)
C_SCIRXDA
I
SCI-A receive data
PE5_GPIO29
I/O/Z
Capture/Compare/PWM-5
(General-purpose Timer)
I/O
EPI-0 signal 35
O
EMAC MII transmit error
M_U0TX
O
UART-0 transmit data
M_USB0PFLT
I
USB-0 external power error state
(optionally used in the host mode)
C_SCITXDA
O
SCI-A transmit data
PE6_GPIO30
I/O/Z
M_MIIMDIO
M_CAN0RX
U19
H2
I/O
EMAC management data input/output
CAN-0 receive data
C_EPWM9A
O
Enhanced PWM-9 output A
PE7_GPIO31
I/O/Z
M_CAN0TX
H1
C_EPWM9B
PU
4 mA
PU
4 mA
PU
4 mA
General-purpose input/output 30
I
M_MIIRXD3
4 mA
General-purpose input/output 29
I/O
M_MIITXER
PU
UART-0 receive data
I/O
M_EPI0S35(5)
4 mA
EPI-0 signal 34
M_EPI0S38(5)
M_CCP5
PU
General-purpose input/output 28
M_CCP3
M_MIIRXD0
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 27
M_CCP1
M_EPI0S25
PU
or
PD(3)
General-purpose input/output 31
I
EMAC MII receive data 3
O
CAN-0 transmit data
O
Enhanced PWM-9 output B
Terminal Configuration and Functions
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F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
DESCRIPTION
PF0_GPIO32
I/O/Z
M_CAN1RX
I
CAN-1 receive data
M_MIIRXCK
I
EMAC MII receive clock
M_I2C0SDA
I/OD
M_TRACED2
D19
C_I2CASDA
O
I/OD
I2C-0 data open-drain bidirectional port
Trace data 2
I
SCI-A receive data
O
ADC start-of-conversion A(6)
O
CAN-1 transmit data
M_MIIRXER
I
EMAC MII receive error
M_I2C0SCL
I/O
E17
M_TRACED3
I/OD
O
C_I2CASCL
I/OD
I2C-0 clock open-drain bidirectional port
Enhanced PWM sync out
O
ADC start-of-conversion B(6)
I
EPI-0 signal 32
M_SSI1CLK
I/O
SSI-1 clock
O
Trace clock
O
External output clock
I/O
Enhanced Capture-1 input/output
P16
C_ECAP1
C_SCIRXDA
I
SCI-A receive data
C_XCLKOUT
O
External output clock
Bmode_pin4
I
Boot mode pin 4
PF3_GPIO35
I/O/Z
General-purpose input/output 35
I
EMAC management data clock
M_MIIMDC
M_EPI0S33(5)
I/O
EPI-0 signal 33
M_SSI1FSS
I/O
SSI-1 frame
O
UART-0 transmit data
M_TRACED0
O
Trace data 0
C_SCITXDA
O
SCI-A transmit data
Bmode_pin3
I
Boot mode pin 3
PF4_GPIO36
I/O/Z
M_U0TX
P17
M_CCP0
M_MIIMDIO
M_EPI0S12
U14
I/O
Capture/Compare/PWM-0
(General-purpose Timer)
I/O
EMAC management data input/output
I/O
EPI-0 signal 12
I
SSI-1 receive data
M_U0RX
I
UART-0 receive data
C_SCIRXDA
I
SCI-A receive data
Terminal Configuration and Functions
4 mA
PU
4 mA
General-purpose input/output 36
M_SSI1RX
24
PU
EMAC PHY MII interrupt
I/O
M_XCLKOUT
4 mA
General-purpose input/output 34
M_EPI0S32(5)
M_TRACECLK
PU
I2C-A clock open-drain bidirectional port
O
M_MIIPHYINTR
4 mA
Trace data 3
C_ADCSOCBO
I/O/Z
PU
Capture/Compare/PWM-3
(General-purpose Timer)
C_EPWMSYNCO
PF2_GPIO34
4 mA
General-purpose input/output 33
M_CAN1TX
M_CCP3
PU
I2C-A data open-drain bidirectional port
C_ADCSOCAO
I/O/Z
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 32
C_SCIRXDA
PF1_GPIO33
PU
or
PD(3)
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www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
PF5_GPIO37
I/O/Z
M_CCP2
M_MIIRXD3
M_EPI0S15
U11
DESCRIPTION
I/O
Capture/Compare/PWM-2
(General-purpose Timer)
I
EMAC MII receive data 3
EPI-0 signal 15
O
SSI-1 transmit data
M_MIITXEN
O
EMAC MII transmit enable
C_ECAP2
I/O
Enhanced Capture-2 input/output
PF6_GPIO38
I/O/Z
W12
M_USB0VBUS
Analog
M_CCP1
M_MIIRXD2
I
EMAC MII receive data 2
PF7_GPIO39
I/O/Z
M_CAN1TX
O
PG0_GPIO40
I/O/Z
M_U2RX
I
M_I2C1SCL
I/OD
General-purpose input/output 39
CAN-1 transmit data
EPI-0 signal 13
M_MIIRXD2
I
EMAC MII receive data 2
M_U4RX
I
UART-4 receive data
M_MIITXCK
I
EMAC MII transmit clock
I/O/Z
O
M_I2C1SDA
M_EPI0S14
I/OD
U12
I/O
EPI-0 signal 14
I
EMAC MII receive data 1
UART-4 transmit data
M_MIITXER
O
EMAC MII transmit error
M_MIICOL
I/O/Z
W14
M_EPI0S39(5)
I
I/O
4 mA
PU
4 mA
PU
4 mA
I2C-1 data open-drain bidirectional port
O
Analog
PU
UART-2 transmit data
M_U4TX
M_USB0DM
4 mA
General-purpose input/output 41
M_MIIRXD1
PG2_GPIO42
PU
I2C-1 clock open-drain bidirectional port
I/O
M_U2TX
4 mA
UART-2 receive data
M_EPI0S13
PG1_GPIO41
PU
General-purpose input/output 40
USB-0 external power enable
(optionally used in the host mode)
V11
4 mA
EPI-0 signal 38
O
M_USB0EPEN
PU
USB0 VBUS power (5-V tolerant)
Capture/Compare/PWM-1
(General-purpose Timer)
I/O
D17
General-purpose input/output 38. If configured as
an output, place a capacitor with a value of 56 pF
or greater near the pin. If configured as an input,
place a series resistor with a value equal to 1 kΩ
or greater near the pin. See the F28M36x
Concerto™ MCUs Silicon Errata for details.
NOTE: For this pin, only the USB0VBUS function
is available on silicon revision 0 devices (GPIO
and the four other functions listed are not
available).
I/O
M_EPI0S38(5)
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 37
I/O
M_SSI1TX
PU
or
PD(3)
General-purpose input/output 42
USB0 data minus
EMAC MII collision detect
EPI-0 signal 39
Terminal Configuration and Functions
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F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
PG3_GPIO43
I/O/Z
M_MIICRS
M_MIIRXDV
I/O/Z(2)
N17
DESCRIPTION
EMAC MII carrier sense
I
EMAC MII receive data valid
Trace data 1
Bmode_pin1
I
Boot mode pin 1
PG4_GPIO44
I/O/Z
M_CAN1RX
D18
PG5_GPIO45
I/O/Z
M_USB0DP
M_CCP5
Analog
W15
M_MIITXEN
M_EPI0S40
I
(5)
PG6_GPIO46
I/O
EPI-0 signal 40
Analog
I
I/O
PG7_GPIO47
I/O/Z
M_MIITXER
General-purpose input/output 46. If configured as
an output, place a capacitor with a value of 56 pF
or greater near the pin. If configured as an input,
place a series resistor with a value equal to 1 kΩ
or greater near the pin. See the F28M36x
Concerto™ MCUs Silicon Errata for details.
NOTE: For this pin, only the USB0ID function is
available on silicon revision 0 devices (GPIO and
the three other functions listed are not available).
M_EPI0S31
I/O
EPI-0 signal 31
M_MIICRS
I
EMAC MII carrier sense
Bmode_pin2
I
Boot mode pin 2
PH0_GPIO48
I/O/Z
I/O
Capture/Compare/PWM-6
(General-purpose Timer)
O
EMAC PHY MII reset
EPI-0 signal 6
M_SSI3TX
O
SSI-3 transmit data
M_MIITXD3
O
EMAC MII transmit data 3
C_ECAP5
I/O
Enhanced Capture-5 input/output
I/O/Z
General-purpose input/output 49
V10
PH1_GPIO49
M_CCP7
M_EPI0S7
M_MIIRXD0
U8
I/O
Capture/Compare/PWM-7
(General-purpose Timer)
I/O
EPI-0 signal 7
I
EMAC MII receive data 0
M_SSI3RX
I
SSI-3 receive data
M_MIITXD2
O
EMAC MII transmit data 2
C_ECAP6
I/O
Enhanced Capture-6 input/output
26
Terminal Configuration and Functions
PU
4 mA
PU
6 mA
PU
4 mA
PU
4 mA
General-purpose input/output 48
I/O
M_EPI0S6
4 mA
General-purpose input/output 47
Capture/Compare/PWM-5
(General-purpose Timer)
M_MIIPHYRST
PU
EPI-0 signal 41
I/O
M_CCP6
4 mA
EMAC MII transmit clock
EMAC MII transmit error
W11
PU
USB0 ID (5-V tolerant)
O
M_CCP5
4 mA
USB0 data plus
EMAC MII transmit enable
M_MIITXCK
PU
General-purpose input/output 45
O
M_USB0ID
M_EPI0S41
CAN-1 receive data
Capture/Compare/PWM-5
(General-purpose Timer)
W13
(5)
General-purpose input/output 44
I/O
I/O/Z
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 43
I
O
M_TRACED1
PU
or
PD(3)
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
PH2_GPIO50
I/O/Z
M_EPI0S1
M_MIITXD3
DESCRIPTION
EPI-0 signal 1
O
EMAC MII transmit data 3
SSI-3 clock
M_MIITXD1
O
EMAC MII transmit data 1
C_EQEP1A
I
Enhanced QEP-1 input A
V7
PH3_GPIO51
I/O/Z
USB-0 external power enable
(optionally used in the host mode)
I/O
EPI-0 signal 0
O
EMAC MII transmit data 2
M_SSI3FSS
I/O
SSI-3 frame
M_MIITXD0
O
EMAC MII transmit data 0
C_EQEP1B
I
Enhanced QEP-1 input B
M_EPI0S0
M_MIITXD2
U7
PH4_GPIO52
I/O/Z
M_USB0PFLT
I
I/O
EPI-0 signal 10
O
EMAC MII transmit data 1
M_SSI1CLK
I/O
SSI-1 clock
M_U3TX
O
UART-3 transmit data
M_MIICOL
I
EMAC MII collision detect
C_EQEP1S
I/O
Enhanced QEP-1 strobe
I/O/Z
I/O
EPI-0 signal 11
M_MIITXD0
O
EMAC MII transmit data 0
I/O
SSI-1 frame
U9
M_U3RX
I
UART-3 receive data
M_MIIPHYRST
O
EMAC PHY MII reset
I/O
Enhanced QEP-1 index
C_EQEP1I
PH6_GPIO54
I/O/Z
I/O
M_MIIRXDV
I
EMAC MII receive data valid
M_MIITXEN
R17
M_SSI0TX
M_MIIPHYINTR
C_SPISIMOA
C_EQEP3A
PU
4 mA
PU
4 mA
PU
4 mA
General-purpose input/output 54
M_EPI0S26
M_SSI1RX
4 mA
General-purpose input/output 53
M_EPI0S11
M_SSI1FSS
PU
USB-0 external power error state
(optionally used in the host mode)
M_MIITXD1
PH5_GPIO53
4 mA
General-purpose input/output 52
M_EPI0S10
U10
PU
General-purpose input/output 51
O
M_USB0EPEN
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 50
I/O
I/O
M_SSI3CLK
PU
or
PD(3)
EPI-0 signal 26
I
SSI-1 receive data
O
EMAC MII transmit enable
O
SSI-0 transmit data
I
EMAC PHY MII interrupt
I/O
SPI-A slave in, master out
I
Enhanced QEP-1 input A
Terminal Configuration and Functions
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F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
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Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
DESCRIPTION
PH7_GPIO55
I/O/Z
M_MIIRXCK
I
M_EPI0S27
I/O
EPI-0 signal 27
M_SSI1TX
O
SSI-1 transmit data
I
EMAC MII transmit clock
I
SSI-0 receive data
M_MIIMDC
O
EMAC management data clock
C_SPISOMIA
I/O
SPI-A master in, slave out
I
Enhanced QEP-3 input B
M_MIITXCK
P18
M_SSI0RX
C_EQEP3B
PJ0_GPIO56
I/O/Z
M_MIIRXER
I
M_EPI0S16
I/O
M_I2C1SCL
M_SSI0CLK
W16
I/OD
I2C-1 clock open-drain bidirectional port
EMAC management data input/output
I/O
SPI-A clock
I/O
Enhanced QEP-3 strobe
M_USB0PFLT
I
M_I2C1SDA
M_MIIRXDV
I/OD
V13
I
EMAC MII receive data valid
C_SPISTEA
I/O
SPI-A slave transmit enable
SSI-0 frame
I/O
Enhanced QEP-3 index
EMAC MII receive data 3
PJ2_GPIO58
I/O/Z
M_EPI0S18
I/O
EPI-0 signal 18
M_CCP0
I/O
Capture/Compare/PWM-0
(General-purpose Timer)
I
General-purpose input/output 58
EMAC MII receive clock
I/O
SSI-0 clock
M_U0TX
O
UART-0 transmit data
M_MIIRXD2
I
EMAC MII receive data 2
C_MCLKRA
I
McBSP-A receive clock
C_EPWM7A
O
Enhanced PWM-7 output A
28
Terminal Configuration and Functions
4 mA
I2C-1 data open-drain bidirectional port
I
V12
PU
USB-0 external power error state
(optionally used in the host mode)
I/O
M_SSI0CLK
4 mA
EPI-0 signal 17
M_MIIRXD3
M_MIIRXCK
PU
General-purpose input/output 57
M_SSI0FSS
C_EQEP3I
4 mA
EPI-0 signal 16
I/O
I/O
PU
EMAC MII receive error
C_SPICLKA
M_EPI0S17
4 mA
General-purpose input/output 56
M_MIIMDIO
I/O/Z
PU
EMAC MII receive clock
SSI-0 clock
PJ1_GPIO57
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 55
I/O
C_EQEP3S
PU
or
PD(3)
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
DESCRIPTION
PJ3_GPIO59
I/O/Z
M_EPI0S19
I/O
EPI-0 signal 19
M_CCP6
I/O
Capture/Compare/PWM-6
(General-purpose Timer)
O
EMAC management data clock
I/O
SSI-0 frame
M_MIIMDC
M_SSI0FSS
U15
I
UART-0 receive data
M_MIIRXD1
I
EMAC MII receive data 1
C_MFSRA
I
McBSP-A receive frame sync
C_EPWM7B
O
Enhanced PWM-7 output B
PJ4_GPIO60
I/O/Z
M_EPI0S28
I/O
EPI-0 signal 28
M_CCP4
I/O
Capture/Compare/PWM-4
(General-purpose Timer)
I
EMAC MII collision detect
V15
M_SSI1CLK
I/O
I
EMAC MII receive data 0
O
Enhanced PWM-8 output A
PJ5_GPIO61
I/O/Z
M_EPI0S29
I/O
EPI-0 signal 29
M_CCP2
I/O
Capture/Compare/PWM-2
(General-purpose Timer)
I
EMAC MII carrier sense
I/O
M_MIIRXDV
I
EMAC MII receive data valid
C_EPWM8B
O
Enhanced PWM-8 output B
PJ6_GPIO62
I/O/Z
M_EPI0S30
I/O
EPI-0 signal 30
M_CCP1
I/O
Capture/Compare/PWM-1
(General-purpose Timer)
V16
M_U2RX
I
UART-2 receive data
M_MIIRXER
I
EMAC MII receive error
C_EPWM9A
O
Enhanced PWM-9 output A
PJ7_GPIO63
I/O/Z
Capture/Compare/PWM-0
(General-purpose Timer)
O
EMAC PHY MII reset
O
UART-2 transmit data
M_MIIRXCK
I
EMAC MII receive clock
M_XCLKIN
I
External oscillator input for USB PLL and CAN
(always available, see Figure 6-16)
C_EPWM9B
O
Enhanced PWM-9 output B
H17
6 mA
PU
6 mA
PU
4 mA
General-purpose input/output 63
I/O
M_U2TX
PU
General-purpose input/output 62
EMAC PHY MII interrupt
M_MIIPHYRST
6 mA
SSI-1 frame
I
M_CCP0
PU
General-purpose input/output 61
M_SSI1FSS
M_MIIPHYINTR
4 mA
SSI-1 clock
C_EPWM8A
V14
PU
General-purpose input/output 60
M_MIIRXD0
M_MIICRS
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 59
M_U0RX
M_MIICOL
PU
or
PD(3)
Terminal Configuration and Functions
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F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
PC0_GPIO64
I/O/Z
M_EPI0S32(5)
I/O
M_MIIRXD2
V4
C_EQEP1A
C_EQEP2I
M_EPI0S33
(5)
M_MIICOL
EMAC MII receive data 2
Enhanced QEP-1 input A
I/O
W4
C_EQEP1B
C_EQEP2S
EMAC MII collision detect
I
Enhanced QEP-1 input B
I/O
Enhanced QEP-2 strobe
I/O
EPI-0 signal 37
C_EQEP2A
PC3_GPIO67
M_EPI0S36
(5)
M_MIITXCK
O
EMAC MII transmit enable
Enhanced QEP-1 strobe
I
Enhanced QEP-2 input A
I/O
V5
C_EQEP1I
C_EQEP2B
EMAC MII transmit clock
Enhanced QEP-1 index
Capture/Compare/PWM-5
(General-purpose Timer)
M_MIITXD3
O
EMAC MII transmit data 3
I
Capture/Compare/PWM-2
(General-purpose Timer)
I
Capture/Compare/PWM-4
(General-purpose Timer)
M_CCP4
M_EPI0S2
I/O
M_CCP1
I
PC5_GPIO69
I/O/Z
M_CCP1
M_CCP3
W7
M_USB0EPEN
M_EPI0S3
PC6_GPIO70
M_CCP3
M_U1RX
M_CCP0
V8
M_USB0PFLT
M_EPI0S4
30
Terminal Configuration and Functions
4 mA
PU
4 mA
PU
4 mA
Capture/Compare/PWM-1
(General-purpose Timer)
General-purpose input/output 69
Capture/Compare/PWM-1
(General-purpose Timer)
I
Capture/Compare/PWM-3
(General-purpose Timer)
O
USB-0 external power enable
(optionally used in the host mode)
I/O
EPI-0 signal 3
General-purpose input/output 70
I
Capture/Compare/PWM-3
(General-purpose Timer)
I
UART-1 receive data
I
Capture/Compare/PWM-0
(General-purpose Timer)
I
USB-0 external power error state
(optionally used in the host mode)
I/O
PU
EPI-0 signal 2
I
I/O/Z
4 mA
General-purpose input/output 68
I
W8
PU
Enhanced QEP-2 input B
M_CCP5
M_CCP2
4 mA
EPI-0 signal 36
I/O
I/O/Z
PU
General-purpose input/output 67
I
I
PC4_GPIO68
4 mA
General-purpose input/output 66
I/O
I/O/Z
PU
EPI-0 signal 33
I
M_EPI0S37(5)
U5
4 mA
General-purpose input/output 65
I/O/Z
C_EQEP1S
PU
Enhanced QEP-2 index
PC2_GPIO66
M_MIITXEN
OUTPUT
BUFFER
STRENGTH
EPI-0 signal 32
I
I/O/Z
PU
or
PD(3)
General-purpose input/output 64
I
I/O
PC1_GPIO65
DESCRIPTION
EPI-0 signal 4
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
PC7_GPIO71
I/O/Z
DESCRIPTION
Capture/Compare/PWM-4
(General-purpose Timer)
I
Capture/Compare/PWM-0
(General-purpose Timer)
M_U1TX
O
UART-1 transmit data
M_USB0PFLT
I
USB-0 external power error state
(optionally used in the host mode)
M_CCP0
V9
M_EPI0S5
I/O
PK0_GPIO72
M_SSI0TX
I/O/Z
SSI-0 transmit data
I/O
SPI-A slave in, master out
PK1_GPIO73
I/O/Z
I/O
SSI-0 receive data
I/O
SPI-A master in, slave out
PK2_GPIO74
I/O/Z
I/O
SSI-0 clock
I/O
SPI-A clock
PK3_GPIO75
I/O/Z
L18
C_SPISTEA
PK4_GPIO76
M_MIITXEN
M_SSI0TX
PK5_GPIO77
M_MIITXCK
W3
M_SSI0RX
SPI-A slave transmit enable
EMAC MII transmit enable
O
SSI-0 transmit data
I
I/O/Z
EMAC MII transmit clock
I/O
SSI-0 clock
PK7_GPIO79
I/O/Z
M_SSI0FSS
I/O
PL0_GPIO80
M_MIIRXD3
I/O/Z
U1
M_SSI1TX
PL1_GPIO81
M_MIIRXD2
M_SSI1RX
M_MIIRXD1
I
M_SSI1CLK
I/O
PL3_GPIO83
I/O/Z
M_MIIRXD0
T1
M_SSI1FSS
I
I/O
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
General-purpose input/output 80
SSI-1 transmit data
I/O/Z
U3
PU
SSI-0 frame
EMAC MII receive data 3
I/O
PL2_GPIO82
EMAC MII carrier sense
O
I
4 mA
General-purpose input/output 79
I
I/O/Z
U2
PU
General-purpose input/output 78
M_SSI0CLK
I
4 mA
SSI-0 receive data
EMAC MII transmit error
V3
PU
General-purpose input/output 77
O
M_MIICRS
V2
4 mA
General-purpose input/output 76
O
I/O
PK6_GPIO78
M_MIITXER
SSI-0 frame
I/O
I/O/Z
PU
General-purpose input/output 75
I/O
I/O/Z
U4
4 mA
General-purpose input/output 74
C_SPICLKA
M_SSI0FSS
M16
PU
General-purpose input/output 73
C_SPISOMIA
M_SSI0CLK
4 mA
General-purpose input/output 72
C_SPISIMOA
N16
PU
EPI-0 signal 5
O
M_SSI0RX
K17
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 71
I
M_CCP4
PU
or
PD(3)
General-purpose input/output 81
EMAC MII receive data 2
SSI-1 receive data
General-purpose input/output 82
EMAC MII receive data 1
SSI-1 clock
General-purpose input/output 83
EMAC MII receive data 0
SSI-1 frame
Terminal Configuration and Functions
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F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
PL4_GPIO84
M_MIICOL
I/O/Z
U18
M_SSI3TX
PL5_GPIO85
M_MIIPHYRST
T2
PL6_GPIO86
M_SSI3CLK
PL7_GPIO87
M_MIIMDC
V18
M_SSI3FSS
PM0_GPIO88
M_MIIMDIO
M_SSI2TX
PM1_GPIO89
M_MIITXD3
R2
PM2_GPIO90
R3
PM3_GPIO91
P1
M_SSI2FSS
PM4_GPIO92
M_MIITXD0
PM5_GPIO93
P3
PM6_GPIO94
P4
C_MCLKXA
PM7_GPIO95
M_MIIRXCK
N1
PN0_GPIO96
L17
C_MCLKRA
J17
C_MFSRA
PN2_GPIO98
M_U1RX
PN3_GPIO99
M_U1TX
32
I/O/Z
General-purpose input/output 87
O
EMAC management data clock
I/O
SSI-3 frame
EMAC management data input/output
O
SSI-2 transmit data
J18
O
EMAC MII transmit data 3
SSI-2 receive data
O
EMAC MII transmit data 2
SSI-2 clock
G18
O
EMAC MII transmit data 1
SSI-2 frame
EMAC MII transmit data 0
O
McBSP-A transmit data
Terminal Configuration and Functions
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
General-purpose input/output 93
I
EMAC MII receive data valid
I
McBSP-A receive data
General-purpose input/output 94
I
EMAC MII receive error
O
McBSP-A transmit clock
General-purpose input/output 95
I
EMAC MII receive clock
O
McBSP-A transmit frame sync
I/O/Z
General-purpose input/output 96
I/OD
I2C-0 clock open-drain bidirectional port
McBSP-A receive clock
I/O/Z
General-purpose input/output 97
I/OD
I2C-0 data open-drain bidirectional port
O
4 mA
General-purpose input/output 92
O
I/O/Z
PU
General-purpose input/output 91
I/O
I
4 mA
General-purpose input/output 90
I/O
I/O/Z
PU
General-purpose input/output 89
I/O
I
4 mA
General-purpose input/output 88
I/O
I
PN1_GPIO97
M_I2C0SDA
SSI-3 clock
I/O/Z
C_MFSXA
M_I2C0SCL
EMAC PHY MII interrupt
I/O
I/O/Z
PU
General-purpose input/output 86
O
I/O/Z
C_MDRA
M_MIIRXER
SSI-3 receive data
I/O/Z
P2
C_MDXA
M_MIIRXDV
EMAC PHY MII reset
I/O
I/O/Z
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 85
O
I/O/Z
M_SSI2CLK
M_MIITXD1
SSI-3 transmit data
I/O/Z
M_SSI2RX
M_MIITXD2
O
I/O/Z
R1
PU
or
PD(3)
General-purpose input/output 84
EMAC MII collision detect
I/O/Z
T3
DESCRIPTION
I
I/O/Z
M_SSI3RX
M_MIIPHYINTR
I/O/Z(2)
McBSP-A receive frame sync
General-purpose input/output 98
UART-1 receive data
General-purpose input/output 99
UART-1 transmit data
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
PN4_GPIO100
M_U3TX
PN5_GPIO101
M_U3RX
ZWT
BALL NO.
I/O/Z(2)
F18
H16
PN6_GPIO102
O
I/O/Z
I
I/O/Z
M_U4RX
M_EPI0S42
I/O/Z
I
(5)
R18
DESCRIPTION
General-purpose input/output 100
UART-3 transmit data
General-purpose input/output 101
UART-3 receive data
M_USB0EPEN
O
USB-0 external power enable
(optionally used in the host mode)
PN7_GPIO103
I/O/Z
General-purpose input/output 103
T17
O
UART-4 transmit data
I/O
EPI-0 signal 43
I
USB-0 external power error state
(optionally used in the host mode)
I/O/Z
General-purpose input/output 104
I/OD
I2C-1 clock open-drain bidirectional port
C_I2CSDAA
I/OD
I2C-A data open-drain bidirectional port
PP1_GPIO105
I/O/Z
General-purpose input/output 105
I/OD
I2C-1 data open-drain bidirectional port
C_I2CSCLA
I/OD
I2C-A clock open-drain bidirectional port
PP2_GPIO106
I/O/Z
General-purpose input/output 106
I/OD
I2C-0 clock open-drain bidirectional port
M_USB0PFLT
PP0_GPIO104
M_I2C1SCL
M_I2C1SDA
M_I2C0SCL
G17
G16
F17
C_EQEP1A
I
PP3_GPIO107
M_I2C0SDA
E18
C_EQEP1B
PP4_GPIO108
M_I2C1SCL
C19
C_EQEP1S
PP5_GPIO109
M_I2C1SDA
C18
C_EQEP1I
C17
PP7_GPIO111
B18
C_EQEP3I
C16
Enhanced QEP-2 input A
Enhanced QEP-3 strobe
C5
Enhanced QEP-2 input B
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
Enhanced QEP-3 index
General-purpose input/output 112
Enhanced QEP-2 index
Enhanced QEP-1 input A
General-purpose input/output 113
Enhanced QEP-2 strobe
I
Enhanced QEP-3 input B
I
PU
General-purpose input/output 111
I/O
I/O/Z
4 mA
General-purpose input/output 110
I
I/O
PU
Enhanced QEP-1 index
I/O
I/O/Z
C6
C_EQEP3B
M_U0RX
I2C-1 data open-drain bidirectional port
I
PQ1_GPIO113
PQ2_GPIO114
General-purpose input/output 109
I/OD
I
4 mA
Enhanced QEP-1 strobe
I/O/Z
I/O/Z
C_EQEP3A
C_EQEP2S
I2C-1 clock open-drain bidirectional port
I/O
PQ0_GPIO112
C_EQEP2I
General-purpose input/output 108
I/OD
I/O/Z
PU
Enhanced QEP-1 input B
I/O/Z
I/O/Z
C_EQEP3S
C_EQEP2B
I2C-0 data open-drain bidirectional port
I/O
PP6_GPIO110
C_EQEP2A
General-purpose input/output 107
I/OD
I/O
4 mA
Enhanced QEP-1 input A
I/O/Z
I
PU
UART-4 receive data
EPI-0 signal 42
M_EPI0S43(5)
OUTPUT
BUFFER
STRENGTH
General-purpose input/output 102
I/O
M_U4TX
PU
or
PD(3)
General-purpose input/output 114
UART-0 receive data
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
PQ3_GPIO115
M_U0TX
PQ4_GPIO116
M_SSI1TX
PQ5_GPIO117
M_SSI1RX
PQ6_GPIO118
C_SCITXDA
PQ7_GPIO119
C_SCIRXDA
PR0_GPIO120
M_SSI3TX
PR1_GPIO121
M_SSI3RX
PR2_GPIO122
M_SSI3CLK
PR3_GPIO123
M_SSI3FSS
PR4_GPIO124
C_EPWM7A
PR5_GPIO125
C_EPWM7B
PR6_GPIO126
C_EPWM8A
PR7_GPIO127
C_EPWM8B
PS0_GPIO128
C_EPWM9A
PS1_GPIO129
C_EPWM9B
PS2_GPIO130
C_EPWM10A
PS3_GPIO131
C_EPWM10B
PS4_GPIO132
C_EPWM11A
PS5_GPIO133
C_EPWM11B
PS6_GPIO134
C_EPWM12A
PS7_GPIO135
C_EPWM12B
34
ZWT
BALL NO.
C4
C3
C2
D3
D2
N18
M18
K18
M17
J3
J2
J1
K3
K2
L3
L2
M3
M2
M1
N3
N2
Terminal Configuration and Functions
I/O/Z(2)
I/O/Z
O
I/O/Z
O
I/O/Z
I
I/O/Z
O
I/O/Z
I
I/O/Z
O
I/O/Z
I
I/O/Z
I/O
I/O/Z
I/O
I/O/Z
O
I/O/Z
O
I/O/Z
O
I/O/Z
O
I/O/Z
O
I/O/Z
O
I/O/Z
O
I/O/Z
O
I/O/Z
O
I/O/Z
O
I/O/Z
O
I/O/Z
O
DESCRIPTION
General-purpose input/output 115
UART-0 transmit data
General-purpose input/output 116
SSI-1 transmit data
General-purpose input/output 117
SSI-1 receive data
General-purpose input/output 118
SCI-A transmit data
General-purpose input/output 119
SCI-A receive data
General-purpose input/output 120
SSI-3 transmit data
General-purpose input/output 121
SSI-3 receive data
General-purpose input/output 122
SSI-3 clock
General-purpose input/output 123
SSI-3 frame
General-purpose input/output 124
Enhanced PWM-7 output A
General-purpose input/output 125
Enhanced PWM-7 output B
General-purpose input/output 126
Enhanced PWM-8 output A
General-purpose input/output 127
Enhanced PWM-8 output B
General-purpose input/output 128
Enhanced PWM-9 output A
General-purpose input/output 129
Enhanced PWM-9 output B
General-purpose input/output 130
Enhanced PWM-10 output A
General-purpose input/output 131
Enhanced PWM-10 output B
General-purpose input/output 132
Enhanced PWM-11 output A
General-purpose input/output 133
Enhanced PWM-11 output B
General-purpose input/output 134
Enhanced PWM-12 output A
General-purpose input/output 135
Enhanced PWM-12 output B
PU
or
PD(3)
OUTPUT
BUFFER
STRENGTH
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
PU
4 mA
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
DESCRIPTION
PU
or
PD(3)
OUTPUT
BUFFER
STRENGTH
I/OD
Digital Subsystem Reset (in) and
Watchdog/Power-on Reset (out). In most
applications, TI recommends that the XRS pin be
tied with the ARS pin. The Digital Subsystem has
a built-in POR circuit, and during a power-on
condition, this pin is driven low by the Digital
Subsystem. This pin is also driven low by the
Digital Subsystem when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low
for the watchdog reset duration of 512 OSCCLK
cycles. If needed, an external circuitry may also
drive this pin to assert device reset. In this case,
this pin should be driven by an open-drain device.
A noise filtering circuit can be connected to this
pin. A resistor with a value from 2.2 kΩ to 10 kΩ
should be placed between XRS and VDDIO. If a
capacitor is placed between XRS and VSS for
noise filtering, it should be 100 nF or smaller.
These values will allow the watchdog to properly
drive the XRS pin to VOL within 512 OSCCLK
cycles when the watchdog reset is asserted.
Regardless of the source, a device reset causes
the Digital Subsystem to terminate execution. The
Cortex-M3 program counter points to the address
contained at the location 0x00000004. The C28
program counter points to the address contained
at the location 0x3FFFC0. When reset is
deactivated, execution begins at the location
designated by the program counter. The output
buffer of this pin is an open-drain with an internal
pullup.
PU
4 mA
I/OD
Analog Subsystem Reset (in) and Power-on Reset
(out). TI recommends that the ARS pin be tied
with the XRS pin. The Analog Subsystem has a
built-in POR circuit, and during a power-on
condition, this pin is driven low by the Analog
Subsystem. If needed, external circuitry may also
drive this pin to assert a device reset. In this case,
TI recommends that this pin be driven by an opendrain device. Regardless of the source, the Analog
Subsystem reset causes the digital logic
associated with the Analog Subsystem, to enter
reset state. The output buffer of this pin is an
open-drain with an internal pullup.
PU
4 mA
Resets
XRS
ARS
C1
A3
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
DESCRIPTION
PU
or
PD(3)
OUTPUT
BUFFER
STRENGTH
Clocks
X1
J19
X2
G19
I
External oscillator input or on-chip crystaloscillator input. To use the on-chip oscillator, a
quartz crystal or a ceramic resonator must be
connected across X1 and X2. See Figure 6-7.
O
On-chip crystal-oscillator output. A quartz crystal
or a ceramic resonator must be connected across
X1 and X2. If X2 is not used, it must be left
unconnected. See Figure 6-7.
H18
Clock Oscillator Ground Pin. Use this pin to
connect the GND of external crystal load
capacitors or the ground pin of 3-terminal ceramic
resonators with built-in capacitors. Do not connect
to board ground. See Figure 6-7.
VSSOSC
H19
Clock Oscillator Ground Pin. Use this pin to
connect the GND of external crystal load
capacitors or the ground pin of 3-terminal ceramic
resonators with built-in capacitors. Do not connect
to board ground. See Figure 6-7.
XCLKIN
see
PJ7_GPIO63
I
XCLKOUT
see
PF2_GPIO34
O/Z
External oscillator output. This pin outputs a clock
divided-down from the internal PLL System Clock.
The divide ratio is defined in the XPLLCLKCFG
register.
PU
VSSOSC
External oscillator input. This pin feeds a clock
from an external 3.3-V oscillator to internal USB
PLL module and to the CAN peripherals.
Boot Pins
Bmode_pin1
see
PG3_GPIO43
I
One of four boot mode pins. Bmode_pin1 selects
a specific configuration source from which the
Concerto device boots on start-up.
Bmode_pin2
see
PG7_GPIO47
I
One of four boot mode pins. Bmode_pin2 selects
a specific configuration source from which the
Concerto device boots on start-up.
PU
Bmode_pin3
see
PF3_GPIO35
I
One of four boot mode pins. Bmode_pin3 selects
a specific configuration source from which the
Concerto device boots on start-up.
PU
Bmode_pin4
see
PF2_GPIO34
I
One of four boot mode pins. Bmode_pin4 selects
a specific configuration source from which the
Concerto device boots on start-up.
PU
JTAG
TRST
N19
I
JTAG test reset with internal pulldown. TRST,
when driven high, gives the scan system control of
the operations of the device. If this signal is not
connected or driven low, the device operates in its
functional mode, and the test reset signals are
ignored. NOTE: TRST is an active-low test pin
and must be maintained low during normal device
operation. An external pull-down resistor is
required on this pin. The value of this resistor
should be based on drive strength of the debugger
pods applicable to the design. A 2.2-kΩ resistor
generally offers adequate protection. Because the
value of the resistor is application-specific, TI
recommends that each target board be validated
for proper operation of the debugger and the
application.
TCK
L19
I
JTAG test clock
TMS
M19
I
JTAG test-mode select (TMS) with internal pullup.
This serial control input is clocked into the TAP
controller on the rising edge of TCK.
36
Terminal Configuration and Functions
PD
PU
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
PU
or
PD(3)
OUTPUT
BUFFER
STRENGTH
ZWT
BALL NO.
I/O/Z(2)
TDI
K19
I
JTAG test data input (TDI) with internal pullup.
TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO
T19
O
JTAG scan out, test data output (TDO). The
contents of the selected register (instruction or
data) are shifted out of TDO on the falling edge of
TCK.
I/O/Z
Emulator pin 0. When TRST is driven high, this
pin is used as an interrupt to or from the JTAG
debug probe system and is defined as input/output
through the JTAG scan. This pin is also used to
put the device into boundary-scan mode. With the
EMU0 pin at a logic-high state and the EMU1 pin
at a logic-low state, a rising edge on the TRST pin
would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is required on
this pin. The value of this resistor should be based
on the drive strength of the debugger pods
applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Because the value
of the resistor is application-specific, TI
recommends that each target board be validated
for proper operation of the debugger and the
application.
NOTE: If EMU0 is 0 and EMU1 is 1 when coming
out of reset, the device enters Wait-in-Reset
mode. WIR suspends bootloader execution,
allowing the JTAG debug probe to connect to the
device and to modify FLASH contents.
PU
4 mA
I/O/Z
Emulator pin 1. When TRST is driven high, this
pin is used as an interrupt to or from the JTAG
debug probe system and is defined as input/output
through the JTAG scan. This pin is also used to
put the device into boundary-scan mode. With the
EMU0 pin at a logic-high state and the EMU1 pin
at a logic-low state, a rising edge on the TRST pin
would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is required on
this pin. The value of this resistor should be based
on the drive strength of the debugger pods
applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Because the value
of the resistor is application-specific, TI
recommends that each target board be validated
for proper operation of the debugger and the
application.
NOTE: If EMU0 is 0 and EMU1 is 1 when coming
out of reset, the device enters Wait-in-Reset
mode. WIR suspends bootloader execution,
allowing the JTAG debug probe to connect to the
device and to modify FLASH contents.
PU
4 mA
NAME
EMU0
EMU1
P19
R19
DESCRIPTION
PU
4 mA
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
I/O/Z(2)
ZWT
BALL NO.
DESCRIPTION
PU
or
PD(3)
OUTPUT
BUFFER
STRENGTH
ITM Trace (Arm Instrumentation Trace Macrocell)
TRACED0
see
PF3_GPIO35
O
ITM Trace data 0
4 mA
TRACED1
see
PG3_GPIO43
O
ITM Trace data 1
4 mA
TRACED2
see
PF0_GPIO32
O
ITM Trace data 2
4 mA
TRACED3
see
PF1_GPIO33
O
ITM Trace data 3
4 mA
TRACECLK
see
PF2_GPIO34
O
ITM Trace clock
4 mA
Test Pins
FLT1
K1
I/O
FLASH Test Pin 1. Reserved for TI. Must be left
unconnected.
FLT2
L1
I/O
FLASH Test Pin 2. Reserved for TI. Must be left
unconnected.
Internal Voltage Regulator Control
VREG18EN
A15
Internal 1.8-V VREG Enable/Disable for VDD18.
Pull low to enable the internal 1.8-V voltage
regulator (VREG18), pull high to disable VREG18.
PD
VREG12EN
E19
Internal 1.2-V VREG Enable/Disable for VDD12.
Pull low to enable the internal 1.2-V voltage
regulator (VREG12), pull high to disable VREG12.
PD
38
Terminal Configuration and Functions
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
DESCRIPTION
PU
or
PD(3)
OUTPUT
BUFFER
STRENGTH
Digital Logic Power Pins for I/Os, Flash, USB, and Internal Oscillators
VDDIO
D4
VDDIO
D5
VDDIO
D15
VDDIO
D16
VDDIO
G7
VDDIO
G13
VDDIO
G8
VDDIO
G9
VDDIO
G10
VDDIO
G11
VDDIO
G12
VDDIO
H7
VDDIO
H13
VDDIO
J7
VDDIO
J13
VDDIO
N8
VDDIO
N9
VDDIO
N10
VDDIO
N11
VDDIO
K7
VDDIO
L7
VDDIO
K13
VDDIO
L13
VDDIO
T4
VDDIO
T5
VDDIO
T7
VDDIO
T8
VDDIO
T15
VDDIO
T16
VDDIO
T13
VDDIO
U13
VDD18
C7
VDD18
D7
VDD18
D12
VDD18
D13
3.3-V Digital I/O and FLASH Power Pin. Tie with a
0.1-µF capacitor (typical) close to the pin. When
the 1.2-V VREG is enabled (by pulling the
VREG12EN pin low), these pins also supply
power to the Digital Subsystem. When the 1.8-V
VREG is enabled (by pulling the VREG18EN pin
low), these pins also supply power to the Analog
Subsystem.
Digital Logic Power Pins (Analog Subsystem)
1.8-V Digital Logic Power Pins (associated with
the Analog Subsystem) - no supply needed when
using internal VREG18. Tie with 1.2-µF (minimum)
ceramic capacitor (10% tolerance) to ground when
using internal VREG. Higher value capacitors may
be used but could impact supply-rail ramp-up time.
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
I/O/Z(2)
DESCRIPTION
PU
or
PD(3)
OUTPUT
BUFFER
STRENGTH
Digital Logic Power Pins (Master and Control Subsystems)
VDD12
M7
VDD12
M13
VDD12
N7
VDD12
N12
VDD12
N13
VDD12
T10
VDD12
T11
VDD12
T12
VSS
A1
VSS
A2
VSS
A18
VSS
A19
1.2-V Digital Logic Power Pins - no supply needed
when using internal VREG12. Tie with 250-nF
(minimum) to 750-nF (maximum) ceramic
capacitor (10% tolerance) to ground when using
internal VREG. Higher value capacitors may be
used but could impact supply-rail ramp-up time.
Digital Logic Ground (Analog, Master, and Control Subsystems)
VSS
B1
VSS
B19
VSS
D6
VSS
D14
VSS
E4
VSS
E16
VSS
H8
VSS
H9
VSS
H10
VSS
H11
VSS
H12
VSS
J4
VSS
J8
VSS
J9
VSS
J10
VSS
J11
VSS
J12
VSS
J16
VSS
K4
VSS
K8
VSS
K9
VSS
K10
VSS
K11
VSS
K12
VSS
K16
40
Terminal Configuration and Functions
Digital Ground
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
NAME
ZWT
BALL NO.
VSS
L4
VSS
L8
VSS
L9
VSS
L10
VSS
L11
VSS
L12
VSS
L16
VSS
M8
VSS
M9
VSS
M10
VSS
M11
VSS
M12
VSS
R4
VSS
R16
VSS
T6
VSS
T9
VSS
T14
VSS
V1
VSS
V19
VSS
W1
VSS
W2
VSS
W18
VSS
W19
I/O/Z(2)
DESCRIPTION
PU
or
PD(3)
OUTPUT
BUFFER
STRENGTH
Digital Ground
(1) Throughout this table, Master Subsystem signals are denoted by the color blue; Control Subsystem signals are denoted by the color
green; and Analog Subsystem signals are denoted by the color orange.
(2) I = Input, O = Output, Z = High Impedance, OD = Open Drain
(3) PU = Pullup, PD = Pulldown
– GPIO_MUX1 pullups can be enabled or disabled by Cortex-M3 software (disabled on reset).
– GPIO_MUX2 pullups can be enabled or disabled by C28x software (disabled on reset).
– AIO_MUX1 and AIO_MUX2 terminals do not have pullups or pulldowns.
– All other pullups are always enabled (XRS, ARS, TMS, TDI, EMU0, EMU1).
– All pulldowns are always enabled (VREG18EN, VREG12EN, TRST).
(4) All I/Os, except for GPIO199, are glitch-free during power up and power down. See Section 6.11.
(5) This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.
(6) Output from the Concerto ePWM is meant for the external ADC (if present).
Terminal Configuration and Functions
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5 Specifications
Absolute Maximum Ratings (1) (2)
5.1
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VDDIO (I/O and Flash) with respect to VSS
–0.3
4.6
VDD18 with respect to VSS
–0.3
2.5
VDD12 with respect to VSS
–0.3
1.5
Analog voltage
VDDA with respect to VSSA
–0.3
4.6
V
Input voltage
VIN (3.3 V)
–0.3
4.6
V
Output voltage
VO
–0.3
Supply ramp rate
VDDIO, VDD18, VDD12, VDDA with respect to VSS
Input clamp current
IIK (VIN < 0 or VIN > VDDIO) (3)
–20
Output clamp current
IOK (VO < 0 or VO > VDDIO)
Free-Air temperature
TA
Junction temperature (4)
Supply voltage
Storage temperature
(1)
(2)
(3)
(4)
(4)
UNIT
V
4.6
V
105
V/s
20
mA
–20
20
mA
–40
125
°C
TJ
–40
150
°C
Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
Continuous clamp current per pin is ±2 mA.
Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see Semiconductor and IC Package Thermal Metrics.
5.2
ESD Ratings – Commercial
VALUE
UNIT
F28M36P63C2, F28M36P53C2, F28M36H53B2, F28M36H33B2 in 289-ball ZWT package
V(ESD)
(1)
(2)
42
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002 (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Specifications
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5.3
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Device supply voltage, I/O, VDDIO (1)
2.97
3.3
3.63
V
Device supply voltage, Analog Subsystem, VDD18
(when internal VREG is disabled and 1.8 V is
supplied externally)
1.71
1.8
1.995
Device supply voltage, Master and Control
Subsystems, VDD12
(when internal VREG is disabled and 1.2 V is
supplied externally)
1.14
V
1.32
V
Supply ground, VSS
0
Analog supply voltage, VDDA (1)
2.97
Analog ground, VSSA
3.3
V
3.63
V
0
Device clock frequency (system clock)
Master Subsystem
Junction temperature, TJ
V
P63C2, P53C2
2
125
H53B2, H33B2
2
100
2
150
T version
–40
105
S version (2)
–40
125
Device clock frequency (system clock)
Control Subsystem
(1)
(2)
1.2
MHz
MHz
°C
VDDIO and VDDA should be maintained within approximately 0.3 V of each other.
Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
5.4
www.ti.com
Power Consumption Summary
Table 5-1. Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK
VREG ENABLED
TEST CONDITIONS (1)
MODE
IDDIO (2)
VREG DISABLED
IDDA
IDD18
IDDIO (2)
IDD12
IDDA
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
–
325 mA
–
40 mA
–
25 mA
–
225 mA
–
75 mA
–
40 mA
The following Cortex-M3 peripherals
are exercised:
•
I2C1
•
SSI1, SSI2
•
UART0, UART1, UART2
•
CAN0
•
USB
•
µDMA
•
Timer0, Timer1
•
µCRC
•
WDOG0, WDOG1
•
Flash
•
Internal Oscillator 1,
Internal Oscillator 2
The following C28x peripherals are
exercised:
Operational
(RAM)
•
McBSP
•
eQEP1, eQEP2
•
eCAP1, eCAP2,
eCAP3, eCAP4
•
SCI-A
•
SPI-A
•
I2C
•
DMA
•
VCU
•
FPU
•
Flash
The following Analog peripherals
are exercised:
(1)
(2)
44
•
ADC1, ADC2
•
Comparator
Comparator
Comparator
Comparator
Comparator
Comparator
1,
2,
3,
4,
5,
6
The following is done in a loop:
• Code is running out of RAM.
• All I/O pins are left unconnected.
• All the communication peripherals are exercised in loop-back mode.
• USB – Only logic is exercised by loading and unloading FIFO.
• µDMA does memory-to-memory transfer.
• DMA does memory-to-memory transfer.
• VCU – CRC calculated and checked.
• FPU – Float operations performed.
• ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled.
• Timers and Watchdog serviced.
• eCAP in APWM mode generates 36.6-kHz output on 4 pins.
• ADC performs continuous conversion.
• FLASH is continuously read and in active state.
• XCLKOUT is turned off.
IDDIO current is dependent on the electrical loading on the I/O pins.
Specifications
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 5-1. Current Consumption at 150-MHz C28x SYSCLKOUT and 75-MHz M3SSCLK (continued)
VREG ENABLED
TEST CONDITIONS (1)
MODE
SLEEP IDLE
SLEEP
STANDBY
DEEP SLEEP
STANDBY
•
PLL is on.
•
Cortex-M3 CPU is not
executing.
•
M3SSCLK is on.
•
C28CLKIN is on.
•
C28x CPU is not executing.
•
C28CPUCLK is off.
•
C28SYSCLK is on.
•
PLL is on.
•
Cortex-M3 CPU is not
executing.
•
M3SSCLK is on.
•
C28CLKIN is off.
•
C28x CPU is not executing.
•
C28CPUCLK is off.
•
C28SYSCLK is off.
•
PLL is off.
•
Cortex-M3 CPU is not
executing.
•
M3SSCLK is 32 kHz.
•
C28CLKIN is off.
•
C28x CPU is not executing.
•
C28CPUCLK is off.
•
C28SYSCLK is off.
IDDIO (2)
VREG DISABLED
IDDA
IDD18
IDDIO (2)
IDD12
IDDA
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
–
146 mA
–
2 mA
–
20 mA
–
110 mA
–
11 mA
–
2 mA
–
126 mA
–
2 mA
–
20 mA
–
90 mA
–
11 mA
–
2 mA
–
76 mA
–
2 mA
–
5 mA
–
60 mA
–
7 mA
–
2 mA
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
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Table 5-2. Current Consumption at 125-MHz C28x SYSCLKOUT and 125-MHz M3SSCLK
VREG ENABLED
TEST CONDITIONS (1)
MODE
IDDIO (2)
VREG DISABLED
IDDA
IDD18
IDDIO (2)
IDD12
IDDA
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
–
325 mA
–
40 mA
–
20 mA
–
225 mA
–
75 mA
–
40 mA
The following Cortex-M3 peripherals
are exercised:
•
I2C1
•
SSI1, SSI2
•
UART0, UART1, UART2
•
CAN0
•
USB
•
µDMA
•
Timer0, Timer1
•
µCRC
•
WDOG0, WDOG1
•
Flash
•
Internal Oscillator 1,
Internal Oscillator 2
The following C28x peripherals are
exercised:
Operational
(RAM)
•
McBSP
•
eQEP1, eQEP2
•
eCAP1, eCAP2,
eCAP3, eCAP4
•
SCI-A
•
SPI-A
•
I2C
•
DMA
•
VCU
•
FPU
•
Flash
The following Analog peripherals
are exercised:
(1)
(2)
46
•
ADC1, ADC2
•
Comparator
Comparator
Comparator
Comparator
Comparator
Comparator
1,
2,
3,
4,
5,
6
The following is done in a loop:
• Code is running out of RAM.
• All I/O pins are left unconnected.
• All the communication peripherals are exercised in loop-back mode.
• USB – Only logic is exercised by loading and unloading FIFO.
• µDMA does memory-to-memory transfer.
• DMA does memory-to-memory transfer.
• VCU – CRC calculated and checked.
• FPU – Float operations performed.
• ePWM – 6 enabled and generates 150-kHz PWM output on 12 pins, HRPWM clock enabled.
• Timers and Watchdog serviced.
• eCAP in APWM mode generates 36.6-kHz output on 4 pins.
• ADC performs continuous conversion.
• FLASH is continuously read and in active state.
• XCLKOUT is turned off.
IDDIO current is dependent on the electrical loading on the I/O pins.
Specifications
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 5-2. Current Consumption at 125-MHz C28x SYSCLKOUT and 125-MHz M3SSCLK (continued)
VREG ENABLED
TEST CONDITIONS (1)
MODE
SLEEP IDLE
SLEEP
STANDBY
DEEP SLEEP
STANDBY
•
PLL is on.
•
Cortex-M3 CPU is not
executing.
•
M3SSCLK is on.
•
C28CLKIN is on.
•
C28x CPU is not executing.
•
C28CPUCLK is off.
•
C28SYSCLK is on.
•
PLL is on.
•
Cortex-M3 CPU is not
executing.
•
M3SSCLK is on.
•
C28CLKIN is off.
•
C28x CPU is not executing.
•
C28CPUCLK is off.
•
C28SYSCLK is off.
•
PLL is off.
•
Cortex-M3 CPU is not
executing.
•
M3SSCLK is 32 kHz.
•
C28CLKIN is off.
•
C28x CPU is not executing.
•
C28CPUCLK is off.
•
C28SYSCLK is off.
IDDIO (2)
VREG DISABLED
IDDA
IDD18
IDDIO (2)
IDD12
IDDA
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
–
146 mA
–
2 mA
–
20 mA
–
130 mA
–
11 mA
–
2 mA
–
126 mA
–
2 mA
–
20 mA
–
120 mA
–
11 mA
–
2 mA
–
76 mA
–
2 mA
–
5 mA
–
60 mA
–
7 mA
–
2 mA
NOTE
The peripheral-I/O multiplexing implemented in the device prevents all available peripherals
from being used at the same time because more than one peripheral function may share an
I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time,
although such a configuration is not useful. If the clocks to all the peripherals are turned on
at the same time, the current drawn by the device will be more than the numbers specified in
the current consumption table.
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F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
5.5
www.ti.com
Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIL
Low-level input voltage (3.3 V)
VSS – 0.3
VDDIO * 0.3
V
VIH
High-level input voltage (3.3 V)
VDDIO * 0.7
VDDIO + 0.3
V
VOL
Low-level output voltage
VDDIO * 0.2
V
VOH
IIL
IIH
High-level output voltage
Input current
(low level)
Input current
(high level)
Pin with pullup
enabled
IOL = IOL MAX
IOH = IOH MAX
VDDIO * 0.8
IOH = 50 μA
VDDIO – 0.2
VDDIO = 3.3 V, VIN = 0 V
V
All GPIO pins
–50
–230
XRS pin
–50
–230
ARS pin
–100
–400
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = 0 V
±2 (1)
Pin with pullup
enabled
VDDIO = 3.3 V, VIN = VDDIO
±2 (1)
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = VDDIO
μA
50
200
IOL
Low-level output sink current,
VOL = VOL(MAX)
All GPIO/AIO pins
4
Group 2 (2)
8
IOH
High-level output source current,
VOH = VOH(MIN)
All GPIO/AIO pins
–4
Group 2 (2)
–8
IOZ
Output current, pullup or
pulldown disabled
CI
Input capacitance
(1)
(2)
48
μA
±2 (1)
VO = VDDIO or 0 V
Digital Subsystem POR reset
release delay time
Time after POR event is removed to XRS release
Analog Subsystem POR reset
release delay time
Time after POR event is removed to ARS release
400
VREG VDD18 output
Internal VREG18 on
1.77
VREG VDD12 output
Internal VREG12 on
mA
mA
μA
2
pF
50
µs
800
µs
1.935
V
1.2
V
For GPIO38 and GPIO46 (USB OTG pins), this parameter is ±8 µA.
Group 2 pins are as follows: PD3_GPIO19, PE2_GPIO26, PE3_GPIO27, PH6_GPIO54, PH7_GPIO55, EMU0, TDO, EMU1,
PD0_GPIO16, AIO7, AIO4.
Specifications
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5.6
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Thermal Resistance Characteristics for ZWT Package (Revision 0 Silicon)
°C/W (1)
AIR FLOW (lfm) (2)
RΘJC
Junction-to-case thermal resistance
10.5
0
RΘJB
Junction-to-board thermal resistance
12.8
0
RΘJA
(High k PCB)
PsiJT
Junction-to-package top
PsiJB
(1)
(2)
Junction-to-free air thermal resistance
Junction-to-board
23.0
0
20.5
150
19.5
250
18.5
500
0.5
0
0.6
150
0.8
250
1.0
500
12.9
0
12.9
150
12.8
250
12.7
500
These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
5.7
Thermal Resistance Characteristics for ZWT Package (Revision A Silicon)
°C/W (1)
AIR FLOW (lfm) (2)
RΘJC
Junction-to-case thermal resistance
7.5
0
RΘJB
Junction-to-board thermal resistance
10.5
0
20.6
0
17.9
150
16.8
250
15.6
500
RΘJA
(High k PCB)
PsiJT
PsiJB
(1)
(2)
Junction-to-free air thermal resistance
Junction-to-package top
Junction-to-board
0.25
0
0.35
150
0.42
250
0.53
500
10.4
0
10.5
150
10.4
250
10.3
500
These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
lfm = linear feet per minute
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49
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
5.8
www.ti.com
Thermal Design Considerations
Based on the end-application design and operational profile, the IDD12, IDD18, and IDDIO currents could vary.
Systems that exceed the recommended maximum power dissipation in the end product may require
additional thermal enhancements. Ambient temperature (TA) varies with the end application and product
design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the
ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be
measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of
the package top-side surface. For more details about thermal metrics and definitions, see Semiconductor
and IC Package Thermal Metrics.
50
Specifications
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5.9
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Timing and Switching Characteristics
5.9.1
Power Sequencing
There is no power sequencing requirement needed to ensure the device is in the proper state after reset
or to prevent the I/Os from glitching during power up and power down. (All I/Os, except for GPIO199, are
glitch-free during power up and power down.) No voltage larger than a diode drop (0.7 V) above VDDIO
should be applied to any digital pin (for analog pins, this value is 0.7 V above VDDA) before powering up
the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended
ways and produce unpredictable results.
VDDIO, VDDA
(3.3 V)
VDD12, VDD18
X1/X2
tOSCST
(B)
(A)
XCLKOUT
User-code dependent
tw(RSL2)
XRS
(D)
tw(RSL1)
Address/data valid, internal boot-ROM code execution phase
Address/Data/
Control
(Internal)
td(EX)
th(boot-mode)(C)
Boot-Mode
Pins
User-code execution phase
User-code dependent
GPIO pins as input
Peripheral/GPIO function
Based on boot code
Boot-ROM execution starts
I/O Pins
GPIO pins as input (state depends on internal PU/PD)
User-code dependent
A.
B.
C.
D.
Upon power up, PLLSYSCLK is OSCCLK/8. Because the XCLKOUTDIV bits in the XCLK register come up with a
reset state of 0, PLLSYSCLK is further divided by 4 before PLLSYSCLK appears at XCLKOUT. XCLKOUT =
OSCCLK/32 during this phase.
Boot ROM configures the SYSDIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. XCLKOUT will
not be visible at the pin until explicitly configured by user code.
After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will
be based on user environment and could be with or without PLL enabled.
The XRS pin will be driven low by on-chip POR circuitry until the VDDIO voltage crosses the POR threshold. (The POR
threshold is lower than the operating voltage requirement.) To allow the external clock to stabilize, the XRS pin may
also need to be driven low by the system for additional time.
Figure 5-1. Power-On Reset
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
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Table 5-3. Reset (XRS) Timing Requirements
MIN
th(boot-mode)
Hold time for boot-mode pins
tw(RSL2)
Pulse duration, XRS low
MAX
UNIT
14000tc(M3C)
cycles
32tc(OCK)
cycles
Table 5-4. Reset (XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
tw(RSL1)
Pulse duration, XRS driven by device
tw(WDRS)
Pulse duration, reset pulse generated by watchdog
td(EX)
Delay time, address/data valid after XRS high
tINTOSCST
Start-up time, internal zero-pin oscillator
3
μs
On-chip crystal-oscillator start-up time
2
ms
tOSCST
(1)
(1)
600
μs
512tc(OCK)
cycles
32tc(OCK)
cycles
Dependent on crystal/resonator and board design.
X1/X2
XCLKOUT
User-Code Dependent
tw(RSL2)
XRS
Address/Data/
Control
(Internal)
td(EX)
User-Code Execution
Boot-ROM Execution Starts
Boot-Mode
Pins
User-Code Execution Phase
Peripheral/GPIO Function
GPIO Pins as Input
th(boot-mode)(A)
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A.
After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will
be based on user environment and could be with or without PLL enabled.
Figure 5-2. Warm Reset
5.9.1.1
Power Management and Supervisory Circuit Solutions
LDO selection depends on the total power consumed in the end application. Go to the Power
management product folder to select a device and to access reference designs, technical documents,
support and training. The Power management guide is also available for download.
52
Specifications
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5.9.2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Clock Specifications
This section provides the frequencies and timing requirements of the input clocks; PLL lock times;
frequencies of the internal clocks; and the frequency and switching characteristics of the output clock.
5.9.2.1
Changing the Frequency of the Main PLL
When configuring the PLL, it should be locked twice in a row. The PLL will be ready to use in the system
when the xPLLSTS[xPLLLOCKS] bit is set after the second lock. The SysCtlClockPllConfig () function in
sysctl.c, found in controlSUITE™, may be referenced as an example of a proper PLL initialization
sequence. For additional information, see the "Clock Control" section of the Concerto F28M36x Technical
Reference Manual.
5.9.2.2
Input Clock Frequency and Timing Requirements, PLL Lock Times
Table 5-5 shows the frequency requirements for the input clocks to the F28M36x devices. Table 5-6
shows the crystal equivalent series resistance requirements. Table 5-8, Table 5-9, Table 5-10, and
Table 5-11 show the timing requirements for the input clocks to the F28M36x devices. Table 5-12 shows
the PLL lock times for the Main PLL and the USB PLL. The Main PLL operates from the X1 or X1/X2 input
clock pins, and the USB PLL operates from the XCLKIN input clock pin.
Table 5-5. Input Clock Frequency
MIN
MAX
UNIT
f(OSC)
Frequency, X1/X2, from external crystal or resonator
2
20
MHz
f(OCI)
Frequency, X1, from external oscillator (PLL enabled)
2
30
MHz
f(OCI)
Frequency, X1, from external oscillator (PLL disabled)
2
100
MHz
f(XCI)
Frequency, XCLKIN, from external oscillator
2
60
MHz
Table 5-6. Crystal Equivalent Series Resistance (ESR) Requirements (1)
CRYSTAL FREQUENCY (MHz)
MAXIMUM ESR (Ω)
(CL1/2 = 12 pF)
MAXIMUM ESR (Ω)
(CL1/2 = 24 pF)
2
175
375
4
100
195
6
75
145
(1)
8
65
120
10
55
110
12
50
95
14
50
90
16
45
75
18
45
65
20
45
50
Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
Table 5-7. Crystal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
Start-up time
(1)
TEST CONDITIONS
MIN
TYP
f = 20 MHz; ESR MAX = 50 Ω;
CL1 = CL2 = 24 pF, C0 = 7 pF
(1)
MAX
UNIT
2
ms
Start-up time is dependent on the crystal and tank circuit components. It is recommended that the crystal vendor characterize the
application with the chosen crystal.
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Table 5-8. X1 Timing Requirements - PLL Enabled (1)
MIN
MAX
tf(OCI)
Fall time, X1
tr(OCI)
Rise time, X1
tw(OCL)
Pulse duration, X1 low as a percentage of tc(OCI)
45%
55%
tw(OCH)
Pulse duration, X1 high as a percentage of tc(OCI)
45%
55%
(1)
UNIT
6
ns
6
ns
The possible Main PLL configuration modes are shown in Table 6-19 to Table 6-22.
Table 5-9. X1 Timing Requirements - PLL Disabled
MIN
MAX
Up to 20 MHz
6
20 MHz to 100 MHz
2
Up to 20 MHz
6
20 MHz to 100 MHz
2
tf(OCI)
Fall time, X1
tr(OCI)
Rise time, X1
tw(OCL)
Pulse duration, X1 low as a percentage of tc(OCI)
45%
55%
tw(OCH)
Pulse duration, X1 high as a percentage of tc(OCI)
45%
55%
UNIT
ns
ns
Table 5-10. XCLKIN Timing Requirements - PLL Enabled (1)
MIN
MAX
UNIT
tf(XCI)
Fall time, XCLKIN
6
ns
tr(XCI)
Rise time, XCLKIN
6
ns
tw(XCL)
Pulse duration, XCLKIN low as a percentage of tc(XCI)
45%
55%
tw(XCH)
Pulse duration, XCLKIN high as a percentage of tc(XCI)
45%
55%
(1)
The possible USB PLL configuration modes are shown in Table 6-23 and Table 6-24.
Table 5-11. XCLKIN Timing Requirements - PLL Disabled
MIN
MAX
Up to 20 MHz
6
20 MHz to 100 MHz
2
Up to 20 MHz
6
20 MHz to 100 MHz
2
tf(XCI)
Fall time, XCLKIN
tr(XCI)
Rise time, XCLKIN
tw(XCL)
Pulse duration, XCLKIN low as a percentage of tc(XCI)
45%
55%
tw(XCH)
Pulse duration, XCLKIN high as a percentage of tc(XCI)
45%
55%
UNIT
ns
ns
Table 5-12. PLL Lock Times
MIN
NOM
input clock
cycles
Lock time, Main PLL (X1, from external oscillator)
2000
t(USB)
Lock time, USB PLL (XCLKIN, from external oscillator)
2000 (1)
54
UNIT
input clock
cycles
t(PLL)
(1)
MAX
(1)
For example, if the input clock to the PLL is 10 MHz, then a single PLL lock time is 100 ns × 2000 = 200 µs. This defines the time of a
single write to the PLL configuration registers until the xPLLSTS[xPLLLOCKS] bit is set. The PLL should be locked twice to ensure a
good PLL output frequency is present.
Specifications
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5.9.2.3
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Output Clock Frequency and Switching Characteristics
Table 5-13 provides the frequency of the output clock from the F28M36x devices. Table 5-14 shows the
switching characteristics of the output clock from the F28M36x devices, XCLKOUT.
Table 5-13. Output Clock Frequency
f(XCO)
MIN
MAX
UNIT
2
37.5
MHz
Frequency, XCLKOUT
Table 5-14. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tf(XCO)
Fall time, XCLKOUT
5
ns
tr(XCO)
Rise time, XCLKOUT
5
ns
tw(XCOL)
Pulse duration, XCLKOUT low
H–2
H+2
ns
tw(XCOH)
Pulse duration, XCLKOUT high
H–2
H+2
ns
(1)
(2)
A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
5.9.2.4
Internal Clock Frequencies
Table 5-15 provides the clock frequencies for the internal clocks of the F28M36x devices.
Table 5-15. Internal Clock Frequencies (150-MHz Devices)
MIN
NOM
MAX
Frequency, USBPLLCLK
f(PLL)
Frequency, PLLSYSCLK
2
150
MHz
f(OCK)
Frequency, OSCCLK
2
100
MHz
f(M3C)
Frequency, M3SSCLK
2
100 (1)
MHz
f(ADC)
Frequency, ASYSCLK
2
37.5
MHz
f(SYS)
Frequency, C28SYSCLK
2
150 (1)
MHz
f(HSP)
Frequency, C28HSPCLK
2
150 (1)
MHz
f(LSP)
Frequency, C28LSPCLK (2)
2
150 (1)
MHz
f(10M)
Frequency, 10MHZCLK
10
MHz
f(32K)
Frequency, 32KHZCLK
32
kHz
(1)
(2)
(3)
60
UNIT
f(USB)
37.5 (3)
MHz
An integer divide ratio must be maintained between the C28x and Cortex-M3 clock frequencies. For example, when the C28x is
configured to run at a maximum frequency of 150 MHz, the fastest allowable frequency for the Cortex-M3 will be 75 MHz. See Figure 610 and Figure 6-12 to see the internal clocks and clock divider options.
Lower LSPCLK will reduce device power consumption.
This is the default reset value if C28SYSCLK = 150 MHz.
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5.9.3
www.ti.com
Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
5.9.3.1
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
f
fall time
X
Unknown, changing, or don't care
level
h
hold time
Z
High impedance
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
5.9.3.2
Test Load Circuit
15 W
25 W
Z0 = 50 W
TD = 6 ns
(A)
DEVICE PIN
DATA SHEET
TIMING
REFERENCE
POINT
TESTER PIN ELECTRONICS
(B)
This test load circuit is used to measure all switching characteristics provided in this document.
TRANSMISSION LINE
20 pF
20 pF
OUTPUT
UNDER
TEST
CONCERTO DEVICE
A.
B.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 5-3. 3.3-V Test Load Circuit
56
Specifications
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5.9.4
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Flash Timing – Master Subsystem
Table 5-16. Master Subsystem – Flash/OTP Endurance
Nf
Flash endurance for the array (write/erase cycles)
NOTP
OTP endurance for the array (write cycles)
MIN
TYP
20000
50000
MAX
UNIT
cycles
1
write
Table 5-17. Master Subsystem – Flash Parameters (1)
PARAMETER
TEST
CONDITIONS
MIN
128 data bits + 16 ECC bits
Program Time (2) 32K Sector
128K Sector
TYP
MAX
40
300
μs
290
580
ms
ms
1160
2320
Erase Time (3)
at < 25 cycles
32K Sector
25
50
128K Sector
40
70
Erase Time (3)
at 50k cycles
32K Sector
115
4000
128K Sector
140
4000
IDDP (4) (5)
VDD current consumption during Erase/Program cycle
IDDIOP (4) (5)
VDDIO current consumption during Erase/Program cycle
IDDIOP (4) (5)
VDDIO current consumption during Erase/Program cycle
(1)
(2)
(3)
(4)
(5)
VREG disabled
VREG enabled
UNIT
105
ms
ms
mA
55
195
mA
The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
before programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
Program time includes overhead of the Flash state machine but does not include the time to transfer the following into RAM:
• Code that uses Flash API to program the Flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
Erase time includes Erase verify by the CPU.
Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during
flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed
during the programming process.
This current is measured with Flash API executing from RAM. There is not any data transfer through JTAG or any peripheral.
Table 5-18. Master Subsystem – Flash/OTP Access Timing (1)
PARAMETER
MIN
MAX
UNIT
ta(f)
Flash access time
25
ns
ta(OTP)
OTP access time
50
ns
(1)
Access time numbers shown in this table are prior to device characterization. Final numbers will be published in the data sheet for the
fully qualified production device.
Table 5-19. Master Subsystem – Flash Data Retention Duration
PARAMETER
tretention
Data retention duration
TEST CONDITIONS
TJ = 85°C
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MIN
MAX
20
Specifications
UNIT
years
57
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F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
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Table 5-20. Master Subsystem – Minimum Required Flash/OTP Wait States at
Different Frequencies
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
WAIT STATE
125
8
3
120
8.33
2
110
9.1
2
100
10
2
90
11.11
2
80
12.5
1
70
14.29
1
60
16.67
1
50
20
1
40
25
0
30
33.33
0
20
50
0
10
100
0
The equation to compute the Flash wait state in Table 5-20 is as follows:
RWAIT =
SYSCLK (MHz)
40 (MHz)
1
round up to the next integer, or 1, whichever is larger.
58
Specifications
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5.9.5
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Flash Timing – Control Subsystem
Table 5-21. Control Subsystem – Flash/OTP Endurance
Nf
Flash endurance for the array (write/erase cycles)
NOTP
OTP endurance for the array (write cycles)
MIN
TYP
20000
50000
MAX
UNIT
cycles
1
write
Table 5-22. Control Subsystem – Flash Parameters (1) (2)
PARAMETER
TEST
CONDITIONS
MIN
128 data bits + 16 ECC bits
TYP
MAX
UNIT
40
300
μs
Program Time (3) 16K Sector
105
210
ms
ms
64K Sector
420
840
Erase Time (4)
at < 25 cycles
16K Sector
25
50
64K Sector
30
55
Erase Time (4)
at 50k cycles
16K Sector
105
4000
64K Sector
115
4000
IDDP (5) (6)
VDD current consumption during Erase/Program cycle
IDDIOP (5) (6)
VDDIO current consumption during Erase/Program cycle
IDDIOP (5) (6)
VDDIO current consumption during Erase/Program cycle
(1)
(2)
(3)
(4)
(5)
(6)
VREG disabled
VREG enabled
90
ms
ms
mA
55
150
mA
The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
before programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
Before trying to erase or program the C28x Flash, ensure that the Cortex-M3 core does not generate a reset while the C28x Flash is
being erased or programmed.
Program time includes overhead of the Flash state machine but does not include the time to transfer the following into RAM:
• Code that uses Flash API to program the Flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
Erase time includes Erase verify by the CPU.
Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during
flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed
during the programming process.
This current is measured with Flash API executing from RAM. There is not any data transfer through JTAG or any peripheral.
Table 5-23. Control Subsystem – Flash/OTP Access Timing (1)
PARAMETER
MIN
MAX
UNIT
ta(f)
Flash access time
25
ns
ta(OTP)
OTP access time
50
ns
(1)
Access time numbers shown in this table are prior to device characterization. Final numbers will be published in the data sheet for the
fully qualified production device.
Table 5-24. Control Subsystem – Flash Data Retention Duration
PARAMETER
tretention
Data retention duration
TEST CONDITIONS
TJ = 85°C
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MIN
MAX
20
Specifications
UNIT
years
59
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Table 5-25. Control Subsystem – Minimum Required Flash/OTP Wait States at
Different Frequencies
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
WAIT STATE
150
6.7
3
140
7.14
3
130
7.7
3
120
8.33
2
110
9.1
2
100
10
2
90
11.11
2
80
12.5
1
70
14.29
1
60
16.67
1
50
20
1
40
25
0
30
33.33
0
20
50
0
10
100
0
The equation to compute the Flash wait state in Table 5-25 is as follows:
RWAIT =
SYSCLK (MHz)
40 (MHz)
1
round up to the next integer, or 1, whichever is larger.
60
Specifications
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www.ti.com
5.9.6
5.9.6.1
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
GPIO Electrical Data and Timing
GPIO - Output Timing
Table 5-26. General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tr(GPO)
Rise time, GPIO switching low to high
All GPIOs
8
tf(GPO)
Fall time, GPIO switching high to low
All GPIOs
8
ns
ns
tfGPO
Toggling frequency, GPIO pins
25
MHz
GPIO
tf(GPO)
tr(GPO)
Figure 5-4. General-Purpose Output Timing
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F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
5.9.6.2
www.ti.com
GPIO - Input Timing
Table 5-27. General-Purpose Input Timing Requirements
MIN
tw(SP)
Sampling period
tw(IQSW)
Input qualifier sampling window
tw(GPI)
(1)
(2)
(2)
UNIT
QUALPRD = 0
1tc(SCO)
cycles
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
cycles
tw(SP) * (n (1) – 1)
cycles
2tc(SCO)
cycles
tw(IQSW) + tw(SP) + 1tc(SCO)
cycles
Synchronous mode
Pulse duration, GPIO low/high
MAX
With input qualifier
"n" represents the number of qualification samples as defined by GPxQSELn register.
For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
tw(SP)
0
0
0
1
1
1
1
Sampling Window
1
1
1
1
Sampling Period determined
by GPxCTRL[QUALPRD]
tw(IQSW)
1
(SYSCLKOUT cycle * 2 * QUALPRD) * 5
(B)
(C)
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A.
B.
C.
D.
This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO
pin will be sampled).
The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLKOUTwide pulse ensures reliable recognition.
Figure 5-5. Sampling Mode
62
Specifications
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5.9.6.3
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0
SYSCLK
GPIOxn
tw(GPI)
Figure 5-6. General-Purpose Input Timing
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
5.9.6.4
www.ti.com
Low-Power Mode Wakeup Timing
Table 5-28 shows the timing requirements, Table 5-29 shows the switching characteristics, and Figure 5-7
shows the timing diagram for IDLE mode.
Table 5-28. IDLE Mode Timing Requirements (1)
MIN
tw(WAKE-INT)
(1)
Pulse duration, external wake-up
signal
Without input qualifier
MAX
2tc(SCO)
With input qualifier
UNIT
cycles
5tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Table 5-27.
Table 5-29. IDLE Mode Switching Characteristics (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, external wake signal to program
execution resume (2)
td(WAKE-IDLE)
Wake-up from Flash
•
Flash module in active state
Without input qualifier
Wake-up from Flash
•
Flash module in sleep state
Without input qualifier
20tc(SCO)
With input qualifier
20tc(SCO) + tw(IQSW)
1050tc(SCO)
With input qualifier
1050tc(SCO) + tw(IQSW)
Without input qualifier
•
(1)
(2)
Wake-up from SARAM
20tc(SCO)
With input qualifier
20tc(SCO) + tw(IQSW)
cycles
cycles
cycles
For an explanation of the input qualifier parameters, see Table 5-27.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
td(WAKE-IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE-INT)
(A)(B)
WAKE INT
A.
B.
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 5-7. IDLE Entry and Exit Timing
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Table 5-30. STANDBY Mode Timing Requirements
MIN
tw(WAKE-INT)
(1)
Pulse duration, external
wake-up signal
Without input qualification
With input qualification (1)
MAX
3tc(OSCCLK)
UNIT
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
QUALSTDBY is a 6-bit field in the LPMCR0 register.
Table 5-31. STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(IDLE-XCOL)
Delay time, IDLE instruction executed
to XCLKOUT low
td(WAKE-STBY)
Delay time, external wake signal to
program execution resume (1)
•
•
TEST CONDITIONS
MIN
MAX
UNIT
32tc(SCO)
45tc(SCO)
cycles
cycles
Wake up from flash
– Flash module in active state
Without input qualifier
Wake up from flash
– Flash module in sleep state
Without input qualifier
With input qualifier
With input qualifier
100tc(SCO)
100tc(SCO) + tw(WAKE-INT)
1125tc(SCO)
1125tc(SCO) + tw(WAKE-INT)
Without input qualifier
•
(1)
Wake up from SARAM
With input qualifier
100tc(SCO)
100tc(SCO) + tw(WAKE-INT)
cycles
cycles
cycles
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
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(A)
(C)
(B)
STANDBY
Device Status
(E)
(D)
STANDBY
(F)
Normal Execution
Flushing Pipeline
(G)
Wake-up Signal
tw(WAKE-INT)
td(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
td(IDLE-XCOL)
A.
B.
C.
D.
E.
F.
G.
IDLE instruction is executed to put the device into STANDBY mode.
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
•
16 cycles, when DIVSEL = 00 or 01
•
32 cycles, when DIVSEL = 10
•
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is
in progress and its access time is longer than this number then it will fail. It is recommended to enter STANDBY
mode from SARAM without an XINTF access in progress.
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
The external wake-up signal is driven active.
After a latency period, the STANDBY mode is exited.
Normal execution resumes. The device will respond to the interrupt (if enabled).
From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 5-8. STANDBY Entry and Exit Timing Diagram
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Table 5-32. HALT Mode Timing Requirements
MIN
tw(WAKE-GPIO)
Pulse duration, GPIO wake-up signal
tw(WAKE-XRS)
Pulse duration, XRS wakeup signal
(1)
MAX
UNIT
toscst + 2tc(OSCCLK) (1)
cycles
toscst + 8tc(OSCCLK)
cycles
See Table 5-4 for an explanation of toscst.
Table 5-33. HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(IDLE-XCOL)
Delay time, IDLE instruction executed to XCLKOUT low
tp
PLL lock-up time
td(WAKE-HALT)
Delay time, PLL lock to program execution resume
•
Wake up from flash
– Flash module in sleep state
•
MIN
MAX
UNIT
32tc(SCO)
45tc(SCO)
cycles
131072tc(OSCCLK)
cycles
1125tc(SCO)
cycles
35tc(SCO)
cycles
Wake up from SARAM
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(A)
(C)
Device Status
(D)
HALT
Flushing Pipeline
(G)
(E)
(B)
(F)
HALT
PLL Lock-up Time
Wake-up Latency
Normal
Execution
(H)
GPIOn
td(WAKE-HALT)
tw(WAKE-GPIO)
tp
X1/X2 or
XCLKIN
Oscillator Start-up Time
XCLKOUT
td(IDLE−XCOL)
A.
B.
C.
D.
E.
F.
G.
H.
IDLE instruction is executed to put the device into HALT mode.
The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before
oscillator is turned off and the CLKIN to the core is stopped:
•
16 cycles, when DIVSEL = 00 or 01
•
32 cycles, when DIVSEL = 10
•
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in
progress and its access time is longer than this number then it will fail. It is recommended to enter HALT mode from
SARAM without an XINTF access in progress.
Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This
enables the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin
asynchronously begins the wakeup process, care should be taken to maintain a low noise environment before
entering and during HALT mode.
Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles. These 131,072 clock cycles are applicable even when the PLL is disabled (that is, code execution
will be delayed by this duration even when the PLL is disabled).
Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the
interrupt (if enabled), after a latency.
Normal operation resumes.
From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 5-9. HALT Wake-Up Using GPIOn
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5.9.7
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External Interrupt Electrical Data and Timing
Table 5-34. External Interrupt Timing Requirements (1)
MIN
tw(INT)
(1)
(2)
(2)
Pulse duration, INT input low/high
MAX
UNIT
Synchronous
1tc(SCO)
cycles
With qualifier
1tc(SCO) + tw(IQSW)
cycles
For an explanation of the input qualifier parameters, see Table 5-27.
This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 5-35. External Interrupt Switching Characteristics (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
td(INT)
(1)
Delay time, INT low/high to interrupt-vector fetch
MIN
MAX
UNIT
tw(IQSW) + 12tc(SCO)
cycles
For an explanation of the input qualifier parameters, see Table 5-27.
tw(INT)
XNMI, XINT1, XINT2
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 5-10. External Interrupt Timing
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5.10 Analog and Shared Peripherals
Concerto Shared Peripherals are accessible from both the Master Subsystem and the Control Subsystem.
The Analog Shared Peripherals include two 12-bit ADCs (Analog-to-Digital Converters), and six
Comparator + DAC (10-bit) modules. The ADC Result Registers are accessible by CPUs and DMAs of the
Master and Control Subsystems. All other analog registers, such as the ADC Configuration and
Comparator Registers, are accessible by the C28x CPU only. The Digital Shared Peripherals include the
IPC peripheral and the EPI. IPC is accessible by both CPUs; EPI is accessible by both CPUs and both
DMAs.
IPC is used for sending and receiving synchronization events between Master and Control subsystems to
coordinate execution of software running on both processors, or exchanging of data between the two
processors. EPI is used by this device to communicate with external memory and other devices.
For detailed information on the processor peripherals, see the Concerto F28M36x Technical Reference
Manual.
5.10.1 Analog-to-Digital Converter
Figure 5-11 shows the internal structure of each of the two ADC peripherals that are present on Concerto.
Each ADC has 16 channels that can be programmed to select analog inputs, select start-of-conversion
trigger, set the sampling window, and select end-of-conversion interrupt to prompt a CPU or DMA to read
16 result registers. The 16 ADC channels can be used independently or in pairs, based on the
assignments inside the SAMPLEMODE register. Pairing up the channels allows two analog inputs to be
sampled simultaneously—thereby, increasing the overall conversion performance.
5.10.1.1 Sample Mode
Each ADC has 16 programmable channels that can be independently programmed for analog-to-digital
conversion when corresponding bits in the SAMPLEMODE register are set to Sequential Mode. For
example, if bit 2 in the SAMPLEMODE register is set to 0, ADC channels 4 and 5 are set to sequential
mode. Both the SOC4CTL and SOC5CTL registers can then be programmed to configure channels 4 and
5 to independently perform analog-to-digital conversions with results being stored in the RESULT4 and
RESULT5 registers. "Independently" means that channel 4 may use a different SOC trigger, different
analog input, and different sampling window than the trigger, input, and window assigned to channel 5.
The 16 programmable channels for each ADC may also be grouped in 8 channel pairs when
corresponding bits in the SAMPLEMODE register are set to Simultaneous Mode. For example, if bit 2 in
the SAMPLEMODE register is set to 1, ADC channels 4 and 5 are set to Simultaneous Mode. The
SOC4CTL register now contains configuration parameters for both channel 4 and channel 5, and the
SOC5CTL register is ignored. While channel 4 and channel 5 are still using dedicated analog inputs (now
selected as pairs in the CHSEL field of SOC4CTL), they both share the same SOC trigger and Sampling
Window, with the results being stored in the RESULT4 and RESULT5 registers.
The Simultaneous mode is made possible by two sample-and-hold units present in each ADC. Each
sample-and-hold unit has its own mux for selecting analog inputs (see Figure 5-11). By programming the
SAMPLEMODE register, the 16 available channels can be configured as 16 independent channels,
8 channel pairs, or any combination thereof (for example, 10 sequential channels and 3 simultaneous
pairs).
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TRIGS(8:1)
ADC_INT(8:1)
INTSOCSEL1 REG
INTSOCSEL2 REG
ADCINT1
ACIB
SOC0CTL REG
ADCINT2
SOC1CTL REG
ACIB (ANALOG COMMON INTERFACE BUS)
SOC2CTL REG
INTSEL1N2 REG
INTSEL3N4 REG
ADC INTERUPT
CONTROL
INTSEL5N6 REG
INTSEL7N8 REG
INTFLG REG
SOCFLG REG
INTFLGCLR REG
SOCFRC REG
INTOVF REG
SOCOVF REG
INTOVFCLR REG
SOCOVFCLR REG
SOC3CTL REG
SOC4CTL REG
SOCx TRIGGER
CONTROL
SOC5CTL REG
SOC6CTL REG
SOC7CTL REG
SOC8CTL REG
SOC9CTL REG
SOCPRICTL REG
EOC(15:0)
SOC(15:0)
AIO_MUX
SAMPLEMODE REG
SOC10CTL REG
SOC11CTL REG
SOC12CTL REG
SOC13CTL REG
SOC14CTL REG
GPIO
ADC CONTROL
4
ASEL
ADC_INA0
SOC15CTL REG
SHSEL
SOC
REGSEL
ANALOG BUS
0
N/C
ADC_INA2
ADC_INA3
ADC_INA4
N/C
ADC_INA6
1
2
RESULT0 REG
3
RESULT1 REG
4
RESULT2 REG
5
RESULT3 REG
6
ADC_INA7
RESULT4 REG
7
A
S/H
A
RESULT5 REG
RESULT6 REG
MUX
12-BIT ADC
CONVERTER
ADCCTL1 REG
BSEL
STORE
RESULT
VREFLOCONV
ADC_INB2
N/C
3
ADC_INB4
ADC_INB7
1
B
S/H
B
RESULT10 REG
RESULT11 REG
2
ADC_INB3
ADC_INB6
RESULT8 REG
RESULT9 REG
0
ADC_INB0
RESULT7 REG
4
VREFLO 1
5
6
ADCCTL1 REG
REFTRIM REG
OFFTRIM REG
REV REG
RESULT12 REG
RESULT13 REG
RESULT14 REG
RESULT15 REG
7
(1) CURRENTLY DEFAULT IS “NO CONNECT”, CHANGE ADDCCTL1 REGISTER TO CONNECT TO VREFLO
Figure 5-11. ADC
Specifications
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5.10.1.2 Start-of-Conversion Triggers
There are eight external SOC triggers that go to each of the two ADC modules (from the Control
Subsystem). In addition to the eight external SOC triggers, there are also two internal SOC triggers
derived from EOC interrupts inside each ADC module (ADCINT1 and ADCINT2). Registers INTSOCSEL1
and 2 are used to configure each of the 16 ADC channels for internal or external SOC sources. If internal
SOC is chosen for a given channel, the INTSOCSEL1 and 2 registers also select whether the internal
source is ADCINT1 or ADCINT2. If external SOC is chosen for a given ADC channel, the TRIGSEL field
of the corresponding SOCxCTL register selects which of the eight external triggers is used for SOC in that
channel. One analog-to-digital conversion can be performed at a time by the 12-bit ADC. The analog-todigital conversion priority is managed according to the state of the PRICTL register.
5.10.1.3 Analog Inputs
Analog inputs to each of the two ADC modules are organized in two groups—A and B, with each group
having a dedicated mux and sample-and-hold unit (see Figure 5-11). Mux A selects one of six possible
analog inputs through AIO MUX. Mux B selects one of seven possible analog inputs—six external inputs
through AIO MUX, and one from the internal VREFLO signal, which is currently tied to the Analog Ground.
The Mux A and Mux B inputs can be simultaneously or sequentially sampled by the two sample-and-hold
units according to the sampling window chosen in the SOCxCTL register for the corresponding channel.
5.10.1.4 ADC Result Registers and EOC Interrupts
Concerto analog-to-digital conversion results are stored in 32 Results Registers (16 for ADC1 and 16 for
ADC2). The 16 ADCx channels can be programmed through the INTSELxNy registers to trigger up to
eight ADCINT interrupts per ADC module, when their results are ready to be read. The eight ADCINT
interrupts from ADC1 and the eight ADCINT interrupts from ADC2 are AND-ed together before
propagating to both the Master Subsystem and the Control Subsystem, announcing that the Result
Registers are ready to be read by a CPU or DMA (see Figure 6-3).
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5.10.1.5 ADC Electrical Data and Timing
Table 5-36. ADC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
MHz
DC SPECIFICATIONS
Resolution
12
Bits
ADC clock
2
37.5
Sample Window
7
64
ADC
clocks
–4
4
LSB
–1
1.5
LSB
ACCURACY
INL (Integral nonlinearity)
DNL (Differential nonlinearity)
Offset error
Executing a single selfrecalibration
–20
0
20
Executing periodic selfrecalibration
–4
0
4
LSB
Overall gain error with internal reference
–60
60
LSB
Overall gain error with external reference
–40
40
LSB
Channel-to-channel offset variation
–4
4
LSB
Channel-to-channel gain variation
–4
4
LSB
VREFLO input current
–100
µA
VREFHI input current
100
µA
ANALOG INPUT
Analog input voltage with internal reference
0
3.3
V
Analog input voltage with external reference
VREFLO
VREFHI
V
VREFLO input voltage
VSSA
0.66
V
VREFHI input voltage
2.64
VDDA
Input capacitance
Input leakage current
V
5
pF
±2
μA
65
dB
62
dB
ADDITIONAL
ADC SNR
ADC SINAD
ADC THD (50 kHz)
–65
dB
ENOB (SNR)
10.1
Bits
66
dB
SFDR
Table 5-37. External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tw(ADCSOCL)
MIN
Pulse duration, ADCSOCxO low
32tc(HCO)
MAX
UNIT
cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 5-12. ADCSOCAO or ADCSOCBO Timing
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5.10.2 Comparator + DAC Units
Figure 5-13 shows the internal structure of the six analog Comparator + DAC units present in Concerto
devices. Each unit compares two analog inputs (A and B) and assigns a value of ‘1’ when the voltage of
the A input is greater than that of the B input, or a value of ‘0’ when the opposite is true. The six A inputs
and six B inputs come from AIO_MUX1 and AIO_MUX2. All six B inputs can also be provided by the 10bit digital-to-analog units that are present in each comparator DAC. The 10-bit value for each DAC unit is
programmed in the respective DACVAL register. Another comparator register, COMPCTL, can be
programmed to select the source of the B input, to enable or disable the comparator circuit, to invert
comparator output, to synchronize comparator output to C28x SYSCLK, and to select the qualification
period (number of clock cycles). All six output signals from the six comparators can be routed out to the
device pins through GPIO_MUX2 pin mux.
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AIO_MUX1
GPIO_MUX2
COMPA(1)
COMPOUT(1)
GPIO
GPIO
COMP1
DAC1
COMPB(1)
4
4
COMP2
COMPCTL REG
COMPSOURCE
COMPDACE
COMPINV
QUALSEL
SYNCSEL
1
COMPA(2)
+
12
1
COMPB(2)
MUX
VDDA
VSSA
V
10-BIT
DAC2
DACVAL(8:0)
DACVAL REG
0
0
COMP2
_
COMPOUT(2)
1
SYNC / QUAL
0
V = ( DACVAL * ( VDDA-VSSA ) ) / 1023
C28SYSCLK
COMP = 0 WHEN VOLTAGE A < VOLTAGE B
COMP = 1 WHEN VOLTAGE A > VOLTAGE B
COMPSTS
COMPSTS REG
COMPA(3)
COMPB(3)
DAC3
COMP3
COMPOUT(3)
8
MUX
AIO_MUX2
COMPA(4)
GPIO
COMPB(4)
DAC4
COMP4
COMPOUT(4)
4
COMPA(5)
12
COMPB(5)
DAC5
COMP5
COMPOUT(5)
MUX
COMPA(6)
COMPB(6)
DAC6
COMP6
COMPOUT(6)
Figure 5-13. Comparator + DAC Units
Specifications
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5.10.2.1 On-Chip Comparator and DAC Electrical Data and Timing
Table 5-38. Electrical Characteristics of the Comparator/DAC
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNITS
Comparator
Comparator Input Range
VSSA – VDDA
V
Comparator response time to GPIO
30
ns
Input Offset
±5
mV
Input Hysteresis (1)
35
mV
DAC
DAC Output Range
VSSA – VDDA
DAC resolution
10
DAC settling time
bits
See Figure 5-14
DAC Gain
–1.5
DAC Offset
%
10
Monotonic
mV
Yes
INL
(1)
V
±3
LSB
Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback
resistance between the output of the comparator and the noninverting input of the comparator.
1100
1000
900
800
Settling Time (ns)
700
600
500
400
300
200
100
0
0
50
100
150
200
250
300
350
400
450
500
DAC Step Size (Codes)
DAC Accuracy
15 Codes
7 Codes
3 Codes
1 Code
Figure 5-14. DAC Settling Time
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5.10.3 Interprocessor Communications
Figure 5-15 shows the internal structure of the IPC peripheral used to synchronize program execution and
exchange of data between the Cortex-M3 and the C28x CPU. IPC can be used by itself when
synchronizing program execution or it can be used in conjunction with Message RAMs when coordinating
data transfers between processors. In either case, the operation of the IPC is the same. There are two
independent sides to the IPC peripheral—MTOC (Master to Control) and CTOM (Control to Master).
The MTOC IPC is used by the Master Subsystem to send events to the Control Subsystem. The MTOC
IPC typically sends events to the Control Subsystem by using the following registers: MTOCIPCSET,
MTOCIPCFLG/MTOCIPCSTS (1), and MTOCIPCACK. Each of the 32 bits of these registers represents
32 independent channels through which the Cortex-M3 CPU can send up to 32 events to the C28x CPU
through software handshaking. Additionally, the first 4 bits of the MTOCIPC registers are supplemented
with interrupts. To send an event through channel 2 from Cortex-M3 to C28x, for example, the Cortex-M3
and C28x CPUs use bit 2 of the MTOCIPCSET, MTOCIPCFLG/MTOCIPCSTS, MTOCIPCACK registers.
The handshake starts with the Cortex-M3 polling bit 2 of the MTOCIPCFLG register to make sure bit 2 is
‘0’. Next, the Cortex-M3 writes a ‘1’ into bit 2 of the MTOCIPCSET register to start the handshake. In the
mean time, the C28x is continually polling the MTOCIPCSTS register while waiting for the message. As
soon as the Cortex-M3 writes ‘1’ to bit 2 of the MTOCIPCSET register, bit 2 of
MTOCIPCFLG/MTOCIPCSTS also turns ‘1’, thus announcing the event to the C28x. As soon as the C28x
CPU reads a ‘1’ from the MTOCIPCSTS register, the C28x CPU should acknowledge by writing a ‘1’ to
bit 2 of the MTOCIPCACK register, which in turn, clears bit 2 of the MTOCIPCFLG/MTOCIPCSTS
register, enabling the Cortex-M3 to send another message. Because the first four channels (bits 0, 1, 2, 3)
are backed up by interrupts, both processors in the above example can use IPC interrupt 2 instead of
polling to increase performance.
A similar handshake is also used when sending data (not just event) from the Master Subsystem to the
Control Subsystem, but with two additional steps. Before setting a bit in the MTOCIPCSET register, the
Cortex-M3 should first load the MTOC Message RAM with a block of data that is to be made available to
the C28x. In the second additional step, the C28x should read the data before setting a bit in the
MTOCIPCACK register. This way, no data gets lost during multiple data transfers through a given block of
the message RAM.
The CTOM IPC is used by the Control Subsystem to send events to the Master Subsystem. The CTOM
IPC typically sends events to the Master Subsystem by using the following three registers: CTOMIPCSET,
CTOMIPCFLG/CTOMIPCSTS, and CTOMIPCACK. The process is exactly the same as that for the MTOC
IPC communication above.
(1)
Physically, MTOCIPCFLG/MTOCIPCSTS is one register, but it is referred to as the MTOCIPCFLG register when the Cortex-M3 CPU
reads it, and as the MTOCIPCSTS register when the C28x CPU reads it.
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INTRS
M3
CPU
WRDATA
(31:0)
SET(31:0)
CTOM
IPC
INT
(3:0)
NVIC
STS(3:0)
STS(31:0)
FLG(31:0)
ACK(31:0)
RDDATA
(31:0)
M3 SYSTEM BUS
M3
32 MTOC IPC CHANNELS
3
4
MTOC_CH0
MTOC_CH1
MTOC_CH2
MTOC_CH29
MTOC_CH30
MTOC_CH31
ACK
FLG
STS
SET
MTOCIPCSET REG
MTOCIPCFLG REG
MTOCIPCSTS REG
...
FLG REG
31
...
0
STS REG
31
...
0
ACK REG
0
C28
PHYSICALLY THIS IS ONE REGISTER
WITH TWO DIFFERENT NAMES – FLG
FOR THE M3 AND STS FOR THE C28
M3
1
2
SYNC HANDSHAKE
FOR ONE OF 32
MTOC CHANNELS
PHYSICALLY THIS IS ONE REGISTER
WITH TWO DIFFERENT NAMES – FLG
FOR THE C28 AND STS FOR THE M3
SYNC HANDSHAKE
FOR ONE OF 32
MTOC CHANNELS
2
1
CTOMIPCSTS REG
CTOMIPCSFLG REG
31
...
0
ACK REG
FLG REG
31
...
0
STS REG
SET REG
31
...
0
MTOCIPCACK REG
CTOM
MTOC
MTOC IPC
31
CTOM
MTOC
MTOC MSG RAM
CTOMIPCSACK REG
SET REG
CTOM IPC
CTOM MSG RAM
CTOMIPCSET REG
STS
ACK
C28
3
CTOM_CH2
CTOM_CH1
CTOM_CH0
FLG
CTOM_CH31
CTOM_CH30
CTOM_CH29
SET
4
32 CTOM IPC CHANNELS
C28 CPU BUS
RDDATA
(31:0)
ACK(31:0)
FLG(31:0)
STS(31:0)
STS(3:0)
MTOC
IPC
INT
(3:0)
INTRS
PIE
SET(31:0)
WRDATA
(31:0)
C28x
CPU
Figure 5-15. IPC
78
Specifications
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
5.10.4 External Peripheral Interface
The EPI provides a high-speed parallel bus for interfacing external peripherals and memory. EPI is
accessible from both the Master Subsystem and the Control Subsystem. EPI has several modes of
operation to enable glueless connectivity to most types of external devices. Some EPI modes of operation
conform to standard microprocessor address/data bus protocols, while others are tailored to support a
variety of fast custom interfaces, such as those communicating with field-programmable gate arrays
(FPGAs) and complex programmable logic devices (CPLDs).
The EPI peripheral can be accessed by the Cortex-M3 CPU, the Cortex-M3 DMA, the C28x CPU, and the
C28x DMA over the high-performance AHB bus. The Cortex-M3 CPU and the µDMA drive AHB bus
cycles directly through the Cortex-M3 Bus Matrix. The C28x CPU and DMA also connect to the Cortex-M3
Bus Matrix, but not directly. Before entering the Cortex-M3 Bus Matrix, the native C28x CPU and DMA bus
cycles are first converted to AHB protocol inside the MEM32-to-AHB Bus Bridge. After that, they pass
through the Frequency Gasket to reduce the bus frequency by a factor of 2 or 4. Inside the Cortex-M3 Bus
Matrix, the Cortex-M3 bus cycles may have to compete with C28x bus cycles for access to the AHB bus
on the way to the EPI peripheral. See Figure 5-16 to see how EPI interfaces to the Concerto Master
Subsystem, the Concerto Control Subsystem, Resets, Clocks, and Interrupts.
NOTE
The Control Subsystem has no direct access to EPI in silicon revision 0 devices.
Depending on how the Real-Time Window registers are configured inside the Bus Matrix, the arbitration
between the Cortex-M3 and C28x bus cycles is fixed-priority with Cortex-M3 having higher priority than
C28x, or the C28x having the option to own the Bus Matrix for a fixed period of time (window)—effectively
stalling all Cortex-M3 accesses during that time. Another EPI register inside the Cortex-M3 Bus Matrix is
the Memory Protection Register, which enables assignments of chip-select spaces to Cortex-M3 or C28x
EPI accesses (or both). The assignments of chip-select spaces prevent a bus cycle (from any processor)
that does not own a given chip-select space, from getting through to EPI. The Real-time Window registers
are the only EPI-related registers that are configurable by the C28x. The Memory Protection Register is
configurable only by the Cortex-M3 CPU, as are all configuration registers inside the EPI peripheral.
Figure 5-16 shows the EPI registers and how they relate to individual blocks within the EPI.
Once a bus cycle arrives at the AHB bus interface inside the EPI peripheral, the bus cycle is routed to the
General-Purpose Block, SDRAM Block, or the Host Bus Module, depending on the operating mode
chosen through the EPI Configuration Register. Write cycles are buffered in a 4-word-deep Write FIFO;
therefore, in most cases, the write cycles do not stall the CPU or DMA unless the Write FIFO becomes
full. Read cycles can be handled in two different ways: blocking read cycles and nonblocking read cycles.
Blocking read cycles are implemented when the content of a Read Data Register is 0. Blocking reads stall
the CPU or DMA until the bus transaction completes. Nonblocking read cycles are triggered when a nonzero value is written into a Read Data Register. A non-zero value being written into a Read Data register
triggers EPI to autonomously perform multiple data reads in the background (without involving CPU or
DMA) according to values stored inside the Read Address Register and the Read Size Register. The
incoming data is then temporarily stored in the Non-Blocking Read (NBR) FIFO until an EPI interrupt is
generated to prompt the CPU or DMA to read the FIFO without risk of stalling. Furthermore, EPI has
actually two sets of Data/Address/Size registers (set 0 and set 1) to enable ping-pong operation of
nonblocking reads. In a ping-pong operation, while the previously fetched data is being read by the CPU
or DMA from one end of the NBR FIFO, the next set of data words is simultaneously being deposited into
the other end of the NBR FIFO.
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EPI
44 PINS
EPI MUX
GENERAL-PURPOSE INTERFACE
SDRAM INTERFACE
HOST BUS INTERFACE
GP
GPIOCSEL
CONFIGREG
REG
GP
GPIOCSEL
CONFIG2REG
REG
SDRAM
GPIOCSEL
CFGREG
REG
4X32 WR FIFO
EPI INTERRUPT
INT MASK REG
GPIOCSEL
REG
HB-16
CONFIG
REG
EPI CONFIG REG
HB-8
GPIOCSEL
CONFIG2
REG
REG
GPIOCSEL
REGREG
HB-16
CONFIG2
EPI STATUS REG
8-BIT MODE
16-BIT MODE
8X32 NBR FIFO
WR FIFO CNT REG
MASK INT STAT REG
HB-8
GPIOCSEL
CONFIGREG
REG
READ FIFO ALIAS 1
READ FIFO ALIAS 2
READ FIFO CNT REG
READ FIFO ALIAS 3
RAW INT STAT REG
READ FIFO ALIAS 4
ERR INT STAT/CLR
READ FIFO ALIAS 5
FIFO LEVEL SEL REG
READ FIFO REG
READ FIFO ALIAS 6
INTERRUPT
SOURCES
READ FIFO ALIAS 7
WRITE
EPI RD SIZE0 REG
EPI RD ADDR0 REG
EPI RD DATA0 REG
EPI NONBLOCKING
ACCESS REGISTERS
EPI RD SIZE0 REG
EPI RD ADDR0 REG
EPI RD DATA1 REG
NON-FIFO READ
(BLOCKING)
FIFO READ
(NONBLOCKING)
GPIO_MUX1
EPI CLK
EPI RST
BAUD RATE CONTROL
AHB BUS INTERFACE
AHB BUS
APB BUS
EPIGPIOCSEL
ADDR MAP
REG
REG
EPI BAUD REG
MEMORY PROTECTION LOGIC ASSIGNS CS
SPACES TO C28 ONLY, M3 ONLY, OR BOTH
EPI REQ
M3SSCLK
M3SYSRST
M3 CLOCKS
RESETS
MEMPROT REG
M3
uDMA
M3 BUS
MATRIX
M3
CPU
NVIC
RTWEPICNTR REG
RTWEPIWD REG
EPI
CHAN 20
CHAN 22
CEPISTATUS REG
VECT# 69
FREQ
GASKET
MEM32 TO AHB BUS BRIDGE
CONVERTS C28 CPU/DMA BUS
CYCLES TO M3 AHB BUS CYCLES
RTWEPIREG REG
C28
DMA
MEM32
TO AHB
BUS
BRIDGE
INT12/INTx.6
REAL-TIME WINDOW MODE
ALLOWS UNINTERRUPTED ACCESS
TO EPI FROM C28 CPU/DMA, WHILE
STALLING M3 CPU/DMA CYCLES
EPI
C28
CPU
PIE
THE M3 FREQUENCY GASKET REDUCES AHB
BUS ACCESS FREQUENCY FOR C28 CPU/DMA
CYCLES BY FACTOR OF 2 OR FACTOR OF 4
Figure 5-16. EPI
80
Specifications
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
EPI can directly interrupt the Cortex-M3 CPU, the Cortex-M3 uDMA, and the C28x CPU (but not the C28x
DMA) through the EPI interrupt. Typically, EPI interrupts are used to prompt the CPU or DMA to move
data to and from EPI. There are four EPI Interrupt registers that control various facets of interrupt
generation, clearing, and masking. The EPI Interrupt can trigger µDMA to perform reads and writes
through DMA Channels 20 and 22. If a CPU is the intended recipient, the Cortex-M3 CPU is interrupted by
NVIC vector 69, and the C28x CPU is interrupted through the INT12/INTx6 vector to the PIE.
During EPI bus cycles, addresses entering the EPI module can propagate unchanged to the pins, or be
remapped to different addresses according to values stored in the EPI Address Map Register in
conjunction with the most significant bit of the incoming address.
The EPI's three primary operating modes are: the General-Purpose Mode, the SDRAM Mode, and the
Host Bus Mode (including 8-bit and 16-bit versions).
5.10.4.1 EPI General-Purpose Mode
The EPI General-Purpose Mode is designed for high-speed clocked interfaces such as ones
communicating with FPGAs and CPLDs. The high-speed clocked interfaces are different from the slower
Host Bus interfaces, which have more relaxed timings that are compatible with established protocols like
ones used to communicate with 8051 devices. Support of bus cycle framing and precisely controlled
clocking are the additional features of the General-Purpose Mode that differentiate the General-Purpose
Mode from the 8-bit and 16-bit Host Bus Modes.
Framing allows multiple bus transactions to be grouped together with an output signal called FRAME. The
slave device responding to the bus cycles may use this signal to recognize related words of data and to
speed up their transfers. The frame lengths are programmable and may vary from 1 to 30 clocks,
depending on the clocking mode used.
Precise clocking is accomplished with a dedicated clock output pin (CLK). Devices responding the bus
cycles can synchronize to CLK for faster transfers. The clock frequency can be precisely controlled
through the Baud Rate Control block. This output clock can be gated or free-running. A gated approach
uses a setup-time model in which the EPI clock controls when bus transactions are starting and stopping.
A free-running EPI clock requires another method for determining when data is live, such as the frame pin
or RD/WR strobes.
These and numerous other aspects of the General-Purpose Mode are controlled through the GeneralPurpose Configuration Register and the General-Purpose Configuration2 Register. The clocking for the
General-Purpose Mode is configured through the EPI Baud Register of the EPI Baud Rate Control block.
See Figure 5-17 for a snapshot of the General-Purpose Mode registers, modes, and features. For more
detailed maps of the General-Purpose Mode, see Table 5-39.
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EPI CONFIG REG
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GP CONFIG REG
MODE = GEN PURP
ASIZE = 3
ADDRESS
RANGE
DATA
SIZE
FRAME
SIGNAL
READY
SIGNAL
RDYEN = 1
A0 – A18
8
YES
YES
RDYEN = 0
A0 – A18
8
YES
NO
RDYEN = 1
A0 – A19
8
NO
YES
RDYEN = 0
A0 – A19
8
NO
NO
RDYEN = 1
A0 – A10
16
YES
YES
RDYEN = 0
A0 – A10
16
YES
NO
RDYEN = 1
A0 – A11
16
NO
YES
RDYEN = 0
A0 – A11
16
NO
NO
RDYEN = 1
A0 – A2
24
YES
YES
RDYEN = 0
A0 – A2
24
YES
NO
RDYEN = 1
A0 – A3
24
NO
YES
RDYEN = 0
A0 – A3
24
NO
NO
RDYEN = X
N/A
32
NO
NO
DSIZE = 0
FRMPIN = 1
FRMPIN = 0
ASIZE = 2
DSIZE = 1
FRMPIN = 1
FRMPIN = 0
ASIZE = 1
DSIZE = 2
FRMPIN = 1
FRMPIN = 0
ASIZE = 0
DSIZE = 3
FRMPIN = X
Figure 5-17. EPI General-Purpose Modes
82
Specifications
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Table 5-39. EPI MODES – General-Purpose Mode (EPICFG/MODE = 0x0)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
ACCESSIBLE BY ACCESSIBLE BY
Cortex-M3
C28x
GENERALPURPOSE
SIGNAL
(D8, A20)
GENERALPURPOSE
SIGNAL
(D16, A12)
GENERALPURPOSE
SIGNAL
(D24, A4)
GENERALPURPOSE
SIGNAL
(D30, NO ADDR)
EPI0S0
D0
D0
D0
D0
PH3_GPIO51
EPI0S1
D1
D1
D1
D1
PH2_GPIO50
EPI0S2
D2
D2
D2
D2
PC4_GPIO68
EPI0S3
D3
D3
D3
D3
PC5_GPIO69
EPI0S4
D4
D4
D4
D4
PC6_GPIO70
EPI0S5
D5
D5
D5
D5
PC7_GPIO71
EPI0S6
D6
D6
D6
D6
PH0_GPIO48
EPI0S7
D7
D7
D7
D7
PH1_GPIO49
EPI0S8
A0
D8
D8
D8
PE0_GPIO24
EPI0S9
A1
D9
D9
D9
PE1_GPIO25
EPI0S10
A2
D10
D10
D10
PH4_GPIO52
EPI0S11
A3
D11
D11
D11
PH5_GPIO53
EPI0S12
A4
D12
D12
D12
PF4_GPIO36
EPI0S13
A5
D13
D13
D13
PG0_GPIO40
EPI0S14
A6
D14
D14
D14
PG1_GPIO41
EPI0S15
A7
D15
D15
D15
PF5_GPIO37
EPI0S16
A8
A0
D16
D16
PJ0_GPIO56
EPI0S17
A9
A1
D17
D17
PJ1_GPIO57
EPI0S18
A10
A2
D18
D18
PJ2_GPIO58
EPI0S19
A11
A3
D19
D19
PD4_GPIO20
EPI0S20
A12
A4
D29
D29
PD2_GPIO18
EPI0S21
A13
A5
D21
D21
PD3_GPIO19
EPI0S22
A14
A6
D22
D22
PB5_GPIO13
EPI0S23
A15
A7
D23
D23
PB4_GPIO12
EPI0S24
A16
A8
A0
D24
PE2_GPIO26
EPI0S25
A17
A9
A1
D25
PE3_GPIO27
EPI0S26
A18
A10
A2
D26
PH6_GPIO54
EPI0S27
A19/RDY
A11/RDY
A3/RDY
D27
PH7_GPIO55
EPI0S28
WR
WR
WR
D28
PD5_GPIO21
PJ4_GPIO60
EPI0S29
RD
RD
RD
D29
PD6_GPIO22
PJ5_GPIO61
EPI0S30
FRAME
FRAME
FRAME
D30
PD7_GPIO23
PJ6_GPIO62
EPI0S31
CLK
CLK
CLK
D31
PG7_GPIO47
EPI0S32
x
x
x
x
PF2_GPIO34
PC0_GPIO64
EPI0S33
x
x
x
x
PF3_GPIO35
PC1_GPIO65
EPI0S34
x
x
x
x
PE4_GPIO28
EPI0S35
x
x
x
x
PE5_GPIO29
EPI0S36
x
x
x
x
PB7_GPIO15
PC3_GPIO67
EPI0S37
x
x
x
x
PB6_GPIO14
PC2_GPIO66
EPI0S38
x
x
x
x
PF6_GPIO38
PE4_GPIO28
EPI0S39
x
x
x
x
PG2_GPIO42
EPI0S40
x
x
x
x
PG5_GPIO45
EPI0S41
x
x
x
x
PG6_GPIO46
EPI0S42
x
x
x
x
PN6_GPIO102
EPI0S43
x
x
x
x
PN7_GPIO103
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
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5.10.4.2 EPI SDRAM Mode
The EPI SDRAM Mode combines high performance, low cost, and low pin use to access up to
512 megabits (Mb) of external memory. Main features of the EPI SDRAM interface are:
• Supports x16 (single data rate) SDRAM
• Supports low-cost SDRAMs up to 64 megabytes (MB) [or 512Mb]
• Includes automatic refresh and access to all banks, rows
• Includes Sleep/STANDBY Mode to keep contents active with minimal power drain
• Multiplexed address/data interface for reduced pin count
See Figure 5-18 for a snapshot of the SDRAM Mode registers and supported memory sizes. For more
detailed maps of the SDRAM Mode, see Table 5-40.
EPI CONFIG REG
SDRAM CFG REG
SDRAM
SIZE
DATA
SIZE
SIZE = 0
64 MBit
16
SIZE = 1
128 MBit
16
SIZE = 2
256 MBit
16
SIZE = 3
512 MBit
16
MODE = SDRAM
Figure 5-18. EPI SDRAM Mode
84
Specifications
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Table 5-40. EPI MODES – SDRAM Mode (EPICFG/MODE = 0x1)
EPI PORT NAME
ACCESSIBLE BY
Cortex-M3
ACCESSIBLE BY
C28x
EPI SIGNAL FUNCTION
DEVICE PIN
COLUMN/ROW
ADDRESS
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
DATA
EPI0S0
A0
D0
PH3_GPIO51
EPI0S1
A1
D1
PH2_GPIO50
EPI0S2
A2
D2
PC4_GPIO68
EPI0S3
A3
D3
PC5_GPIO69
EPI0S4
A4
D4
PC6_GPIO70
EPI0S5
A5
D5
PC7_GPIO71
EPI0S6
A6
D6
PH0_GPIO48
EPI0S7
A7
D7
PH1_GPIO49
EPI0S8
A8
D8
PE0_GPIO24
EPI0S9
A9
D9
PE1_GPIO25
EPI0S10
A10
D10
PH4_GPIO52
EPI0S11
A11
D11
PH5_GPIO53
EPI0S12
A12
D12
PF4_GPIO36
EPI0S13
BA0
D13
PG0_GPIO40
EPI0S14
BA1
D14
PG1_GPIO41
EPI0S15
D15
PF5_GPIO37
EPI0S16
DQML
PJ0_GPIO56
EPI0S17
DQMH
PJ1_GPIO57
EPI0S18
CAS
PJ2_GPIO58
EPI0S19
RAS
PD4_GPIO20
PJ3_GPIO59
EPI0S28
WE
PD5_GPIO21
PJ4_GPIO60
EPI0S29
CS
PD6_GPIO22
PJ5_GPIO61
EPI0S30
CKE
PD7_GPIO23
PJ6_GPIO62
EPI0S31
CLK
PG7_GPIO47
EPI0S20
x
PD2_GPIO18
EPI0S21
x
PD3_GPIO19
EPI0S22
x
PB5_GPIO13
EPI0S23
x
PB4_GPIO12
EPI0S24
x
PE2_GPIO26
EPI0S25
x
PE3_GPIO27
EPI0S26
x
PH6_GPIO54
EPI0S27
x
PH7_GPIO55
EPI0S32
x
PF2_GPIO34
PC0_GPIO64
EPI0S33
x
PF3_GPIO35
PC1_GPIO65
EPI0S34
x
PE4_GPIO28
EPI0S35
x
PE5_GPIO29
EPI0S36
x
PB7_GPIO15
PC3_GPIO67
EPI0S37
x
PB6_GPIO14
PC2_GPIO66
EPI0S38
x
PF6_GPIO38
PE4_GPIO28
EPI0S39
x
PG2_GPIO42
EPI0S40
x
PG5_GPIO45
EPI0S41
x
PG6_GPIO46
EPI0S42
x
PN6_GPIO102
EPI0S43
x
PN7_GPIO103
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Specifications
85
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
5.10.4.3 EPI Host Bus Mode
There are two versions of the EPI Host Bus Mode: an 8-bit version (HB-8) and a 16-bit version (HB-16).
Section 5.10.4.3.1 discusses the EPI 8-Bit Host Bus Mode. Section 5.10.4.3.2 discusses the EPI 16-Bit
Host Bus Mode.
5.10.4.3.1 EPI 8-Bit Host Bus (HB-8) Mode
The 8-Bit Host Bus (HB-8) Mode uses fewer data pins than the 16-Bit Host Bus (HB-16) Mode; hence,
more pins are available for address. The HB-8 Mode is also slower than the General-Purpose Mode in
order to accommodate older logic. The HB-8 Mode is selected with the MODE field of EPI Configuration
Register. Within the HB-8 Mode, two additional registers are used to select address/data muxing, chip
selects, and other options. These registers are the HB-8 Configuration Register and the HB-8
Configuration2 Register. See Figure 5-19 for a snapshot of HB-8 registers, modes, and features.
EPI CONFIG REG
HP8 CONFIG REG
HB8 CONFIG2 REG
MODE = HB-8
MODE = MUXED
ADDRESS
RANGE
DATA
SIZE
READY
SIGNAL
CSCFG = ALE
A0 – A27
8
NO
CSCFG = 1 CS
A0 – A27
8
NO
CSCFG = 2 CS
A0 – A26
8
NO
CSCFG = ALE + 2 CS
A0 – A25
8
NO
MODE = NOMUX
CSCFG = ALE
A0 – A19
8
NO
CSCFG = 1 CS
A0 – A19
8
NO
CSCFG = 2 CS
A0 – A18
8
NO
CSCFG = ALE + 2 CS
A0 – A17
8
NO
CSCFG = 2 CS
N/A
8
NO
CSCFG = ALE + 2 CS
N/A
8
NO
MODE = FIFO
Figure 5-19. EPI 8-Bit Host Bus Mode
5.10.4.3.1.1 HB-8 Muxed Address/Data Mode
The HB-8 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the
Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-8 Muxed
Mode is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address
signals, the HB-8 Muxed Mode also features the ALE signal (indicating to an external latch to capture
address and hold the address until the data phase); RD and WR data strobes; and 1–4 CS (chip select)
signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG
field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Muxed Mode, see Table 541.
86
Specifications
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www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 5-41. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
Muxed (EPIHB16CFG/MODE = 0x0)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
ACCESSIBLE BY ACCESSIBLE BY
Cortex-M3
C28x
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
EPI0S0
AD0
AD0
AD0
AD0
PH3_GPIO51
EPI0S1
AD1
AD1
AD1
AD1
PH2_GPIO50
EPI0S2
AD2
AD2
AD2
AD2
PC4_GPIO68
EPI0S3
AD3
AD3
AD3
AD3
PC5_GPIO69
EPI0S4
AD4
AD4
AD4
AD4
PC6_GPIO70
EPI0S5
AD5
AD5
AD5
AD5
PC7_GPIO71
EPI0S6
AD6
AD6
AD6
AD6
PH0_GPIO48
EPI0S7
AD7
AD7
AD7
AD7
PH1_GPIO49
EPI0S8
A8
A8
A8
A8
PE0_GPIO24
EPI0S9
A9
A9
A9
A9
PE1_GPIO25
EPI0S10
A10
A10
A10
A10
PH4_GPIO52
EPI0S11
A11
A11
A11
A11
PH5_GPIO53
EPI0S12
A12
A12
A12
A12
PF4_GPIO36
EPI0S13
A13
A13
A13
A13
PG0_GPIO40
EPI0S14
A14
A14
A14
A14
PG1_GPIO41
EPI0S15
A15
A15
A15
A15
PF5_GPIO37
EPI0S16
A16
A16
A16
A16
PJ0_GPIO56
EPI0S17
A17
A17
A17
A17
PJ1_GPIO57
EPI0S18
A18
A18
A18
A18
PJ2_GPIO58
EPI0S19
A19
A19
A19
A19
PD4_GPIO20
EPI0S20
A20
A20
A20
A20
PD2_GPIO18
EPI0S21
A21
A21
A21
A21
PD3_GPIO19
EPI0S22
A22
A22
A22
A22
PB5_GPIO13
EPI0S23
A23
A23
A23
A23
PB4_GPIO12
EPI0S24
A24
A24
A24
A24
PE2_GPIO26
EPI0S25
A25
A25
A25
A25
PE3_GPIO27
EPI0S26
A26
A26
A26
CS0
PH6_GPIO54
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
PJ3_GPIO59
EPI0S27
A27
A27
CS1
CS1
PH7_GPIO55
EPI0S30
ALE
CS0
CS0
ALE
PD7_GPIO23
PJ6_GPIO62
EPI0S29
WR
WR
WR
WR
PD6_GPIO22
PJ5_GPIO61
EPI0S28
RD
RD
RD
RD
PD5_GPIO21
PJ4_GPIO60
EPI0S31
x
x
x
x
PG7_GPIO47
EPI0S32
x
x
x
x
PF2_GPIO34
PC0_GPIO64
EPI0S33
x
x
x
x
PF3_GPIO35
PC1_GPIO65
EPI0S34
x
x
x
x
PE4_GPIO28
EPI0S35
x
x
x
x
PE5_GPIO29
EPI0S36
x
x
x
x
PB7_GPIO15
PC3_GPIO67
EPI0S37
x
x
x
x
PB6_GPIO14
PC2_GPIO66
EPI0S38
x
x
x
x
PF6_GPIO38
PE4_GPIO28
EPI0S39
x
x
x
x
PG2_GPIO42
EPI0S40
x
x
x
x
PG5_GPIO45
EPI0S41
x
x
x
x
PG6_GPIO46
EPI0S42
x
x
x
x
PN6_GPIO102
EPI0S43
x
x
x
x
PN7_GPIO103
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5.10.4.3.1.2 HB-8 Non-Muxed Address/Data Mode
The HB-8 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the NonMuxed Mode has reduced address reach as compared to the Muxed Mode. The HB-8 Non-Muxed Mode
is selected with the MODE field of the HB-8 Configuration Register. In addition to data and address
signals, the HB-8 Non-Muxed Mode also features the ALE signal (indicating to an external latch to capture
address and hold the address until the data phase); RD and WR data strobes; and 1–4 CS (chip select)
signals to enable one of four external peripherals. The ALE and CS options are chosen with the CSCFG
field of the HB-8 Configuration2 Register. For more detailed maps of the HB-8 Non-Muxed Mode, see
Table 5-42.
Table 5-42. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
Non-Muxed (EPIHB16CFG/MODE = 0x1)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
ACCESSIBLE BY ACCESSIBLE BY
Cortex-M3
C28x
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
EPI0S0
D0
D0
D0
D0
PH3_GPIO51
EPI0S1
D1
D1
D1
D1
PH2_GPIO50
EPI0S2
D2
D2
D2
D2
PC4_GPIO68
EPI0S3
D3
D3
D3
D3
PC5_GPIO69
EPI0S4
D4
D4
D4
D4
PC6_GPIO70
EPI0S5
D5
D5
D5
D5
PC7_GPIO71
EPI0S6
D6
D6
D6
D6
PH0_GPIO48
EPI0S7
D7
D7
D7
D7
PH1_GPIO49
EPI0S8
A0
A0
A0
A0
PE0_GPIO24
EPI0S9
A1
A1
A1
A1
PE1_GPIO25
EPI0S10
A2
A2
A2
A2
PH4_GPIO52
EPI0S11
A3
A3
A3
A3
PH5_GPIO53
EPI0S12
A4
A4
A4
A4
PF4_GPIO36
EPI0S13
A5
A5
A5
A5
PG0_GPIO40
EPI0S14
A6
A6
A6
A6
PG1_GPIO41
EPI0S15
A7
A7
A7
A7
PF5_GPIO37
EPI0S16
A8
A8
A8
A8
PJ0_GPIO56
EPI0S17
A9
A9
A9
A9
PJ1_GPIO57
EPI0S18
A10
A10
A10
A10
PJ2_GPIO58
EPI0S19
A11
A11
A11
A11
PD4_GPIO20
EPI0S20
A12
A12
A12
A12
PD2_GPIO18
EPI0S21
A13
A13
A13
A13
PD3_GPIO19
EPI0S22
A14
A14
A14
A14
PB5_GPIO13
EPI0S23
A15
A15
A15
A15
PB4_GPIO12
EPI0S24
A16
A16
A16
A16
PE2_GPIO26
EPI0S25
A17
A17
A17
A17
PE3_GPIO27
EPI0S26
A18
A18
A18
CS0
PH6_GPIO54
88
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
PJ3_GPIO59
EPI0S27
A19
A19
CS1
CS1
PH7_GPIO55
EPI0S30
ALE
CS0
CS0
ALE
PD7_GPIO23
PJ6_GPIO62
EPI0S29
WR
WR
WR
WR
PD6_GPIO22
PJ5_GPIO61
EPI0S28
RD
RD
RD
RD
PD5_GPIO21
PJ4_GPIO60
EPI0S31
x
x
x
x
PG7_GPIO47
EPI0S32
x
x
x
x
PF2_GPIO34
PC0_GPIO64
EPI0S33
x
x
x
x
PF3_GPIO35
PC1_GPIO65
Specifications
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 5-42. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
Non-Muxed (EPIHB16CFG/MODE = 0x1) (continued)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
ACCESSIBLE BY ACCESSIBLE BY
Cortex-M3
C28x
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
EPI0S34
x
x
x
x
PE4_GPIO28
EPI0S35
x
x
x
x
PE5_GPIO29
EPI0S36
x
x
x
x
PB7_GPIO15
PC3_GPIO67
EPI0S37
x
x
x
x
PB6_GPIO14
PC2_GPIO66
EPI0S38
x
x
x
x
PF6_GPIO38
PE4_GPIO28
EPI0S39
x
x
x
x
PG2_GPIO42
EPI0S40
x
x
x
x
PG5_GPIO45
EPI0S41
x
x
x
x
PG6_GPIO46
EPI0S42
x
x
x
x
PN6_GPIO102
EPI0S43
x
x
x
x
PN7_GPIO103
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
5.10.4.3.1.3 HB-8 FIFO Mode
The HB-8 FIFO Mode uses 8 bits of data, removes ALE and address pins, and optionally adds external
FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication
devices (including USB2 devices), and some FPGA configuration (FIFO through block RAM). This FIFO
Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is
important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can
potentially block other CPU or DMA accesses. For more detailed maps of the HB-8 FIFO Mode, see
Table 5-43.
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F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 5-43. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),
FIFO Mode (EPIHB16CFG/MODE = 0x3)
EPI PORT NAME
DEVICE PIN
WITH TWO
CHIP SELECTS
(CSCFG = 0x2)
EPI0S0
D0
D0
PH3_GPIO51
EPI0S1
D1
D1
PH2_GPIO50
EPI0S2
D2
D2
PC4_GPIO68
EPI0S3
D3
D3
PC5_GPIO69
EPI0S4
D4
D4
PC6_GPIO70
EPI0S5
D5
D5
PC7_GPIO71
EPI0S6
D6
D6
PH0_GPIO48
EPI0S7
D7
D7
PH1_GPIO49
EPI0S25
x
CS1
PE3_GPIO27
EPI0S30
CS0
CS0
PD7_GPIO23
EPI0S27
FFULL
FFULL
PH7_GPIO55
EPI0S26
FEMPTY
FEMPTY
PH6_GPIO54
EPI0S29
WR
WR
PD6_GPIO22
PJ5_GPIO61
EPI0S28
RD
RD
PD5_GPIO21
PJ4_GPIO60
EPI0S8
x
x
PE0_GPIO24
EPI0S9
x
x
PE1_GPIO25
EPI0S10
x
x
PH4_GPIO52
EPI0S11
x
x
PH5_GPIO53
EPI0S12
x
x
PF4_GPIO36
EPI0S13
x
x
PG0_GPIO40
EPI0S14
x
x
PG1_GPIO41
EPI0S15
x
x
PF5_GPIO37
EPI0S16
x
x
PJ0_GPIO56
EPI0S17
x
x
PJ1_GPIO57
EPI0S18
x
x
PJ2_GPIO58
EPI0S19
x
x
PD4_GPIO20
EPI0S20
x
x
PD2_GPIO18
EPI0S21
x
x
PD3_GPIO19
EPI0S22
x
x
PB5_GPIO13
EPI0S23
x
x
PB4_GPIO12
EPI0S24
x
x
PE2_GPIO26
EPI0S32
x
x
PF2_GPIO34
EPI0S31
x
x
PG7_GPIO47
EPI0S33
x
x
PF3_GPIO35
EPI0S34
x
x
PE4_GPIO28
EPI0S35
x
x
PE5_GPIO29
EPI0S36
x
x
PB7_GPIO15
PC3_GPIO67
EPI0S37
x
x
PB6_GPIO14
PC2_GPIO66
EPI0S38
x
x
PF6_GPIO38
PE4_GPIO28
EPI0S39
x
x
PG2_GPIO42
EPI0S40
x
x
PG5_GPIO45
EPI0S41
x
x
PG6_GPIO46
EPI0S42
x
x
PN6_GPIO102
EPI0S43
x
x
PN7_GPIO103
ACCESSIBLE BY
Cortex-M3
90
EPI SIGNAL FUNCTION
WITH ONE
CHIP SELECT
(CSCFG = 0x1)
ACCESSIBLE BY
C28x
Specifications
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
PJ6_GPIO62
PJ3_GPIO59
PC0_GPIO64
PC1_GPIO65
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F28M36H53B2, F28M36H33B2
www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
5.10.4.3.2 EPI 16-Bit Host Bus (HB-16) Mode
The 16-Bit Host Bus (HB-16) Mode uses fewer address pins than the 8-Bit Host Bus (HB-8) Mode; hence,
more pins are available for data. The HB-16 Mode is also slower than the General-Purpose Mode in order
to accommodate older logic. The HB-16 Mode is selected with the MODE field of EPI Configuration
Register. Within the HB-16 Mode, two additional registers are used to select address/data muxing, byte
selects, chip selects, and other options. These registers are the HB-16 Configuration Register and the
HB-16 Configuration2 Register. See Figure 5-20 for a snapshot of HB-16 registers, modes, and features.
EPI CONFIG REG
HP16 CONFIG REG
HB16 CONFIG2 REG
MODE = HB-16
ADDRESS
RANGE
DATA
SIZE
READY
SIGNAL
CSCFG = ALE
A0 – A25
16
NO
CSCFG = 1 CS
A0 – A25
16
NO
CSCFG = 2 CS
A0 – A24
16
NO
CSCFG = ALE + 2 CS
A0 – A23
16
NO
MODE = MUXED
BSEL = YES
BSEL = NO
CSCFG = ALE
A0 – A27
16
NO
CSCFG = 1 CS
A0 – A27
16
NO
CSCFG = 2 CS
A0 – A26
16
NO
CSCFG = ALE + 2 CS
A0 – A25
16
NO
MODE = NOMUX
BSEL = YES
CSCFG = ALE
A0 – A9
16
NO
CSCFG = 1 CS
A0 – A9
16
YES
CSCFG = 2 CS
A0 – A8
16
YES
CSCFG = ALE + 2 CS
A0 – A7
16
YES
CSCFG = 3 CS
A0 – A18
16
YES
CSCFG = 4 CS
A0 – A16
16
YES
BSEL = NO
CSCFG = ALE
A0 – A11
16
NO
CSCFG = 1 CS
A0 – A11
16
YES
CSCFG = 2 CS
A0 – A10
16
YES
CSCFG = ALE + 2 CS
A0 – A9
16
YES
CSCFG = 3 CS
A0 – A20
16
YES
CSCFG = 4 CS
A0 – A18
16
YES
CSCFG = 2 CS
N/A
16
NO
CSCFG = ALE + 2 CS
N/A
16
NO
MODE = FIFO
BSEL = DON’T CARE
Figure 5-20. EPI 16-Bit Host Bus Mode
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F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
5.10.4.3.2.1 HB-16 Muxed Address/Data Mode
The HB-16 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the
Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-16 Muxed
Mode is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address
signals, the HB-16 Muxed Mode also features the ALE signal (indicating to an external latch to capture
address and hold the address until the data phase); RD and WR data strobes; 1–4 CS (chip select)
signals to enable one of four external peripherals; and two BSEL (byte select) signals to accommodate
byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the BSEL field of the
HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG field of the HB-16
Configuration2 Register. For more detailed maps of the HB-16 Muxed Mode without Byte Selects, see
Table 5-44. For more detailed maps of the HB-16 Muxed Mode with Byte Selects, see Table 5-45.
Table 5-44. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
ACCESSIBLE BY ACCESSIBLE BY
Cortex-M3
C28x
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
EPI0S0
AD0
AD0
AD0
AD0
PH3_GPIO51
EPI0S1
AD1
AD1
AD1
AD1
PH2_GPIO50
EPI0S2
AD2
AD2
AD2
AD2
PC4_GPIO68
EPI0S3
AD3
AD3
AD3
AD3
PC5_GPIO69
EPI0S4
AD4
AD4
AD4
AD4
PC6_GPIO70
EPI0S5
AD5
AD5
AD5
AD5
PC7_GPIO71
EPI0S6
AD6
AD6
AD6
AD6
PH0_GPIO48
EPI0S7
AD7
AD7
AD7
AD7
PH1_GPIO49
EPI0S8
AD8
AD8
AD8
AD8
PE0_GPIO24
EPI0S9
AD9
AD9
AD9
AD9
PE1_GPIO25
EPI0S10
AD10
AD10
AD10
AD10
PH4_GPIO52
EPI0S11
AD11
AD11
AD11
AD11
PH5_GPIO53
EPI0S12
AD12
AD12
AD12
AD12
PF4_GPIO36
EPI0S13
AD13
AD13
AD13
AD13
PG0_GPIO40
EPI0S14
AD14
AD14
AD14
AD14
PG1_GPIO41
EPI0S15
AD15
AD15
AD15
AD15
PF5_GPIO37
EPI0S16
A16
A16
A16
A16
PJ0_GPIO56
EPI0S17
A17
A17
A17
A17
PJ1_GPIO57
EPI0S18
A18
A18
A18
A18
PJ2_GPIO58
EPI0S19
A19
A19
A19
A19
PD4_GPIO20
EPI0S20
A20
A20
A20
A20
PD2_GPIO18
EPI0S21
A21
A21
A21
A21
PD3_GPIO19
EPI0S22
A22
A22
A22
A22
PB5_GPIO13
EPI0S23
A23
A23
A23
A23
PB4_GPIO12
EPI0S24
A24
A24
A24
A24
PE2_GPIO26
EPI0S25
A25
A25
A25
A25
PE3_GPIO27
EPI0S26
A26
A26
A26
CS0
PH6_GPIO54
92
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
PJ3_GPIO59
EPI0S27
A27
A27
CS1
CS1
PH7_GPIO55
EPI0S30
ALE
CS0
CS0
ALE
PD7_GPIO23
PJ6_GPIO62
EPI0S29
WR
WR
WR
WR
PD6_GPIO22
PJ5_GPIO61
EPI0S28
RD
RD
RD
RD
PD5_GPIO21
PJ4_GPIO60
Specifications
Copyright © 2012–2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 5-44. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3) (continued)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
ACCESSIBLE BY ACCESSIBLE BY
Cortex-M3
C28x
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
EPI0S31
x
x
x
x
PG7_GPIO47
EPI0S32
x
x
x
x
PF2_GPIO34
PC0_GPIO64
EPI0S33
x
x
x
x
PF3_GPIO35
PC1_GPIO65
EPI0S34
x
x
x
x
PE4_GPIO28
EPI0S35
x
x
x
x
PE5_GPIO29
EPI0S36
x
x
x
x
PB7_GPIO15
PC3_GPIO67
EPI0S37
x
x
x
x
PB6_GPIO14
PC2_GPIO66
EPI0S38
x
x
x
x
PF6_GPIO38
PE4_GPIO28
EPI0S39
x
x
x
x
PG2_GPIO42
EPI0S40
x
x
x
x
PG5_GPIO45
EPI0S41
x
x
x
x
PG6_GPIO46
EPI0S42
x
x
x
x
PN6_GPIO102
EPI0S43
x
x
x
x
PN7_GPIO103
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
Table 5-45. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
ACCESSIBLE BY ACCESSIBLE BY
Cortex-M3
C28x
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
EPI0S0
AD0
AD0
AD0
AD0
PH3_GPIO51
EPI0S1
AD1
AD1
AD1
AD1
PH2_GPIO50
EPI0S2
AD2
AD2
AD2
AD2
PC4_GPIO68
EPI0S3
AD3
AD3
AD3
AD3
PC5_GPIO69
EPI0S4
AD4
AD4
AD4
AD4
PC6_GPIO70
EPI0S5
AD5
AD5
AD5
AD5
PC7_GPIO71
EPI0S6
AD6
AD6
AD6
AD6
PH0_GPIO48
EPI0S7
AD7
AD7
AD7
AD7
PH1_GPIO49
EPI0S8
AD8
AD8
AD8
AD8
PE0_GPIO24
EPI0S9
AD9
AD9
AD9
AD9
PE1_GPIO25
EPI0S10
AD10
AD10
AD10
AD10
PH4_GPIO52
EPI0S11
AD11
AD11
AD11
AD11
PH5_GPIO53
EPI0S12
AD12
AD12
AD12
AD12
PF4_GPIO36
EPI0S13
AD13
AD13
AD13
AD13
PG0_GPIO40
EPI0S14
AD14
AD14
AD14
AD14
PG1_GPIO41
EPI0S15
AD15
AD15
AD15
AD15
PF5_GPIO37
EPI0S16
A16
A16
A16
A16
PJ0_GPIO56
EPI0S17
A17
A17
A17
A17
PJ1_GPIO57
EPI0S18
A18
A18
A18
A18
PJ2_GPIO58
EPI0S19
A19
A19
A19
A19
PD4_GPIO20
EPI0S20
A20
A20
A20
A20
PD2_GPIO18
EPI0S21
A21
A21
A21
A21
PD3_GPIO19
EPI0S22
A22
A22
A22
A22
PB5_GPIO13
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
Copyright © 2012–2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2
PJ3_GPIO59
Specifications
93
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 5-45. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3) (continued)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
ACCESSIBLE BY ACCESSIBLE BY
Cortex-M3
C28x
WITH
ADDRESS
LATCH ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
EPI0S23
A23
A23
A23
A23
PB4_GPIO12
EPI0S24
A24
A24
A24
BSEL0
PE2_GPIO26
EPI0S25
A25
A25
BSEL0
BSEL1
PE3_GPIO27
EPI0S26
BSEL0
BSEL0
BSEL1
CS0
PH6_GPIO54
EPI0S27
BSEL1
BSEL1
CS1
CS1
PH7_GPIO55
EPI0S30
ALE
CS0
CS0
ALE
PD7_GPIO23
PJ6_GPIO62
EPI0S29
WR
WR
WR
WR
PD6_GPIO22
PJ5_GPIO61
EPI0S28
RD
RD
RD
RD
PD5_GPIO21
PJ4_GPIO60
EPI0S31
x
x
x
x
PG7_GPIO47
EPI0S32
x
x
x
x
PF2_GPIO34
PC0_GPIO64
EPI0S33
x
x
x
x
PF3_GPIO35
PC1_GPIO65
EPI0S34
x
x
x
x
PE4_GPIO28
EPI0S35
x
x
x
x
PE5_GPIO29
EPI0S36
x
x
x
x
PB7_GPIO15
PC3_GPIO67
EPI0S37
x
x
x
x
PB6_GPIO14
PC2_GPIO66
EPI0S38
x
x
x
x
PF6_GPIO38
PE4_GPIO28
EPI0S39
x
x
x
x
PG2_GPIO42
EPI0S40
x
x
x
x
PG5_GPIO45
EPI0S41
x
x
x
x
PG6_GPIO46
EPI0S42
x
x
x
x
PN6_GPIO102
EPI0S43
x
x
x
x
PN7_GPIO103
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
5.10.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
The HB-16 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the NonMuxed Mode has reduced address reach as compared to the Muxed Mode. The HB-16 Non-Muxed Mode
is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address
signals, the HB-16 Non-Muxed Mode also features the ALE signal (indicating to an external latch to
capture address and hold the address until the data phase); RD and WR data strobes; 1–4 CS (chip
select) signals to enable one of four external peripherals; and two BSEL (byte select) signals to
accommodate byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the
BSEL field of the HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG
field of the HB-16 Configuration2 Register. For Non-Muxed bus cycles, most of the CSCFG modes also
support a RDY signal. The RDY input to EPI is used by an external peripheral to extend bus cycles when
the peripheral needs more time to complete reading or writing of data. While most EPI modes use up to
32 pins, the Non-Muxed CSCFG modes with 3 and 4 Chip Selects use 12 additional pins to extend the
address reach and the number of CS signals. For detailed maps of HB-16 Non-Muxed Modes without
Byte Selects, see Table 5-46 and Table 5-47. For detailed maps of HB-16 Non-Muxed Modes with Byte
Selects, see Table 5-48 and Table 5-49.
94
Specifications
Copyright © 2012–2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 5-46. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH
ADDRESS LATCH
ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
EPI0S0
D0
D0
D0
D0
PH3_GPIO51
EPI0S1
D1
D1
D1
D1
PH2_GPIO50
EPI0S2
D2
D2
D2
D2
PC4_GPIO68
EPI0S3
D3
D3
D3
D3
PC5_GPIO69
EPI0S4
D4
D4
D4
D4
PC6_GPIO70
EPI0S5
D5
D5
D5
D5
PC7_GPIO71
EPI0S6
D6
D6
D6
D6
PH0_GPIO48
EPI0S7
D7
D7
D7
D7
PH1_GPIO49
EPI0S8
D8
D8
D8
D8
PE0_GPIO24
EPI0S9
D9
D9
D9
D9
PE1_GPIO25
EPI0S10
D10
D10
D10
D10
PH4_GPIO52
EPI0S11
D11
D11
D11
D11
PH5_GPIO53
EPI0S12
D12
D12
D12
D12
PF4_GPIO36
EPI0S13
D13
D13
D13
D13
PG0_GPIO40
EPI0S14
D14
D14
D14
D14
PG1_GPIO41
EPI0S15
D15
D15
D15
D15
PF5_GPIO37
EPI0S16
A0
A0
A0
A0
PJ0_GPIO56
EPI0S17
A1
A1
A1
A1
PJ1_GPIO57
EPI0S18
A2
A2
A2
A2
PJ2_GPIO58
EPI0S19
A3
A3
A3
A3
PD4_GPIO20
EPI0S20
A4
A4
A4
A4
PD2_GPIO18
EPI0S21
A5
A5
A5
A5
PD3_GPIO19
EPI0S22
A6
A6
A6
A6
PB5_GPIO13
EPI0S23
A7
A7
A7
A7
PB4_GPIO12
EPI0S24
A8
A8
A8
A8
PE2_GPIO26
EPI0S25
A9
A9
A9
A9
PE3_GPIO27
EPI0S26
A10
A10
A10
CS0
PH6_GPIO54
ACCESSIBLE BY
Cortex-M3
ACCESSIBLE BY
C28x
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
PJ3_GPIO59
EPI0S27
A11
A11
CS1
CS1
PH7_GPIO55
EPI0S30
ALE
CS0
CS0
ALE
PD7_GPIO23
PJ6_GPIO62
EPI0S29
WR
WR
WR
WR
PD6_GPIO22
PJ5_GPIO61
EPI0S28
RD
RD
RD
RD
PD5_GPIO21
PJ4_GPIO60
EPI0S32
x
RDY
RDY
RDY
PF2_GPIO34
PC0_GPIO64
EPI0S31
x
x
x
x
PG7_GPIO47
EPI0S33
x
x
x
x
PF3_GPIO35
EPI0S34
x
x
x
x
PE4_GPIO28
EPI0S35
x
x
x
x
PE5_GPIO29
EPI0S36
x
x
x
x
PB7_GPIO15
PC3_GPIO67
EPI0S37
x
x
x
x
PB6_GPIO14
PC2_GPIO66
EPI0S38
x
x
x
x
PF6_GPIO38
PE4_GPIO28
EPI0S39
x
x
x
x
PG2_GPIO42
EPI0S40
x
x
x
x
PG5_GPIO45
EPI0S41
x
x
x
x
PG6_GPIO46
EPI0S42
x
x
x
x
PN6_GPIO102
EPI0S43
x
x
x
x
PN7_GPIO103
Copyright © 2012–2020, Texas Instruments Incorporated
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Product Folder Links: F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2
PC1_GPIO65
Specifications
95
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 5-47. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE=0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7)
EPI PORT NAME
ACCESSIBLE
BY
Cortex-M3
96
ACCESSIBLE
BY
C28x
EPI SIGNAL
FUNCTION
WITH
THREE
CHIP SELECTS
(CSCFG = 0x7)
DEVICE PIN
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
EPI PORT NAME
ACCESSIBLE
BY
Cortex-M3
ACCESSIBLE
BY
C28x
EPI SIGNAL
FUNCTION
DEVICE PIN
WITH
FOUR
CHIP SELECTS
(CSCFG = 0x5)
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
EPI0S0
D0
PH3_GPIO51
EPI0S0
D0
PH3_GPIO51
EPI0S1
D1
PH2_GPIO50
EPI0S1
D1
PH2_GPIO50
EPI0S2
D2
PC4_GPIO68
EPI0S2
D2
PC4_GPIO68
EPI0S3
D3
PC5_GPIO69
EPI0S3
D3
PC5_GPIO69
EPI0S4
D4
PC6_GPIO70
EPI0S4
D4
PC6_GPIO70
EPI0S5
D5
PC7_GPIO71
EPI0S5
D5
PC7_GPIO71
EPI0S6
D6
PH0_GPIO48
EPI0S6
D6
PH0_GPIO48
EPI0S7
D7
PH1_GPIO49
EPI0S7
D7
PH1_GPIO49
EPI0S8
D8
PE0_GPIO24
EPI0S8
D8
PE0_GPIO24
EPI0S9
D9
PE1_GPIO25
EPI0S9
D9
PE1_GPIO25
EPI0S10
D10
PH4_GPIO52
EPI0S10
D10
PH4_GPIO52
EPI0S11
D11
PH5_GPIO53
EPI0S11
D11
PH5_GPIO53
EPI0S12
D12
PF4_GPIO36
EPI0S12
D12
PF4_GPIO36
EPI0S13
D13
PG0_GPIO40
EPI0S13
D13
PG0_GPIO40
EPI0S14
D14
PG1_GPIO41
EPI0S14
D14
PG1_GPIO41
EPI0S15
D15
PF5_GPIO37
EPI0S15
D15
PF5_GPIO37
EPI0S16
A0
PJ0_GPIO56
EPI0S16
A0
PJ0_GPIO56
EPI0S17
A1
PJ1_GPIO57
EPI0S17
A1
PJ1_GPIO57
EPI0S18
A2
PJ2_GPIO58
EPI0S18
A2
PJ2_GPIO58
EPI0S19
A3
PD4_GPIO20
EPI0S19
A3
PD4_GPIO20
EPI0S20
A4
PD2_GPIO18
EPI0S20
A4
PD2_GPIO18
EPI0S21
A5
PD3_GPIO19
EPI0S21
A5
PD3_GPIO19
EPI0S22
A6
PB5_GPIO13
EPI0S22
A6
PB5_GPIO13
EPI0S23
A7
PB4_GPIO12
EPI0S23
A7
PB4_GPIO12
EPI0S24
A8
PE2_GPIO26
EPI0S24
A8
PE2_GPIO26
EPI0S25
A9
PE3_GPIO27
EPI0S25
A9
PE3_GPIO27
EPI0S26
A10
PH6_GPIO54
EPI0S26
A10
PH6_GPIO54
EPI0S36
A11
PB7_GPIO15
PC3_GPIO67
EPI0S36
A11
PB7_GPIO15
PC3_GPIO67
EPI0S37
A12
PB6_GPIO14
PC2_GPIO66
EPI0S37
A12
PB6_GPIO14
PC2_GPIO66
EPI0S38
A13
PF6_GPIO38
PE4_GPIO28
EPI0S38
A13
PF6_GPIO38
PE4_GPIO28
EPI0S39
A14
PG2_GPIO42
EPI0S39
A14
PG2_GPIO42
EPI0S27
A15
PH7_GPIO55
EPI0S40
A15
PG5_GPIO45
EPI0S35
A16
PE5_GPIO29
EPI0S41
A16
PG6_GPIO46
EPI0S40
A17
PG5_GPIO45
EPI0S42
A17
PN6_GPIO102
EPI0S41
A18
PG6_GPIO46
EPI0S43
A18
PN7_GPIO103
EPI0S42
A19
PN6_GPIO102
EPI0S30
CS0
PD7_GPIO23
EPI0S43
A20
PN7_GPIO103
EPI0S27
CS1
PH7_GPIO55
EPI0S30
CS0
PD7_GPIO23
EPI0S34
CS2
PE4_GPIO28
EPI0S34
CS2
PE4_GPIO28
EPI0S33
CS3
PF3_GPIO35
PC1_GPIO65
EPI0S33
CS3
PF3_GPIO35
PC1_GPIO65
EPI0S29
WR
PD6_GPIO22
PJ5_GPIO61
EPI0S29
WR
PD6_GPIO22
PJ5_GPIO61
EPI0S28
RD
PD5_GPIO21
PJ4_GPIO60
EPI0S28
RD
PD5_GPIO21
PJ4_GPIO60
EPI0S32
RDY
PF2_GPIO34
PC0_GPIO64
EPI0S32
RDY
PF2_GPIO34
PC0_GPIO64
EPI0S31
x
PG7_GPIO47
EPI0S31
x
PG7_GPIO47
EPI0S35
x
PE5_GPIO29
Specifications
PJ3_GPIO59
PJ6_GPIO62
PJ3_GPIO59
PJ6_GPIO62
Copyright © 2012–2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 5-48. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH
ADDRESS LATCH
ENABLE
(CSCFG = 0x0)
WITH
ONE
CHIP SELECT
(CSCFG = 0x1)
WITH
TWO
CHIP SELECTS
(CSCFG = 0x2)
WITH
ALE AND TWO
CHIP SELECTS
(CSCFG = 0x3)
EPI0S0
D0
D0
D0
D0
PH3_GPIO51
EPI0S1
D1
D1
D1
D1
PH2_GPIO50
EPI0S2
D2
D2
D2
D2
PC4_GPIO68
EPI0S3
D3
D3
D3
D3
PC5_GPIO69
EPI0S4
D4
D4
D4
D4
PC6_GPIO70
EPI0S5
D5
D5
D5
D5
PC7_GPIO71
EPI0S6
D6
D6
D6
D6
PH0_GPIO48
EPI0S7
D7
D7
D7
D7
PH1_GPIO49
EPI0S8
D8
D8
D8
D8
PE0_GPIO24
EPI0S9
D9
D9
D9
D9
PE1_GPIO25
EPI0S10
D10
D10
D10
D10
PH4_GPIO52
EPI0S11
D11
D11
D11
D11
PH5_GPIO53
EPI0S12
D12
D12
D12
D12
PF4_GPIO36
EPI0S13
D13
D13
D13
D13
PG0_GPIO40
EPI0S14
D14
D14
D14
D14
PG1_GPIO41
EPI0S15
D15
D15
D15
D15
PF5_GPIO37
EPI0S16
A0
A0
A0
A0
PJ0_GPIO56
EPI0S17
A1
A1
A1
A1
PJ1_GPIO57
EPI0S18
A2
A2
A2
A2
PJ2_GPIO58
EPI0S19
A3
A3
A3
A3
PD4_GPIO20
EPI0S20
A4
A4
A4
A4
PD2_GPIO18
EPI0S21
A5
A5
A5
A5
PD3_GPIO19
EPI0S22
A6
A6
A6
A6
PB5_GPIO13
EPI0S23
A7
A7
A7
A7
PB4_GPIO12
EPI0S24
A8
A8
A8
BSEL0
PE2_GPIO26
EPI0S25
A9
A9
BSEL0
BSEL1
PE3_GPIO27
EPI0S26
BSEL0
BSEL0
BSEL1
CS0
PH6_GPIO54
EPI0S27
BSEL1
BSEL1
CS1
CS1
PH7_GPIO55
EPI0S30
ALE
CS0
CS0
ALE
PD7_GPIO23
PJ6_GPIO62
EPI0S29
WR
WR
WR
WR
PD6_GPIO22
PJ5_GPIO61
EPI0S28
RD
RD
RD
RD
PD5_GPIO21
PJ4_GPIO60
EPI0S32
x
RDY
RDY
RDY
PF2_GPIO34
PC0_GPIO64
EPI0S31
x
x
x
x
PG7_GPIO47
EPI0S33
x
x
x
x
PF3_GPIO35
EPI0S34
x
x
x
x
PE4_GPIO28
EPI0S35
x
x
x
x
PE5_GPIO29
EPI0S36
x
x
x
x
PB7_GPIO15
PC3_GPIO67
EPI0S37
x
x
x
x
PB6_GPIO14
PC2_GPIO66
EPI0S38
x
x
x
x
PF6_GPIO38
PE4_GPIO28
EPI0S39
x
x
x
x
PG2_GPIO42
EPI0S40
x
x
x
x
PG5_GPIO45
EPI0S41
x
x
x
x
PG6_GPIO46
EPI0S42
x
x
x
x
PN6_GPIO102
EPI0S43
x
x
x
x
PN7_GPIO103
ACCESSIBLE BY
Cortex-M3
ACCESSIBLE BY
C28x
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
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PJ3_GPIO59
PC1_GPIO65
Specifications
97
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F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
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Table 5-49. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Non-Muxed (EPIHB16CFG/MODE = 0x1), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Additional Chip Selects (EPIHB16CFG2/CSCFG = 0x5,7)
EPI PORT NAME
ACCESSIBLE
BY
Cortex-M3
98
ACCESSIBLE
BY
C28x
EPI SIGNAL
FUNCTION
WITH
THREE
CHIP SELECTS
(CSCFG = 0x7)
DEVICE PIN
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
EPI PORT NAME
ACCESSIBLE
BY
Cortex-M3
ACCESSIBLE
BY
C28x
EPI SIGNAL
FUNCTION
DEVICE PIN
WITH
FOUR
CHIP SELECTS
(CSCFG = 0x5)
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
EPI0S0
D0
PH3_GPIO51
EPI0S0
D0
PH3_GPIO51
EPI0S1
D1
PH2_GPIO50
EPI0S1
D1
PH2_GPIO50
EPI0S2
D2
PC4_GPIO68
EPI0S2
D2
PC4_GPIO68
EPI0S3
D3
PC5_GPIO69
EPI0S3
D3
PC5_GPIO69
EPI0S4
D4
PC6_GPIO70
EPI0S4
D4
PC6_GPIO70
EPI0S5
D5
PC7_GPIO71
EPI0S5
D5
PC7_GPIO71
EPI0S6
D6
PH0_GPIO48
EPI0S6
D6
PH0_GPIO48
EPI0S7
D7
PH1_GPIO49
EPI0S7
D7
PH1_GPIO49
EPI0S8
D8
PE0_GPIO24
EPI0S8
D8
PE0_GPIO24
EPI0S9
D9
PE1_GPIO25
EPI0S9
D9
PE1_GPIO25
EPI0S10
D10
PH4_GPIO52
EPI0S10
D10
PH4_GPIO52
EPI0S11
D11
PH5_GPIO53
EPI0S11
D11
PH5_GPIO53
EPI0S12
D12
PF4_GPIO36
EPI0S12
D12
PF4_GPIO36
EPI0S13
D13
PG0_GPIO40
EPI0S13
D13
PG0_GPIO40
EPI0S14
D14
PG1_GPIO41
EPI0S14
D14
PG1_GPIO41
EPI0S15
D15
PF5_GPIO37
EPI0S15
D15
PF5_GPIO37
EPI0S16
A0
PJ0_GPIO56
EPI0S16
A0
PJ0_GPIO56
EPI0S17
A1
PJ1_GPIO57
EPI0S17
A1
PJ1_GPIO57
EPI0S18
A2
PJ2_GPIO58
EPI0S18
A2
PJ2_GPIO58
EPI0S19
A3
PD4_GPIO20
EPI0S19
A3
PD4_GPIO20
EPI0S20
A4
PD2_GPIO18
EPI0S20
A4
PD2_GPIO18
EPI0S21
A5
PD3_GPIO19
EPI0S21
A5
PD3_GPIO19
EPI0S22
A6
PB5_GPIO13
EPI0S22
A6
PB5_GPIO13
EPI0S23
A7
PB4_GPIO12
EPI0S23
A7
PB4_GPIO12
EPI0S24
A8
PE2_GPIO26
EPI0S24
A8
PE2_GPIO26
EPI0S40
A9
PG5_GPIO45
EPI0S40
A9
PG5_GPIO45
EPI0S41
A10
PG6_GPIO46
EPI0S41
A10
PG6_GPIO46
EPI0S36
A11
PB7_GPIO15
PC3_GPIO67
EPI0S36
A11
PB7_GPIO15
PC3_GPIO67
EPI0S37
A12
PB6_GPIO14
PC2_GPIO66
EPI0S37
A12
PB6_GPIO14
PC2_GPIO66
EPI0S38
A13
PF6_GPIO38
PE4_GPIO28
EPI0S38
A13
PF6_GPIO38
PE4_GPIO28
EPI0S39
A14
PG2_GPIO42
EPI0S39
A14
PG2_GPIO42
EPI0S27
A15
PH7_GPIO55
EPI0S42
A15
PN6_GPIO102
EPI0S35
A16
PE5_GPIO29
EPI0S43
A16
PN7_GPIO103
EPI0S42
A17
PN6_GPIO102
EPI0S25
BSEL0
PE3_GPIO27
EPI0S43
A18
PN7_GPIO103
EPI0S26
BSEL1
PH6_GPIO54
EPI0S25
BSEL0
PE3_GPIO27
EPI0S30
CS0
PD7_GPIO23
EPI0S26
BSEL1
PH6_GPIO54
EPI0S27
CS1
PH7_GPIO55
EPI0S30
CS0
PD7_GPIO23
EPI0S34
CS2
PE4_GPIO28
EPI0S34
CS2
PE4_GPIO28
EPI0S33
CS3
PF3_GPIO35
PC1_GPIO65
EPI0S33
CS3
PF3_GPIO35
PC1_GPIO65
EPI0S29
WR
PD6_GPIO22
PJ5_GPIO61
EPI0S29
WR
PD6_GPIO22
PJ5_GPIO61
EPI0S28
RD
PD5_GPIO21
PJ4_GPIO60
EPI0S28
RD
PD5_GPIO21
PJ4_GPIO60
EPI0S32
RDY
PF2_GPIO34
PC0_GPIO64
EPI0S32
RDY
PF2_GPIO34
PC0_GPIO64
EPI0S31
x
PG7_GPIO47
EPI0S31
x
PG7_GPIO47
EPI0S35
x
PE5_GPIO29
Specifications
PJ3_GPIO59
PJ6_GPIO62
PJ3_GPIO59
PJ6_GPIO62
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
5.10.4.3.2.3 HB-16 FIFO Mode
The HB-16 FIFO Mode uses 16 bits of data, removes ALE and address pins, and optionally adds external
FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication
devices (including USB2 devices), and some FPGA configuration (FIFO through block RAM). This FIFO
Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is
important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can
potentially block other CPU or DMA accesses. For detailed maps of the HB-16 FIFO Mode, see Table 550.
Table 5-50. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
FIFO Mode (EPIHB16CFG/MODE = 0x3)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH ONE
CHIP SELECT
(CSCFG = 0x1)
WITH TWO
CHIP SELECTS
(CSCFG = 0x2)
EPI0S0
D0
D0
PH3_GPIO51
EPI0S1
D1
D1
PH2_GPIO50
EPI0S2
D2
D2
PC4_GPIO68
EPI0S3
D3
D3
PC5_GPIO69
EPI0S4
D4
D4
PC6_GPIO70
EPI0S5
D5
D5
PC7_GPIO71
EPI0S6
D6
D6
PH0_GPIO48
EPI0S7
D7
D7
PH1_GPIO49
EPI0S8
D8
D8
PE0_GPIO24
EPI0S9
D9
D9
PE1_GPIO25
EPI0S10
D10
D10
PH4_GPIO52
EPI0S11
D11
D11
PH5_GPIO53
EPI0S12
D12
D12
PF4_GPIO36
EPI0S13
D13
D13
PG0_GPIO40
EPI0S14
D14
D14
PG1_GPIO41
EPI0S15
D15
D15
PF5_GPIO37
EPI0S25
x
CS1
PE3_GPIO27
EPI0S30
CS0
CS0
PD7_GPIO23
ACCESSIBLE BY
Cortex-M3
ACCESSIBLE BY
C28x
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
PJ6_GPIO62
EPI0S27
FFULL
FFULL
PH7_GPIO55
EPI0S26
FEMPTY
FEMPTY
PH6_GPIO54
EPI0S29
WR
WR
PD6_GPIO22
EPI0S28
RD
RD
PD5_GPIO21
PJ4_GPIO60
EPI0S32
x
x
PF2_GPIO34
PC0_GPIO64
EPI0S16
x
x
PJ0_GPIO56
EPI0S17
x
x
PJ1_GPIO57
EPI0S18
x
x
PJ2_GPIO58
EPI0S19
x
x
PD4_GPIO20
EPI0S20
x
x
PD2_GPIO18
EPI0S21
x
x
PD3_GPIO19
EPI0S22
x
x
PB5_GPIO13
EPI0S23
x
x
PB4_GPIO12
EPI0S24
x
x
PE2_GPIO26
EPI0S31
x
x
PG7_GPIO47
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PJ5_GPIO61
PJ3_GPIO59
Specifications
99
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F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 5-50. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
FIFO Mode (EPIHB16CFG/MODE = 0x3) (continued)
EPI PORT NAME
EPI SIGNAL FUNCTION
DEVICE PIN
WITH ONE
CHIP SELECT
(CSCFG = 0x1)
WITH TWO
CHIP SELECTS
(CSCFG = 0x2)
EPI0S33
x
x
PF3_GPIO35
EPI0S34
x
x
PE4_GPIO28
EPI0S35
x
x
PE5_GPIO29
EPI0S36
x
x
PB7_GPIO15
PC3_GPIO67
EPI0S37
x
x
PB6_GPIO14
PC2_GPIO66
EPI0S38
x
x
PF6_GPIO38
PE4_GPIO28
EPI0S39
x
x
PG2_GPIO42
EPI0S40
x
x
PG5_GPIO45
EPI0S41
x
x
PG6_GPIO46
EPI0S42
x
x
PN6_GPIO102
EPI0S43
x
x
PN7_GPIO103
ACCESSIBLE BY
Cortex-M3
ACCESSIBLE BY
C28x
(AVAILABLE GPIOMUX_1
MUXING CHOICES FOR EPI)
PC1_GPIO65
5.10.4.4 EPI Electrical Data and Timing
The signal names in Figure 5-21 through Figure 5-29 are defined in Table 5-51.
Table 5-51. Signals in Figure 5-21 Through Figure 5-29
SIGNAL
100
Specifications
DESCRIPTION
AD
Address/Data
Address
Address output
ALE
Address latch enable
BAD
Bank Address/Data
BSEL0, BSEL1
Byte select
CAS
Column address strobe
CKE
Clock enable
CLK, Clock
Clock
Command
Command signal
CS
Chip select
Data
Data signals
DQMH
Data mask high
DQML
Data mask low
Frame
Frame signal
iRDY
Ready input
Muxed Address/Data
Multiplexed Address/Data
RAS
Row address strobe
RD/OE
Read enable/Output enable
WE, WR
Write enable
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 5-52. EPI SDRAM Interface Switching Characteristics
(see Figure 5-21, Figure 5-22, and Figure 5-23)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
UNIT
E1
tc(CK)
Cycle time, SDRAM clock
20
ns
E2
tw(CKH)
Pulse duration, SDRAM clock high
10
ns
E3
tw(CKL)
Pulse duration, SDRAM clock low
10
ns
E4
td(CK-OV)
Delay time, clock to output valid
–5
5
ns
E5
td(CK-OIV)
Delay time, clock to output invalid
–5
5
ns
E6
td(CK-OZ)
Delay time, clock to output high-impedance
–5
5
ns
E7
tsu(AD-CK)
Setup time, input before clock
10
E8
th(CK-AD)
Hold time, input after clock
E9
tPU
Power-up time
E10
tpc
E11
E12
ns
0
ns
100
µs
Precharge time, all banks
20
ns
trf
Autorefresh
66
ns
tMRD
Program mode register
40
ns
CLK
(EPI0S31)
E1
CKE
(EPI0S30)
E2
E3
NOP
Command
(EPI0S[29:28,19:18])
NOP
NOP
AREF
PRE
NOP
PRE
NOP
NOP
LOAD
AREF
NOP
AREF
Active
DQMH, DQML
(EPI0S[17:16])
AD11, AD[9:0]
(EPI0S[11,9:0]
Code
Row
All Banks
AD10
(EPI0S[10])
Code
Row
Single Bank
BAD[1:0]
(EPI0S[14:13])
Bank
AD [15,12]
(EPI0S [15,12])
E10
E9
A.
B.
C.
D.
E11
E12
If CS is high at clock high time, all applied commands are NOP.
The Mode register may be loaded before the autorefresh cycles if desired.
JEDEC and PC100 specify three clocks.
Outputs are ensured High-Z after command is issued.
Figure 5-21. SDRAM Initialization and Load Mode Register Timing
CLK
(EPI0S31)
CKE
(EPI0S30)
E4
E5
E6
CS
(EPI0S29)
WE
(EPI0S28)
RAS
(EPI0S19)
CAS
(EPI0S18)
E7
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Row
Activate
Column
NOP
NOP
Read
E8
Data 0
Data 1
...
Data n
Burst
Term
NOP
AD [15:0] driven in
AD [15:0] driven out
AD [15:0] driven out
Figure 5-22. SDRAM Read Timing
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CLK
(EPI0S31)
CKE
(EPI0S30)
E4
E5
E6
CS
(EPI0S29)
WE
(EPI0S28)
RAS
(EPI0S19)
CAS
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Row
Activate
Column-1
NOP
NOP
Data 0
Data 1
...
Data n
Burst
Term
Write
AD [15:0] driven out
AD [15:0] driven out
Figure 5-23. SDRAM Write Timing
102
Specifications
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 5-53. EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics
(see Figure 5-24, Figure 5-25, Figure 5-26, and Figure 5-27)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
E16
td(WR-WDATAV)
MIN
TYP
Delay time, WR to write data valid
MAX
5
UNIT
ns
EPI
clocks
E17
td(WRIV-DATA)
Delay time, WR invalid to data
2
E18
td(CS-OV)
Delay time, CS to output valid
–5
5
E19
td(CS-OIV)
Delay time, CS to output invalid
–5
5
ns
ns
EPI
clocks
E20
tw(STL)
Pulse duration, WR/RD strobe low
2
E22
tw(ALEH)
Pulse duration, ALE high
E23
tw(CSL)
Pulse duration, CS low
4
EPI
clocks
E24
td(ALE-ST)
Delay time, ALE rising to WR/RD strobe falling
2
EPI
clocks
E25
td(ALE-ADHZ)
Delay time, ALE falling to Address/Data high-impedance
1
EPI
clocks
EPI
clocks
1
Table 5-54. EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements (1)
(see Figure 5-24 and Figure 5-26)
NO.
(1)
MIN
MAX
UNIT
E14
tsu(RDATA)
Setup time, read data
10
ns
E15
th(RDATA)
Hold time, read data
0
ns
Setup time for FEMPTY and FFULL signals from clock edge is 2 system clocks (MIN).
E22
ALE
(EPI0S30)
E18
E23
CS
(EPI0S30)
WR
(EPI0S29)
E18
E24
RD/OE
(EPI0S28)
BSEL0/BSEL1
E19
E20
(A)
Address
E15
E14
Data
A.
Data
BSEL0 and BSEL1 are available in Host-Bus 16 mode only.
Figure 5-24. Host-Bus 8/16 Mode Read Timing
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E22
ALE
(EPI0S30)
E18
E23
CS
(EPI0S30)
E18
E19
E20
WR
(EPI0S29)
E24
RD/OE
(EPI0S28)
BSEL0/BSEL1
(A)
Address
E16
E17
Data
Data
A.
BSEL0 and BSEL1 are available in Host-Bus 16 mode only.
Figure 5-25. Host-Bus 8/16 Mode Write Timing
E22
ALE
(EPI0S30)
CS
(EPI0S30)
E18
E23
WR
(EPI0S29)
E19
E18
E24
E20
RD/OE
(EPI0S28)
E25
BSEL0/BSEL1
(A)
A.
E15
E14
Muxed
Address/Data
Address
Data
BSEL0 and BSEL1 are available in Host-Bus 16 mode only.
Figure 5-26. Host-Bus 8/16 Mode Muxed Read Timing
E22
ALE
(EPI0S30)
E18
E23
CS
(EPI0S30)
E18
E19
E20
WR
(EPI0S29)
E24
RD/OE
(EPI0S28)
BSEL0/BSEL1
(A)
Muxed
Address
Address/Data
A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only.
E16
Data
Figure 5-27. Host-Bus 8/16 Mode Muxed Write Timing
104
Specifications
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 5-55. EPI General-Purpose Interface Switching Characteristics (see Figure 5-28)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
UNIT
E26
tw(CKH)
Pulse duration, general-purpose clock high
10
ns
E27
tw(CKL)
Pulse duration, general-purpose clock low
10
E30
td(CK-OV)
Delay time, falling clock edge to output valid
–5
5
ns
E31
td(CK-OIV)
Delay time, falling clock edge to output invalid
–5
5
ns
E33
tc(CK)
Cycle time, general-purpose clock
20
ns
ns
Table 5-56. EPI General-Purpose Interface Timing Requirements (see Figure 5-28 and Figure 5-29)
NO.
MIN
E28
tsu(IN-CK)
Setup time, input signal before rising clock edge
E29
th(CK-IN)
Hold time, input signal after rising clock edge
E32
tsu(IRDY-CK)
Setup time, iRDY assertion or deassertion before falling clock edge
MAX
UNIT
10
ns
0
ns
10
ns
E33
Clock
(EPI0S31)
E27
E26
E30
Frame
(EPI0S30)
RD
(EPI0S29)
WR
(EPI0S28)
Address
E30
E28
Data
Data
E31
Data
E29
Read
A.
Write
This figure illustrates accesses where the FRM50 bit is clear, the FRMCNT field is 0x0, the RD2CYC bit is clear, and
the WR2CYC bit is clear.
Figure 5-28. General-Purpose Mode Read and Write Timing
Clock
(EPI0S31)
Frame
(EPI0S30)
E32
E32
RD
(EPI0S29)
iRDY
(EPI0S27)
Address
Data
Figure 5-29. General-Purpose Mode iRDY Timing
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5.11 Master Subsystem Peripherals
Master Subsystem peripherals are located on the APB Bus and AHB Bus, and are accessible from the
Cortex-M3 CPU/µDMA. The AHB peripherals include EPI, USB, and two CAN modules. The APB
peripherals include EMAC, two I2Cs, five UARTs, four SSIs, four GPTIMERs, two WDOGs, NMI WDOG,
and a µCRC module (Cyclic Redundancy Check). The Cortex-M3 CPU/µDMA also have access to Analog
(Result Registers only) and Shared peripherals (see Section 5.10).
For detailed information on the processor peripherals, see the Concerto F28M36x Technical Reference
Manual.
5.11.1 Synchronous Serial Interface
This device has four SSI modules. Each SSI has a Master or Slave interface for synchronous serial
communication with peripheral devices that have Texas Instruments™ SSIs, SPI, or Freescale™ serial
format.
The SSI peripheral performs serial-to-parallel conversion on data received from a peripheral device. The
CPU accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories, allowing up to eight 16-bit values to be stored independently in both transmit and
receive modes. The SSI also supports µDMA transfers. The transmit and receive FIFOs can be
programmed as destination/source addresses in the µDMA module. An µDMA operation is enabled by
setting the appropriate bit or bits in the SSIDMACTL register.
Figure 5-30 shows the SSI peripheral.
5.11.1.1 Bit Rate Generation
The SSI includes a programmable bit-rate clock divider and prescaler to generate the serial output clock.
Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral
devices. The serial bit rate is derived by dividing-down the input clock (SysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register. The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR
is the value programmed in the SSI Control 0 (SSICR0) register. The frequency of the output clock SSIClk
is defined by:
SSIClk = SysClk / [CPSDVSR * (1 + SCR)]
NOTE
For master mode, the system clock must be at least four times faster than SSIClk, with the
restriction that SSIClk cannot be faster than 25 MHz. For slave mode, the system clock must
be at least 12 times faster than SSIClk.
106
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SSIxIRQ
INTR
M3 NVIC
M3
CPU
M3 CLOCKS
M3SSCLK
M3CLKENBx
REGISTER
ACCESS
SSI
CLOCK
PRESCALER
DMA
CONTROL
DMAxREQ
M3
uDMA
SSICPSR REG
SSIDMACTL REG
TX/RX FIFO
ACCESS
SSIxCLK
SSITX
TX FIFO
( 8 ´ 16 )
CONTROL
/ STATUS
PIN
SSIRX
RX
FIFO
STAT
SSICR0 REG
SSICR1 REG
TRANSMIT
/ RECEIVE
LOGIC
SSIDR REG
SSISR REG
GPIO_MUX1
TX
FIFO
STAT
PIN
SSICLK
PIN
RX FIFO
( 8 ´ 16 )
SSIFSS
PIN
INTxREQ
SSIIM REG
SSIPCELLID0 REG
SSIPERIPHLD0 REG
SSIPERIPHLD4 REG
SSIMIS REG
SSIPCELLID1 REG
SSIPERIPHLD1REG
SSIPERIPHLD5 REG
SSIRIS REG
SSIPCELLID2 REG
SSIPERIPHLD2 REG
SSIPERIPHLD6 REG
SSIICR REG
SSIPCELLID3 REG
SSIPERIPHLD3 REG
SSIPERIPHLD7 REG
IDENTIFICATION REGISTERS
INTR CONTROL
Figure 5-30. SSI
Specifications
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5.11.1.2 Transmit FIFO
The transmit FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. The CPU writes data
to the FIFO through the SSI Data (SSIDR) register, and data is stored in the FIFO until the data is read
out by the transmission logic. When configured as a master or a slave, parallel data is written into the
transmit FIFO before serial conversion and transmission to the attached slave or master, respectively,
through the SSITx pin.
In slave mode, the SSI transmits data each time the master initiates a transaction. If the transmit FIFO is
empty and the master initiates a transaction, the slave transmits the 8th most recent value in the transmit
FIFO. If less than eight values have been written to the transmit FIFO since the SSI module clock was
enabled using the SSI bit in the RGCG1 register, then "0" is transmitted. Care should be taken to ensure
that valid data is in the FIFO as needed. The SSI can be configured to generate an interrupt or an µDMA
request when the FIFO is empty.
5.11.1.3 Receive FIFO
The receive FIFO is a 16-bit-wide, 8-location-deep, first-in, first-out memory buffer. Received data from the
serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading
the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is
registered before parallel loading into the attached slave or master receive FIFO, respectively.
5.11.1.4 Interrupts
The SSI can generate interrupts when the following conditions are observed:
• Transmit FIFO service (when the transmit FIFO is half full or less)
• Receive FIFO service (when the receive FIFO is half full or more)
• Receive FIFO time-out
• Receive FIFO overrun
• End of transmission
All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI
generates a single interrupt request to the controller regardless of the number of active interrupts. Each of
the four individual maskable interrupts can be masked by clearing the appropriate bit in the SSI Interrupt
Mask (SSIIM) register. Setting the appropriate mask bit enables the interrupt.
The individual outputs, along with a combined interrupt output, allow the use of either a global interrupt
service routine or modular device drivers to handle interrupts. The transmit and receive dynamic data-flow
interrupts have been separated from the status interrupts so that data can be read or written in response
to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw
Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers.
The receive FIFO has a time-out period that is 32 periods at the rate of SSIClk (whether or not SSIClk is
currently active) and is started when the RX FIFO goes from EMPTY to not-EMPTY. If the RX FIFO is
emptied before 32 clocks have passed, the time-out period is reset. As a result, the ISR should clear the
Receive FIFO Time-out Interrupt just after reading out the RX FIFO by writing a "1" to the RTIC bit in the
SSI Interrupt Clear (SSIICR) register. The interrupt should not be cleared so late that the ISR returns
before the interrupt is actually cleared, or the ISR may be reactivated unnecessarily.
The End-of-Transmission (EOT) interrupt indicates that the data has been transmitted completely. This
interrupt can be used to indicate when it is safe to turn off the SSI module clock or enter sleep mode. In
addition, because transmitted data and received data complete at exactly the same time, the interrupt can
also indicate that read data is ready immediately, without waiting for the receive FIFO time-out period to
complete.
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5.11.1.5 Frame Formats
Each data frame is between 4 bits and 16 bits long, depending on the size of data programmed, and is
transmitted starting with the MSB. The following basic frame types can be selected:
• Texas Instruments Synchronous Serial
• Freescale SPI
For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions
at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk
is used to provide a receive time-out indication that occurs when the receive FIFO still contains data after
a time-out period.
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5.11.2 Universal Asynchronous Receiver/Transmitter
This device has five UART modules. The CPU accesses data, control, and status information. The UART
also supports µDMA transfers. Each UART performs functions of parallel-to-serial and serial-to-parallel
conversions. Each of the five UART modules is similar in functionality to a 16C550 UART, but is not
register-compatible.
The UART is configured for transmit and receive through the TXE bit and the RXE bit, respectively, of the
UART Control (UARTCTL) register. Transmit and receive are both enabled out of reset. Before any control
registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the
UART is disabled during a TX or RX operation, the current transaction is completed before the UART
stops.
The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to an
infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the
UARTCTL register.
Figure 5-31 shows the UART peripheral.
5.11.2.1 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The
number formed by these two values is used by the baud-rate generator to determine the bit period. Having
a fractional baud-rate divider allows the UART to generate all the standard baud rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register, and the 6bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register. The baud
rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the
BRD, and BRDF is the fractional part, separated by a decimal place).
BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)
where UARTSysClk is the system clock connected to the UART, and ClkDiv is either 16 (if HSE in
UARTCTL is clear) or 8 (if HSE is set).
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can
be calculated by taking the fractional part of the baud-rate divisor, multiplying this fractional part by 64,
and adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 8x or 16x the baud rate [referred to as
Baud8 and Baud16, depending on the setting of the HSE bit (bit 5 in UARTCTL)]. This reference clock is
divided by 8 or 16 to generate the transmit clock, and is used for error detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register, the UARTIBRD and UARTFBRD
registers form an internal 30-bit register. This internal register is only updated when a write operation to
UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the
UARTLCRH register for the changes to take effect.
110
Specifications
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UARTxIRQ
INTR
M3 NVIC
M3
CPU
M3 CLOCKS
M3SSCLK
UARTCLKENBx
REGISTER
ACCESS
UART
UARTxCLK
DMA
CONTROL
DMAxREQ
BAUDE RATE
GENERATOR
M3
uDMA
UARTIBRD REG
UARTDMACTL REG
UARTFBRD REG
TX/RX FIFO
ACCESS
XCLK
RX
FIFO
STAT
UARTCR0 REG
UARTCR1 REG
UARTDR REG
UARTSR REG
RECEIVER
RX FIFO
( 8 ´ 16 )
UARTIFLS REG
UARTIM REG
INTxREQ
UARTMIS REG
UARTRIS REG
UARTICR REG
UxTX
(WITH SIR TRANSMIT
ENCODER)
PIN
GPIO_MUX1
TX
FIFO
STAT
TRANSMITTER
TX FIFO
( 8 ´ 16 )
CONTROL
/ STATUS
(WITH SIR RECEIVE
DECODER)
UARTPCELLID0
UARTPERIPHLD0
UARTPERIPHLD4
UARTPCELLID1
UARTPERIPHLD1
UARTPERIPHLD5
UARTPCELLID2
UARTPERIPHLD2
UARTPERIPHLD6
UARTPCELLID3
UARTPERIPHLD3
UARTPERIPHLD7
UxRX
PIN
IDENTIFICATION REGISTERS
INTR CONTROL
Figure 5-31. UART
Specifications
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5.11.2.2 Transmit and Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The
control logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first),
parity bit, and the stop bits according to the programmed configuration in the control registers.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse
has been detected. Overrun, parity, frame error checking, and line-break detection are also performed,
and their status accompanies the data that is written to the receive FIFO.
5.11.2.3 Data Transmission and Reception
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra 4 bits
per character for status information. For transmission, data is written into the transmit FIFO. If the UART is
enabled, a data frame starts transmitting with the parameters indicated in the UARTLCRH register. Data
continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag
(UARTFR) register is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is
nonempty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the
transmit FIFO is empty, and the last character has been transmitted from the shift register, including the
stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled.
When the receiver is idle (the UnRx signal is continuously "1"), and the data input goes Low (a start bit
has been received), the receive counter begins running and data is sampled on the eighth cycle of
Baud16 or the fourth cycle of Baud8, depending on the setting of the HSE bit (bit 5 in UARTCTL).
The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE
clear) or the fourth cycle of Baud 8 (HSE set), otherwise the start bit is ignored. After a valid start bit is
detected, successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is,
1 bit period later), according to the programmed length of the data characters and value of the HSE bit in
UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are defined in
the UARTLCRH register.
Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred.
When a full word is received, the data is stored in the receive FIFO along with any error bits associated
with that word.
112
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5.11.2.4 Interrupts
The UART can generate interrupts when the following conditions are observed:
• Overrun Error
• Break Error
• Parity Error
• Framing Error
• Receive Time-out
• Transmit (when the condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the
EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer)
• Receive (when the condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can
only generate a single interrupt request to the controller at any given time. Software can service multiple
interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status
(UARTMIS) register.
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask
(UARTIM) register by setting the corresponding IM bits. If interrupts are not used, the raw interrupt status
is always visible through the UART Raw Interrupt Status (UARTRIS) register.
Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a "1" to the
corresponding bit in the UART Interrupt Clear (UARTICR) register.
The receive time-out interrupt is asserted when the receive FIFO is not empty, and no further data is
received over a 32-bit period. The receive time-out interrupt is cleared either when the FIFO becomes
empty through reading all the data (or by reading the holding register), or when a "1" is written to the
corresponding bit in the UARTICR register.
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5.11.3 Cortex-M3 Inter-Integrated Circuit
This device has two Cortex-M3 I2C peripherals. The Cortex-M3 I2C bus provides bidirectional data
transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to
external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone
generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in
product development and manufacture. The microcontroller includes two I2C modules, providing the ability
to interact (both transmit and receive) with other I2C devices on the bus.
The two Cortex-M3 I2C modules include the following features:
• Devices on the I2C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
• Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
• Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
• Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due to an
error)
– Slave generates interrupts when data has been transferred or requested by a master or when a
START or STOP condition is detected
• Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode
Figure 5-32 shows the Cortex-M3 I2C peripheral.
5.11.3.1 Functional Overview
Each I2C module comprises both master and slave functions. For proper operation, the SDA and SCL
pins must be configured as open-drain signals.
The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL. SDA is the bidirectional
serial data line and SCL is the bidirectional serial clock line. The bus is considered idle when both lines
are high.
Every transaction on the I2C bus is 9 bits long, consisting of eight data bits and a single acknowledge bit.
The number of bytes per transfer (defined as the time between a valid START and STOP condition) is
unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB
first. When a receiver cannot receive another complete byte, the receiver can hold the clock line SCL Low
and force the transmitter into a wait state. The data transfer continues when the receiver releases the
clock SCL.
5.11.3.2 Available Speed Modes
The I2C bus can run in either standard mode (100 Kbps) or fast mode (400 Kbps). The selected mode
should match the speed of the other I2C devices on the bus.
114
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I2CxIRQ
INTR
M3 NVIC
M3
CPU
M3 CLOCKS
M3SSCLK
M3CLKENBx
REGISTER
ACCESS
I2CxCLK
2
I C (M3)
2
I2CMSA REG
IC
CONTROL
I2CMCS REG
I2CSOAR REG
I2CMCR REG
I2CSCSR REG
I2CMDR REG
I2CSDR REG
I2CMIMR REG
I2CSIMR REG
I2CxSCL
I2CSDA_M
PIN
2
I2CMRISREG
I2CSRISREG
I2CMMIS REG
I2CSMIS REG
I2CMICR REG
I2CSICR REG
I C I/O
SELECT
I2CSCL_S
2
I C SLAVE CORE
I2CSDA_S
GPIO_MUX1
I2CMTPR REG
I2CSCL_M
2
I C MASTER CORE
I2CxSDA
PIN
Figure 5-32. I2C (Cortex-M3)
Specifications
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5.11.3.3 I2C Electrical Data and Timing
Table 5-57. I2C Timing
TEST CONDITIONS
MIN
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
MAX
UNIT
400
kHz
fSCL
SCL clock frequency
vil
Low level input voltage
Vih
High level input voltage
Vhys
Input hysteresis
Vol
Low level output voltage
3 mA sink current
tLOW
Low period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
1.3
μs
tHIGH
High period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
μs
lI
Input current with an input
voltage between 0.1 VDDIO and
0.9 VDDIO MAX
116
Specifications
0.3 VDDIO
V
0.7 VDDIO
V
0.05 VDDIO
V
0
–10
0.4
10
V
μA
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5.11.4 Cortex-M3 Controller Area Network
NOTE
The CAN module uses the popular IP known as D_CAN. This document uses the names
“CAN” and “D_CAN” interchangeably to reference this peripheral.
This device has two Cortex-M3 CAN peripherals. CAN is a serial communications protocol that efficiently
supports distributed real-time control with a high level of security. The CAN module supports bit rates up
to 1 Mbit/s and is compliant with the ISO11898-1 (CAN 2.0B) protocol specification.
CAN implements the following features:
• CAN protocol version 2.0 part A, B
• Bit rates up to 1 Mbit/s
• Multiple clock sources
• 32 message objects
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Message RAM parity check mechanism
• Two interrupt lines
• Global power down and wakeup support
Figure 5-33 shows the Cortex-M3 CAN peripheral.
5.11.4.1 Functional Overview
CAN performs CAN protocol communication according to ISO 11898-1 (identical to Bosch® CAN protocol
specification 2.0 A, B). The bit rate can be programmed to values up to 1 Mbit/s. Additional transceiver
hardware is required for the connection to the physical layer (CAN bus).
For communication on a CAN network, individual message objects can be configured. The message
objects and identifier masks are stored in the Message RAM. All functions concerning the handling of
messages are implemented in the message handler. Those functions are: acceptance filtering, the transfer
of messages between the CAN Core and the Message RAM, and the handling of transmission requests.
The register set of the CAN is accessible directly by the CPU through the module interface. These
registers are used to control/configure the CAN Core and the message handler, and to access the
message RAM.
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CANxIRQ
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INTR
M3 NVIC
M3
CPU
M3 CLOCKS
M3SSCLK
M3CLKENBx
REGISTER
ACCESS
CAN (M3)
CANxCLK
CANxTX
MODULE INTERFACE
PIN
MESSAGE
RAM
CAN
CORE
GPIO_MUX1
REGISTERS AND MESSAGE
OBJECT ACCESS (IFX)
32 MESSAGE
OBJECTS
MESSAGE RAM
INTERFACE
CANxRX
MESSAGE HANDLER
PIN
Figure 5-33. CAN (Cortex-M3)
118
Specifications
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5.11.5 Cortex-M3 Universal Serial Bus Controller
This device has one Cortex-M3 USB controller. The USB controller operates as a full-speed or low-speed
function controller during point-to-point communications with the USB Host, Device, or OTG functions. The
controller complies with the USB 2.0 standard, which includes SUSPEND and RESUME signaling. Thirtytwo endpoints, which comprised of 2 hardwired endpoints for control transfers (one endpoint for IN and
one endpoint for OUT) and 30 endpoints defined by firmware, along with a dynamic sizable FIFO, support
multiple packet queuing. DMA access to the FIFO allows minimal interference from system software.
Software-controlled connect and disconnect allow flexibility during USB device start-up. The controller
complies with the Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) of the OTG
standard.
The USB controller includes the following features:
• Complies with USB-IF certification standards
• USB 2.0 full-speed (12-Mbps) and low-speed (1.5-Mbps) operation
• Integrated PHY
• Four transfer types: Control, Interrupt, Bulk, and Isochronous
• 32 endpoints:
– One dedicated control IN endpoint and one dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
• 4KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte
isochronous packet size
• VBUS droop and valid ID detection and interrupt
• Efficient transfers using DMA controller:
– Separate channels for transmit and receive for up to three IN endpoints and three OUT endpoints
– Channel requests asserted when FIFO contains required amount of data
• Electrical specifications are compliant with the USB Specification Rev. 2.0 (full-speed and low-speed
support) and the On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0. Some components of
the USB system are integrated within the Concerto microcontroller and are specific to its design.
Figure 5-34 shows the USB peripheral.
5.11.5.1 Functional Description
The USB controller provides full OTG negotiation by supporting both the SRP and the HNP. The SRP
allows devices on the B side of a cable to request the A-side devices' turn on VBUS. The HNP is used
after the initial session request protocol has powered the bus and provides a method to determine which
end of the cable will act as the Host controller. When the device is connected to non-OTG peripherals or
devices, the controller can detect which cable end was used and provides a register to indicate if the
controller should act as the Host controller or the Device controller. This indication and the mode of
operation are handled automatically by the USB controller. This autodetection allows the system to use a
single A/B connector instead of having both A and B connectors in the system, and supports full OTG
negotiations with other OTG devices.
In addition, the USB controller provides support for connecting to non-OTG peripherals or Host controllers.
The USB controller can be configured to act as either a dedicated Host or Device, in which case, the
USB0VBUS and USB0ID signals can be used as GPIOs. However, when the USB controller is acting as a
self-powered Device, a GPIO input must be connected to VBUS and configured to generate an interrupt
when the VBUS level drops. This interrupt is used to disable the pullup resistor on the USB0DP signal.
NOTE
When the USB is used, the system clock frequency (SYSCLK) must be at least 20 MHz.
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M3 NVIC
INTR
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M3
CPU
M3 CLOCKS
M3SSCLK
USBCLKENB
USBPLLCLK
REGISTER
ACCESS
USBMAC_IRQ
USB
CPU
INTERFACE
ENDPOINT CONTROL
EP REGISTER
DECODER
TRANSMIT
EP 0-31
CONTROL
USB0EPEN
RECEIVE
COMMON
REGS
PIN
USB0PFLT
CYCLE
CONTROL
HOST TRANSACTION
SCHEDULER
PIN
COMBINE
ENDPOINTS
FIFO DECODER
GPIO_MUX1
PHY
USB0VBUS
INTERRUPT
CONTROL
DMAxREQ
M3
uDMA
FIFO RAM CONTROLLER
TX
BUFF
RX
BUFF
PACKET
ENCODE / DECODE
UTM
SYNCHRONIZATION
PACKET ENCODE
DATA SYNC
TX
BUFF
RX
BUFF
(5V TOLERANT)
PIN
USB0ID
PACKET DECODE
HNP / SRP
CRC GEN/CHECK
TIMERS
(5V TOLERANT)
PIN
USB0DM
PIN
TX/RX FIFO
ACCESS
CYCLE CONTROL
USB0DP
PIN
USBMAC REQ
Figure 5-34. USB
120
Specifications
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5.11.6 Cortex-M3 Ethernet Media Access Controller
The Cortex-M3 EMAC conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASETX standards. This device has one Ethernet Media Access Controller.
The EMAC module has the following features:
• Conforms to the IEEE 802.3-2002 specification
– 10BASE-T/100BASE-TX IEEE-802.3 compliant
• Multiple operational modes
– Full- and half-duplex 100-Mbps
– Full- and half-duplex 10-Mbps
– Power-saving and power-down modes
• Highly configurable:
– Programmable MAC address
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
• IEEE 1588 Precision Time Protocol: Provides highly accurate time stamps for individual packets
• Efficient transfers using the Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive channel request asserted on packet receipt
– Transmit channel request asserted on empty transmit FIFO
Figure 5-35 shows the EMAC peripheral.
5.11.6.1 Functional Overview
The Ethernet Controller is functionally divided into two layers: the Media Access Controller (MAC) layer
and the Network Physical (PHY) layer. The MAC resides inside the device, and the PHY outside of the
device. These layers correspond to the OSI model layers 2 and 1, respectively. The CPU accesses the
Ethernet Controller through the MAC layer. The MAC layer provides transmit and receive processing for
Ethernet frames. The MAC layer also provides the interface to the external PHY layer through an internal
Media Independent Interface (MII). The PHY layer communicates with the Ethernet bus.
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EMAC_IRQ
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M3 NVIC
INTR
M3
CPU
M3 CLOCKS
M3SSCLK
EMACCLKENB
REGISTER
ACCESS
EMAC
MIITXCLK
DMAxREQ
M3
uDMA
INTR CONTROL
TX/RX FIFO
ACCESS
RECEIVE
CONTROL
PIN
MIITXEN
MACRIS REG
PIN
MACIACK REG
MACRCTL REG
MACIM REG
MACNP REG
MIITXD(3:0)
TRANSMIT
FIFO
PIN
EMACRX_REQ
EMACTX_REQ
MIICRS
DATA ACCESS
PIN
MIICOL
GPIO_MUX1
MACDDATA REG
TIMER SUPPORT
MACTS REG
PIN
MIIRXCLK
TRANSMIT
CONTROL
MACTCTL REG
PIN
RECEIVE
FIFO
MIIRXDV
MACTHR REG
PIN
MACTR REG
MIIRXER
PIN
MIIRXD(3:0)
INDIVIDUAL
ADDRESS
MII CONTROL
PIN
MACMCTL REG
MACMDV REG
MACIA0 REG
MACIA1 REG
MDIO_CK
MACMTXD REG
MACMRXD REG
PIN
MDIO
MADIX REG
MACMAR REG
MDIO_D
PIN
Figure 5-35. EMAC
122
Specifications
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5.11.6.2 MII Signals
The individual EMAC and Management Data Input/Output (MDIO) signals for the MII interface are
summarized in Table 5-58.
Table 5-58. EMAC and MDIO Signals for MII Interface
SIGNAL
TYPE (1)
DESCRIPTION
MIITXCK
I
Transmit clock. The transmit clock is a continuous clock that provides the timing reference
for transmit operations. The MIITXD and MIITXEN signals are tied to this clock. The clock is
generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100-Mbps
operation.
MIITXER
O
This pin is always driven low from the MAC controller on the device.
MIITXD[3-0]
O
Transmit data. The transmit data pins are a collection of four data signals comprising 4 bits
of data. MTDX0 is the least-significant bit (LSB). The signals are synchronized by MIITXCLK
and are valid only when MIITXEN is asserted.
MIITXEN
O
Transmit enable. The transmit enable signal indicates that the MIITXD pins are generating
nibble data for use by the PHY. MIITXEN is driven synchronously to MIITXCLK.
I
Collision detected. In half-duplex operation, the MIICOL pin is asserted by the PHY when the
PHY detects a collision on the network. The MIICOL pin remains asserted while the collision
condition persists. This signal is not necessarily synchronous to MIITXCLK or MIIRXCLK. In
full-duplex operation, the MIICOL pin is used for hardware transmit flow control. Asserting
the MIICOL pin will stop packet transmissions; packets in the process of being transmitted
when MIICOL is asserted will complete transmission. The MIICOL pin should be held low if
hardware transmit flow control is not used.
I
Carrier sense. In half-duplex operation, the MIICRS pin is asserted by the PHY when the
network is not idle in either transmit or receive. The pin is deasserted when both transmit
and receive are idle. This signal is not necessarily synchronous to MIITXCLK or MIIRXCLK.
In full-duplex operation, the MIICRS pin should be held low.
MIIRXCK
I
Receive clock. The receive clock is a continuous clock that provides the timing reference for
receive operations. The MIIRXD, MIIRXDV, and MIIRXER signals are tied to this clock. The
clock is generated by the PHY and is 2.5 MHz at 10-Mbps operation and 25 MHz at 100Mbps operation.
MIIRXD[3-0]
I
Receive data. The receive data pins are a collection of four data signals comprising 4 bits of
data. MRDX0 is the least-significant bit. The signals are synchronized by MIIRXCLK and are
valid only when MIIRXDV is asserted.
MIIRXDV
I
Receive data valid. The receive data valid signal indicates that the MIIRXD pins are
generating nibble data for use by the EMAC. MIIRXDV is driven synchronously to
MIIRXCLK.
MIIRXER
I
Receive error. The receive error signal is asserted for one or more MIIRXCLK periods to
indicate that an error was detected in the received frame. The MIIRXER signal being
asserted is meaningful only during data reception when MIIRXDV is active.
MDIO_CK
O
Management data clock. The MDIO data clock is sourced by the MDIO module on the
system. MDIO_CK is used to synchronize MDIO data access operations done on the MDIO
pin. The frequency of this clock is controlled by the CLKDIV bits in the MDIO Control
Register (CONTROL).
MDIO_D
I/O
Management data input output. The MDIO data pin drives PHY management data into and
out of the PHY by way of an access frame that consists of start-of-frame, read/write
indication, PHY address, register address, and data bit cycles. The MDIO_D pin acts as an
output for all but the data bit cycles, at which time the pin is an input for read operations.
MIICOL
MIICRS
(1)
I = Input, O = Output, I/O = Input/Output
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5.11.6.3 EMAC Electrical Data and Timing
Table 5-59. Timing Requirements for MIITXCK (see Figure 5-36)
100 Mbps
NO.
Cycle time, MIITXCK (25 MHz)
10 Mbps
MIN
MAX
40
40
MIN
MAX
400
400
UNIT
1
tc(TXCK)
2
tw(TXCKH)
Pulse duration, MIITXCK high
16
24
196
204
ns
3
tw(TXCKL)
Pulse duration, MIITXCK low
16
24
196
204
ns
Cycle time, MIITXCK (2.5 MHz)
ns
1
2
3
MIITXCK
Figure 5-36. 100/10Mb/s MII Transmit Clock Timing
Table 5-60. Timing Requirements for MIIRXCK (see Figure 5-37)
100 Mbps
NO.
Cycle time, MIIRXCK (25 MHz)
10 Mbps
MIN
MAX
40
40
MIN
MAX
400
400
UNIT
1
tc(RXCK)
2
tw(RXCKH)
Pulse duration, MIIRXCK high
16
24
196
204
ns
3
tw(RXCKL)
Pulse duration, MIIRXCK low
16
24
196
204
ns
Cycle time, MIIRXCK (2.5 MHz)
ns
1
2
3
MIIRXCK
Figure 5-37. 100/10Mb/s MII Receive Clock Timing
124
Specifications
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Table 5-61. Switching Characteristics for EMAC MII Transmit (see Figure 5-38)
over recommended operating conditions (unless otherwise noted)
NO.
1
PARAMETER
td(TXCKH-MTXDV)
Delay time, MIITXCK high to transmit selected signals valid
MIN
MAX
5
25
UNIT
ns
MAX
UNIT
1
MIITXCK
MIITXD[3:0],
MIITXEN
Figure 5-38. 100/10Mb/s MII Transmit Timing
Table 5-62. Timing Requirements for EMAC MII Receive (see Figure 5-39)
NO.
MIN
NOM
1
tsu(MRXDV-RXCKH)
Setup time, receive selected signals valid before MIIRXCK high
8
ns
2
th(RXCKH-MRXDV)
Hold time, receive selected signals valid after MIIRXCK high
7
ns
1
2
MIIRXCK
MIIRXD[3:0],
MIIRXDV,
MIIRXER (Inputs)
Figure 5-39. 100/10Mb/s MII Receive Timing
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5.11.6.4 MDIO Electrical Data and Timing
Table 5-63. Switching Characteristics for MDIO_CK (see Figure 5-40)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(MCK)
Cycle time, MDIO_CK (2.5 MHz)
400
400
ns
2
tw(MCKH)
Pulse duration, MDIO_CK high
196
204
ns
3
tw(MCKL)
Pulse duration, MDIO_CK low
196
204
ns
MIN
MAX
UNIT
5
25
ns
MAX
UNIT
1
2
3
MDIO_CK
Figure 5-40. MII Serial Management Timing
Table 5-64. Switching Characteristics for MDIO as Output (see Figure 5-41)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
1
td(MCKH-MDV)
Delay time, MDIO_CK high to MDIO_D valid
1
MDIO_CK
MDIO_D
Figure 5-41. MII Serial Management Timing – MDIO as Output
Table 5-65. Timing Requirements for MDIO as Input (see Figure 5-42)
NO.
MIN
4
tsu(MDV-MCKH)
Setup time, MDIO_D valid before MDIO_CK high
5
th(MCKH-MDV)
Hold time, MDIO_D valid after MDIO_CK high
NOM
20
ns
7
ns
MDIO_CK
4
5
MDIO_D
(Input)
Figure 5-42. MII Serial Management Timing – MDIO as Input
126
Specifications
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5.12 Control Subsystem Peripherals
Control Subsystem peripherals are accessible from the C28x CPU through the C28x Memory Bus, and
from the C28x DMA through the C28x DMA Bus. They include one NMI Watchdog, three Timers, four
Serial Port Peripherals (SCI, SPI, McBSP, I2C), and three types of Control Peripherals (ePWM, eQEP,
eCAP). Additionally, the C28x CPU/DMA also have access to the EPI, and to Analog and Shared
peripherals (see Section 5.10).
For detailed information on the processor peripherals, see the Concerto F28M36x Technical Reference
Manual.
5.12.1 High-Resolution PWM and Enhanced PWM Modules
There are 12 PWM modules in the Concerto device. Eight of these are of the HRPWM type with highresolution control on both A and B signal outputs, and four are of the ePWM type. The HRPWM modules
have all the features of the ePWM plus they offer significantly higher PWM resolution (time granularity on
the order of 150 ps). Figure 5-43 shows the eight HRPWM modules (PWM 1–8) and four ePWM modules
(PWM 9–PWM12).
The synchronization inputs to the PWM modules include the SYNCI signal from the GPTRIP1 output of
GPIO_MUX1, and the TBCLKSYNC signal from the CPCLKCR0 register. Synchronization output
SYNCO1 comes from the ePWM1 module and is stretched by 8 HSPCLK cycles before entering
GPIO_MUX1. There are two groups of trip signal inputs to PWM modules. TRIP1–15 inputs come from
GPTRIP1–12 (from GPIO_MUX1), ECCDBLERR signal (from C28x Local and Shared RAM), and PIEERR
signal from the C28x CPU. TZ1–6 (Trip Zone) inputs come from GPTRIP 1–3 (from GPIO_MUX1),
EQEPERR (from the eQEP peripheral), CLOCKFAIL (from M3 CLOCKS), and EMUSTOP (from the C28x
CPU).
There are 12 SOCA PWM outputs and 12 SOCB PWM outputs—a pair from each PWM module. The
12 SOCA outputs are OR-ed together and stretched by 32 HSPCLK cycles before entering GPIO_MUX1
as a single SOCAO signal. The 12 SOCB outputs are OR-ed together and stretched by 32 HSPCLK
cycles before entering GPIO_MUX1 as a single SOCBO signal. The 18 SOCA/B outputs from
PWM1–PWM9 also go to the Analog Subsystem, where they can be selected to become conversion
triggers to ADC modules.
The 12 PWM modules also drive two other sets of outputs which can interrupt the C28x CPU through the
C28x PIE block. These are 12 EPWMINT interrupts and 12 EPWMTZINT trip-zone interrupts. See
Figure 5-44 for the internal structure of the HRPWM and ePWM modules. The green-colored blocks are
common to both ePWM and HRPWM modules, but only the HRPWMs have the grey-colored hi-resolution
blocks.
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ANALOG
SUBSYSTEM
SOCA (9:1)
SOCA
(12:10)
SOCB(9:1)
SOCAO
PULSE STRETCH
32 HSPCLK CYCLES
SOCBO
SOCB
(12:10)
GPTRIP6
EPWM (12:1) A
SYNCI
C28x DMA
GPTRIP1
GPTRIP2
GPTRIP3
GPTRIP4
GPTRIP5
GPTRIP6
GPTRIP7
GPTRIP8
GPTRIP9
GPTRIP10
GPTRIP11
GPTRIP12
‘0’
ECCDBLERR
PIEERR
PULSE STRETCH
32 HSPCLK CYCLES
TRIPIN1
TRIPIN2
TRIPIN3
TRIPIN4
TRIPIN5
TRIPIN6
TRIPIN7
TRIPIN8
TRIPIN9
TRIPIN10
TRIPIN11
TRIPIN12
TRIPIN13
TRIPIN14
TRIPIN15
PWM
1
PWM
3
PWM
2
PWM
4
PWM
5
TZ1
TZ2
TZ3
TZ4
TZ5
TZ6
PWM
6
PWM
7
PWM
8
PWM
9
PWM
10
PWM
11
GPTRIP1
GPTRIP2
GPTRIP3
EQEPERR
CLOCKFAIL
EMUSTOP
PWM
12
EPWM (12:1) B
GPIO_MUX1
EPWM
TBCLKSYNC
EPWM (12:1) TZINT
C28X PIE
EPWM (12:1) INT
SYNCO1
CPCLKCR0 REG
SYNCO
PULSE STRETCH
8 HSPCLK CYCLES
EQEP(3:1)INT
ECAP(6:1)INT
SYNCI
GPTRIP7
GPTRIP8
GPTRIP9
GPTRIP10
GPTRIP11
GPTRIP12
ECAP
1
ECAP1INP
ECAP2INP
ECAP3INP
ECAP4INP
ECAP5INP
ECAP6INP
ECAP
2
EQEP 1
ECAP
SYNCO
3
EQEP 2
ECAP
4
ECAP
ECAP
5
ECAP
6
EQEP
EQEP3
EQEP1A
EQEP1B
EQEP1S
EQEP1I
EQEP2A
EQEP2B
EQEP2S
EQEP2I
EQEP3A
EQEP3B
EQEP3S
EQEP3I
ECAP(6:1)
LEGEND:
PWM
1-8
EPWM +
HiRES PWM
PWM
9-12
EPWM
ONLY
GPTRIP(1-12)
GPIO_MUX1
ECCDBLERR
C28x LOCAL RAM
PIEERR
SHARED RAM
EMUSTOP
EQEPERR
C28x
CPU
CLOCKFAIL
C28x
CLOCKS
Copyright © 2017, Texas Instruments Incorporated
Figure 5-43. PWM, eCAP, eQEP
128
Specifications
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C28SYSCLK
TBCLKSYNC
TRIPIN(15:1)
SYNCO (1)
SYNCI
TIME BASE
DCAEVT1.SYNC
DCAEVT1.SOC
DCBEVT1.SYNC
DCBEVT1.SOC
PHS
(TB)
TBCLK
PRD
DIGITAL
COMPARE
CTR=ZER
CTR=
CMPB
CTR=PRD
TBCTR
(15:0)
CTR=ZER
CTR=PRD
CTR_DIR
TBCLK
TBCTR
(15:0)
HiRES
CONTROL
DCAEVT1.SYNC
COUNTER
COMPARE
CMPA
CAL
CMPB
CNTRL
RED
(DC)
FED
DCBEVT1.SYNC
(CC)
DCAEVT1.FORCE
DCAEVT2.FORCE
DCBEVT1.FORCE
DCBEVT2.FORCE
DCAEVT1.INTER
DCAEVT2.INTER
DCBEVT1.INTER
DCBEVT2.INTER
CTR=ZER
CTR=PRD
EPWM_A
CTR_DIR
CTR=CMPA
ACTION
QUALIFIER
DEAD
BAND
PWM
CHOPPER
TRIP
ZONE
HiRES
PWM
(AQ)
(DB)
(PC)
(TZ)
(HRPWM)
CTR=CMPB
EPWM_B
SWFSYNC
SYNCI
CTR=ZER
CTR=PRD
C28SYSCLK
CTR=CMPA
CTR=CMPB
CTR=CMPC
CTR=CMPD
DCAEVT1.SOC
EVENT
TRIGGER
SYNCI
DCBEVT1.SOC
(ET)
EPWM_TZINT
EPWM_INT
SOCA
SOCB
(1) SYNCO OUTPUTS FROM PWM MODULES 3, 6, 9 AND 12 ARE NOT CONNECTED, THUS THEY ARE NOT USEABLE.
EPWM_INT
TZ (6:1)
Copyright © 2017, Texas Instruments Incorporated
Figure 5-44. Internal Structure of PWM
Specifications
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5.12.1.1 HRPWM Electrical Data and Timing
Table 5-66 shows the high-resolution PWM switching characteristics.
Table 5-66. High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
PARAMETER
MIN
TYP
MAX
UNIT
150
310
ps
Micro Edge Positioning (MEP) step size (1)
(1)
The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
5.12.1.2 ePWM Electrical Data and Timing
Table 5-67 shows the PWM timing requirements and Table 5-68 shows the PWM switching
characteristics.
Table 5-67. ePWM Timing Requirements (1)
MIN
tw(SYCIN)
Sync input pulse width
UNIT
Asynchronous
2tc(SCO)
cycles
Synchronous
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
With input qualifier
(1)
MAX
For an explanation of the input qualifier parameters, see Table 5-27.
Table 5-68. ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tw(PWM)
Pulse duration, PWMx output high/low
tw(SYNCOUT)
Sync output pulse width
td(PWM)tza
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
130
Specifications
TEST CONDITIONS
MIN
MAX
20
ns
8tc(SCO)
cycles
25
no pin load
UNIT
20
ns
ns
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5.12.1.2.1 Trip-Zone Input Timing
Table 5-69. Trip-Zone Input Timing Requirements (1)
MIN
tw(TZ)
Pulse duration, TZx input low
UNIT
Asynchronous
1tc(SCO)
cycles
Synchronous
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
With input qualifier
(1)
MAX
For an explanation of the input qualifier parameters, see Table 5-27.
SYSCLK
tw(TZ)
(A)
TZ
td(TZ-PWM)HZ
(B)
PWM
A.
B.
TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 5-45. PWM Hi-Z Characteristics
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5.12.2 Enhanced Capture Module
There are six identical eCAP modules in Concerto devices: eCAP1, 2, 3, 4, 5, and 6. Each eCAP module
represents one complete capture channel. Its main function is to accurately capture the timings of external
events. One can also use eCAP modules for PWM, when they are not being used for input captures. This
secondary function is selected by flipping the CAP/APWM bit of the ECCTL2 Register. For PWM function,
the counter operates in count-up mode, providing a time base for asymmetrical pulse width (PWM)
waveforms. The CAP1 and CAP2 registers become the period and compare registers, respectively; while
the CAP3 and CAP4 registers become the shadow registers of the main period and capture registers,
respectively.
The left side of Figure 5-46 shows internal components associated with the capture block, and the right
side depicts the PWM block. The two blocks share a set of four registers that are used in both Capture
and PWM modes. Other components include the Counter block that uses the SYNCIN and SYNCOUT
ports to synchronize with other modules; and the Interrupt Trigger and Flag Control block that sends
Capture, PWM, and Counter events to the C28x PIE block through the ECAPxINT output. There are six
ECAPxINT interrupts—one for each eCAP module.
The eCAP peripherals are clocked by C28SYSCLK, and its registers are accessible by the C28x CPU.
This peripheral clock can be enabled or disabled by flipping a bit in one of the system control registers.
5.12.2.1 eCAP Electrical Data and Timing
Table 5-70 shows the eCAP timing requirement and Table 5-71 shows the eCAP switching characteristics.
Table 5-70. eCAP Timing Requirement (1)
MIN
Asynchronous
tw(CAP)
Capture input pulse width
Synchronous
With input qualifier
(1)
MAX
UNIT
2tc(SCO)
cycles
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
For an explanation of the input qualifier parameters, see Table 5-27.
Table 5-71. eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
tw(APWM)
132
TEST CONDITIONS
Pulse duration, APWMx output high/low
Specifications
MIN
20
MAX
UNIT
ns
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EPWM1 OR
OTHER ECAP
PERIPHERALS
SYNCIN
SYNC IN
COUNTER
SYNCOUT
CTRPHS REG
SYNC OUT
TSCTR REG
RST
OTHER ECAP
PERIPHERALS
DELTA
MODE
CAPTURE
MODE
MASTER
SUBSYSTEM
ECAPx
CTR_OVF
CTR(31:0)
PWM
MODE
LD1
POLARITY
SELECT
CAP1/PERIOD REG
PRD(31:0)
C28CLKIN
LD2
POLARITY
SELECT
C28SYSCLK
ECAPxENCLK
CMP(31:0)
POLARITY
SELECT
LD3
REGISTER
ACCESS
POLARITY
SELECT
LD4
CAP3/PER SHDW
PWM
COMPARE
LOGIC
SYSTEM
CONTROL
REGISTERS
C28x
CPU
CAP2/COMP REG
CAPTURE
EVENT
QUALIFIER
4
CAP4/CMP SHDW
4
CTR=PER
EVENT
PRESCALE
CAPTURE
CONTROL
CEVT (4:1)
(CAPTURE EVENTS)
PIN
GPIO_MUX1
ECAPx
INTERRUPT TRIGGER
AND FLAG CONTROL
CTR=CMP
CTR_OVF
MODE
SELECT
ECCTL2 REG
ECAPxINT
C28x PIE
Copyright © 2017, Texas Instruments Incorporated
Figure 5-46. eCAP
Specifications
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5.12.3 Enhanced Quadrature Encoder Pulse Module
The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position,
direction, and speed information from rotating machines used in high-performance motion and positioncontrol systems. There are three Type 0 eQEP modules in each Concerto device.
Each eQEP peripheral comprises five major functional blocks: Quadrature Capture Unit (QCAP), Position
Counter/Control Unit (PCCU), Quadrature Decoder (QDU), Unit Time Base for speed and frequency
measurement (UTIME), and Watchdog timer for detecting stalls (QWDOG). The C28x CPU controls and
communicates with these modules through a set of associated registers (see Figure 5-47). The eQEP
peripherals are clocked by C28SYSCLK, and its registers are accessible by the C28x CPU. This
peripheral clock can be enabled or disabled by flipping a bit in one of the system control registers.
Each eQEP peripheral connects through the GPIO_MUX1 block to four device pins. Two of the four pins
are always inputs, while the other two can be inputs or outputs, depending on the operating mode. The
PCCU block of each eQEP also drives one interrupt to the C28x PIE. There is a total of three EQEPxINT
interrupts—one from each of the three eQEP modules.
5.12.3.1 eQEP Electrical Data and Timing
Table 5-72 shows the eQEP timing requirement and Table 5-73 shows the eQEP switching
characteristics.
Table 5-72. eQEP Timing Requirements (1)
MIN
tw(QEPP)
tw(INDEXH)
Asynchronous (2)/synchronous
QEP input period
With input qualifier
QEP Index Input High time
2[1tc(SCO) + tw(IQSW)]
cycles
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
cycles
(2)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
(1)
(2)
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
Asynchronous /synchronous
With input qualifier
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
cycles
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
cycles
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
cycles
Asynchronous (2)/synchronous
With input qualifier
Asynchronous (2)/synchronous
With input qualifier
UNIT
cycles
Asynchronous (2)/synchronous
With input qualifier
MAX
2tc(SCO)
For an explanation of the input qualifier parameters, see Table 5-27.
Refer to the F28M36x Concerto™ MCUs Silicon Errata for limitations in the asynchronous mode.
Table 5-73. eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
MAX
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
PARAMETER
4tc(SCO)
cycles
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync
output
6tc(SCO)
134
Specifications
TEST CONDITIONS
MIN
cycles
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MASTER
SUBSYSTEM
EQEPx
QCPRD REG
QCAPCTL REG
QCTMR REG
16
C28CLKIN
16
C28SYSCLK
QUADRATURE CAPTURE UNIT
OCTMRLAT REG
QCPRDLAT REG
EQEPxENCLK
( QCAP )
16
SYSTEM
CONTROL
REGISTERS
REGISTER
ACCESS
REGISTERS USED
BY MULTIPLE UNITS
QUTMR REG
QWDTMR REG
QUPRD REG
QWDPRD REG
32
QEPCTL REG
16
QDECCTL REG
UTOUT
QEPSTS REG
C28x
CPU
UTIME
QWDOG
16
QFLG REG
WDTOUT
EQEPxAIN
EQEPxA
/XCLK
PIN
C28x PIE
QCLK
EQEPxINT
QDIR
QI
POSITION COUNTER/CONTROL UNIT
QS
PHE
PCSOUT
QPOSSLAT REG
QPOSILAT REG
16
/XDIR
( QDU )
EQEPxIIN
EQEPxIOUT
GPIO_MUX1
( PCCU )
QPOSLAT REG
EQEPxB
EQEPxBIN
QUADRATURE
DECODER
PIN
EQEPxI
EQEPxIOE
32
32
QEINT REG
EQEPxSIN
QPOSINIT REG
QFRC REG
EQEPxSOUT
QPOSMAX REG
QCLR REG
EQEPxSOE
QPOSCNT REG
PIN
16
QPOSCMP REG
QPOSCTL REG
EQEPxS
PIN
Copyright © 2017, Texas Instruments Incorporated
Figure 5-47. eQEP
Specifications
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5.12.4 C28x Inter-Integrated Circuit Module
This device has one C28x I2C peripheral. The I2C provides an interface between a Concerto device and
devices compliant with the NXP® I2C-bus specification and user manual (UM10204) and connected by
way of an I2C bus. External components attached to this 2-wire serial bus can transmit 1-bit to 8-bit data
to and receive 1-bit to 8-bit data from the device through the I2C module.
NOTE
A unit of data transmitted or received by the I2C module can have fewer than 8 bits;
however, for convenience, a unit of data is called a data byte in this section. The number of
bits in a data byte is selectable through the BC bits of the mode register, I2CMDR.
The I2C module has the following features:
• Compliance with the NXP I2C-bus specification and user manual (UM10204):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit-and-receive and receive-and-transmit mode
– Data transfer rate of from 10 Kbps up to 400 Kbps (I2C Fast-mode rate)
• One 4-word receive FIFO and one 4-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable or disable capability
• Free data format mode
The I2C module does not support:
• High-speed mode (Hs-mode)
• CBUS-compatibility mode
Figure 5-48 shows the C28x I2C peripheral.
136
Specifications
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MASTER
SUBSYSTEM
2
I C (C28)
REGISTER
ACCESS CLK
C28CLKIN
C28SYSCLK
I2CPSC REG
I2CA_ENCLK
I2CCLK
I2CCLK
MASTER CLOCK
DIVIDER
I2CCLKH REG
CLOCK
PRESCALER
I2CCLKL REG
SYSTEM
CONTROL
REGISTERS
SLAVE CLOCK
SYNCHRONIZER
I2CASCL
MODE AND STATUS
REGISTERS
C28x
CPU
I2CFFTX REG
I2CMDR REG
GPIO_MUX1
REGISTER
ACCESS
PIN
I2CSTR REG
I2CDXR REG
TX FIFO
INTR
I2CXSR REG
I2CINT2A
C28x PIE
I2COAR REG
I2CINT1A
I2CSAR REG
I2CCNT REG
I2CASDA
PIN
I2CIER REG
I2CISRC REG
INTERRUPT
CONTROL AND
ARBITRATION
I2CRXR REG
I2CDRR REG
RX FIFO
TX/RX
LOGIC
I2CFFRX REG
Figure 5-48. I2C (C28x)
Specifications
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5.12.4.1 Functional Overview
Each device connected to an I2C Bus is recognized by a unique address. Each device can operate as
either a transmitter or a receiver, depending on the function of the device. A device connected to the I2C
Bus can also be considered as the master or the slave when performing data transfers. A master device is
the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer.
During this transfer, any device addressed by this master is considered a slave. The I2C module supports
the multi-master mode, in which one or more devices capable of controlling an I2C Bus can be connected
to the same I2C Bus.
For data communication, the I2C module has a serial data pin (SDA) and a serial clock pin (SCL). These
two pins carry information between the C28x device and other devices connected to the I2C Bus. The
SDA and SCL pins both are bidirectional. They each must be connected to a positive supply voltage using
a pullup resistor. When the bus is free, both pins are high. The driver of these two pins has an open-drain
configuration to perform the required wired-AND function. There are two major transfer techniques:
1. Standard Mode: Send exactly n data values, where n is a value you program in an I2C module
register.
2. Repeat Mode: Keep sending data values until you use software to initiate a STOP condition or a new
START condition.
The I2C module consists of the following primary blocks:
• A serial interface: one data pin (SDA) and one clock pin (SCL)
• Data registers and FIFOs to temporarily hold receive data and transmit data traveling between the
SDA pin and the CPU
• Control and status registers
• A peripheral bus interface to enable the CPU to access the I2C module registers and FIFOs.
5.12.4.2 Clock Generation
The device clock generator receives a signal from an external clock source and produces an I2C input
clock with a programmed frequency. The I2C input clock is equivalent to the CPU clock and is then
divided twice more inside the I2C module to produce the module clock and the master clock.
5.12.4.3 I2C Electrical Data and Timing
Table 5-74. I2C Timing
TEST CONDITIONS
MIN
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
MAX
UNIT
400
kHz
fSCL
SCL clock frequency
vil
Low level input voltage
Vih
High level input voltage
Vhys
Input hysteresis
Vol
Low level output voltage
3 mA sink current
tLOW
Low period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
1.3
μs
tHIGH
High period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
μs
lI
Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX
138
Specifications
0.3 VDDIO
0.7 VDDIO
V
0.05 VDDIO
0
–10
V
V
0.4
10
V
μA
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5.12.5 C28x Serial Communications Interface
This device has one SCI peripheral. SCI is a two-wire asynchronous serial port, commonly known as a
UART. The SCI module supports digital communications between the CPU and other asynchronous
peripherals that use the standard non-return-to-zero (NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and
each has its own separate enable and interrupt bits. Both can be operated independently for half-duplex
communication, or simultaneously for full-duplex communication. To specify data integrity, the SCI checks
received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to
different speeds through a 16-bit baud-select register.
Features of the SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates
• Data-word format
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– One or two stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ format
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (bits 7–0), and the upper
byte (bits 15–8) is read as zeros. Writing to the upper byte has no effect.
•
•
Auto baud-detect hardware logic
16-level transmit and receive FIFO
Figure 5-49 shows the C28x SCI peripheral.
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MASTER
SUBSYSTEM
SCI (C28)
SCICTL2 REG
SCICTL1A REG
TX INTERRUPT LOGIC
AUTO-BAUD DETECT LOGIC
SCIFFTXA REG
SCEFFCT REG
TX FIFO
TX DELAY
C28CLKIN
C28SYSCLK
REGISTER
ACCESS
SCITXBUF REG
SCIA_ENCLK
/1
/2
/4
…
/14
C28LSPCLK
BAUD-RATE GEN
SCITXDA
TXSHF REG
GPIO_MUX1
SYSTEM
CONTROL
REGISTERS
SCIHBAUD REG
SCILBAUD REG
C28x
CPU
SCICCRA REG
REGISTER ACCESS
RXSHF REG
PIN
SCIRXDA
PIN
SCIRXEMUA REG
SCIRXBUF REG
TX/RX
LOGIC
RX FIFO
INTR
SCIFFRXA REG
SCIPRI REG
SCIRXINA
RX INTERRUPT LOGIC
C28x PIE
SCRXST REG
SCITXINA
Figure 5-49. SCI (C28x)
140
Specifications
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5.12.5.1 Architecture
The major elements used in full-duplex operation include:
• A transmitter (TX) and its major registers:
– SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be
transmitted
– TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts
data onto the SCITXD pin, 1 bit at a time
• A receiver (RX) and its major registers:
– RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, 1 bit at a time
– SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data
from a remote processor is loaded into the RXSHF register and then into the SCIRXBUF and
SCIRXEMU registers
• A programmable baud generator
• Data-memory-mapped control and status registers enable the CPU to access the I2C module registers
and FIFOs.
The SCI receiver and transmitter can operate either independently or simultaneously.
5.12.5.2 Multiprocessor and Asynchronous Communication Modes
The SCI has two multiprocessor protocols: the idle-line multiprocessor mode and the address-bit
multiprocessor mode. These protocols allow efficient data transfer between multiple processors.
The SCI offers the UART communications mode for interfacing with many popular peripherals. The
asynchronous mode requires two lines to interface with many standard devices such as terminals and
printers that use RS-232-C formats.
Data transmission characteristics include:
• One start bit
• One to eight data bits
• An even/odd parity bit or no parity bit
• One or two stop bits with a programmed frequency
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5.12.6 C28x Serial Peripheral Interface
This device has one C28x SPI. The SPI is a high-speed synchronous serial input/output (I/O) port that
allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a
programmed bit-transfer rate. The SPI is normally used for communications between the DSP controller
and external peripherals or another controller. Typical applications include external I/O or peripheral
expansion through devices such as shift registers, display drivers, and ADCs. Multi-device
communications are supported by the master/slave operation of the SPI. The port supports a 16-level,
receive-and-transmit FIFO for reducing CPU servicing overhead.
The SPI module features include:
• SPISOMI: SPI slave-output/master-input pin
• SPISIMO: SPI slave-input/master-output pin
• SPISTE: SPI slave transmit-enable pin
• SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
• Two operational modes: master and slave
• Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited
by the maximum speed of the I/O buffers used on the SPI pins.
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive-and-transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
• Twelve SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (bits 7−0), and the upper
byte (bits 15−8) is read as zeros. Writing to the upper byte has no effect.
•
•
16-level transmit and receive FIFO
Delayed transmit control
Figure 5-50 shows the C28x SPI peripheral.
142
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MASTER
SUBSYSTEM
SPI (C28)
TX INTERRUPT LOGIC
C28CLKIN
SPICTL REG
SPIFFTX REG
SPISIMOA
SPIFFCT REG
C28SYSCLK
REGISTER
ACCESS
SPITXBUF REG
TX FIFO (1)
PIN
TX DELAY
SPISOMIA
SPIA_ENCLK
C28LSPCLK
GPIO_MUX1
SYSTEM
CONTROL
REGISTERS
/1
/2
/4
…
/14
SPI BIT RATE
SPIDAT REG
SPIBRR REG
PIN
SPISTEA
SPICCR REG
PIN
C28x
CPU
REGISTER ACCESS
SPIRXBUF REG
TX/RX
LOGIC
RX FIFO (1)
SPIRXEMU REG
INTR
SPICLKA
PIN
SPIFFRX REG
SPIPRI REG
SPITXINA
SPIST REG
C28x PIE
SPIRXINA
RX INTERRUPT LOGIC
(1) RX FIFO AND TX FIFO CAN BE BYPASSED BY CONFIGURING BIT SPIFFENA OF THE SPIFFTX REGISTER
Figure 5-50. SPI (C28x)
Specifications
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5.12.6.1 Functional Overview
The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK
signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the
SPICLK and latched into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit
(SPICTL.3) is high, data is transmitted and received a half-cycle before the SPICLK transition. As a result,
both controllers send and receive data simultaneously. The application software determines whether the
data is meaningful or dummy data. There are three possible methods for data transmission:
• Master sends data; slave sends dummy data
• Master sends data; slave sends data
• Master sends dummy data; slave sends data
The master can initiate a data transfer at any time because it controls the SPICLK signal. The software,
however, determines how the master detects when the slave is ready to broadcast data.
144
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5.12.6.2 SPI Electrical Data and Timing
This section contains both Master Mode and Slave Mode timing data.
5.12.6.2.1 Master Mode Timing
Table 5-75 lists the master mode timing (clock phase = 0) and Table 5-76 lists the master mode timing
(clock phase = 1). Figure 5-51 and Figure 5-52 show the timing waveforms.
Table 5-75. SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
over recommended operating conditions (unless otherwise noted)
NO.
1
(1)
(2)
(3)
(4)
(5)
PARAMETER
BRR EVEN
BRR ODD
MIN
MAX
4tc(LSPCLK)
UNIT
MIN
MAX
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10
ns
0.5tc(SPC)M –
0.5tc(LSPCLK) + 10
ns
10
ns
tc(SPC)M
Cycle time, SPICLK
2
tw(SPC1)M
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M +
0.5tc(LSPCLK) – 10
3
tw(SPC2)M
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
4
td(SIMO)M
Delay time, SPICLK to
SPISIMO valid
5
tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
8
tsu(SOMI)M
Setup time, SPISOMI before
SPICLK
9
th(SOMI)M
Hold time, SPISOMI valid after
SPICLK
23
td(SPC)M
24
td(STE)M
10
0.5tc(SPC)M – 10
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
ns
35
35
ns
0
0
ns
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M –
3tc(SYSCLK) – 10
1.5tc(SPC)M –
3tc(SYSCLK) – 10
ns
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)M – 10
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
ns
The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
23
24
SPISTE
Figure 5-51. SPI Master Mode External Timing (Clock Phase = 0)
146
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Table 5-76. SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5)
over recommended operating conditions (unless otherwise noted)
NO.
1
(1)
(2)
(3)
(4)
(5)
BRR EVEN
PARAMETER
BRR ODD
MIN
MAX
4tc(LSPCLK)
UNIT
MIN
MAX
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
0.5tc(SPC)M –
0.5tc(LSPCLK) + 10
ns
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10
ns
tc(SPC)M
Cycle time, SPICLK
2
tw(SPC1)M
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
3
tw(SPC2)M
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M +
0.5tc(LSPCLK) – 10
6
td(SIMO)M
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M – 10
0.5tc(SPC)M +
0.5tc(LSPCLK) – 10
ns
7
tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M – 10
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
ns
10
tsu(SOMI)M
Setup time, SPISOMI before
SPICLK
35
35
ns
11
th(SOMI)M
Hold time, SPISOMI valid after
SPICLK
0
0
ns
23
td(SPC)M
Delay time, SPISTE active to
SPICLK
2tc(SPC)M –
3tc(SYSCLK) – 10
2tc(SPC)M –
3tc(SYSCLK) – 10
ns
24
td(STE)M
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC) – 10
0.5tc(SPC) –
0.5tc(LSPCLK) – 10
ns
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
Master Out Data Is Valid
SPISIMO
10
11
Master In Data Must
Be Valid
SPISOMI
23
24
SPISTE
Figure 5-52. SPI Master Mode External Timing (Clock Phase = 1)
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5.12.6.2.2 Slave Mode Timing
Table 5-77 lists the slave mode timing (clock phase = 0) and Table 5-78 lists the slave mode timing (clock
phase = 1). Figure 5-53 and Figure 5-54 show the timing waveforms.
Table 5-77. SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
12
tc(SPC)S
Cycle time, SPICLK
13
tw(SPC1)S
14
tw(SPC2)S
15
td(SOMI)S
Delay time, SPICLK to SPISOMI valid
16
tv(SOMI)S
Valid time, SPISOMI data valid after SPICLK
19
tsu(SIMO)S
20
th(SIMO)S
25
26
(1)
(2)
(3)
(4)
(5)
MAX
UNIT
4tc(SYSCLK)
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
ns
Pulse duration, SPICLK second pulse
2tc(SYSCLK) – 1
ns
35
ns
0
ns
Setup time, SPISIMO valid before SPICLK
1.5tc(SYSCLK)
ns
Hold time, SPISIMO data valid after SPICLK
1.5tc(SYSCLK)
ns
tsu(STE)S
Setup time, SPISTE active before SPICLK
1.5tc(SYSCLK)
ns
th(STE)S
Hold time, SPISTE inactive after SPICLK
1.5tc(SYSCLK)
ns
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
16
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
25
26
SPISTE
Figure 5-53. SPI Slave Mode External Timing (Clock Phase = 0)
148
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Table 5-78. SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
12
tc(SPC)S
Cycle time, SPICLK
13
tw(SPC1)S
14
tw(SPC2)S
17
td(SOMI)S
Delay time, SPICLK to SPISOMI valid
18
tv(SOMI)S
Valid time, SPISOMI data valid after SPICLK
21
tsu(SIMO)S
22
th(SIMO)S
25
26
(1)
(2)
(3)
(4)
MAX
UNIT
4tc(SYSCLK)
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
ns
Pulse duration, SPICLK second pulse
2tc(SYSCLK) – 1
ns
35
ns
0
ns
Setup time, SPISIMO valid before SPICLK
1.5tc(SYSCLK)
ns
Hold time, SPISIMO data valid after SPICLK
1.5tc(SYSCLK)
ns
tsu(STE)S
Setup time, SPISTE active before SPICLK
1.5tc(SYSCLK)
ns
th(STE)S
Hold time, SPISTE inactive after SPICLK
1.5tc(SYSCLK)
ns
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
SPISOMI
Data Valid
SPISOMI Data Is Valid
Data Valid
18
21
22
SPISIMO Data
Must Be Valid
SPISIMO
25
26
SPISTE
Figure 5-54. SPI Slave Mode External Timing (Clock Phase = 1)
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5.12.7 C28x Multichannel Buffered Serial Port
This device provides one high-speed McBSP that allows direct interface to codecs and other devices. The
CPU accesses data, control, and status information. The MCBSP also supports µDMA transfers.
The McBSP consists of a data-flow path and a control path connected to external devices by six pins.
Data is communicated to devices interfaced with the McBSP through the data transmit (DX) pin for
transmission and through the data receive (DR) pin for reception. Control information in the form of
clocking and frame synchronization is communicated through the following pins: CLKX (transmit clock),
CLKR (receive clock), FSX (transmit frame synchronization), and FSR (receive frame synchronization).
The CPU and the DMA controller communicate with the McBSP through 16-bit-wide registers accessible
through the internal peripheral bus. The CPU or the DMA controller writes the data to be transmitted to the
data transmit registers (DXR1, DXR2). Data written to the DXRs is shifted out to DX through the transmit
shift registers (XSR1, XSR2). Similarly, receive data on the DR pin is shifted into the receive shift registers
(RSR1, RSR2) and copied into the receive buffer registers (RBR1, RBR2). The contents of the RBRs is
then copied to the DRRs, which can be read by the CPU or the DMA controller. This method allows
simultaneous movement of internal and external data communications.
DRR2, RBR2, RSR2, DXR2, and XSR2 are not used (written, read, or shifted) if the serial word length is
8 bits, 12 bits, or 16 bits. For larger word lengths, these registers are needed to hold the most significant
bits.
The frame and clock loop-back is implemented at chip level to enable CLKX and FSX to drive CLKR and
FSR. If the loop-back is enabled, the CLKR and FSR get their signals from the CLKX and FSX pads
instead of the CLKR and FSR pins.
150
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McBSP features include:
• Full-duplex communication
• Double-buffered transmission and triple-buffered reception, allowing a continuous data stream
• Independent clocking and framing for reception and transmission
• The capability to send interrupts to the CPU and to send DMA events to the DMA controller
• 128 channels for transmission and reception
• Multichannel selection modes that enable or disable block transfers in each of the channels
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected A/D and D/A devices
• Support for external generation of clock signals and frame-synchronization signals
• A programmable sample rate generator for internal generation and control of clock signals and frame
synchronization signals
• Programmable polarity for frame-synchronization pulses and clock signals
• Direct interface to:
– T1/E1 framers
– IOM-2 compliant devices
– AC97-compliant devices (the necessary multi-phase frame capability is provided)
– I2S compliant devices
– SPI devices
• A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits
NOTE
A value of the chosen data size is referred to as a serial word or word in this section.
Elsewhere, word is used to describe a 16-bit value.
•
•
•
•
µ-law and A-law companding
The option of transmitting/receiving 8-bit data with the LSB first
Status bits for flagging exception/error conditions
ABIS mode is not supported
Figure 5-55 shows the C28x McBSP peripheral.
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MASTER
SUBSYSTEM
MCBSP
MCR2 REG
MCR1 REG
C28CLKIN
C28SYSCLK
REG
ACCESS
MCBSPA_ENCLK
SYSTEM
CONTROL
REGISTERS
/1
/2
/4
…
/14
C28LSPCLK
XCERA REG
RCERA REG
XCERB REG
RCERB REG
XCERC REG
RCERC REG
XCERD REG
RCERD REG
XCERE REG
RCERE REG
XCERF REG
RCERF REG
XCERG REG
RCERG REG
XCERH REG
RCERH REG
MULTI CHANNEL
SELECTION
(128 CHAN)
PERIPH
LOGIC
MCLKXA
SPCR2 REG
SPCR1 REG
PIN
C28x
CPU
ALL REG
ACCESS
MFSXA
XCR2 REG
XCR1 REG
PIN
GENERATION AND CONTROL
OF CLOCK AND FRAME SYNC
SPCR2 REG
INTR
MDXA
SPCR1 REG
PIN
SRGR1 REG
GPIO_MUX1
SRGR2 REG
PCR REG
C28x PIE
MCLKRA
MXINTA
MRINTA
MFFINT REG
RX/TX
INTERRUPT
LOGIC
PIN
MFSRA
PIN
DXR2 REG
DXR1 REG
COMPRESS
DRR1 REG
DRR2 REG
EXPAND
XSR REG
C28
DMA
DRR / DXR
REG ACCESS
RBR REG
RSR REG
MDRA
PIN
Figure 5-55. McBSP (C28x)
152
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5.12.7.1 McBSP Electrical Data and Timing
5.12.7.1.1 McBSP Transmit and Receive Timing
Table 5-79. McBSP Timing Requirements (1)
(2)
NO.
MIN
McBSP module clock (CLKG, CLKX, CLKR) range
(2)
(3)
UNIT
(3)
MHz
1
ms
kHz
25
McBSP module cycle time (CLKG, CLKX, CLKR) range
(1)
MAX
1
40
ns
M11
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
M12
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P–7
M13
tr(CKRX)
Rise time, CLKR/X
CLKR/X ext
7
ns
M14
tf(CKRX)
Fall time, CLKR/X
CLKR/X ext
7
ns
M15
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
M16
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
M17
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
M18
th(CKRL-DRV)
Hold time, DR valid after CLKR low
M19
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
M20
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKR int
18
CLKR ext
2
CLKR int
0
CLKR ext
6
CLKR int
18
CLKR ext
5
CLKR int
0
CLKR ext
3
CLKX int
18
CLKX ext
2
CLKX int
0
CLKX ext
6
ns
ns
ns
ns
ns
ns
ns
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be LSPCLK,
CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (30 MHz).
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Table 5-80. McBSP Switching Characteristics (1)
(2)
over recommended operating conditions (unless otherwise noted)
NO.
M1
PARAMETER
tc(CKRX)
MIN
Cycle time, CLKR/X
CLKR/X int
2P
M2
tw(CKRXH)
Pulse duration, CLKR/X high
CLKR/X int
D–5
(3)
M3
tw(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
C–5
(3)
MAX
ns
D+5
(3)
ns
C+5
(3)
ns
CLKR int
0
4
CLKR ext
3
27
CLKX int
0
4
CLKX ext
3
27
M4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
M5
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
M6
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
following last data bit
CLKX int
8
CLKX ext
14
Delay time, CLKX high to DX valid.
CLKX int
9
This applies to all bits except the first bit transmitted.
CLKX ext
28
M7
M8
M9
M10
td(CKXH-DXV)
ten(CKXH-DX)
Delay time, CLKX high to DX valid
DXENA = 0
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
DXENA = 1
Enable time, CLKX high to DX driven
DXENA = 0
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
DXENA = 1
Delay time, FSX high to DX valid
DXENA = 0
td(FXH-DXV)
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode.
DXENA = 1
Enable time, FSX high to DX driven
DXENA = 0
ten(FXH-DX)
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode
(1)
(2)
(3)
154
DXENA = 1
CLKX int
8
CLKX ext
14
CLKX int
P+8
CLKX ext
P + 14
CLKX int
0
CLKX ext
6
CLKX int
P
CLKX ext
P+6
FSX int
UNIT
ns
ns
ns
ns
ns
8
FSX ext
14
FSX int
P+8
FSX ext
P + 14
FSX int
ns
0
FSX ext
6
FSX int
P
FSX ext
P+6
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
2P = 1/CLKG in ns.
C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
Specifications
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M1, M11
M2, M12
M13
M3, M12
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR
(RDATDLY=00b)
Bit (n−1)
(n−2)
(n−3)
M17
(n−4)
M18
DR
(RDATDLY=01b)
Bit (n−1)
(n−2)
(n−3)
M17
M18
DR
(RDATDLY=10b)
Bit (n−1)
(n−2)
Figure 5-56. McBSP Receive Timing
M1, M11
M2, M12
M13
M3, M12
CLKX
M5
M5
FSX (int)
M19
M20
FSX (ext)
M9
M7
M10
DX
(XDATDLY=00b)
Bit 0
Bit (n−1)
(n−2)
(n−3)
M7
M8
DX
(XDATDLY=01b)
Bit 0
Bit (n−1)
M7
M6
DX
(XDATDLY=10b)
(n−2)
M8
Bit 0
Bit (n−1)
Figure 5-57. McBSP Transmit Timing
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5.12.7.1.2 McBSP as SPI Master or Slave Timing
Table 5-81. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
NO.
M30
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
M31
th(CKXL-DRV)
Hold time, DR valid after CLKX low
M32
tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
M33
tc(CKX)
Cycle time, CLKX
(1)
MASTER
SLAVE
MIN
MIN
MAX
MAX
UNIT
30
8P – 10
ns
1
8P – 10
ns
8P + 10
ns
16P
ns
2P (2)
For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
2P = 1/CLKG
(2)
Table 5-82. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
over recommended operating conditions (unless otherwise noted)
NO.
MASTER
PARAMETER
MIN
SLAVE
MAX
MIN
MAX
UNIT
M24
th(CKXL-FXL)
Hold time, FSX low after CLKX low
2P (1)
ns
M25
td(FXL-CKXH)
Delay time, FSX low to CLKX high
P
ns
M28
tdis(FXH-DXHZ)
Disable time, DX high impedance following
last data bit from FSX high
6
6P + 6
ns
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1)
2P = 1/CLKG
M32
LSB
M33
MSB
CLKX
M25
M24
FSX
M28
DX
M29
Bit 0
Bit(n-1)
M30
DR
Bit 0
(n-2)
(n-3)
(n-4)
M31
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5-58. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
156
Specifications
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Table 5-83. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
MASTER
NO.
MIN
M39
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
M40
th(CKXH-DRV)
Hold time, DR valid after CLKX high
M41
tsu(FXL-CKXH)
Setup time, FSX low before CLKX high
M42
tc(CKX)
Cycle time, CLKX
(1)
(2)
SLAVE
MAX
MIN
MAX
UNIT
30
8P – 10
ns
1
8P – 10
ns
16P + 10
ns
16P
ns
2P (2)
For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
2P = 1/CLKG
Table 5-84. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
over recommended operating conditions (unless otherwise noted)
NO.
(1)
MASTER
PARAMETER
MIN
SLAVE
MAX
MIN
MAX
UNIT
M34
th(CKXL-FXL)
Hold time, FSX low after CLKX low
P
ns
M35
td(FXL-CKXH)
Delay time, FSX low to CLKX high
2P (1)
ns
M37
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX low
P+6
7P + 6
ns
M38
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
2P = 1/CLKG
LSB
M42
MSB
M41
CLKX
M34
M35
FSX
M37
DX
M38
Bit 0
Bit(n-1)
M39
DR
Bit 0
(n-2)
(n-3)
(n-4)
M40
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5-59. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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Table 5-85. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
NO.
M49
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
M50
th(CKXH-DRV)
Hold time, DR valid after CLKX high
M51
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M52
tc(CKX)
Cycle time, CLKX
(1)
MASTER
SLAVE
MIN
MIN
MAX
MAX
UNIT
30
8P – 10
ns
1
8P – 10
ns
8P + 10
ns
16P
ns
2P (2)
For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
2P = 1/CLKG
(2)
Table 5-86. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MASTER
SLAVE
MIN
MIN
MAX
MAX
UNIT
2P (1)
ns
Delay time, FSX low to CLKX low
P
ns
M47
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
6
6P + 6
ns
M48
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
M43
th(CKXH-FXL)
Hold time, FSX low after CLKX high
M44
td(FXL-CKXL)
(1)
2P = 1/CLKG
M51
LSB
M52
MSB
CLKX
M43
M44
FSX
M47
DX
M48
Bit 0
Bit(n-1)
M49
DR
Bit 0
(n-2)
(n-3)
(n-4)
M50
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5-60. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
158
Specifications
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Table 5-87. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
MASTER
NO.
MIN
M58 tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
M59 th(CKXL-DRV)
Hold time, DR valid after CLKX low
M60 tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
M61 tc(CKX)
Cycle time, CLKX
(1)
(2)
SLAVE
MAX
MIN
MAX
UNIT
30
8P – 10
ns
1
8P – 10
ns
16P + 10
ns
16P
ns
2P (2)
For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
2P = 1/CLKG
Table 5-88. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1)
over recommended operating conditions (unless otherwise noted)
NO.
MASTER (2)
PARAMETER
MIN
M53
th(CKXH-FXL)
Hold time, FSX low after CLKX high
M54
td(FXL-CKXL)
Delay time, FSX low to CLKX low
M55
td(CLKXH-DXV)
Delay time, CLKX high to DX valid
M56
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last
data bit from CLKX high
M57
td(FXL-DXV)
Delay time, FSX low to DX valid
(1)
(2)
SLAVE
MAX
MIN
MAX
P
UNIT
ns
2P (1)
ns
–2
0
3P + 6
5P + 20
ns
P+6
7P + 6
ns
6
4P + 6
ns
2P = 1/CLKG
C = CLKX low pulse width = P
D = CLKX high pulse width = P
M60
LSB
M61
MSB
CLKX
M53
M54
FSX
M56
DX
M55
M57
Bit 0
Bit(n-1)
M58
DR
Bit 0
(n-2)
(n-3)
(n-4)
M59
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5-61. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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6 Detailed Description
The Concerto MCU comprises three subsystems: the Master Subsystem, the Control Subsystem, and the
Analog Subsystem. While the Master and Control Subsystem each have dedicated local memories and
peripherals, they can also share data and events through shared memories and peripherals. The Analog
Subsystem has two ADC converters and six Analog Comparators. Both the Master and Control
Subsystems access the Analog Subsystem through the Analog Common Interface Bus (ACIB). The NMI
Blocks force communication of critical events to the Master and Control Subsystem processors and their
Watchdog Timers. The Reset Block responds to Watchdog Timer NMI Reset, External Reset, and other
events to initialize subsystem processors and the rest of the chip to a known state. The Clocking Blocks
support multiple low-power modes where clocks to the processors and peripherals can be slowed down or
stopped in order to manage power consumption.
NOTE
Throughout this document, the Master Subsystem is denoted by the color blue; the Control
Subsystem is denoted by the color green; and the Analog Subsystem is denoted by the color
orange.
160
Detailed Description
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6.1
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Memory Maps
Section 6.1.1 shows the Control Subsystem Memory Map. Section 6.1.2 shows the Master Subsystem
Memory Map.
6.1.1
Control Subsystem Memory Map
Table 6-1. Control Subsystem M0, M1 RAM
(1)
C DMA ACCESS (1)
C ADDRESS
(x16 ALIGNED) (1)
no
0000 0000 – 0000 03FF
M0 RAM (ECC)
2K
no
0000 0400 – 0000 07FF
M1 RAM (ECC)
2K
CONTROL SUBSYSTEM M0, M1 RAM
SIZE
(BYTES)
The letter "C" refers to the Control Subsystem.
Table 6-2. Control Subsystem Peripheral Frame 0
C DMA ACCESS (1)
CONTROL SUBSYSTEM PERIPHERAL FRAME 0
(INCLUDES ANALOG)
SIZE
(BYTES)
0000 0800 – 0000 087F
Reserved
0000 0880 – 0000 0890
Control Subsystem Device Configuration Registers (Read
Only)
0000 0891 – 0000 0ADF
Reserved
0000 0AE0 – 0000 0AEF
C28x CSM Registers
0000 0AF0 – 0000 0AFF
Reserved
0000 0B00 – 0000 0B0F
ADC1 Result Registers
0000 0B10 – 0000 0B3F
Reserved
0000 0B40 – 0000 0B4F
ADC2 Result Registers
0000 0B50 – 0000 0BFF
Reserved
no
0000 0C00 – 0000 0C07
CPU Timer 0
16
no
0000 0C08 – 0000 0C0F
CPU Timer 1
16
no
0000 0C10 – 0000 0C17
CPU Timer 2
16
0000 0C18 – 0000 0CDF
Reserved
no
0000 0CE0 – 0000 0CFF
PIE Registers
64
no
0000 0D00 – 0000 0DFF
PIE Vector Table
512
no
0000 0E00 – 0000 0EFF
PIE Vector Table Copy (Read Only)
512
0000 0F00 – 0000 0FFF
Reserved
0000 1000 – 0000 11FF
C28x DMA Registers
0000 1200 – 0000 16FF
Reserved
0000 1700 – 0000 177F
Analog Subsystem Control Registers
256
0000 1780 – 0000 17FF
Hardware BIST Registers
256
0000 1800 – 0000 3FFF
Reserved
no
no
yes
yes
no
no
no
(1)
C ADDRESS
(x16 ALIGNED) (1)
34
32
32
32
1K
The letter "C" refers to the Control Subsystem.
Detailed Description
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Table 6-3. Control Subsystem Peripheral Frame 3
C ADDRESS
(x16 ALIGNED) (1)
C DMA ACCESS (1)
no
no
no
no
no
no
yes
(1)
(2)
162
CONTROL SUBSYSTEM
PERIPHERAL FRAME 3
0000 4000 – 0000 4181
C28x Flash Control Registers
0000 4182 – 0000 42FF
Reserved
0000 4300 – 0000 4323
C28x Flash ECC Error Log
Registers
0000 4324 – 0000 43FF
Reserved
0000 4400 – 0000 443F
M Clock Control Registers (2)
0000 4440 – 0000 48FF
Reserved
0000 4900 – 0000 497F
RAM Configuration Registers
0000 4980 – 0000 49FF
Reserved
0000 4A00 – 0000 4A7F
RAM ECC/Parity/Access Error
Log Registers
0000 4A80 – 0000 4DFF
Reserved
0000 4E00 – 0000 4E3F
CtoM and MtoC IPC Registers
0000 4E40 – 0000 4FFF
Reserved
SIZE
(BYTES)
M ADDRESS
(BYTE-ALIGNED) (2)
µDMA
ACCESS
128
400F B800 – 400F B87F
no
256
400F B200 – 400F B2FF
no
256
400F B300 – 400F B3FF
no
128
400F B700 – 400F B77F
no
772
72
0000 5000 – 0000 503F
McBSP-A
0000 5040 – 0000 50FF
Reserved
128
yes
0000 5100 – 0000 517F
EPWM1 (Hi-Resolution)
256
yes
0000 5180 – 0000 51FF
EPWM2 (Hi-Resolution)
256
yes
0000 5200 – 0000 527F
EPWM3 (Hi-Resolution)
256
yes
0000 5280 – 0000 52FF
EPWM4 (Hi-Resolution)
256
yes
0000 5300 – 0000 537F
EPWM5 (Hi-Resolution)
256
yes
0000 5380 – 0000 53FF
EPWM6 (Hi-Resolution)
256
yes
0000 5400 – 0000 547F
EPWM7 (Hi-Resolution)
256
yes
0000 5480 – 0000 54FF
EPWM8 (Hi-Resolution)
256
yes
0000 5500 – 0000 557F
EPWM9
256
yes
0000 5580 – 0000 55FF
EPWM10
256
yes
0000 5600 – 0000 567F
EPWM11
256
yes
0000 5680 – 0000 56FF
EPWM12
256
0000 5700 – 0000 57FF
Reserved
The letter "C" refers to the Control Subsystem.
The letter "M" refers to the Master Subsystem.
Detailed Description
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Table 6-4. Control Subsystem Peripheral Frame 1
C DMA ACCESS (1)
C ADDRESS
(x16 ALIGNED) (1)
0000 5800 – 0000 59FF
Reserved
no
0000 5A00 – 0000 5A1F
ECAP1
64
no
0000 5A20 – 0000 5A3F
ECAP2
64
no
0000 5A40 – 0000 5A5F
ECAP3
64
no
0000 5A60 – 0000 5A7F
ECAP4
64
no
0000 5A80 – 0000 5A9F
ECAP5
64
no
0000 5AA0 – 0000 5ABF
ECAP6
64
0000 5AC0 – 0000 5AFF
Reserved
0000 5B00 – 0000 5B3F
EQEP1
128
no
0000 5B40 – 0000 5B7F
EQEP2
128
no
0000 5B80 – 0000 5BBF
EQEP3
128
0000 5BC0 – 0000 5EFF
Reserved
0000 5F00 – 0000 5FFF
C GPIO Group 1 Registers (1)
0000 6000 – 0000 63FF
Reserved
no
0000 6400 – 0000 641F
COMP1 Registers
64
no
0000 6420 – 0000 643F
COMP2 Registers
64
no
0000 6440 – 0000 645F
COMP3 Registers
64
no
0000 6460 – 0000 647F
COMP4 Registers
64
no
0000 6480 – 0000 649F
COMP5 Registers
64
no
0000 64A0 – 0000 64BF
COMP6 Registers
64
0000 64C0 – 0000 6F7F
Reserved
0000 6F80 – 0000 6FFF
C GPIO Group 2 Registers and AIO Mux Registers (1)
no
no
no
(1)
CONTROL SUBSYSTEM PERIPHERAL FRAME 1
SIZE
(BYTES)
512
256
The letter "C" refers to the Control Subsystem.
Table 6-5. Control Subsystem Peripheral Frame 2
C DMA ACCESS (1)
CONTROL SUBSYSTEM PERIPHERAL FRAME 2
SIZE
(BYTES)
0000 7000 – 0000 70FF
Reserved
0000 7010 – 0000 702F
C28x System Control Registers
0000 7030 – 0000 703F
Reserved
no
0000 7040 – 0000 704F
SPI-A
32
no
0000 7050 – 0000 705F
SCI-A
32
no
0000 7060 – 0000 706F
NMI Watchdog Interrupt Registers
32
no
0000 7070 – 0000 707F
External Interrupt Registers
32
0000 7080 – 0000 70FF
Reserved
no
0000 7100 – 0000 717F
ADC1 Configuration Registers
(Only 16-bit read/write access supported)
256
no
0000 7180 – 0000 71FF
ADC2 Configuration Registers
(Only 16-bit read/write access supported)
256
0000 7200 – 0000 78FF
Reserved
0000 7900 – 0000 793F
I2C-A
0000 7940 – 0000 7FFF
Reserved
no
no
(1)
C ADDRESS
(x16 ALIGNED) (1)
64
128
The letter "C" refers to the Control Subsystem.
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Table 6-6. Control Subsystem RAMs
C DMA ACCESS (1)
C ADDRESS
(x16 ALIGNED) (1)
M ADDRESS
(BYTE-ALIGNED) (2)
µDMA
ACCESS
no
0000 8000 – 0000 8FFF
L0 RAM (ECC, Secure)
8K
no
0000 9000 – 0000 9FFF
L1 RAM (ECC, Secure)
8K
yes
0000 A000 – 0000 AFFF
L2 RAM (Parity)
8K
yes
0000 B000 – 0000 BFFF
L3 RAM (Parity)
8K
yes
0000 C000 – 0000 CFFF
S0 RAM (Parity, Shared)
8K
2000 8000 – 2000 9FFF
yes
yes
0000 D000 – 0000 DFFF
S1 RAM (Parity, Shared)
yes
0000 E000 – 0000 EFFF
S2 RAM (Parity, Shared)
8K
2000 A000 – 2000 BFFF
yes
8K
2000 C000 – 2000 DFFF
yes
0000 F000 – 0000 FFFF
yes
S3 RAM (Parity, Shared)
8K
2000 E000 – 2000 FFFF
yes
yes
0001 0000 – 0001 0FFF
S4 RAM (Parity, Shared)
8K
2001 0000 – 2001 1FFF
yes
yes
0001 1000 – 0001 1FFF
S5 RAM (Parity, Shared)
8K
2001 2000 – 2001 3FFF
yes
yes
0001 2000 – 0001 2FFF
S6 RAM (Parity, Shared)
8K
2001 4000 – 2001 5FFF
yes
yes
0001 3000 – 0001 3FFF
S7 RAM (Parity, Shared)
8K
2001 6000 – 2001 7FFF
yes
0001 4000 – 0003 F7FF
Reserved
yes
0003 F800 – 0003 FBFF
CtoM MSG RAM (Parity)
2K
2007 F000 – 2007 F7FF
yes
read only
yes
read only
0003 FC00 – 0003 FFFF
MtoC MSG RAM (Parity)
2K
2007 F800 – 2007 FFFF
yes
0004 0000 – 0004 7FFF
Reserved
0004 8000 – 0004 8FFF
L0 RAM - ECC Bits
8K
no
0004 9000 – 0004 9FFF
L1 RAM - ECC Bits
8K
no
0004 A000 – 0004 AFFF
L2 RAM - Parity Bits
8K
no
0004 B000 – 0004 BFFF
L3 RAM - Parity Bits
8K
no
0004 C000 – 0004 CFFF
S0 RAM - Parity Bits
8K
2008 8000 – 2008 9FFF
no
no
0004 D000 – 0004 DFFF
S1 RAM - Parity Bits
8K
2008 A000 – 2008 BFFF
no
no
0004 E000 – 0004 EFFF
S2 RAM - Parity Bits
8K
2008 C000 – 2008 DFFF
no
no
0004 F000 – 0004 FFFF
S3 RAM - Parity Bits
8K
2008 E000 – 2008 FFFF
no
no
0005 0000 – 0005 0FFF
S4 RAM - Parity Bits
8K
2009 0000 – 2009 1FFF
no
no
0005 1000 – 0005 1FFF
S5 RAM - Parity Bits
8K
2009 2000 – 2009 3FFF
no
no
0005 2000 – 0005 2FFF
S6 RAM - Parity Bits
8K
2009 4000 – 2009 5FFF
no
8K
2009 6000 – 2009 7FFF
no
no
no
164
SIZE
(BYTES)
0005 3000 – 0005 3FFF
S7 RAM - Parity Bits
0005 4000 – 0007 EFFF
Reserved
0007 F000 – 0007 F3FF
M0 RAM - ECC Bits
2K
no
0007 F400 – 0007 F7FF
M1 RAM - ECC Bits
2K
no
0007 F800 – 0007 FBFF
CtoM MSG RAM - Parity Bits
2K
200F F000 – 200F F7FF
no
no
0007 FC00 – 0007 FFFF
MtoC MSG RAM - Parity Bits
2K
200F F800 – 200F FFFF
no
0008 0000 – 0009 FFFF
Reserved
no
(1)
(2)
CONTROL SUBSYSTEM
RAMS
The letter "C" refers to the Control Subsystem.
The letter "M" refers to the Master Subsystem.
Detailed Description
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 6-7. Control Subsystem Flash, ECC, OTP, Boot ROM
CONTROL SUBSYSTEM
FLASH, ECC, OTP,
BOOT ROM
C DMA ACCESS (1)
C ADDRESS
(x16 ALIGNED) (1)
no
0010 0000 – 0010 1FFF
Sector N
16K
no
0010 2000 – 0010 3FFF
Sector M
16K
no
0010 4000 – 0010 5FFF
Sector L
16K
no
0010 6000 – 0010 7FFF
Sector K
16K
no
0010 8000 – 0010 FFFF
Sector J
64K
no
0011 0000 – 0011 7FFF
Sector I
64K
no
0011 8000 – 0011 FFFF
Sector H
64K
no
0012 0000 – 0012 7FFF
Sector G
64K
no
0012 8000 – 0012 FFFF
Sector F
64K
no
0013 0000 – 0013 7FFF
Sector E
64K
no
0013 8000 – 0013 9FFF
Sector D
16K
no
0013 A000 – 0013 BFFF
Sector C
16K
no
0013 C000 – 0013 DFFF
Sector B
16K
0013 E000 – 0013 FFFF
Sector A
(CSM password in the high
address)
16K
0014 0000 – 001F FFFF
Reserved
0020 0000 – 0020 7FFF
Flash - ECC Bits
(1/8 of Flash used = 64KB)
0020 8000 – 0024 01FF
Reserved
0024 0200 – 0024 03FF
TI one-time programmable
(OTP) memory
0024 0400 – 002F FFFF
Reserved
yes
0030 0000 – 003F 7FFF
EPI0
(External Peripheral/Memory
Interface) (3)
no
003F 8000 – 003F FFFF
C28x Boot ROM (64KB)
no
no
no
(1)
(2)
(3)
(4)
The
The
The
The
SIZE
(BYTES)
M ADDRESS
(BYTE-ALIGNED) (2)
µDMA
ACCESS
6000 0000 – DFFF FFFF
yes
64K
1K
2M (4)
64K
letter "C" refers to the Control Subsystem.
letter "M" refers to the Master Subsystem.
Control Subsystem has no direct access to EPI in silicon revision 0 devices.
Control Subsystem has less address reach to EPI memory than the Master Subsystem.
Detailed Description
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6.1.2
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Master Subsystem Memory Map
Table 6-8. Master Subsystem Flash, ECC, OTP, Boot ROM
µDMA ACCESS
M ADDRESS
(BYTE-ALIGNED) (1)
no
0000 0000 – 0000 FFFF
Boot ROM - Dual-mapped to 0x0100 0000
(Both maps access same physical location.)
0001 0000 – 001F FFFF
Reserved
no
0020 0000 – 0020 7FFF
Sector N
(Zone 1 CSM password in the low address.)
32K
no
0020 8000 – 0020 FFFF
Sector M
32K
no
0021 0000 – 0021 7FFF
Sector L
32K
no
0021 8000 – 0021 FFFF
Sector K
32K
no
0022 0000 – 0023 FFFF
Sector J
128K
no
0024 0000 – 0025 FFFF
Sector I (not available for 512KB Flash configuration)
128K
no
0026 0000 – 0027 FFFF
Sector H (not available for 512KB Flash configuration)
128K
no
0028 0000 – 0029 FFFF
Sector G (not available for 512KB Flash configuration)
128K
no
002A 0000 – 002B FFFF
Sector F (not available for 512KB Flash configuration)
128K
no
002C 0000 – 002D FFFF
Sector E
128K
no
002E 0000 – 002E 7FFF
Sector D
32K
no
002E 8000 – 002E FFFF
Sector C
32K
no
002F 0000 – 002F 7FFF
Sector B
32K
002F 8000 – 002F FFFF
Sector A
(Zone 2 CSM password in the high address.)
32K
0030 0000 – 005F FFFF
Reserved
0060 0000 – 0061 FFFF
Flash - ECC Bits
(1/8 of Flash used = 128KB)
0062 0000 – 0068 047F
Reserved
no
0068 0480 – 0068 080F
TI OTP
no
0068 0810 – 0068 0813
OTP – Ethernet Media Access Controller (EMAC) Address 0
no
0068 0814 – 0068 0817
OTP – Ethernet Media Access Controller (EMAC) Address 1
no
0068 0818 – 0068 0FFF
TI OTP
no
no
no
166
4
4
2024
OTP – Security Lock
Reserved
no
0068 100C – 0068 100F
OTP – Zone 2 Flash Start Address
0068 1010 – 0068 101B
Reserved
no
0068 101C – 0068 101F
OTP – Main Oscillator Clock Frequency
0068 1020 – 0068 102B
Reserved
0068 102C – 0068 102F
OTP ENTRY POINT
0068 1030 – 0070 01FF
Reserved
0070 0200 – 0070 0203
OTP – ECC Bits – Application Use
(1/8 of OTP used = 3 Bytes)
0070 0204 – 00FF FFFF
Reserved
0100 0000 – 0100 FFFF
Boot ROM – Dual-mapped to 0x0000 0000
(Both maps access same physical location.)
0101 0000 – 03FF FFFF
Reserved
no
64K
912
0068 1000 – 0068 1003
no
SIZE
(BYTES)
128K
0068 1004 – 0068 100B
no
(1)
MASTER SUBSYSTEM FLASH, ECC, OTP, BOOT ROM
4
4
4
4
4
64K
The letter "M" refers to the Master Subsystem.
Detailed Description
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 6-8. Master Subsystem Flash, ECC, OTP, Boot ROM (continued)
µDMA ACCESS
no
M ADDRESS
(BYTE-ALIGNED) (1)
MASTER SUBSYSTEM FLASH, ECC, OTP, BOOT ROM
0400 0000 – 07FF FFFF
ROM/Flash/OTP/Boot ROM – Mirror-mapped for µCRC.
Accessing this area of memory by the µCRC peripheral will
cause an access in 0000 0000 – 03FF FFFF memory space.
Mirrored boot ROM: 0x0400 0000 – 0x0400 FFFF (Not dualmapped ROM address)
Mirrored Flash bank: 0x0420 0000 – 0x042F FFFF
Mirrored Flash OTP: 0x0468 0000 – 0x0468 1FFF
(Read cycles from this space cause the µCRC peripheral to
continuously update data checksum inside a register, when
reading a block of data.)
0800 0000 – 1FFF FFFF
Reserved
SIZE
(BYTES)
64M
Table 6-9. Master Subsystem RAMs
µDMA
ACCESS
M ADDRESS
(BYTE-ALIGNED) (1)
C ADDRESS
(x16 ALIGNED) (2)
C DMA ACCESS (2)
no
2000 0000 – 2000 1FFF
C0 RAM (ECC, Secure)
8K
no
2000 2000 – 2000 3FFF
C1 RAM (ECC, Secure)
8K
yes
2000 4000 – 2000 5FFF
C2 RAM (Parity)
8K
yes
2000 6000 – 2000 7FFF
C3 RAM (Parity)
8K
yes
2000 8000 – 2000 9FFF
S0 RAM (Parity, Shared)
yes
2000 A000 – 2000 BFFF
S1 RAM (Parity, Shared)
8K
0000 C000 – 0000 CFFF
yes
8K
0000 D000 – 0000 DFFF
yes
2000 C000 – 2000 DFFF
yes
S2 RAM (Parity, Shared)
8K
0000 E000 – 0000 EFFF
yes
yes
yes
2000 E000 – 2000 FFFF
S3 RAM (Parity, Shared)
8K
0000 F000 – 0000 FFFF
yes
2001 0000 – 2001 1FFF
S4 RAM (Parity, Shared)
8K
0001 0000 – 0001 0FFF
yes
yes
2001 2000 – 2001 3FFF
S5 RAM (Parity, Shared)
8K
0001 1000 – 0001 1FFF
yes
yes
2001 4000 – 2001 5FFF
S6 RAM (Parity, Shared)
8K
0001 2000 – 0001 2FFF
yes
yes
2001 6000 – 2001 7FFF
S7 RAM (Parity, Shared)
8K
0001 3000 – 0001 3FFF
yes
yes
2001 8000 – 2001 9FFF
C4 RAM (Parity)
8K
yes
2001 A000 – 2001 BFFF
C5 RAM (Parity)
8K
yes
2001 C000 – 2001 DFFF
C6 RAM (Parity)
8K
yes
2001 E000 – 2001 FFFF
C7 RAM (Parity)
8K
yes
2002 0000 – 2002 1FFF
C8 RAM (Parity)
8K
yes
2002 2000 – 2002 3FFF
C9 RAM (Parity)
8K
yes
2002 4000 – 2002 5FFF
C10 RAM (Parity)
8K
yes
2002 6000 – 2002 7FFF
C11 RAM (Parity)
8K
yes
2002 8000 – 2002 9FFF
C12 RAM (Parity)
8K
yes
2002 A000 – 2002 BFFF
C13 RAM (Parity)
8K
yes
2002 C000 – 2002 DFFF
C14 RAM (Parity)
8K
yes
2002 E000 – 2002 FFFF
C15 RAM (Parity)
8K
2003 0000 – 2007 EFFF
Reserved
yes
read only
2007 F000 – 2007 F7FF
CtoM MSG RAM (Parity)
2K
0003 F800 – 0003 FBFF
yes
yes
2007 F800 – 2007 FFFF
MtoC MSG RAM (Parity)
2K
0003 FC00 – 0003 FFFF
yes
read only
no
2008 0000 – 2008 1FFF
C0 RAM - ECC Bits
8K
no
2008 2000 – 2008 3FFF
C1 RAM - ECC Bits
8K
no
2008 4000 – 2008 5FFF
C2 RAM - Parity Bits
8K
no
2008 6000 – 2008 7FFF
C3 RAM - Parity Bits
8K
no
2008 8000 – 2008 9FFF
S0 RAM - Parity Bits
8K
0004 C000 – 0004 CFFF
no
(1)
(2)
MASTER SUBSYSTEM RAMS
SIZE
(BYTES)
The letter "M" refers to the Master Subsystem.
The letter "C" refers to the Control Subsystem.
Detailed Description
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Table 6-9. Master Subsystem RAMs (continued)
µDMA
ACCESS
MASTER SUBSYSTEM RAMS
SIZE
(BYTES)
C ADDRESS
(x16 ALIGNED) (2)
C DMA ACCESS (2)
no
2008 A000 – 2008 BFFF
S1 RAM - Parity Bits
8K
0004 D000 – 0004 DFFF
no
no
2008 C000 – 2008 DFFF
S2 RAM - Parity Bits
8K
0004 E000 – 0004 EFFF
no
no
2008 E000 – 2008 FFFF
S3 RAM - Parity Bits
8K
0004 F000 – 0004 FFFF
no
no
2009 0000 – 2009 1FFF
S4 RAM - Parity Bits
8K
0005 0000 – 0005 0FFF
no
no
2009 2000 – 2009 3FFF
S5 RAM - Parity Bits
8K
0005 1000 – 0005 1FFF
no
no
2009 4000 – 2009 5FFF
S6 RAM - Parity Bits
8K
0005 2000 – 0005 2FFF
no
no
2009 6000 – 2009 7FFF
S7 RAM - Parity Bits
8K
0005 3000 – 0005 3FFF
no
no
2009 8000 – 2009 9FFF
C4 RAM - Parity Bits
8K
no
2009 A000 – 2009 BFFF
C5 RAM - Parity Bits
8K
no
2009 C000 – 2009 DFFF
C6 RAM - Parity Bits
8K
no
2009 E000 – 2009 FFFF
C7 RAM - Parity Bits
8K
no
200A 0000 – 200A 1FFF
C8 RAM - Parity Bits
8K
no
200A 2000 – 200A 3FFF
C9 RAM - Parity Bits
8K
no
200A 4000 – 200A 5FFF
C10 RAM - Parity Bits
8K
no
200A 6000 – 200A 7FFF
C11 RAM - Parity Bits
8K
no
200A 8000 – 200A 9FFF
C12 RAM - Parity Bits
8K
no
200A A000 – 200A BFFF
C13 RAM - Parity Bits
8K
no
200A C000 – 200A DFFF
C14 RAM - Parity Bits
8K
no
200A E000 – 200A FFFF
C15 RAM - Parity Bits
8K
200B 0000 – 200F EFFF
Reserved
no
200F F000 – 200F F7FF
CtoM MSG RAM - Parity Bits
2K
0007 F800 – 0007 FBFF
no
no
200F F800 – 200F FFFF
MtoC MSG RAM - Parity Bits
2K
0007 FC00 – 0007 FFFF
no
2010 0000 – 21FF FFFF
Reserved
2200 0000 – 23FF FFFF
Bit Banded RAM Zone
(Dedicated address for each
RAM bit of Cortex-M3 RAM
blocks above)
32M
2400 0000 – 27FF FFFF
All RAM Spaces – MirrorMapped for µCRC.
Accessing this memory by the
µCRC peripheral will cause an
access to
2000 0000 – 23FF FFFF
memory space.
(Read cycles from this space
cause the µCRC peripheral to
continuously update data
checksum inside a register
when reading a block of data.)
64M
2800 0000 – 3FFF FFFF
Reserved
yes
yes
168
M ADDRESS
(BYTE-ALIGNED) (1)
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 6-10. Master Subsystem Peripherals
µDMA
ACCESS
M ADDRESS
(BYTE-ALIGNED) (1)
yes
4000 0000 – 4000 0FFF
Watchdog Timer 0 Registers
4K
yes
4000 1000 – 4000 1FFF
Watchdog Timer 1 Registers
4K
SIZE
(BYTES)
4000 2000 – 4000 3FFF
Reserved
yes
4000 4000 – 4000 4FFF
M GPIO Port A (APB Bus) (1)
4K
yes
4000 5000 – 4000 5FFF
M GPIO Port B (APB Bus) (1)
4K
yes
4000 6000 – 4000 6FFF
M GPIO Port C (APB Bus)
(1)
4K
yes
4000 7000 – 4000 7FFF
M GPIO Port D (APB Bus) (1)
4K
yes
4000 8000 – 4000 8FFF
SSI0
4K
yes
4000 9000 – 4000 9FFF
SSI1
4K
yes
4000 A000 – 4000 AFFF
SSI2
4K
yes
4000 B000 – 4000 BFFF
SSI3
4K
yes
4000 C000 – 4000 CFFF
UART0
4K
yes
4000 D000 – 4000 DFFF
UART1
4K
yes
4000 E000 – 4000 EFFF
UART2
4K
yes
4000 F000 – 4000 FFFF
UART3
4K
4K
yes
4001 0000 – 4001 0FFF
UART4
4001 1000 – 4001 FFFF
Reserved
no
4002 0000 – 4002 07FF
I2C0 Master
2K
no
4002 0800 – 4002 0FFF
I2C0 Slave
2K
no
4002 1000 – 4002 17FF
I2C1 Master
2K
no
4002 1800 – 4002 1FFF
I2C1 Slave
2K
4002 2000 – 4002 3FFF
Reserved
yes
4002 4000 – 4002 4FFF
M GPIO Port E (APB Bus) (1)
4K
yes
4002 5000 – 4002 5FFF
M GPIO Port F (APB Bus) (1)
4K
yes
4002 6000 – 4002 6FFF
M GPIO Port G (APB Bus) (1)
4K
(1)
4K
yes
4002 7000 – 4002 7FFF
M GPIO Port H (APB Bus)
4002 8000 – 4002 FFFF
Reserved
yes
4003 0000 – 4003 0FFF
GP Timer 0
4K
yes
4003 1000 – 4003 1FFF
GP Timer 1
4K
yes
4003 2000 – 4003 2FFF
GP Timer 2
4K
yes
4003 3000 – 4003 3FFF
GP Timer 3
4K
4003 4000 – 4003 CFFF
Reserved
4003 D000 – 4003 DFFF
M GPIO Port J (APB Bus) (1)
4003 E000 – 4003 FFFF
Reserved
4004 8000 – 4004 8FFF
ENET MAC0
4004 9000 – 4004 FFFF
Reserved
4005 0000 – 4005 0FFF
USB MAC0
4005 1000 – 4005 7FFF
Reserved
4005 8000 – 4005 8FFF
M GPIO Port A (AHB Bus) (1)
4K
yes
4005 9000 – 4005 9FFF
M GPIO Port B (AHB Bus)
(1)
4K
yes
4005 A000 – 4005 AFFF
M GPIO Port C (AHB Bus) (1)
4K
yes
4005 B000 – 4005 BFFF
M GPIO Port D (AHB Bus) (1)
4K
yes
4005 C000 – 4005 CFFF
M GPIO Port E (AHB Bus)
(1)
4K
yes
4005 D000 – 4005 DFFF
M GPIO Port F (AHB Bus) (1)
4K
yes
4005 E000 – 4005 EFFF
M GPIO Port G (AHB Bus) (1)
4K
yes
yes
yes
yes
(1)
(2)
MASTER SUBSYSTEM
PERIPHERALS
C ADDRESS
(x16 ALIGNED) (2)
C DMA ACCESS (2)
4K
4K
4K
The letter "M" refers to the Master Subsystem.
The letter "C" refers to the Control Subsystem.
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www.ti.com
Table 6-10. Master Subsystem Peripherals (continued)
µDMA
ACCESS
M ADDRESS
(BYTE-ALIGNED) (1)
yes
4005 F000 – 4005 FFFF
M GPIO Port H (AHB Bus) (1)
4K
yes
4006 0000 – 4006 0FFF
M GPIO Port J (AHB Bus) (1)
4K
yes
4006 1000 – 4006 1FFF
M GPIO Port K (AHB Bus) (1)
4K
yes
4006 2000 – 4006 2FFF
M GPIO Port L (AHB Bus)
(1)
4K
yes
4006 3000 – 4006 3FFF
M GPIO Port M (AHB Bus) (1)
4K
yes
4006 4000 – 4006 4FFF
M GPIO Port N (AHB Bus) (1)
4K
yes
4006 5000 – 4006 5FFF
M GPIO Port P (AHB Bus) (1)
4K
yes
4006 6000 – 4006 6FFF
M GPIO Port Q (AHB Bus)
(1)
4K
yes
4006 7000 – 4006 7FFF
M GPIO Port R (AHB Bus) (1)
4K
yes
4006 8000 – 4006 8FFF
M GPIO Port S (AHB Bus) (1)
4K
SIZE
(BYTES)
4006 9000 – 4006 FFFF
Reserved
no
4007 0000 – 4007 3FFF
CAN0
16K
no
4007 4000 – 4007 7FFF
CAN1
16K
4007 8000 – 400C FFFF
Reserved
no
400D 0000 – 400D 0FFF
EPI0 (Registers only)
400D 1000 – 400F 9FFF
Reserved
400F A000 – 400F A303
M Flash Control Registers (1)
400F A304 – 400F A5FF
Reserved
400F A600 – 400F A647
M Flash ECC Error Log
Registers (1)
no
no
C ADDRESS
(x16 ALIGNED) (2)
C DMA ACCESS (2)
4K
772
72
400F A648 – 400F AFFF
Reserved
no
400F B000 – 400F B1FF
Reserved
no
400F B200 – 400F B2FF
RAM Configuration Registers
256
0000 4900 – 0000 497F
no
no
400F B300 – 400F B3FF
RAM ECC/Parity/Access Error
Log Registers
256
0000 4A00 – 0000 4A7F
no
128
0000 4E00 – 0000 4E3F
no
0000 4400 – 0000 443F
no
(1)
no
400F B400 – 400F B5FF
M CSM Registers
512
no
400F B600 – 400F B67F
µCRC
128
400F B680 – 400F B6FF
Reserved
400F B700 – 400F B77F
CtoM and MtoC IPC Registers
400F B780 – 400F B7FF
Reserved
no
400F B800 – 400F B87F
M Clock Control Registers(1)
128
no
400F B880 – 400F B8BF
M LPM Control Registers(1)
64
no
400F B8C0 – 400F B8FF
M Reset Control Registers(1)
64
no
400F B900 – 400F B93F
Device Configuration Registers
64
400F B940 – 400F B97F
Reserved
no
400F B980 – 400F B9FF
M Write Protect Registers(1)
no
no
no
no
yes
170
MASTER SUBSYSTEM
PERIPHERALS
(1)
400F BA00 – 400F BA7F
M NMI Registers
400F BA80 – 400F BAFF
Reserved
400F BB00 – 400F BBFF
Reserved
400F BC00 – 400F EFFF
Reserved
400F F000 – 400F FFFF
µDMA Registers
4010 0000 – 41FF FFFF
Reserved
4200 0000 – 43FF FFFF
Bit Banded Peripheral Zone
(Dedicated address for each
register bit of Cortex-M3
peripherals above.)
4400 0000 – 4FFF FFFF
Reserved
Detailed Description
0000 0880 – 0000 0890
(Read Only)
128
128
4K
32M
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 6-11. Master Subsystem Analog and EPI
µDMA
ACCESS
yes
yes
yes
(1)
(2)
(3)
(4)
The
The
The
The
M ADDRESS
(BYTE-ALIGNED) (1)
MASTER SUBSYSTEM
ANALOG AND EPI
5000 0000 – 5000 15FF
Reserved
5000 1600 – 5000 161F
ADC1 Result Registers
5000 1620 – 5000 167F
Reserved
5000 1680 – 5000 169F
ADC2 Result Registers
5000 16A0 – 5FFF FFFF
Reserved
6000 0000 – DFFF FFFF
EPI0
(External Peripheral/Memory
Interface)
SIZE
(BYTES)
C ADDRESS
(x16 ALIGNED) (2)
C DMA ACCESS (2)
0030 0000 – 003F 7FFF (3) (4)
yes
32
32
2G
letter "M" refers to the Master Subsystem.
letter "C" refers to the Control Subsystem.
Control Subsystem has no direct access to EPI in silicon revision 0 devices.
Control Subsystem has less address reach to EPI memory than the Master Subsystem.
Table 6-12. Cortex-M3 Private Bus
µDMA
ACCESS
Cortex-M3 ADDRESS
(BYTE-ALIGNED)
no
E000 0000 – E000 0FFF
ITM (Instrumentation Trace Macrocell)
4K
no
E000 1000 – E000 1FFF
DWT (Data Watchpoint and Trace)
4K
no
E000 2000 – E000 2FFF
FPB (Flash Patch and Breakpoint)
4K
E000 3000 – E000 E007
Reserved
E000 E008 – E000 E00F
System Control Block
8
16
no
no
no
no
no
no
Cortex-M3 PRIVATE BUS
E000 E010 – E000 E01F
System Timer
E000 E020 – E000 E0FF
Reserved
E000 E100 – E000 E4EF
Nested Vectored Interrupt Controller (NVIC)
E000 E4F0 – E000 ECFF
Reserved
E000 ED00 – E000 ED3F
System Control Block
E000 ED40 – E000 ED8F
Reserved
E000 ED90 – E000 EDB8
Memory Protection Unit
E000 EDB9 – E000 EEFF
Reserved
E000 EF00 – E000 EF03
Nested Vectored Interrupt Controller
E000 EF04 – FFFF FFFF
Reserved
SIZE
(BYTES)
1008
64
41
4
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6.2
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Identification
Table 6-13. Device Identification Registers
NAME
C ADDRESS
(x16 ALIGNED) (1)
DID0.REVID
M ADDRESS
(BYTE ALIGNED) (2)
400F E000 – 400F E001
REVID
0x0000 0883
DID1.PARTNO
0x0000 0882
Device Identification 0 Register - Revision_ID
REVID - Current Revision ID of device
400F E006
PARTID.PARTNO
DESCRIPTION
Silicon Revision Number
REVID
0
0x0000
A
0x0001
B
0x0001
E
0x0005
F
0x0005
Device Identification 1 Register - Part_Number
C28x Device PARTID Register - Device Part Number
Device
(1)
(2)
172
PARTNO (M3/C28x)
F28M36P63C2
0xFF
F28M36P53C2
0xFA
F28M36H53B2
0xEC
F28M36H33B2
0xE8
The letter "C" refers to the Control Subsystem.
The letter "M" refers to the Master Subsystem.
Detailed Description
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6.3
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Master Subsystem
The Master Subsystem includes the Cortex-M3 CPU, µDMA, Nested Vectored Interrupt Controller (NVIC),
Cortex-M3 Peripherals, and Local Memory. Additionally, the Cortex-M3 CPU and µDMA can access the
Control Subsystem through Shared Resources: IPC (CPU only), Message RAM, and Shared RAM; and
read ADC Result Registers through the Analog Common Interface Bus. The Master Subsystem can also
receive events from the NMI block and send events to the Resets block.
Figure 6-1 shows the Master Subsystem.
6.3.1
Cortex-M3 CPU
The 32-bit Cortex-M3 processor offers high performance, fast interrupt handling, and access to a variety of
communication peripherals (including Ethernet and USB). The Cortex-M3 features a Memory Protection
Unit (MPU) to provide a privileged mode for protected operating system functionality. A bus bridge
adjacent to the MPU can route program instructions and data on the I-CODE and D-CODE buses that
connect to the Boot ROM and Flash. Other data is typically routed through the Cortex-M3 System Bus
connected to the local RAMs. The System Bus also goes to the Shared Resources block (also accessible
by the Control Subsystem) and to the Analog Subsystem through the ACIB. Another bus bridge allows bus
cycles from both the Cortex-M3 System Bus and those of the µDMA bus to access the Master Subsystem
peripherals (through the APB bus or the AHP bus).
Most of the interrupts to the Cortex-M3 CPU come from the NVIC, which manages the interrupt requests
from peripherals and assigns handling priorities. There are also several exceptions generated by CortexM3 CPU that can return to the Cortex-M3 as interrupts after being prioritized with other requests inside the
NVIC. In addition to programmable priority interrupts, there are also three levels of fixed-priority interrupts
of which the highest priority, level-3, is given to M3PORRST and M3SYSRST resets from the Resets
block. The next highest priority, level-2, is assigned to the M3NMIINT, which originates from the NMI
block. The M3HRDFLT (Hard Fault) interrupt is assigned to level-1 priority, and this interrupt is caused by
one of the error condition exceptions (Memory Management, Bus Fault, Usage Fault) escalating to Hard
Fault because they are not enabled or not properly serviced.
The Cortex-M3 CPU has two low-power modes: Sleep and Deep Sleep.
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M3PORRST
M3 NMI
RESETS
M3SYSRST
M3NMIINT
M3NMIINT
M3NMIRST
M3NMI
M3NMIINT
M3WDRST
(1:0)
NVIC
M3HRDFLT
3
2
FIXED
PRIORITY
INTERRUPTS
1
M3 PERIPHERALS
M3SWRST
WDOG (2)
uCRC
NMI WDOG
GP TIMER (4)
SSI (4)
2
CAN (2)
UART (5)
I C (2)
EMAC
USB + PHY
(OTG)
EPI
GPIO_MUX1
PERIPHERAL
I/O s
M3DBGRST
EOC INTERRUPTS
ANALOG SUBSYSTEM
APB BUS
AHB BUS
EPI
REQ
USB
MAC
REQ
EMACRX
EMACTX
REQ
UART
(5:1)
REQ
uDMA
ADC
INT
(8:1)
GPIO
(S:A)
IRQ
EPI
IRQ
USB
MAC
IRQ
EMAC
IRQ
I2C
(1:0)
IRQ
M3
CPU
GPTA/B
(3:0)
(3:0)
REQ
SSI
(3:0)
REQ
BUS
MATRIX
DMA INTRS
CAN0/1
(1:0)
(1:0)
IRQ
UART
(1:5)
IRQ
SSI
(0:3)
IRQ
GPTA/B
(3:0)
(3:0)
IRQ
DMA
ERR
IRQ
DMA
SW
IRQ
WDT
(1:0)
IRQ
NVIC
(NESTED VECTORED INTERRUPT CONTROLLER)
FLFSM
INTERRUPTS
CTOM IPC (4:1)
APB BUS (REG ACCESS ONLY)
uDMA BUS
M3 SYSTEM BUS
MEMORY MNGMT
FLSINGER
RAMSINGERR
USAGE FAULT
SVCALL
DBG MONITOR
PENDING SV
SYS TICK
EXCEPTIONS
FROM M3 CORE
PROGRAMMABLE
PRIORITY
INTERRUPTS
LOCAL MEMORY
SECURE
C0/C1
RAM
(ECC)
C2 - C15
RAM
(parity)
BOOT
ROM
SECURE
FLASH
(ECC)
IPC
REGS
S0-S7
SHARED
RAM
(parity)
MTOC
MSG
RAM
(parity)
CTOM
MSG
RAM
(parity)
SHARED RESOURCES
FREQ
GASKET
MPU /
BRIDGE
BUS
BRIDGE
DATA
INSTRUCTIONS
I-CODE BUS
D-CODE BUS
RAMACCVIOL
RAMUNCERR
FLASHUNCERR
RAMUNCERR
CONTROL SUBSYSTEM
BUS CNTRL/FAULT LOGIC
BUSFAULT
Figure 6-1. Master Subsystem
174
Detailed Description
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6.3.2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Cortex-M3 DMA and NVIC
The Cortex-M3 direct memory access (µDMA) module provides a hardware method of transferring data
between peripherals, between memory, and between peripherals and memory without intervention from
the Cortex-M3 CPU. The NVIC manages and prioritizes interrupt handling for the Cortex-M3 CPU.
The Cortex-M3 peripherals use REQ/DONE handshaking to coordinate data transfer requests with the
µDMA. If a DMA channel is enabled for a given peripheral, REQ/DONE from the peripheral will trigger the
data transfer, following which an IRQ request may be sent from the µDMA to the NVIC to announce to the
Cortex-M3 that the transfer has completed. If a DMA channel is not enabled for a given peripheral,
REQ/DONE will directly drive IRQ to the NVIC so that the Cortex-M3 CPU can transfer the data. For those
peripherals that are not supported by the µDMA, IRQs are supplied directly to the NVIC, bypassing the
DMA. This case is true for both Watchdogs, CANs, I2Cs, and the Analog-to-Digital Converters sending
ADCINT[8:1] interrupts from the Analog Subsystem. The NMI Watchdog does not send any events to the
µDMA or the NVIC (only to the Resets block).
6.3.3
Cortex-M3 Interrupts
Table 6-14 shows all interrupt assignments for the Cortex-M3 processor. Most interrupts (16–107) are
associated with interrupt requests from Cortex-M3 peripherals. The first 15 interrupts (1–15) are processor
exceptions generated by the Cortex-M3 core itself. These processor exceptions are detailed in Table 6-15.
Table 6-14. Interrupts from NVIC to Cortex-M3
INTERRUPT NUMBER
(BIT IN INTERRUPT
REGISTERS)
VECTOR NUMBER
VECTOR ADDRESS OR
OFFSET
–
0–15
0x0000.0000–0x0000.003C
0
16
0x0000.0040
GPIO Port A
1
17
0x0000.0044
GPIO Port B
2
18
0x0000.0048
GPIO Port C
3
19
0x0000.004C
GPIO Port D
4
20
0x0000.0050
GPIO Port E
5
21
0x0000.0054
UART0
6
22
0x0000.0058
UART1
7
23
0x0000.005C
SSI0
8
24
0x0000.0060
I2C0
9–17
25–33
–
18
34
0x0000.0088
Watchdog Timers 0 and 1
19
35
0x0000.008C
Timer 0A
20
36
0x0000.0090
Timer 0B
21
37
0x0000.0094
Timer 1A
22
38
0x0000.0098
Timer 1B
23
39
0x0000.009C
Timer 2A
24
40
0x0000.00A0
Timer 2B
25–27
41–43
–
Reserved
28
44
0x0000.00B0
29
45
–
30
46
0x0000.00B8
GPIO Port F
31
47
0x0000.00BC
GPIO Port G
32
48
0x0000.00C0
GPIO Port H
33
49
0x0000.00C4
UART2
34
50
0x0000.00C8
SSI1
35
51
0x0000.00CC
Timer 3A
DESCRIPTION
Processor exceptions
Reserved
System Control
Reserved
Detailed Description
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Table 6-14. Interrupts from NVIC to Cortex-M3 (continued)
176
INTERRUPT NUMBER
(BIT IN INTERRUPT
REGISTERS)
VECTOR NUMBER
VECTOR ADDRESS OR
OFFSET
36
52
0x0000.00D0
Timer 3B
37
53
0x0000.00D4
I2C1
38–41
54–57
–
42
58
0x0000.00E8
Ethernet Controller
44
60
0x0000.00F0
USB
45
61
–
46
62
0x0000.00F8
µDMA Software
47
63
0x0000.00FC
µDMA Error
48–52
64–68
–
53
69
0x0000.0114
EPI
54
70
0x0000.0118
GPIO Port J
55
71
0x0000.011C
GPIO Port K
56
72
0x0000.0120
GPIO Port L
57
73
0x0000.0124
SSI 2
58
74
0x0000.0128
SSI 3
59
75
0x0000.012C
UART3
UART4
DESCRIPTION
Reserved
Reserved
Reserved
60
76
0x0000.0130
61–63
77–79
–
64
80
0x0000.0140
CAN0 INT0
65
81
0x0000.0144
CAN0 INT1
66
82
0x0000.0148
CAN1 INT0
67
83
0x0000.014C
CAN1 INT1
68–71
84–87
–
Reserved
72
88
0x0000.0160
ADCINT1
73
89
0x0000.0164
ADCINT2
74
90
0x0000.0168
ADCINT3
75
91
0x0000.016C
ADCINT4
76
92
0x0000.0170
ADCINT5
77
93
0x0000.0174
ADCINT6
78
94
0x0000.0178
ADCINT7
79
95
0x0000.017C
ADCINT8
80
96
0x0000.0180
CTOMIPC1
81
97
0x0000.0184
CTOMIPC2
82
98
0x0000.0188
CTOMIPC3
83
99
0x0000.018C
CTOMIPC4
84–87
100–103
–
88
104
0x0000.01A0
RAM Single Error
89
105
0x0000.01A4
System / USB PLL Out of Lock
90
106
0x0000.01A8
M3 Flash Single Error
Reserved
Reserved
91
107
0x0000.01AC
Reserved
92–110
108–126
–
Reserved
111
127
0x0000.01FC
GPIO Port M
GPIO Port N
112
128
0x0000.0200
113–115
129–131
–
116
132
0x0000.0210
117–123
133–139
–
Detailed Description
Reserved
GPIO Port P
Reserved
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Table 6-14. Interrupts from NVIC to Cortex-M3 (continued)
INTERRUPT NUMBER
(BIT IN INTERRUPT
REGISTERS)
VECTOR NUMBER
VECTOR ADDRESS OR
OFFSET
DESCRIPTION
124
140
0x0000.0230
125–131
141–147
–
GPIO Port Q
132
148
0x0000.0250
GPIO Port R
133
149
0x0000.0254
GPIO Port S
Reserved
Table 6-15. Exceptions from Cortex-M3 Core to NVIC
EXCEPTION TYPE
–
Reset
Nonmaskable Interrupt
(NMI)
Hard Fault
Memory Management
PRIORITY (1)
VECTOR NUMBER
VECTOR ADDRESS OR
OFFSET
ACTIVATION
–
0
0x0000.0000
Stack top is loaded from
the first entry of the vector
table on reset.
–3 (highest)
1
0x0000.0004
Asynchronous
–2
2
0x0000.0008
Asynchronous
On Concerto devices
activated by clock fail
condition, C28 PIE error,
external M3GPIO NMI
input signal, and C28 NMI
WD time-out reset.
–1
3
0x0000.000C
–
programmable
4
0x0000.0010
Synchronous
5
0x0000.0014
Synchronous when
precise and asynchronous
when imprecise.
On Concerto devices
activated by memory
access errors and RAM
and flash uncorrectable
data errors.
Synchronous
Bus Fault
programmable
Usage Fault
programmable
6
0x0000.0018
–
7–10
–
SVCall
programmable
11
0x0000.002C
Synchronous
Debug Monitor
programmable
12
0x0000.0030
Synchronous
–
13
–
PendSV
programmable
14
0x0000.0038
Asynchronous
SysTick
programmable
15
0x0000.003C
Asynchronous
Interrupts
programmable
16 and above
0x0000.0040 and above
Asynchronous
–
–
(1)
Reserved
Reserved
0 is the default priority for all the programmable priorities
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6.3.4
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Cortex-M3 Vector Table
Each peripheral interrupt of Table 6-14 is assigned an address offset containing the location of the
peripheral interrupt handler (relative to the vector table base) for that particular interrupt (vector numbers
16–107).
Similarly, each exception interrupt of Table 6-15 (including Reset) is also assigned an address offset
containing the location of the exception interrupt handler (relative to the vector table base) for that
particular interrupt (vector numbers 1–15).
In addition to interrupt vectors, the vector table also contains the initial stack pointer value at table
location 0.
Following system reset, the vector table base is fixed at address 0x0000.0000. Privileged software can
write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
memory location, in the range 0x0000 0200 to 0x3FFF FE00. When configuring the VTABLE register, the
offset must be aligned on a 512-byte boundary.
6.3.5
Cortex-M3 Local Peripherals
The Cortex-M3 local peripherals include two Watchdogs, an NMI Watchdog, four General-Purpose Timers,
four SSI peripherals, two CAN peripherals, five UARTs, two I2C peripherals, Ethernet, USB + PHY, EPI,
and µCRC (Cyclic Redundancy Check). The USB and EPI are accessible through the AHB Bus
(Advanced High-Performance Bus). The EPI peripheral is also accessible from the Control Subsystem.
The remaining peripherals are accessible through the APB Bus (Advanced Peripheral Bus). The APB and
AHB bus cycles originate from the CPU System Bus or the µDMA Bus through a bus bridge.
While the Cortex-M3 CPU has access to all the peripherals, the µDMA has access to most, with the
exception of the µCRC, Watchdogs, NMI Watchdog, CAN peripherals, and the I2C peripheral. The CortexM3 peripherals connect to the Concerto device pins through GPIO_MUX1. Most of the peripherals also
generate event signals for the µDMA and the NVIC. The Watchdogs receive M3SWRST from the NVIC
(triggered by software) and send M3WDRST[1:0] reset requests to the Reset block. The NMI Watchdog
receives the M3NMI event from the NMI block and sends the M3NMIRST request to the Resets block.
See Section 5.11 for more information on the Cortex-M3 peripherals.
6.3.6
Cortex-M3 Local Memory
The Local Memory includes Boot ROM; Secure Flash with ECC; Secure C0/C1 RAM with ECC; and
C2/C3 RAM with Parity Error Checking. The Boot ROM and Flash are both accessible through the ICODE and D-CODE Buses. Flash registers can also be accessed by the Cortex-M3 CPU through the
APB Bus. All Local Memory is accessible from the Cortex-M3 CPU; the C2/C3 RAM is also accessible by
the µDMA.
Two types of error correction events can be generated during access of the Local Memory: uncorrectable
errors and single errors. The uncorrectable errors (including one from the Shared Memories) generate a
Bus Fault Exception to the Cortex-M3 CPU. The less critical single errors go to the NVIC where they can
result in maskable interrupts to the Cortex-M3 CPU.
178
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6.3.7
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Cortex-M3 Accessing Shared Resources and Analog Peripherals
There are several memories, digital peripherals, and analog peripherals that can be accessed by both the
Master and Control Subsystems. They are grouped into Shared Resources and the Analog Subsystem.
The Shared Resources include the EPI, IPC registers, MTOC Message RAM, CTOM Message RAM, and
eight individually configurable Shared RAM blocks. The RAMs of the Shared Resources block have Parity
Error Checking.
The Message RAMs and the Shared RAMs can be accessed by the Cortex-M3 CPU and µDMA. The
MTOC Message RAM is intended for sending data from the Master Subsystem to the Control Subsystem,
having R/W access for the Cortex-M3/µDMA and read-only access for the C28x/DMA. The CTOM
Message RAM is intended for sending data from the Control Subsystem to the Master Subsystem, having
R/W access for the C28x/DMA and read-only access for the Cortex-M3/µDMA.
The IPC registers provide up to 32 handshaking channels to coordinate the transfer of data through the
Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the
Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays
associated with polling).
The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way;
however, the direction of the data flow can be individually set for each block to be from Master to Control
Subsystem or from Control to Master Subsystem.
The Analog Subsystem has ADC1, ADC2, and Analog Comparator peripherals that can be accessed
through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and
DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the
C28x CPU only. The Cortex-M3 CPU accesses the ACIB through the System Bus, and the µDMA through
the µDMA Bus. The ACIB arbitrates for access to the ADC and Analog Comparator registers between
CPU/DMA bus cycles of the Master Subsystem with those of the Control Subsystem. In addition to
managing bus cycles, the ACIB also transfers End-of-Conversion ADC interrupts to the Master Subsystem
(as well as to the Control Subsystem). The eight EOC sources from ADC1 and the eight EOC sources
from ADC2 are AND-ed together by the ACIB, with the resulting eight ADC interrupts going to destinations
in both the Master Subsystem and the Control Subsystem.
See Section 5.10 for more information on shared resources and analog peripherals.
6.4
Control Subsystem
The Control Subsystem includes the C28x CPU/FPU/VCU, Peripheral Interrupt Expansion (PIE) block,
DMA, C28x Peripherals, and Local Memory. Additionally, the C28x CPU and DMA have access to Shared
Resources: IPC (CPU only), Message RAM, and Shared RAM; and to Analog Peripherals through the
Analog Common Interface Bus.
Figure 6-2 shows the Control Subsystem.
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RAMUNCERR
RAMUNCERR
MASTER SUBSYSTEM
EPI
GPIO_MUX1
C28x NMI
ECCDBLERR
FLASHUNCERR
SHARED RESOURCES
FREQ
GASKET
BUS
BRIDGE
MTOC
MSG
RAM
(parity)
S0-S7
SHARED
RAM
(parity)
IPC
REGS
GPI (63:0)
C28x LOCAL MEMORY
CTOM
MSG
RAM
(parity)
MTOCIPC (4:1)
SECURE
FLASH
(ECC)
BOOT
ROM
FLFSM
FLSINGERR
RAMACCVIOL
ANALOG
SUBSYSTEM
SECURE
L0/L1
RAM
(ECC)
LPM WAKEUP
M0/M1
RAM
(ECC)
L2/L3
RAM
(parity)
RAMSINGERR
LVF
LPMWAKE
LUF
PIE (PERIPHERAL INTERRUPT EXPANSION)
C28x
FPU
PIEINTRS (12:1)
EOC INTERRUPTS
DINTCH (6:1)
ADCINT (8:1)
ADCINT (4:1)
MXINTA, MRINTA
I2CINT1A, I2CINT2A
SCIRXINTA, SCITXINTA
TINT 0,1,2
C28x
CPU
SOC TRIGGERS
C28x
DMA
TINT 0,1,2
SPIRXINTA, SPITXINTA
EQEP(3:1)INT
XINT 2
XINT 1,2,3
EPWM(12:1)INT
EPWM(12:1)TZINT
SOCA (9:1), SOCB(9:1)
SOCA (9:1), SOCB(9:1)
ECAP(6:1)INT
C28 DMA BUS
C28 CPU BUS
TINT1
C28x PERIPHERALS
TINT2
C28NMI
NMI
WDOG
TIMER (3)
XINT (3)
ECAP (6)
EQEP
ERR
EPWM
(12)
EQEP (3)
McBSP
SPI
SCI
2
IC
GPIO_MUX1
PERIPHERAL
I/O s
ECCDBLERR
C28x
VCU
C28NMIINT
EMUSTOP
PIENMIERR
SOCAO
SOCBO
GPIO_MUX1
SYNCO
CLOCKFAIL
M3 CLOCKS
GPTRIP
(12:1)
GPTRIP
(12:7)
GPTRIP
(6:4)
GPIO_MUX1
C28NMIRST
RESETS
M3 NMI
C28x NMI
Figure 6-2. Control Subsystem
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6.4.1
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
C28x CPU/FPU/VCU
The F28M36x Concerto MCU family is a member of the TMS320C2000 MCU platform. The Concerto
C28x CPU/FPU has the same 32-bit fixed-point architecture as TI's existing Entry performance MCUs,
combined with a single-precision (32-bit) IEEE 754 FPU of TI’s existing Premium performance MCUs.
Each F28M36x device is a very efficient C/C++ engine, enabling users to develop their system control
software in a high-level language. Each F28M36x device also enables math algorithms to be developed
using C/C++. The device is equally efficient at DSP math tasks and at system control tasks. The 32 × 32bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems
efficiently. With the addition of the fast interrupt response with automatic context save of critical registers,
the device is capable of servicing many asynchronous events with minimal latency. The device has an 8level-deep protected pipeline with pipelined memory accesses. This pipelining enables the device to
execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead
hardware minimizes the latency for conditional discontinuities. Special conditional store operations further
improve performance. The VCU extends the capabilities of the C28x CPU and C28x+FPU processors by
adding additional instructions to accelerate Viterbi, Complex Arithmetic, 16-bit FFTs, and CRC algorithms.
No changes have been made to existing instructions, pipeline, or memory bus architecture. Therefore,
programs written for the C28x are completely compatible with the C28x+VCU.
There are two events generated by the FPU block that go to the C28x PIE: LVF and LUV. Inside PIE,
these and other events from C28x peripherals and memories result in 12 PIE interrupts PIEINTS[12:1] into
the C28x CPU. The C28x CPU also receives three additional interrupts directly (instead of through PIE)
from Timer 1 (TINT1), from Timer 2 (TINT2), and from the NMI block (C28uNMIINT).
The C28x has two low-power modes: IDLE and STANDBY.
6.4.2
C28x Core Hardware Built-In Self-Test
The Concerto microcontroller C28x CPU core includes a HWBIST feature for testing the CPU core logic
for errors. Tests using HWBIST can be initiated through a software library provided by TI.
6.4.3
C28x Peripheral Interrupt Expansion
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F28M36x, 72 of the possible 96 interrupts are
used. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines
(INT1 to INT12). Each of 12 interrupt lines supports up to 8 simultaneously active interrupts. Each of the
96 interrupts has its own vector stored in a dedicated RAM block that can be overwritten by the user. The
vector is automatically fetched by the CPU on servicing the interrupt. Eight CPU clock cycles are needed
to fetch the vector and save critical CPU registers. Hence, the CPU can quickly respond to interrupt
events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be
enabled or disabled within the PIE block.
See Table 6-16 for PIE interrupt assignments.
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Table 6-16. PIE Peripheral Interrupts (1)
PIE INTERRUPTS
CPU INTERRUPTS
(1)
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
INT1
C28.LPMWAKE
(C28LPM)
0x0D4E
TINT0
(TIMER 0)
0x0D4C
Reserved
–
0x0D4A
XINT2
–
0x0D48
XINT1
–
0x0D46
Reserved
–
0x0D44
ADCINT2
(ADC)
0x0D42
ADCINT1
(ADC)
0x0D40
INT2
EPWM8_TZINT
(ePWM8)
0x0D5E
EPWM7_TZINT
(ePWM7)
0x0D5C
EPWM6_TZINT
(ePWM6)
0x0D5A
EPWM5_TZINT
(ePWM5)
0x0D58
EPWM4_TZINT
(ePWM4)
0x0D56
EPWM3_TZINT
(ePWM3)
0x0D54
EPWM2_TZINT
(ePWM2)
0x0D52
EPWM1_TZINT
(ePWM1)
0x0D50
INT3
EPWM8_INT
(ePWM8)
0x0D6E
EPWM7_INT
(ePWM7)
0x0D6C
EPWM6_INT
(ePWM6)
0x0D6A
EPWM5_INT
(ePWM5)
0x0D68
EPWM4_INT
(ePWM4)
0x0D66
EPWM3_INT
(ePWM3)
0x0D64
EPWM2_INT
(ePWM2)
0x0D62
EPWM1_INT
(ePWM1)
0x0D60
INT4
EPWM9_TZINT
(ePWM9)
0x0D7E
EPWM10_TZINT
(ePWM10)
0x0D7C
ECAP6_INT
(eCAP6)
0x0D7A
ECAP5_INT
(eCAP5)
0x0D78
ECAP4_INT
(eCAP4)
0x0D76
ECAP3_INT
(eCAP3)
0x0D74
ECAP2_INT
(eCAP2)
0x0D72
ECAP1_INT
(eCAP1)
0x0D70
INT5
EPWM9_INT
(ePWM9)
0x0D8E
EPWM10_INT
(ePWM10)
0x0D8C
Reserved
–
0x0D8A
Reserved
–
0x0D88
Reserved
–
0x0D86
EQEP3_INT
(eQEP3)
0x0D84
EQEP2_INT
(eQEP2)
0x0D82
EQEP1_INT
(eQEP1)
0x0D80
INT6
EPWM11_TZINT
(ePWM11)
0x0D9E
EPWM12_TZINT
(ePWM12)
0x0D9C
MXINTA
(McBSPA)
0x0D9A
MRINTA
(McBSPA)
0x0D98
Reserved
–
0x0D96
Reserved
–
0x0D94
SPITXINTA
(SPIA)
0x0D92
SPIRXINTA
(SPIA)
0x0D90
INT7
EPWM11_INT
(ePWM11)
0x0DAE
EPWM12_INT
(ePWM12)
0x0DAC
DINTCH6
(C28 DMA)
0x0DAA
DINTCH5
(C28 DMA)
0x0DA8
DINTCH4
(C28 DMA)
0x0DA6
DINTCH3
(C28 DMA)
0x0DA4
DINTCH2
(C28 DMA)
0x0DA2
DINTCH1
(C28 DMA)
0x0DA0
INT8
Reserved
–
0x0DBE
Reserved
–
0x0DBC
Reserved
–
0x0DBA
Reserved
–
0x0DB8
Reserved
–
0x0DB6
Reserved
–
0x0DB4
I2CINT2A
(I2CA)
0x0DB2
I2CINT1A
(I2CA)
0x0DB0
INT9
Reserved
–
0x0DCE
Reserved
–
0x0DCC
Reserved
–
0x0DCA
Reserved
–
0x0DC8
Reserved
–
0x0DC6
Reserved
–
0x0DC4
SCITXINTA
(SCIA)
0x0DC2
SCIRXINTA
(SCIA)
0x0DC0
INT10
ADCINT8
(ADC)
0x0DDE
ADCINT7
(ADC)
0x0DDC
ADCINT6
(ADC)
0x0DDA
ADCINT5
(ADC)
0x0DD8
ADCINT4
(ADC)
0x0DD6
ADCINT3
(ADC)
0x0DD4
ADCINT2
(ADC)
0x0DD2
ADCINT1
(ADC)
0x0DD0
INT11
Reserved
–
0x0DEE
Reserved
–
0x0DEC
Reserved
–
0x0DEA
Reserved
–
0x0DE8
MTOCIPCINT4
(IPC)
0x0DE6
MTOCIPCINT3
(IPC)
0x0DE4
MTOCIPCINT2
(IPC)
0x0DE2
MTOCIPCINT1
(IPC)
0x0DE0
INT12
LUF
(C28FPU)
0x0DFE
LVF
(C28FPU)
0x0DFC
EPI_INT
(EPI)
0x0DFA
Reserved
–
0x0DF4
C28FLSINGERR
(Memory)
0x0DF2
XINT3
(Ext. Int. 3)
0x0DF0
C28RAMACCVIOL C28RAMSINGERR
(Memory)
(Memory)
0x0DF8
0x0DF6
Out of the 96 possible interrupts, 72 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).
6.4.4
C28x Direct Memory Access
The C28x DMA module provides a hardware method of transferring data between peripherals, between
memory, and between peripherals and memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Additionally, the DMA has the capability to orthogonally rearrange
the data as the data is transferred as well as “ping-pong” data between buffers. These features are useful
for structuring data into blocks for optimal CPU processing. The interrupt trigger source for each of the six
DMA channels can be configured separately and each channel contains its own independent PIE interrupt
to notify the CPU when a DMA transfer has either started or completed. Five of the six channels are
exactly the same, while Channel 1 has one additional feature: the ability to be configured at a higher
priority than the others.
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6.4.5
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
C28x Local Peripherals
The C28x local peripherals include an NMI Watchdog, three Timers, four Serial Port Peripherals (SCI,
SPI, McBSP, I2C), an EPI, and three types of Control Peripherals (ePWM, eQEP, eCAP). All peripherals
are accessible by the C28x CPU through the C28x Memory Bus. Additionally, the McBSP and ePWM are
accessible by the C28x DMA Bus. The EPI peripheral is also accessible from the Master Subsystem. The
Serial Port Peripherals and the Control Peripherals connect to the pins in Concerto through the
GPIO_MUX1 block. Internally, the C28x peripherals generate events to the PIE block, C28x DMA, and the
Analog Subsystem. The C28x NMI Watchdog receives a C28NMI event from the NMI block and sends a
counter time-out event to the Cortex-M3 NMI block and the Resets block to flag a potentially critical
condition.
The ePWM peripheral receives events that can be used to trip the ePWM outputs EPWMxA and
EPWMxB. These events include ECCDBLERR event from the C28x Local Memory, PIENMIERR and
EMUSTOP events from the C28x CPU, and up to 12 trips from GPIO_MUX1.
See Section 5.12 for more information on C28x peripherals.
6.4.6
C28x Local Memory
The C28x Local Memory includes Boot ROM; Secure Flash with ECC; Secure L0/L1 RAM with ECC;
L2/L3 RAM with Parity Error Checking; and M0/M1 with ECC. All local memories are accessible from the
C28x CPU; the L2/L3 RAM is also accessible by the C28x DMA. Two types of error correction events can
be generated during access of the C28x Local Memory: uncorrectable errors and single errors. The
uncorrectable errors propagate to the NMI block where they can become the C28NMI to the C28x NMI
Watchdog and the C28NMIINT nonmaskable interrupt to the C28x CPU. The less critical single errors go
to the PIE block where they can become maskable interrupts to the C28x CPU.
6.4.7
C28x Accessing Shared Resources and Analog Peripherals
There are several memories, digital peripherals, and analog peripherals that can be accessed by both the
Master and Control Subsystems. They are grouped into the Shared Resources and the Analog
Subsystem.
The Shared Resources include the EPI, IPC registers, MTOC Message RAM, CTOM Message RAM, and
eight individually configurable Shared RAM blocks.
The Message RAMs and the Shared RAMs can be accessed by the C28x CPU and DMA and have ParityError Checking. The MTOC Message RAM is intended for sending data from the Master Subsystem to the
Control Subsystem, having R/W access for the Cortex-M3/µDMA and read-only access for the C28x/DMA.
The CTOM Message RAM is intended for sending data from the Control Subsystem to the Master
Subsystem, having R/W access for the C28x/DMA and read-only access for the Cortex-M3/µDMA.
The IPC registers provide up to 32 handshaking channels to coordinate transfer of data through the
Message RAMs by polling. Four of these channels are also backed up by four interrupts to PIE on the
Control Subsystem side, and four interrupts to the NVIC on the Master Subsystem side (to reduce delays
associated with polling).
The eight Shared RAM blocks are similar to the Message RAMs, in that the data flow is only one way;
however, the direction of the data flow can be individually set for each block to be from Master to Control
Subsystem or from Control to Master Subsystem.
See Section 5.10 for more information on shared resources and analog peripherals.
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Analog Subsystem
The Analog Subsystem has ADC1, ADC2, and six Analog Comparator + DAC units that can be accessed
through the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and
DMAs of the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the
C28x CPU only. The C28x CPU accesses the ACIB through the C28x Memory Bus, and the C28x DMA
through the C28x DMA Bus. The ACIB arbitrates for access to ADC and Analog Comparator registers
between CPU/DMA bus cycles of the C28x Subsystem with those of the Cortex-M3 Subsystem. In
addition to managing bus cycles, the ACIB also transfers Start-Of-Conversion triggers to the Analog
Subsystem and returns End-Of-Conversion ADC interrupts to both the Master Subsystem and the Control
Subsystem.
There are 22 possible Start-Of-Conversion (SOC) sources from the C28x Subsystem that are mapped to a
total of 8 possible SOC triggers inside the Analog Subsystem (to ADC1 and ADC2).
Going the other way, eight End-Of-Conversion (EOC) sources from ADC1 and eight EOC sources from
ADC2 are AND-ed together to form eight interrupts going to destinations in both the Master and Control
Subsystems. Inside the C28x Subsystem, all eight EOC interrupts go to the PIE, but only four of the same
eight go to the C28x DMA.
The Concerto MCU Analog Subsystem has two independent Analog-to-Digital Converters (ADC1, ADC2);
six Analog Comparators + DAC units; and an ACIB to facilitate analog data communications with the two
digital subsystems of Concerto (Cortex-M3 and C28x).
Figure 6-3 shows the Analog Subsystem.
6.5.1
ADC1
The ADC1 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which
12 are currently pinned out. The analog channels are internally preassigned to two Sample-and-Hold (S/H)
units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored
in ADC1 result registers. The two S/H units enable simultaneous sampling of two analog signals at a time.
Additional channels or channel pairs are converted sequentially. SOC triggers from the Control Subsystem
initiate analog-to-digital conversions. EOC interrupts from ADCs notify the Master and Control Subsystems
that the conversion results are ready to be read from ADC1 result registers.
See Section 5.10.1 for more information on ADC peripherals.
6.5.2
ADC2
The ADC2 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which
12 are currently pinned out. The analog channels are internally preassigned to two S/H units A and B,
both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored in the ADC2
result registers. The two S/H units enable simultaneous sampling of two analog signals at a time.
Additional channels or channel pairs are converted sequentially. SOC triggers from the Control Subsystem
initiate analog-to-digital conversions. EOC interrupts from ADCs notify the Master and Control Subsystems
that the conversion results are ready to be read from ADC2 result registers.
See Section 5.10.1 for more information on ADC peripherals.
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12
AIO_MUX1
GPIO
MUX
4
ADC1INA0
ADC1INA2
ADC1INA3
ADC1INA4
ADC1INA6
ADC1INA7
ANALOG
COMMON
INTERFACE
BUS
ADC1INB0
ADC1INB2
ADC1INB3
ADC1INB4
ADC1INB6
ADC1INB7
ANALOG BUS
MCIBSTATUS REG
ANALOG BUS
GPIO_MUX2
GPIO
8
MUX
8
M3
SYSTEM
BUS
COMPB1
COMPB2
COMPB3
ADC1INT (8:1)
ADCINT(8:1)
ADC2INT (8:1)
COMPOUT (6:1)
VSSA
(0V)
COMPA4
COMPA5
COMPA6
M3
uDMA
BUS
EOC
INTERRUPTS
(8:1)
VDDA
(3.3V)
6
COMPARATOR
+ DAC UNITS
M3
uDMA
TRIGS (8:1)
ADC
1
COMPA1
COMPA2
COMPA3
M3
CPU
C28
DMA
BUS
C28
CPU
BUS
COMPB4
COMPB5
COMPB6
CCIBSTATUS REG
C28x
CPU
TRIGS (8:1)
ADC
2
SOC
TRIGGERS
(8:1)
ADCINT
(4:1)
C28x
DMA
TINT (2:0)
ADC2INA0
ADC2INA2
ADC2INA3
ADC2INA4
ADC2INA6
ADC2INA7
ADC2INB0
ADC2INB2
ADC2INB3
ADC2INB4
ADC2INB6
ADC2INB7
ADCEXTTRIG
SOC (9:1) A
TRIG8SEL REG
SOC (9:1) B
TRIG7SEL REG
...
GPIO
TRIG2SEL REG
MUX
4
AIO_MUX2
TRIG1SEL REG
TIMER
(3)
GPIO
EPWM
(9)
12
Figure 6-3. Analog Subsystem
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Analog Comparator + DAC
There are six Comparator blocks enabling simultaneous comparison of multiple pairs of analog inputs,
resulting in six digital comparison outputs. The external analog inputs that are being compared in the
comparators come from AIO_MUX1 and AIO_MUX2 blocks. These analog inputs can be compared
against each other or the outputs of 10-bit DACs (Digital-to-Analog Converters) inside individual
Comparator modules. The six comparator outputs go to the GPIO_MUX2 block where they can be
mapped to six out of eight available pins.
To use these comparator outputs to trip the C28x EPWMA/B outputs, they must be first routed externally
from pins of the GPIO_MUX2 block to selected pins of the GPIO_MUX1 block before they can be
assigned to selected 12 ePWM Trip Inputs.
See Section 5.10.2 for more information on the analog comparator + DAC.
6.5.4
Analog Common Interface Bus
The ACIB links the Master and Control Subsystems with the Analog Subsystem. The ACIB enables the
Cortex-M3 CPU/µDMA and C28x CPU/DMA to access Analog Subsystem registers, to send SOC Triggers
to the Analog Subsystem, and to receive EOC Interrupts from the Analog Subsystem. The Cortex-M3
uses its System Bus and the µDMA Bus to read from ADC Result registers. The C28x uses its Memory
Bus and the DMA bus to access ADC Result registers and other registers of the Analog Subsystem. The
ACIB arbitrates between up to four possibly simultaneously occurring bus cycles on the Master/Control
Subsystem side of ACIB to access the ADC and Analog Comparator registers on the Analog Subsystem
side.
Additionally, ACIB maps up to 22 SOC trigger sources from the Control Subsystem to 8 SOC trigger
destinations inside the Analog Subsystem (shared between ADC1 and ADC2), and up to 16 ADC EOC
interrupt sources from the Analog Subsystem to 8 destinations inside the Master and Control Subsystems.
The eight ADC interrupts are the result of AND-ing of eight EOC interrupts from ADC1 with 8 EOC
interrupts from ADC2. The total of 16 possible ADC1 and ADC2 interrupts are sharing the 8 interrupt lines
because it is unlikely that any application would need all 16 interrupts at the same time.
Eight registers (TRIG1SEL–TRIG8SEL) configure eight corresponding SOC triggers to assign 1 of 22
possible trigger sources to each SOC trigger.
There are two registers that provide status of ACIB to the Master Subsystem and to the Control
Subsystem.
The Cortex-M3 can read the MCIBSTATUS register to verify that the Analog Subsystem is properly
powered up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and
interrupts are correctly propagating between the Master, Control, and Analog subsystems.
The C28x can read the CCIBSTATUS register to verify that the Analog Subsystem is properly powered
up; the Analog System Clock (ASYSCLK) is present; and that the bus cycles, triggers, and interrupts are
correctly propagating between the Master, Control, and Analog subsystems.
186
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6.6
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Master Subsystem NMIs
The Cortex-M3 NMI Block generates an M3NMIINT nonmaskable interrupt to the Cortex-M3 CPU and an
M3NMI event to the NMI Watchdog in response to potentially critical conditions existing inside or outside
the Concerto MCU. When able to respond to the M3NMIINT interrupt, the Cortex-M3 CPU may address
the NMI condition and disable the NMI Watchdog. Otherwise, the NMI Watchdog counts out and an
M3NMIRST reset signal is sent to the Resets block.
The inputs to the Cortex-M3 NMI block include the C28NMIRST, PIENMIERR, CLOCKFAIL, ACIBERR,
EXTGPIO, MLBISTERR, and CLBISTERR signals. The C28NMIRST comes from the C28x NMI
Watchdog; C28NMIRST indicates that the C28x was not able to prevent the C28x NMI Watchdog counter
from counting out. PIENMIERR indicates that an error condition was generated during the NMI vector
fetch from the C28x PIE block. The CLOCKFAIL input comes from the Master Clocks Block, announcing a
missing clock source to the Main Oscillator. ACIBERR indicates an abnormal condition inside the Analog
Common Interface Bus. EXTGPIO comes from the GPIO_MUX1 to announce an external emergency.
MLBISTERR is generated by the Cortex-M3 core to signal that a BIST time-out or signature mismatch
error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST time-out or
signature mismatch error has been detected.
The Cortex-M3 NMI block can be accessed through the Cortex-M3 NMI configuration registers—including
the MNMIFLG, MNMIFLGCLR, and MNMIFLGFRC registers—to examine flag bits for the NMI sources,
clear the flags, and force the flags to active state, respectively.
Figure 6-4 shows the Cortex-M3 NMI and C28x NMI.
6.7
Control Subsystem NMIs
The C28x NMI Block generates a C28NMIINT nonmaskable interrupt to the C28x CPU and a C28NMI
event to the C28x NMI Watchdog in response to potentially critical conditions existing inside the Concerto
MCU. When able to respond to the C28NMIINT interrupt, the C28x CPU may address the NMI condition
and disable the C28x NMI Watchdog. Otherwise, the C28x NMI Watchdog counts out and the
C28NMIRST reset signal is sent to the Resets block and the Cortex-M3 NMI Block, where the Cortex-M3
NMI Block can generate an NMI to the Cortex-M3 processor.
The inputs to the C28x NMI block include the CLOCKFAIL, ACIBERR, RAMUNCERR, FLASHUNCERR,
PIENMIERR, CLBISTERR, and MLBISTERR signals. The CLOCKFAIL input comes from the Clocks
Block, announcing a missing clock source to the Main Oscillator. ACIBERR indicates an abnormal
condition inside the Analog Common Interface Bus. The RAMUCERR and FLASHUNCERR announce the
occurrence of uncorrectable error conditions during access to the Flash or RAM (local or shared).
PIENMIERR indicates that an error condition was generated during NMI vector fetch from the C28x PIE
block. MLBISTERR is generated by the Cortex-M3 core to signal that a BIST time-out or signature
mismatch error has been detected. CLBISTERR is generated by the C28x core to signal that a BIST timeout or signature mismatch error has been detected.
The C28x NMI block can be accessed through the C28x NMI configuration registers—including the
CNMIFLG, CNMIFLGCLR, and CNMIFLGFRC registers—to examine flag bits for the NMI sources, clear
the flags, and force the flags to active state, respectively.
Figure 6-4 shows the Cortex-M3 NMI and C28x NMI.
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M3
BIST
1.2V
VREG
M3BISTERR
M3 NMI
WDOG
VREGWARN
M3NMI
M3 WDOG
(2)
M3NMIRST
M3WDRST (1:0)
NMI
M3NMI
M3BISTERR
M3EXTNMI
GPIO_MUX
M3 NMI
C28BISTERR
M3NMIINT
M3 CPU
C28NMIRST
ACIBERR
ANALOG
SUBSYSTEM
M3WDRST (1:0)
M3NMIRST
RESETS
C28NMIRST
CLOCKFAIL
CLOCKS
PIENMIERR
M3BISTERR
RAMUNCERR
SHARED RAM
C28NMIINT
C28x NMI
C28BISTERR
C28x CPU
C28NMI
C28x LOCAL
RAM
C28BISTERR
C28x
BIST
FLASHUNCERR
C28x
FLASH
C28NMI
C28NMIRST
C28x NMI
WDOG
Figure 6-4. Cortex-M3 NMI and C28x NMI
188
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6.8
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Resets
The Concerto MCU has two external reset pins: XRS for the Master and Control Subsystems and ARS for
the Analog Subsystem. Texas Instruments (TI) recommends that these two pins be externally tied together
with a board signal trace.
The XRS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset
signal out from inside of the chip. A reset pulse driven into the XRS pin resets the Master and Control
Subsystems. A reset pulse can also be driven out of the XRS pin by the Power-On Reset (POR) block of
the Master and Control Subsystems (see Section 6.9). A reset pulse can be driven out of the XRS pin
when the two Cortex-M3 Watchdogs or the Cortex-M3 NMI Watchdog time-out.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for at least eight X1 cycles after the input clock is
stable. This requirement is to enable the entire device to start from a known condition.
2. TI recommends that no voltage larger than 0.7 V be applied to any pin before powering up the device.
Voltages applied to pins on an unpowered device can lead to unpredictable results.
The ARS pin can receive an external reset signal from outside into the chip, and the pin can drive a reset
signal out from inside of the chip. A reset pulse driven into the ARS pin resets the Analog Subsystem. A
reset pulse can be driven out of the ARS pin by the POR block of the Analog Subsystem.
Figure 6-5 shows the resets.
6.8.1
Cortex-M3 Resets
The Cortex-M3 CPU and NVIC (Nested Vectored Interrupt Controller) are both reset by the POR or the
M3SYSRST reset signal. In both cases, the Cortex-M3 CPU restarts program execution from the address
provided by the reset entry in the vector table. A register can later be referenced to determine the source
of the reset. The M3SYSRST signal also propagates to the Cortex-M3 peripherals and the rest of the
Cortex-M3 Subsystem.
The M3SYSRST has four possible sources: XRS, M3WDOGS, M3SWRST, and M3DBGRST. The
M3WDOGS is set in response to time-out conditions of the two Cortex-M3 Watchdogs or the Cortex-M3
NMI Watchdog. The M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a
debugger-generated reset that is also output by the NVIC. In addition to driving M3SYSRST, these two
resets also propagate to the C28x Subsystem and the Analog Subsystem.
The M3RSNIN bit can be set inside the CRESCNF register to selectively reset the C28x Subsystem from
the Cortex-M3, and ACIBRST bit of the same register selectively resets the Analog Common Interface
Bus. In addition to driving reset signals to other parts of the chip, the Cortex-M3 can also detect a
C28SYSRST reset being set inside the C28x Subsystem by reading the CRES bit of the CRESSTS
register.
Cortex-M3 software can also set bits in the SRCR register to selectively reset individual Cortex-M3
peripherals, provided they are enabled inside the DC (Device Configuration) register. The Reset Cause
register (MRESC) can be read to find out if the latest reset was caused by External Reset, POR,
Watchdog Timer 0, Watchdog Timer 1, or Software Reset from NVIC.
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M3 WDOG (1)
M3WDOGS
M3 WDOG (0)
JTAG
CONTROLLER
CRESSTS REG
M3 BIST
( SETS DEFAULT VALUES )
SOFTWARE
CRESCNF REG
MLBISTRST
M3PORRST
POR
ACIBRST
M3RSNIN
C28SYSRST
VOLTAGE
REGULATION
AND
POWER-ON-RESET
XRS
M3
NVIC
M3
CPU
XRS
M3
NMI
WDOG
M3SYSRST
XRS
FLASH PUMP
M3SYSRST
M3SWRST
PERIPHERAL SOFTWARE RESETS
M3DBGRST
M3
SUBSYSTEM
SRCR REG
MRESC REG
CONTAINS RESET CAUSES
DC REG
GLOBAL PERIPHERAL ENABLES
ACIBRST
ANALOG
SUBSYSTEM
ARS
PIN
SRXRST
XRS
GPIO_MUX
SHARED
RESOURCES
M3WDOGS
POR
C28x BIST
C28x
SUBSYSTEM
CLBISTRST
XRS
PIN
‘0’
C28RSTIN
C28SYSRST
XRS
DEGLITCH
C28x
CPU
SYNC
ACIBRST
M3SSCLK
XRS
C28x
NMI
WDOG
RESET INPUT SIGNAL STATUS
DEVICECNF REG
C28NMIWD
Figure 6-5. Resets
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6.8.2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
C28x Resets
The C28x CPU is reset by the C28RSTIN signal, and the C28x CPU in turn resets the rest of the C28x
Subsystem with the C28SYSRST signal. When reset, the C28x restarts program execution from the
address provided at the top of the Boot ROM Vector Table.
The C28RSTIN has five possible sources: XRS, C28NMIWD, M3SWRST, M3DBGRST, and the
M3RSNIN. The C28NMIWD is set in response to time-out conditions of the C28x NMI Watchdog. The
M3SWRST is a software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated
reset that is also output by the NVIC. These two resets must be first enabled by the Cortex-M3 processor
in order to propagate to the C28x Subsystem. M3RSNIN reset comes from the Cortex-M3 Subsystem to
selectively reset the C28x Subsystem from Cortex-M3 software.
The C28x processor can learn the status of the internal ACIBRST reset signal and the external XRS pin
by reading the DEVICECNF register.
6.8.3
Analog Subsystem and Shared Resources Resets
Both the Analog Subsystem and the resources shared between the C28x and Cortex-M3 subsystems
(IPC, MSG RAM, Shared RAM) are reset by the SRXRST reset signal. Additionally, the Analog
Subsystem is also reset by the internal ACIBRST signal from the Cortex-M3 Subsystem and the external
ARS pin, (should be externally tied to the XRS pin), which can be reset by the POR circuitry.
The SRXRST has three possible sources: XRS, M3SWRST, and M3DBGRST. The M3SWRST is a
software-generated reset output by the NVIC. The M3DBGRS is a debugger-generated reset that is also
output by the NVIC. These two resets must be first enabled by the Cortex-M3 processor in order to
propagate to the Analog Subsystem and the Shared Resources.
Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore,
EPI is reset by M3SYSRST.
6.8.4
Device Boot Sequence
The boot sequence of Concerto is used to configure the Master Subsystem and the Control Subsystem for
execution of application code. The boot sequence involves both internal resources, and resources external
to the device. These resources include: Master Subsystem Bootloader code (M-Bootloader) factoryprogrammed inside the Master Subsystem Boot ROM (M-Boot ROM); Control Subsystem Bootloader code
(C-Bootloader) factory-programmed inside the Control Subsystem Boot ROM (C-Boot ROM); four
GPIO_MUX pins for Master boot mode selection; internal Flash and RAM memories; and selected CortexM3 and C28x peripherals for loading the application code into the Master and Control Subsystems.
The boot sequence starts when the Master Subsystem comes out of reset, which can be caused by
device power up, external reset, debugger reset, software reset, Cortex-M3 watchdog reset, or Cortex-M3
NMI watchdog reset. While the M-Bootloader starts executing first, the C-Bootloader starts soon after, and
then both bootloaders work in tandem to configure the device, load application code for both processors (if
not already in the Flash), and branch the execution of each processor to a selected location in the
application code.
Execution of the M-Bootloader commences when an internal reset signal goes from active to inactive
state. At that time, the Control Subsystem and the Analog Subsystem continue to be in reset state until
the Master Subsystem takes them out of reset. The M-Bootloader first initializes some device-level
functions, then the M-Bootloader initializes the Master Subsystem. Next, the M-Bootloader takes the
Control Subsystem and the Analog Subsystem/ACIB out of reset. When the Control Subsystem comes out
of reset, its own C-Bootloader starts executing in parallel with the M-Bootloader. After initializing the
Control Subsystem, the C-Bootloader enters the C28x processor into the IDLE mode (to wait for the MBootloader to wake up the C28x processor later through the MTOCIPC1 interrupt). Next, the M-Bootloader
reads four GPIO pins (see Table 6-17) to determine the boot mode for the rest of the M-Bootloader
operation.
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Table 6-17. Master Subsystem Boot Mode Selection
BOOT MODE #
MASTER SUBSYSTEM BOOT MODES
PF2_GPIO34
(Bmode_pin4)(1)
PF3_GPIO35
(Bmode_pin3)(1)
PG7_GPIO47
(Bmode_pin2)(1)
PG3_GPIO43
(Bmode_pin1)(1)
0(2)
Boot from Parallel GPIO
0
0
0
0
1(2)
Boot to Master Subsystem RAM
0
0
0
1
2(2)
Boot from Master Subsystem serial peripherals
(UART0/SSI0/I2C0)
0
0
1
0
3(2)
Boot from Master Subsystem CAN interface
0
0
1
1
(2)
4
Boot from Master Subsystem Ethernet interface
0
1
0
0
(2)(4)
5
Not supported (Defaults to Boot-to-Flash), future
boot from Cortex-M3 USB
0
1
0
1
(2)(4)(5)
Boot-to-OTP
0
1
1
0
7(2)(4)
Boot to Master Subsystem Flash memory
0
1
1
1
8
Not supported (Defaults to Boot-to-Flash)
1
0
0
0
9(4)
Boot from Master Subsystem serial peripheral –
SSI0 Master
1
0
0
1
10(4)
Boot from Master Subsystem serial peripheral –
I2C0 Master
1
0
1
0
11
Not supported (Defaults to Boot-to-Flash)
1
0
1
1
12(3)
Boot from Master Subsystem Ethernet interface
1
1
0
0
13(4)
Not supported (Defaults to Boot-to-Flash)
1
1
0
1
(4)
14
Not supported (Defaults to Boot-to-Flash)
1
1
1
0
15(4)
Boot to Master Subsystem Flash memory
1
1
1
1
6
(4)
(1) By default, GPIO terminals are not pulled up (they are floating).
(2) Boot Modes 0–7 are pin-compatible with the F28M35x members of the Concerto family (they use same GPIO terminals).
(3) Boot Mode 12 is the same as Boot Mode 4, except it uses a different set of GPIO terminals.
(4) This Boot Mode uses a faster Flash power-up sequence. The maximum supported OSCCLK frequency for this mode is 30 MHz.
(5) Supported only in TMS version. On all other versions, this mode defaults to Boot-to-Flash.
Boot Mode 7 and Boot Mode 15 cause the Master program to branch execution to the application in the
Master Flash memory. This branching requires that the Master Flash be already programmed with valid
code; otherwise, a hard fault exception is generated and the Cortex-M3 goes back to the above reset
sequence. (Therefore, for a factory-fresh device, the M-Bootloader will be in a continuous reset loop until
the JTAG debug probe is connected and a debug session started.) If the Master Subsystem Flash has
already been programmed, the application code will start execution. Typically, the Master Subsystem
application code will then establish data communication with the C28x [through the IPC (Interprocessor
Communications peripheral)] to coordinate the rest of the boot process with the Control Subsystem. Boot
Mode 15 (Fast Boot to Flash Mode) supported on this device is a special boot to Flash mode, which
configures Flash for a faster power up, thus saving some boot time. Boot Mode 7 and other modes which
default to Flash do not configure Flash for a faster power up like Boot Mode 15 does. Following reset, the
internal pullup resistors on GPIOs are disabled. Therefore, Boot Mode 15, for example, will typically
require four external pullups.
Boot Mode 1 causes the Master boot program to branch to Cortex-M3 RAM, where the Cortex-M3
processor starts executing code that has been preloaded earlier. Typically, this mode is used during
development of application code meant for Flash, but which has to be first tested running out of RAM. In
this case, the user would typically load the application code into RAM using the debugger, and then issue
a debugger reset, while setting the four boot pins to 0001b. From that point on, the rest of the boot
process on the Master Subsystem side is controlled by the application code.
Boot Modes 0, 2, 3, 4, 9, 10, and 12 are used to load the Master application code from an external
peripheral before branching to the application code. This process is different from the process in Boot
Modes 1, 7, and 15, where the application code was either already programmed in Flash or loaded into
RAM by the JTAG debug probe. If the boot mode selection pins are set to 0000b, the M-Bootloader
(running out of M-Boot ROM) will start uploading the Master application code from preselected Parallel
GPIO_MUX pins. If the boot pins are set to 0010b, the application code will be loaded from the Master
192
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Subsystem UART0, SSI0, or I2C0 peripheral. (SSI0 and I2C0 are configured to work in Slave mode in this
Boot Mode.) If the boot pins are set to 0011b, the application code will be loaded from the Master
Subsystem CAN interface. Furthermore, if the boot pins are set to 0100b, the application code will be
loaded through the Master Subsystem Ethernet interface; the IOs used in this Boot Mode are compatible
with the F28M35x device. If the boot pins are set to 1001b or 1010b, then the application code will be
loaded through the SSI0 or I2C0 interface, respectively. SSI0 and I2C0 loaders work in Master Mode in
this boot mode. If the boot pins are set to 1100b, then the application code will be loaded through the
Master Subsystem Ethernet interface; the IOs used in this Boot Mode are F28M36x IOs, which are
available only in a BGA package.
Regardless of the type of boot mode selected, once the Master application code is resident in Master
Flash or RAM, the next step for the M-Bootloader is to branch to Master Flash or RAM. At that point, the
application code takes over control from the M-Bootloader, and the boot process continues as prescribed
by the application code. At this stage, the Master application program typically establishes communication
with the C-Bootloader, which by now, would have already initialized the Control Subsystem and forced the
C28x to go into IDLE mode. To wake the Control Subsystem out of IDLE mode, the Master application
issues the Master-to-Control-IPC-interrupt 1 (MTOCIPCINT1) . Once the data communication has been
established through the IPC, the boot process can now also continue on the Control Subsystem side.
The rest of the Control Subsystem boot process is controlled by the Master Subsystem application issuing
IPC instructions to the Control Subsystem, with the C-Bootloader interpreting the IPC commands and
acting on them to continue the boot process. At this stage, a boot mode for the Control Subsystem can be
established. The Control Subsystem boot modes are similar to the Master Subsystem boot modes, except
for the mechanism by which they are selected. The Control Subsystem boot modes are chosen through
the IPC commands from the Master application code to the C-Bootloader, which interprets them and acts
accordingly. The choices are, as above, to branch to already existing Control application code in Flash, to
branch to preloaded code in RAM (development mode), or to upload the Control application code from
one of several available peripherals (see Table 6-18). As before, once the Control application code is in
place (in Flash or RAM), the C-Bootloader branches to Flash or RAM, and from that point on, the
application code takes over.
Table 6-18. Control Subsystem Boot Mode Selection
CONTROL SUBSYSTEM
BOOT MODES
MTOCIPCBOOTMODE
REGISTER VALUE
DESCRIPTION
BOOT_FROM_RAM
0x0000 0001
Upon receiving this command from the Master Subsystem, C-Boot
ROM will branch to the Control Subsystem RAM entry point location
and start executing code from there.
BOOT_FROM_FLASH
0x0000 0002
Upon receiving this command, C-Boot ROM will branch to the
Control Subsystem FLASH entry point and start executing code from
there.
BOOT_FROM_SCI
0x0000 0003
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem SCI peripheral.
BOOT_FROM_SPI
0x0000 0004
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem SPI interface.
BOOT_FROM_I2C
0x0000 0005
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem I2C interface.
BOOT_FROM_PARALLEL
0x0000 0006
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem GPIO.
BOOT_FROM_SPI (1)
0x0000 0007
Upon receiving this command, C-Boot ROM will boot from the
Control Subsystem SPI interface.
(1)
MTOCBOOTMODE 0x0000 0001–MTOCBOOTMODE 0x0000 0006 are compatible with the F28M35x members of the Concerto family,
but MTOCBOOTMODE 0x0000 0007 uses GPIO terminals that are not available on the F28M35x.
The boot process can be considered completed once the Cortex-M3 and C28x are both running out of
their respective application programs. Following the boot sequence, the C-Bootloader is still available to
interpret and act upon an assortment of IPC commands that can be issued from the Master Subsystem to
perform a variety of configuration, housekeeping, and other functions.
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Internal Voltage Regulation and Power-On-Reset Functionality
While the analog functions of Concerto draw power from a single dedicated external power source—VDDA,
its digital circuits are powered by three separate rails: 3.3-V VDDIO, 1.8-V VDD18, and 1.2-V VDD12. This
section describes the sourcing, regulation, and POR functionality for these three digital power rails.
Concerto devices can be internally divided into an Analog Subsystem and a Digital Subsystem (having the
Cortex-M3-based Master Subsystem and the C28x-based Control Subsystem). The Digital Subsystem
uses VDD12 to power the two processors, internal memory, and peripherals. The Analog Subsystem uses
VDD18 to power the digital logic associated with the analog functions. Both Digital and Analog Subsystems
share a common VDDIO rail to power their 3.3-V I/O buffers through which the Concerto digital signals
communicate with the outside world.
The Analog and Digital Subsystems each have their own POR circuits that operate independently. With
the ARS and XRS reset pins externally tied together, both systems can come out of reset together, and
can also be put in reset together by driving both reset pins low. See Figure 6-6 for a snapshot of the
voltage regulation and POR functions provided within the Analog and Digital Subsystems of Concerto.
6.9.1
Analog Subsystem: Internal 1.8-V VREG
The internal 1.8-V Voltage Regulator (VREG) generates VDD18 power from VDDIO. The 1.8-V VREG is
enabled by pulling the VREG18EN pin to a low state. When enabled, the 1.8-V VREG provides 1.8 V to
digital logic associated with the analog functions of the Analog Subsystem.
When the internal 1.8-V VREG function is enabled, the 1.8 V power no longer has to be provided
externally; however, a 1.2-µF (10% tolerance) capacitor is required for each VDD18 pin to stabilize the
internally generated voltages. These load capacitors are not required if the internal 1.8-V VREG is
disabled, and the 1.8 V is provided from an external supply.
While removing the need for an external power supply, enabling the internal VREG might affect the VDDIO
power consumption.
194
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CONNECT THE 2 RESET PINS EXTERNALLY THROUGH A BOARD TRACE
ARS
PIN
XRS
PIN
CONCERTO
DEVICE
M3WDOGS
ARS
XRS
DEGLITCH
DEGLITCH
‘0’
‘0’
POWER-ON-RESET
(DIGITAL SUBSYSTEM)
1.8-V
POR
3.3-V
POR
1.8 V
TRISTATE
3.3 V
POR
3.3-V
POR
1.2 V
1.2-V
POR
ANALOG SUBSYSTEM GPIOS
DIGITAL LOGIC
(DIGITAL SUBSYSTEM)
M3
NVIC
M3 CPU
M3 NMI
M3 WDOGS
(0,1)
M3 NMI
WDOG
DIGITAL LOGIC
(ANALOG SUBSYSTEM)
RESETS
ACIBRST
M3RSNIN
I/O
1.8 V
1.2 V
1.8 V
CONTROL
SUBSYSTEM
I/O
1.2 V
1.8-V VREG
(ANALOG SUBSYSTEM)
1.2-V VREG
(DIGITAL SUBSYSTEM)
3.3 V
VREG18EN
PIN
CRESCNF REG
RST
DIGITAL SUBSYSTEM GPIOS
TRISTATE
POWER-ON-RESET
(ANALOG SUBSYSTEM)
POR
3.3 V
1.8-V
SUPPLY
PINS
3.3-V
SUPPLY
PINS
1.2-V
SUPPLY
PINS
VREG12EN
PIN
Figure 6-6. Voltage Regulation and Monitoring
Detailed Description
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Digital Subsystem: Internal 1.2-V VREG
The internal 1.2-V VREG generates VDD12 power from VDDIO. The 1.2-V VREG is enabled by pulling the
VREG12EN pin to a low state. When enabled, the 1.2-V VREG internally provides 1.2 V to digital logic
associated with the processors, memory, and peripherals of the Digital Subsystem.
When the internal 1.2-V VREG function is enabled, the 1.2 V power no longer has to be provided
externally; however, the minimum and maximum capacitance required for each VDD12 pin to stabilize the
internally generated voltages are 250 nF and 750 nF, respectively. These load capacitors are not required
if the internal 1.2-V VREG is disabled and the 1.2 V is provided from an external supply.
While removing the need for an external power supply, enabling the internal VREG might affect the VDDIO
power consumption.
6.9.3
Analog and Digital Subsystems: Power-On-Reset Functionality
The Analog and Digital Subsystems' each have a POR circuit that creates a clean reset throughout the
device enabling glitchless GPIOs during the power-on procedure. The POR function keeps both ARS and
XRS driven low during device power up. This functionality is always enabled, even when VREG is
disabled.
While in most applications, the POR generated reset has a long enough duration to also reset other
system ICs, some applications may require a longer lasting pulse. In these cases, the ARS and XRS reset
pins (which are open-drain) can also be driven low to match the time the device is held in a reset state
with the rest of the system.
When POR drives the ARS and XRS pins low, the POR also resets the digital logic associated with both
subsystems and puts the GPIO pins in a high impedance state.
In addition to the POR reset, the Resets block of the Digital Subsystem also receives reset inputs from the
NVIC, the Cortex-M3 Watchdogs (0, 1), and from the Cortex-M3 NMI Watchdog. The resulting reset
output signal is then fed back to the XRS pin after being AND-ed with the POR reset (see Figure 6-6).
On a related note, only the Master Subsystem comes out of reset immediately following a device power
up. The Control and Analog Subsystems continue to be held in reset until the Master Processor (CortexM3) brings them out of reset by writing a "1" to the M3RSNIN and ACIBRST bits of the CRESCNF
Register (see Figure 6-6).
6.9.4
Connecting ARS and XRS Pins
In most Concerto applications, TI recommends that the ARS and XRS pins be tied together by external
means such as through a signal trace on a PCB board. Tying the ARS and XRS pins together ensures
that all reset sources will cause both the Analog and Digital Subsystems to enter the reset state together,
regardless of where the reset condition occurs.
196
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6.10 Input Clocks and PLLs
Concerto devices have multiple input clock pins from which all internal clocks and the output clock are
derived. Figure 6-7 shows the recommended methods of connecting crystals, resonators, and oscillators
to pins X1/X2 and XCLKIN.
CONCERTO DEVICE
CONCERTO DEVICE
X1
vssosc
X2
X1
vssosc
X2
RESONATOR
CRYSTAL
RD
C L2
C L1
CONCERTO DEVICE
CONCERTO DEVICE
X1
vssosc
X2
XCLKIN
NC
3.3V
CLK
VDD
OUT
3.3V
CLK
VDD
OUT
GND
3.3V OSCILLATOR
GND
3.3V OSCILLATOR
Figure 6-7. Connecting Input Clocks to a Concerto™ Device
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6.10.1 Internal Oscillator (Zero-Pin)
Each Concerto device contains a zero-pin internal oscillator. This oscillator outputs two fixed-frequency
clocks: 10MHZCLK and 32KHZCLK. These clocks are not configurable by the user and should not be
used to clock the device during normal operation. They are used inside the Master Subsystem to
implement low-power modes. The 10MHZCLK is also used by the Missing Clock Detect circuit.
6.10.2 Crystal Oscillator/Resonator (Pins X1/X2 and VSSOSC)
The main oscillator circuit connects to an external crystal through pins X1 and X2. If a resonator is used
(version of a crystal with built-in load capacitors), its ground terminal should be connected to the pin
VSSOSC (not board ground). The VSSOSC pin should also be used to ground the external load capacitors
connected to the two crystal terminals as shown in Figure 6-7.
6.10.3 External Oscillators (Pins X1, VSSOSC, XCLKIN)
Concerto has two pins (X1 and XCLKIN) into which a single-ended clock can be driven from external
oscillators or other clock sources. When connecting an external clock source through the X1 terminal, the
X2 terminal should be left unconnected. Most internal clocks of this device are derived from the X1 clock
input (or X1/X2 crystal) . The XCLKIN clock is only used by the USB PLL and CAN peripherals. Figure 6-7
shows how to connect external oscillators to the X1 and XCLKIN terminals.
Locate the external oscillator as close to the MCU as practical. Ideally, the return ground trace should be
an isolated trace directly underneath the forward trace or run adjacent to the trace on the same layer.
Spacing should be kept minimal, with any other nearby traces double-spaced away, so that the
electromagnetic fields created by the two opposite currents cancel each other out as much as possible,
thus reducing parasitic inductances that radiate EMI.
6.10.4 Main PLL
The Main PLL uses the reference clock from pins X1 (external oscillator) or X1/X2 (external
crystal/resonator). The input clock is multiplied by an integer multiplier and a fractional multiplier as
selected by the SPLLIMULT and SPLLFMULT fields of the SYSPLLMULT register. For example, to
achieve PLL multiply of 28.5, the integer multiplier should be set to 28, and the fractional multiplier to 0.5.
The output clock from the Main PLL must be between 150 MHz and 300 MHz. The PLL output clock is
then divided by 2 before entering a mux that selects between this clock and the PLL input clock –
OSCCLK (used in PLL bypass mode). The PLL bypass mode is selected by setting the SPLLIMULT field
of the SYSPLLMULT register to 0. The output clock from the mux next enters a divider controlled by the
SYSDIVSEL register, after which the output clock becomes the PLLSYSCLK. Figure 6-8 shows the Main
PLL function and configuration examples. Table 6-19 to Table 6-22 list the integer multiplier configuration
values.
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SYSPLLMULT REG
SPLLIMULT
SYSPLLCTL REG
SPLLFMULT
SPLLEN (2)
SYSDIVSEL REG
SPLLCLKEN
OSCCLK
7
SYSDIVSEL (1:0)
= 00 ( /1 )
0
2
/1
/2
/4
/8
MAIN PLL
PIN
X1
INTEGER
MULTIPLIER
MAIN
OSC
FRACTIONAL
MULTIPLIER
/2
OSCCLK
0000000 :
0000001 :
0000010 :
0000011 :
.
.
.
´
´
´
´
1
1
2
3
00: NOT USED
01:
´ 0.25
10:
´ 0.50
11:
´ 0.75
PLLSYSCLK
1
OUPUT OF
MAIN PLL
IS ALWAYS
DIVIDED BY 2
1111101: ´ 125
1111110: ´ 126
1111111: ´ 127
(1) OUTPUT OF THE MAIN PLL MUST RANGE BETWEEN 150–300 MHz.
(2) WHEN SPLLEN BIT = 0, THE MAIN PLL IS POWERED OFF.
EXAMPLE 1:
X1 = 100 MHZ
SPLLIMULT = 0000000 ( BYPASS PLL)
EXAMPLE 2:
X1 = 10 MHz
SPLLIMULT = 0010100 ( ´ 20 )
SPLLFMULT = 00 ( NOT USED)
N/A
PLLSYSCLK = 100 MHz
PLLSYSCLK = [ ( 10 ´ 20)
/ 2 ] / 1 = 100 MHz
EXAMPLE 3:
X1 = 10 MHz
SPLLIMULT = 0010100 ( ´ 20 )
SPLLFMULT = 10 ( ´ 0.50)
PLLSYSCLK = [ ( 10 ´ 20.5)
/ 2 ] / 1 = 102.5 MHz
Figure 6-8. Main PLL
Detailed Description
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Table 6-19. Main PLL Integer Multiplier Configuration
(Bypass PLL to × 31)
200
Detailed Description
SPLLIMULT(6:0)
MULT VALUE
0000000 b
Bypass PLL
0000001 b
×1
0000010 b
×2
0000011 b
×3
0000100 b
×4
0000101 b
×5
0000110 b
×6
0000111 b
×7
0001000 b
×8
0001001 b
×9
0001010 b
× 10
0001011 b
× 11
0001100 b
× 12
0001101 b
× 13
0001110 b
× 14
0001111 b
× 15
0010000 b
× 16
0010001 b
× 17
0010010 b
× 18
0010011 b
× 19
0010100 b
× 20
0010101 b
× 21
0010110 b
× 22
0010111 b
× 23
0011000 b
× 24
0011001 b
× 25
0011010 b
× 26
0011011 b
× 27
0011100 b
× 28
0011101 b
× 29
0011110 b
× 30
0011111 b
× 31
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Table 6-20. Main PLL Integer Multiplier Configuration
(× 32 to × 63)
SPLLIMULT(6:0)
MULT VALUE
0100000 b
× 32
0100001 b
× 33
0100010 b
× 34
0100011 b
× 35
0100100 b
× 36
0100101 b
× 37
0100110 b
× 38
0100111 b
× 39
0101000 b
× 40
0101001 b
× 41
0101010 b
× 42
0101011 b
× 43
0101100 b
× 44
0101101 b
× 45
0101110 b
× 46
0101111 b
× 47
0110000 b
× 48
0110001 b
× 49
0110010 b
× 50
0110011 b
× 51
0110100 b
× 52
0110101 b
× 53
0110110 b
× 54
0110111 b
× 55
0111000 b
× 56
0111001 b
× 57
0111010 b
× 58
0111011 b
× 59
0111100 b
× 60
0111101 b
× 61
0111110 b
× 62
0111111 b
× 63
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Table 6-21. Main PLL Integer Multiplier Configuration
(× 64 to × 95)
202
Detailed Description
SPLLIMULT(6:0)
MULT VALUE
1000000 b
× 64
1000001 b
× 65
1000010 b
× 66
1000011 b
× 67
1000100 b
× 68
1000101 b
× 69
1000110 b
× 70
1000111 b
× 71
1001000 b
× 72
1001001 b
× 73
1001010 b
× 74
1001011 b
× 75
1001100 b
× 76
1001101 b
× 77
1001110 b
× 78
1001111 b
× 79
1010000 b
× 80
1010001 b
× 81
1010010 b
× 82
1010011 b
× 83
1010100 b
× 84
1010101 b
× 85
1010110 b
× 86
1010111 b
× 87
1011000 b
× 88
1011001 b
× 89
1011010 b
× 90
1011011 b
× 91
1011100 b
× 92
1011101 b
× 93
1011110 b
× 94
1011111 b
× 95
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Table 6-22. Main PLL Integer Multiplier Configuration
(× 96 to × 127)
SPLLIMULT(6:0)
MULT VALUE
1100000 b
× 96
1100001 b
× 97
1100010 b
× 98
1100011 b
× 99
1100100 b
× 100
1100101 b
× 101
1100110 b
× 102
1100111 b
× 103
1101000 b
× 104
1101001 b
× 105
1101010 b
× 106
1101011 b
× 107
1101100 b
× 108
1101101 b
× 109
1101110 b
× 110
1101111 b
× 111
1110000 b
× 112
1110001 b
× 113
1110010 b
× 114
1110011 b
× 115
1110100 b
× 116
1110101 b
× 117
1110110 b
× 118
1110111 b
× 119
1111000 b
× 120
1111001 b
× 121
1111010 b
× 122
1111011 b
× 123
1111100 b
× 124
1111101 b
× 125
1111110 b
× 126
1111111 b
× 127
6.10.5 USB PLL
The USB PLL uses the reference clock selectable between the input clock arriving at the XCLKIN pin, or
the internal OSCCLK (originating from the external crystal or oscillator through the X1/X2 pins). An input
mux selects the source of the USB PLL reference based on the UPLLCLKSRC bit of the UPLLCTL
Register (see Figure 6-9). The input clock is multiplied by an integer multiplier and a fractional multiplier as
selected by the UPLLIMULT and UPLLFMULT fields of the UPLLMULT register. For example, to achieve
PLL multiply of 28.5, the integer multiplier should be set to 28, and the fractional multiplier to 0.5. The
output clock from the USB PLL must always be 240 MHz. The PLL output clock is then divided
by 4—resulting in 60 MHz that the USB needs—before entering a mux that selects between this clock and
the PLL input clock (used in the PLL bypass mode). The PLL bypass mode is selected by setting the
UPLLIMULT field of the UPLLMULT register to 0. The output clock from the mux becomes the
USBPLLCLK (there is not another clock divider). Figure 6-9 shows the USB PLL function and
configuration examples. Table 6-23 and Table 6-24 list the integer multiplier configuration values.
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UPLLMULT REG
UPLLCLKSRC
UPLLIMULT
UPLLCTL REG
UPLLFMULT
UPLLEN (2)
UPLLCLKEN
0
6
2
PIN
X1
USB PLL
MAIN
OSC
OSCCLK
0
INTEGER
MULTIPLIER
/4
PLLINP
XCLKIN
USBPLLCLK
FRACTIONAL
MULTIPLIER
000000 :
000001 :
000010 :
000011 :
.
.
.
1
PIN
XCLKIN
´
´
´
´
1
1
2
3
00: NOT USED
01:
´ 0.25
10:
´ 0.50
11:
´ 0.75
1
OUPUT OF
THE USB PLL
IS ALWAYS
DIVIDED BY 4
111101: ´ 61
111110: ´ 62
111111: ´ 63
(1) OUPUT OF THE USB PLL MUST BE ALWAYS 240MHz ( SO THAT USBPLLCLK IS 60MHZ )
(2) WHEN UPLLEN BIT = 0, THE USB PLL IS POWERED OFF
EXAMPLE 1:
X1 OR XCLKIN = 60 MHZ
UPLLIMULT = 000000 ( BYPASS PLL)
EXAMPLE 2:
X1 OR XCLKIN = 10 MHz
UPLLIMULT = 011000 ( ´ 24 )
UPLLFMULT = 00 ( NOT USED)
N/A
PLLSYSCLK = 60 MHz
PLLSYSCLK = ( 10 ´ 24)
/ 4 = 60 MHz
EXAMPLE 3:
X1 OR XCLKIN = 64 MHz
UPLLIMULT = 000011 ( ´ 3)
UPLLFMULT = 11 ( ´ 0.75)
PLLSYSCLK = ( 64 ´ 3.75 )
/ 4 = 60 MHz
Figure 6-9. USB PLL
204
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Table 6-23. USB PLL Integer Multiplier Configuration
(Bypass PLL to × 31)
SPLLIMULT(5:0)
MULT VALUE
000000 b
Bypass PLL
000001 b
×1
000010 b
×2
000011 b
×3
000100 b
×4
000101 b
×5
000110 b
×6
000111 b
×7
001000 b
×8
001001 b
×9
001010 b
× 10
001011 b
× 11
001100 b
× 12
001101 b
× 13
001110 b
× 14
001111 b
× 15
010000 b
× 16
010001 b
× 17
010010 b
× 18
010011 b
× 19
010100 b
× 20
010101 b
× 21
010110 b
× 22
010111 b
× 23
011000 b
× 24
011001 b
× 25
011010 b
× 26
011011 b
× 27
011100 b
× 28
011101 b
× 29
011110 b
× 30
011111 b
× 31
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Table 6-24. USB PLL Integer Multiplier Configuration
(× 32 to × 63)
206
Detailed Description
SPLLIMULT(5:0)
MULT VALUE
100000 b
× 32
100001 b
× 33
100010 b
× 34
100011 b
× 35
100100 b
× 36
100101 b
× 37
100110 b
× 38
100111 b
× 39
101000 b
× 40
101001 b
× 41
101010 b
× 42
101011 b
× 43
101100 b
× 44
101101 b
× 45
101110 b
× 46
101111 b
× 47
110000 b
× 48
110001 b
× 49
110010 b
× 50
110011 b
× 51
110100 b
× 52
110101 b
× 53
110110 b
× 54
110111 b
× 55
111000 b
× 56
111001 b
× 57
111010 b
× 58
111011 b
× 59
111100 b
× 60
111101 b
× 61
111110 b
× 62
111111 b
× 63
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6.11 Master Subsystem Clocking
The internal PLLSYSCLK clock, normally used as a source for all Master Subsystem clocks, is a divideddown output of the Main PLL or X1 external clock input, as defined by the SPLLCKEN bit of the
SYSPLLCTL register.
There is also a second oscillator that internally generates two clocks: 32KHZCLK and 10MHZCLK. The
10MHZCLK is used by the Missing Clock Circuit to detect a possible absence of an external clock source
to the Main Oscillator that drives the Main PLL. Detection of a missing clock results in a substitution of the
10MHZCLK for the PLLSYSCLK. The CLKFAIL signal is also sent to the NMI Block and the Control
Subsystem where this signal can trip the ePWM peripherals.
The 32KHZCLK and 10MMHZCLK clocks are also used by the Cortex-M3 Subsystem as possible sources
for the Deep Sleep Clock.
There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT, SYSPLLSTAT and
SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the C28x processor has
read access. The C28x can request write access to the above registers through the CLKREQEST register.
Cortex-M3 can regain write ownership of these registers through the MCLKREQUEST register.
The Master Subsystem operates in one of three modes: Run Mode, Sleep Mode, or Deep Sleep Mode.
Table 6-25 shows the Master Subsystem low-power modes and their effect on both CPUs, clocks, and
peripherals. Figure 6-10 shows the Cortex-M3 clocks and the Master Subsystem low-power modes.
Table 6-25. Master Subsystem Low-Power Modes
Cortex-M3
LOW-POWER
MODE
STATE OF
Cortex-M3
CPU
CLOCK TO
Cortex-M3
PERIPHERALS
REGISTER USED
TO GATE CLOCKS
TO Cortex-M3
PERIPHERALS
MAIN
PLL
USB
PLL
CLOCK TO C28x
CLOCK TO
SHARED
RESOURCES
CLOCK TO
ANALOG
SUBSYSTEM
Run
Active
M3SSCLK (1)
RCGC
On
On
PLLSYSCLK (2)
PLLSYSCLK (2)
ASYSCLK (3)
(2)
(2)
ASYSCLK (3)
Sleep
Deep Sleep
(1)
(2)
(3)
(4)
(5)
Stopped
Stopped
M3SSCLK
(1)
M3DSDIVCLK
(5)
RCGC or SCGC
(4)
On
On
RCGC or DCGC
(4)
Off
Off
PLLSYSCLK
Off
PLLSYSCLK
Off
Off
PLLSYSCLK or OSCCLK divided-down per the M3SSDIVSEL register. In case of a missing source clock, M3SSCLK becomes
10MHZCLK divided-down per the M3SSDIVSEL register.
PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register. In case the PLL is bypassed, the
PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL register. In case of a missing source clock, the 10MHZCLK is
substituted for the PLLSYSCLK.
PLLSYSCLK or OSCCLK divided-down per the CCLKCTL register. In case of a missing source clock, ASYSCLK becomes 10MHZCLK.
Depends on the ACG bit of the RCC register.
32KHZCLK or 10MHZCLK or OSCCLK chosen/divided-down per the DSLPCLKCFG register, then again divided by the M3SSDIVSEL
register (source determined inside the DSLPCLKCFG register).
Figure 6-11 shows the system clock/PLL.
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REGISTER
ACCESS
M3 CPU
INTR
ASSERT ANY INTERRUPT
TO EXIT SLEEP OR DEEP SLEEP
NVIC
SELECTS TYPE
OF WAKEUP
execution of WFI or WFE instr
activates low power modes
REGISTER
ACCESS
SLEEPEXIT
FCLK
HCLK
M3SSCLK
M3SSCLK
PERIPH
LOGIC
WDOG 0
SYSCTRL REG
M3SSCLK
SELECTS BETWEEN SLEEP
AND DEEP SLEEP MODES
RCC REG
uCRC
M3CLKENBx
M3SSCLK
ACG
OSCCLK
SLEEPDEEP
ENABLE
CLOCK MODE
ENTER A LOW POWER MODE
PERIPH
LOGIC
CLOCKS
(Auto Clock Gate)
WDOG 1
M3SSCLK
OSCCLK
CAN
1,2
XCLKIN
M3RUN
NMI WDOG
GP TIMER (4)
PERIPHERAL
CLOCK
ENABLES
SSI (4)
RCGC REG
( CLOCK GATING – RUN )
SCGS REG
( CLOCK GATING – SLEEP )
DCGC REG
( CLOCK GATING – DEEP SLEEP )
M3CLKENBx
UART (5)
M3SLEEP
USB + PHY
(OTG)
M3DEEPSLEEP
USBPLLCLK
M3DEEPSLEEP
DC REG
DSLPCLKCFG REG
( GLOBAL PERIPHERAL ENABLES )
DSOSCSRC
2
I C (2)
32KHZCLK
OSCCLK
EMAC
M3SSDIVSEL REG
DSDIVOVRIDE
/1
/2
…
/16
10MHZCLK
USB PLL
OSCCLK
M3SSDIVSEL
M3DSDIVCLK
/1
/2
/4
1
XCLKIN
M3SSCLK
0
OSCCLK
XCLKIN
GPIO_MUX1
EPI
MCLKREQUEST REG
uDMA
SYSDIVSEL REG
SYSDIVSEL
SYSPLLSTAT REG
32KHZCLK
10MHZCLK
OSCCLK
IPC
SYSPLLMULT REG
X2
SYSPLLCTL REG
X1
MAIN OSC
MISSING
CLK DETECT
INTERNAL
OSC
0
MAIN PLL
/2
10MHZCLK
M3 NMI
CLOCKFAIL
M3SSCLK
OFF
OSCCLK
/1
/2
/4
/8
1
SHARED
RAMS
PLLSYSCLK
0
CLOCKFAIL
10MHZCLK
CLOCKFAIL
MSG
RAMS
1
CLPMSTAT REG
SHARED
RESOURCES
OSCCLK
CONTROL SUBSYSTEM
Figure 6-10. Cortex-M3 Clocks and Low-Power Modes
208
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PLLSYSCLK
150 MHz Max
OSCCLK
System
PLL
/1
/1
/2
0*
/2
/4*
1
/4
/8*
XPLLCLKOUT Pin
100 MHz Max
/1
Master (M3)
Subsystem
/2
/4*
M3 Read/Write
C28 Read Only**
150 MHz Max
/1
0
on*
off
Control (C28)
Subsystem
M3 Read/Write
0
XTAL
X1
0*
1
off
/1
XTAL OSC
XCLKIN
/2
37.5 MHz Max
Analog
/4
X2
/8*
X1/X2 Ext. XTAL 4 – 20 MHz
X1 Ext. CLK source up to 30 MHz
C28 Read/Write
* Default at reset
** Semaphore request write
Figure 6-11. System Clock/PLL
Detailed Description
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6.11.1 Cortex-M3 Run Mode
In Run Mode, the Cortex-M3 processor, memory, and most of the peripherals are clocked by the
M3SSCLK, which is a divide-down version of the PLLSYSCLK (from Main PLL). The USB is clocked from
a dedicated USB PLL, the CAN peripherals are clocked by M3SSCLK, OSCCLK, or XCLKIN, and one of
two watchdogs (WDOG1) is also clocked by the OSCCLK. Clock selection for these peripherals is
accomplished through corresponding peripheral configuration registers. Clock gating for individual
peripherals is defined inside the RCGS register. RCGS, SCGS, and DCGS clock-gating settings only
apply to peripherals that are enabled in a corresponding DC (Device Configuration) register.
Execution of the WFI instruction (Wait-for-Interrupt) shuts down the HCLK to the Cortex-M3 CPU and
forces the Cortex-M3 Subsystem into Sleep or Deep Sleep low-power mode, depending on the state of
the SLEEPDEEP bit of the Cortex-M3 SYSCTRL register. To come out of a low-power mode, any properly
configured interrupt event terminates the Sleep or Deep Sleep Mode and returns the Cortex-M3
processor/subsystem to Run Mode.
6.11.2 Cortex-M3 Sleep Mode
In Sleep Mode, the Cortex-M3 processor and memory are prevented from clocking, and thus the code is
no longer executing. The gating for the peripheral clocks may change based on the ACG bit of the RCC
register. When ACG = 0, the peripheral clock gating is used as defined by the RCGS registers (same as in
Run Mode); and when ASC = 1, the clock gating comes from the SCGS register. RCGS and SCGS clockgating settings only apply to peripherals that are enabled in a corresponding DC register. Peripheral clock
frequency for the enabled peripherals in Sleep Mode is the same as during the Run Mode.
Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Sleep Mode
depends on the SLEEPEXIT bit of the SYSCTRL register. When the SLEEPEXIT bit is 1, the processor
will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up. After that,
the processor goes back to Sleep Mode. When the SLEEPEXIT bit is 0, the processor wakes up
permanently (for the ISR and thereafter).
210
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6.11.3 Cortex-M3 Deep Sleep Mode
In Deep Sleep Mode, the Cortex-M3 processor and memory are prevented from clocking and thus the
code is no longer executing. The Main PLL, USB PLL, ASYSCLK to the Analog Subsystem, and input
clock to the C28x CPU and Shared Resources are turned off. The gating for the peripheral clocks may
change based on the ACG bit of the RCC register. When ACG = 0, the peripheral clock gating is used as
defined by the RCGS registers (same as in Run Mode); and when ASC = 1, the clock gating comes from
the DCGS register. RCGS and DCGS clock gating settings only apply to peripherals that are enabled in a
corresponding DC register.
Peripheral clock frequency for the enabled peripherals in Deep Sleep Mode is different from the Run
Mode. One of three sources for the Deep Sleep clocks (32KHZCLK, 10MHZCLK, or OSCLK) is selected
with the DSOSCSRC bits of the DSLPCLKCFG register. This clock is divided-down according to
DSDIVOVRIDE bits of the DSLPCLKCFG register. The output of this Deep Sleep Divider is further
divided-down per the M3SSDIVSEL bits of the D3SSDIVSEL register to become the Deep Sleep Clock. If
32KHXCLK or 10MHZCLK is selected in Deep Sleep mode, the internal oscillator circuit (that generates
OSCCLK) is turned off.
The Cortex-M3 processor should enter the Deep Sleep mode only after first confirming that the C28x is
already in the STANDBY mode. Typically, just before entering the STANDBY mode, the C28x will record
in the CLPMSTAT that it is about to do so. The Cortex-M3 processor can read the CLPMSTAT register to
check if the C28x is in STANDBY mode, and only then should the Cortex-M3 processor go into Deep
Sleep. The reason for the Cortex-M3 processor to confirm that the C28x is in STANDBY mode before the
Cortex-M3 processor enters the Deep Sleep mode is that the Deep Sleep mode shuts down the clock to
C28x and its peripherals, and if this clock shutdown is not expected by the C28x, unintended
consequences could result for some of the C28x control peripherals.
Deep Sleep Mode is terminated by any properly configured interrupt event. Exiting from the Deep Sleep
Mode depends on the SLEEPEXIT bit of the SYSCTRL register. When the SLEEPEXIT bit is 1, the
processor will temporarily wake up only for the duration of the ISR of the interrupt causing the wake-up.
After that, the processor goes back to Deep Sleep Mode. When the SLEEPEXIT bit is 0, the processor
wakes up permanently (for the ISR and thereafter).
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6.12 Control Subsystem Clocking
The CLKIN input clock to the C28x processor is normally a divided-down output of the Main PLL or X1
external clock input. There are four registers associated with the Main PLL: SYSPLLCTL, SYSPLLMULT,
SYSPLLSTAT and SYSDIVSEL. Typically, the Cortex-M3 processor writes to these registers, while the
C28x processor has read access. The C28x can request write access to the above registers through the
CLKREQEST register. The Cortex-M3 can regain write ownership of these registers through the
MCLKREQUEST register.
Individual C28x peripherals can be turned on or off by gating C28SYSCLK to those peripherals, which is
done through the CPCLKCR0,2,3 registers.
The C28x processor outputs two clocks: C28CPUCLK and C28SYSCLK. The C28SYSCLK is used by
C28x peripherals, C28x Timer 0, C28x Timer 1, and C28x Timer 2. C28x Timer 2 can also be clocked by
OSCCLK or 10MHZCLK (see Figure 6-12). The C28CPUCLK is used by the C28x CPU, FPU, VCU, and
PIE.
The Control Subsystem operates in one of three modes: Normal Mode, IDLE Mode, or STANDBY Mode.
Table 6-26 shows the Control Subsystem low-power modes and their effect on the C28x CPU, clocks, and
peripherals. Figure 6-12 shows the Control Subsystem clocks and low-power modes.
Table 6-26. Control Subsystem Low-Power Modes (1)
STATE OF C28x CPU
C28CPUCLK (2)
C28SYSCLK (3)
REGISTERS USED TO
GATE CLOCKS TO
C28x PERIPHERALS
Normal
Active
On
On
CPCLKCR0,1,3
IDLE
Stopped
Off
On
CPCLKCR0,1,3
STANDBY
Stopped
Off
Off
N/A
C28x
LOW-POWER MODE
(1)
(2)
(3)
The input clock to the C28x CPU is PLLSYSCLK from the Master Subsystem. This clock is turned off when the Master Subsystem
enters the Deep Sleep mode.
C28CPUCLK is an output from the C28x CPU. C28CPUCLK clocks the C28x FPU, VCU, and PIE.
C28SYSCLK is an output from the C28x CPU. C28SYSCLK clocks C28x peripherals.
6.12.1 C28x Normal Mode
In Normal Mode, the C28x processor, Local Memory, and C28x peripherals are clocked by the
C28SYSCLK, which is derived from the C28CLKIN input clock to the C28x processor. The FPU, VCU, and
PIE are clocked by the C28CPUCLK, which is also derived from the C28CLKIN. Timer 2 can also be
clocked by the TMR2CLK, which is a divided-down version of one of three source clocks—C28SYSCLK,
OSCCLK, and 10MHZCLK—as selected by the CLKCTL register. Additionally, the LOSPCP register can
be programmed to provide a dedicated clock (C28LSPCLK) to the SCI, SPI, and McBSP peripherals.
Clock gating for individual peripherals is defined inside the CPCLKCR0,1,3 registers. Execution of the
IDLE instruction stops the C28x processor from clocking and activates the IDLES signal. The IDLES
signal is gated with two LPM bits of the CPCLKCR0 register to enter the C28x Subsystem into IDLE mode
or STANDBY Mode.
6.12.2 C28x IDLE Mode
In IDLE Mode, the C28x processor stops executing instructions and the C28CPUCLK is turned off. The
C28SYSCLK continues to run. Exit from IDLE Mode is accomplished by any enabled interrupt or the
C28NMIINT (C28x nonmaskable interrupt).
Upon exit from IDLE Mode, the C28CPUCLK is restored. If LPMWAKE interrupt is enabled, the
LPMWAKE ISR is executed. Next, the C28x processor starts fetching instructions from a location
immediately following the IDLE instruction that originally triggered the IDLE Mode.
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GPIO_MUX1
C28x NMI
MASTER SUBSYSTEM
CLOCKFAIL
SRXRST
CLKDIV
10MHZCLK
OSCCLK
SYSDIVSEL REG
CLPMSTAT REG
OFF
/1
/2
/4
/8
SYSPLLSTAT REG
SOCBO
SOCAO
SYNCO
SYSPLLMULT REG
SYSPLLCTL REG
CCLKREQUEST REG
M3SSCLK
C28x must control pin
CXCLK REG
/32
PLLSYSCLK
XPLLCLKCFG REG
XCLKOUTDIV
/4
/2
/1
OFF
C28SYSCLK
LOSPCP REG
ASYSCLK
M3 must
control pin
XPLLCLKOUTDIV
OFF
0
1
2
3
C28SYSCLK
CLKOFF REG
/4
PF2_GPIO34
PULSE
STRETCH
ACIBRST
ANALOG SUBSYSTEM
ASYSRST
CCLKCTL REG
C28SYSCLK
XCLKOUT
GPIO_MUX1
EPWM (12)
‘0’
LSPCLK
C28LSPCLK
SCI
SPI
PIEINTRS (1)
2
IC
MTOCIPC(1)
TIMER 2
STANDBY
MODE
C28CLKIN
C28x CPU
EXIT
STANDBY
MODE
C28 DMA
execution of IDLE instruction
activates the IDLES signal
ENTER
STANDBY
MODE
IDLES
EXIT
IDLE
MODE
ENTER
IDLE
MODE
Requests To Wake From IDLE Mode
Requests To Wake From STANDBY Mode
McBSP
(NOTE: IN REVISION 0 OF SILICON, XCLKOUT = PLLSYSCLK DIVIDED DOWN BY 1, 2 OR 4)
TINT2
/1
/2
/4
…
/14
TINT 1
TIMER 1
TIMER 0
C28 XINT(3)
PIEINTRS (12:1)
C28x
PIE
C28NMIINT
C28 FPU/VCU
EQEP (3)
C28x
PIE
LPM(1)
LPM(0)
CLPMCR0 REG
ECAP (6)
C28SYSCLK
C28CPUCLK
C28SYSCLK
LPMWAKE
PCLKCR3 REG
CLKCTL REG
SELECT QUALIFICATION
LPM WAKEUP
PCLKCR0 REG
LPMSEL1 REG
GPI (63:0)
LPMSEL2 REG
C28CLKENBx
C28SYSCLK
OSCCLK
GPIO_MUX1
IPC
C28x NMI
10MHZCLK
CTMR2CLK
PRESCALE
/1
/2
/4
/8
/16
TMR2CLK
TMR2CLKSRCSEL
SELECT ONE OF 62 GPIs
PCLKCR1 REG
Figure 6-12. C28x Clocks and Low-Power Modes
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6.12.3 C28x STANDBY Mode
In STANDBY Mode, the C28x processor stops executing instructions and the C28CLKIN, C28CPUCLK,
and C28SYSCLK are turned off. Exit from STANDBY Mode is accomplished by one of 64 GPIOs from the
GPIO_MUX1 block, or MTOCIPCINT2 (interrupt from MTOC IPC peripheral). The wakeup GPIO selected
inside the GPIO_MUX block enters the Qualification Block as the LPMWAKE signal. Inside the
Qualification Block, the LPMWAKE signal is sampled per the QUALSTDBY bits (bits [7:2] of the
CPCLKCR0 register) before propagating into the wake request logic.
Cortex-M3 should use CLPMSTAT register bits to tell the C28x to go into STANDBY mode before going
into Deep Sleep mode. Otherwise, the clock to the C28x will be turned off suddenly when the control
software is not expecting this clock to shut off. When the device is in Deep Sleep/STANDBY mode, wakeup should happen only from the Master Subsystem, because all C28x clocks are off (C28CLKIN,
C28CPUCLK, C28SYSCLK), thus preventing the C28x from waking up first.
Upon exit from STANDBY Mode, the C28CLKIN, C28SYSCLK, and C28CPUCLK are restored. If the
LPMWAKE interrupt is enabled, the LPMWAKE ISR is executed. Next, the C28x processor starts fetching
instructions from a location immediately following the IDLE instruction that originally triggered the
STANDBY Mode.
NOTE
For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function
is available on silicon revision 0 devices (GPIO and other functions listed in Table 4-1 are not
available).
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6.13 Analog Subsystem Clocking
The Analog Subsystem is clocked by ASYSCLK, which is a divided-down version of the PLLSYSCLK as
defined by CLKDIV bits of the CCLKCTL register. The CCLKCTL register is exclusively accessible by the
C28x processor. The CCLKCTL register is reset by ASYSRST, which is derived from two Analog
Subsystem resets—ACIBRST and SRXRST. Therefore, while normally the C28x controls the frequency of
ASYSCLK, it is possible for the Cortex-M3 software to restore the ASYSCLK to its default value by
resetting the Analog Subsystem.
The ASYSCLK is shut down when the Cortex-M3 processor enters the Deep Sleep mode.
6.14 Shared Resources Clocking
The IPC, Shared RAMs, and Message RAMs are clocked by PLLSYSCLK. EPI is clocked by M3SSCLK.
The PLLSYSCLK normally refers to the output of the Main PLL divided-down per the SYSDIVSEL register.
In case the PLL is bypassed, the PLLSYSCLK becomes the OSCCLK divided-down per the SYSDIVSEL
register. In case of a missing source clock, the 10MHZCLK is substituted for the PLLSYSCLK.
Although EPI is a shared peripheral, it is physically located inside the Cortex-M3 Subsystem; therefore,
EPI is clocked by M3SSCLK.
6.15 Loss of Input Clock (NMI Watchdog Function)
The Concerto devices use two type of input clocks. The main clock, for clocking most of the digital logic of
the Master, Control, and Analog subsystems, enters the chip through pins X1 and X2 when using external
crystal or just pin X1 when using an external oscillator. The second clock enters the chip through the
XCLKIN pin and this second clock can be used to clock the USB PLL and CAN peripherals. Only the main
clock has a built-in Missing Clock Detection circuit to recognize when the clock source vanishes and to
enable other chip components to take corrective or recovery action from such event (see Figure 6-13).
The Missing Clock Detection circuit itself is clocked by the 10MHZCLK (from an internal zero-pin oscillator)
so that, if the main clock disappears, the circuit is still working. Immediately after detecting a missing
source clock, the Missing Clock Detection circuit outputs the CLOCKFAIL signal to the Cortex-M3 NMI
circuit, the C28x NMI, ePWM peripherals, and the PLLSYSCLK mux. When the PLLSYSCLK mux senses
an active CLOCKFAIL signal, the PLLSYSCLK mux revives the PLLSYSCLK using the 10MHZCLK.
Simultaneously, the ePWM peripherals can use the CLOCKFAIL signal to stop down driving motor control
outputs. The NMI blocks respond to the CLOCKFAIL signal by sending an NMI interrupt to a
corresponding CPU, while starting the associated NMI watchdog counter.
If the software does not respond to the clock-fail condition, the watchdog timers will overflow, resulting in
the device reset. If the software does react to the NMI, the software can prevent the impending reset by
disabling the watchdog timers, and then the software can initiate necessary corrective action such as
switching over to an alternative clock source (if available) or the software can initiate a shut-down
procedure for the system.
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X2
PIN
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1
MAIN
OSC
X1
PIN
OSCCLK
MAIN
PLL
4
ADDITIONAL CLOCK CONTROL LOGIC
PLLSYSCLK
10MHZCLK
MISSING
CLK DETECT
C28CLKIN
M3SSCLK
3
2
M3
CPU
INTERNAL
OSC
7
5
3
CLOCKFAIL
M3 NMI
CLOCKFAIL
RESETS
3
C28x NMI
THE INPUT CLOCK IS DISRUPTED
2
CLOCKFAIL SIGNAL BECOMES ACTIVE
3
CLOCK FAIL SIGNAL IS SENT TO M3 NMI BLOCK, C28 NMI
BLOCK, EPWM MODULES AND THE PLLSYSCLK MUX
4
PLLSYSCLK SWITCHES TO THE 10MHZCLK
5
CPUS RESPOND TO NMIS AND THE
WATCHDOGS START COUNTING
6
SOFTWARE TAKES CORRECTIVE/RECOVERY ACTION
7
IF SOFTWARE DOES NOT STOP THE WATCHDOG COUNTERS, THE
WATCHDOGS WILL RESET THE DEVICE AFTER THE COUNT RUNS OUT
M3 NMI WDOG
OTHER NMI
SOURCES
TYPICAL ACTIVITY FOLLOWING
A MISSING CLOCK DETECTION :
1
M3NMI
C28NMI
C28x NMI WDOG
CLOCKFAIL
5
3
7
C28x
CPU
EPWM
6
EPWM_A
EPWM_B
C28CLKIN
GPIO_MUX1
PIN
PIN
Figure 6-13. Missing Clock Detection
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6.16 GPIOs and Other Pins
Most Concerto external pins are shared among many internal peripherals. This sharing of pins is
accomplished through several I/O muxes where a specific physical pin can be assigned to selected
signals of internal peripherals.
Most of the I/O pins of the Concerto MCU can also be configured as programmable GPIOs. Exceptions
include the X1 and X2 oscillator inputs; the XRS digital reset and ARS analog reset; the VREG12EN and
VREG18EN internal voltage regulator enables; and five JTAG pins. The 144 primary GPIOs are grouped
in 2 programmable blocks: GPIO_MUX1 block (136 pins) and GPIO_MUX2 block (8 pins). Additionally,
eight secondary GPIOs are available through the AIO_MUX1 block (four pins) and AIO_MUX2 block (four
pins). Figure 6-14 shows the GPIOs and other pins.
6.16.1 GPIO_MUX1
One-hundred and thirty-six pins of the GPIO_MUX1 block can be selectively mapped through
corresponding sets of registers to all Cortex-M3 peripherals, to all C28x peripherals, to 136 GeneralPurpose Inputs, to 136 General-Purpose Outputs, or a mixture of all of the above. The first 64 pins of
GPIO_MUX1 (GPIO0–GPIO63) can also be mapped to 12 ePWM Trip Inputs, 6 eCAP inputs, 3 External
Interrupts to the C28x PIE, and the C28x STANDBY Mode Wakeup signal (LMPWAKE). Additionally, each
GPIO_MUX1 pin can have a pullup enabled or disabled. By default, all pullups and outputs are disabled
on reset, and all pins of the GPIO_MUX1 block are mapped to Cortex-M3 peripherals (and not to C28x
peripherals).
Figure 6-15 shows the internal structure of GPIO_MUX1. The blue blocks represent the Master
Subsystem side of GPIO_MUX1, and the green blocks are the Control Subsystem side. The grey block in
the center, Pin-Level Mux, is where the GPIO_MUX1 pins are individually assigned between the two
subsystems, based on how the configuration registers are programmed in the blue and green blocks (see
Figure 6-16 for the configuration registers).
Pin-Level Mux assigns Master Subsystem peripheral signals, Control Subsystem peripheral signals, or
GPIOs to the 136 GPIO_MUX1 pins. In addition to connecting peripheral I/Os of the two subsystems to
pins, the Pin-Level Mux also provides other signals to the subsystems: XCLKIN and GPIO[S:A] IRQ
signals to the Master Subsystem, plus GPTRIP[12:1] and GPI[63:0] signals to the Control Subsystem.
XCLKIN carries a clock from an external pin to USB PLL and CAN modules. The 17 GPIO[S:A] IRQ
signals are interrupt requests from selected external pins to the NVIC interrupt controller. The 12
GPTRIP[12:1] signals carry trip events from selected external pins to C28x control peripherals—ePWM,
eCAP, and eQEP. Sixty-four GPI signals go to the C28x LPM GPIO Select block where one of them can
be selected to wake up the C28x CPU from Low-Power Mode. One-hundred and thirty-six (136) GPI
signals go to the C28x QUAL block where they can be configured with a qualification sampling period (see
Figure 6-16).
The configuration registers for the muxing of Master Subsystem peripherals are organized in 17 sets
(A–S), with each set being responsible for eight pins. The first nine sets of these registers (A–J) are
programmable by the Cortex-M3 CPU through the AHB bus or the APB bus. The remaining sets of
registers (K–S) are programmable by the AHB bus only. The configuration register for the muxing of
Control Subsystem peripherals are organized in five sets (A–E), with each set being responsible for up to
32 pins. These registers are programmable by the C28x CPU through the C28x CPU bus. Figure 6-16
shows set A of the Master Subsystem GPIO configuration registers, set A of the Control Subsystem
registers, and the muxing logic for one GPIO pin as driven by these registers.
Detailed Description
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12
AIO_MUX1
MII TX1
MII TX0
MII TX2
MII TX3
MII TXEN
MII MDC
MII PHYRSTN
MII TXER
MII MDIO
MII PHYINTRN
MII CRS
MII COL
MII RXCK
MII TXCK
MII RXDV
MII RXER
MII RX0
MII RX2
MII RX1
UART
(5)
NVIC
CAN
(2)
2
SSI
(4)
IC
(2)
I2C (1:0) SCL
I2C (1:0) SDA
SSI (3:0) RX
SSI (3:0) TX
SSI (3:0) CLK
SSI (3:0) FSS
XCLKIN
GPIO
CAN (1:0) TX
CAN (1:0) RX
GPIO_MUX1
U (4:0) RX
VDDA
(3.3V)
U (4:0) TX
GPIO (H:A) IRQ
M3EXTNMI
GPIO
GPIO_MUX2
MUX
136
136
SCLA
SDAA
SPISOMI
SPISIMO
SPICLK
SPISTE
EQEP (3:1) I
EQEP (3:1) B
EQEP (3:1) S
EQEP (3:1) A
ECAP (6:1)
GPTRIP (12:7)
LPM WAKEUP
GPTRIP (6:4)
VSSA
(0V)
GPTRIP (12:1)
COMPOUT (6:1)
EPWM (12:1) B
GPI (63:0)
EPWM (12:1) A
MUX
8
MII RX3
EMAC
ADC
1
6
COMPARATOR
+ DAC UNITS
8
USB0OFLT
COMPB1
COMPB2
COMPB3
USB0EPEN
USB
M3
NMI
COMPA1
COMPA2
COMPA3
USB0VBUS
USB
PLL
EPI
USB0ID
ADC1INB0
ADC1INB2
ADC1INB3
ADC1INB4
ADC1INB6
ADC1INB7
USB0DP
ADC1INA0
ADC1INA2
ADC1INA3
ADC1INA4
ADC1INA6
ADC1INA7
XCLKIN
4
USB0DM
MUX
EPI0S (43:0)
GPIO
LPMWAKE
COMPA4
COMPA5
COMPA6
COMPB4
COMPB5
COMPB6
EPWM
(12)
C28X
CPU
ADC
2
XINT
(3)
ECAP
(6)
EQEP
(3)
2
SPI
IC
McBSP
DEBUG
VREGS
CLOCKS
RESETS
SCIRXDA
SCITXDA
MFSXA
MDXA
MDRA
MCLXA
MCLRA
MFSRA
M3EXTNMI
XCLKIN
X1
X2
XRS
ARS
12
JTAG (7)
AIO_MUX2
VREG18EN
MUX
4
VREG12EN
GPIO
SCI
NMI
LPMWAKE
ADC2INB0
ADC2INB2
ADC2INB3
ADC2INB4
ADC2INB6
ADC2INB7
XCLKOUT
ADC2INA0
ADC2INA2
ADC2INA3
ADC2INA4
ADC2INA6
ADC2INA7
Figure 6-14. GPIOs and Other Pins
218
Detailed Description
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
M3 AHB BUS
BUS BRIDGE
M3 APB BUS
XCLKIN
XCLKIN
EMAC
2
SSI
(4)
IC
(2)
M3
uDMA
I2C (1:0) SCL
INTERRUPTS
NVIC
M3 PERIPHERAL SIGNAL ROUTING
M3 MUX
A
M3 MUX
B
8
M3 MUX
D
8
M3 MUX
E
8
M3 MUX
F
8
8
M3 MUX
G
M3 MUX
H
8
M3 MUX
J
8
M3 MUX
C
8
M3 MUX
K
M3 MUX
L
8
8
M3
CPU
I2C (1:0) SDA
SSI (3:0) TX
SSI (3:0) RX
SSI (3:0) FSS
SSI (3:0) CLK
CAN
(2)
CAN (1:0) TX
UART
(5)
U (4:0) TX
MII TX1
MII TX0
MII TX3
MII TX2
MII TXEN
MII MDC
MII TXER
MII PHYRSTN
MII MDIO
MII PHYINTRN
MII CRS
MII COL
MII TXCK
MII RXCK
MII RXER
MII RXDV
MII RX1
MII RX0
MII RX3
MII RX2
EPI0S (43:0)
USB0EPEN
USB0OFLT
USB0VBUS
USB0ID
USB0DP
M3
EXT
NMI
USB0DM
M3
NMI
EPI
CAN (1:0) RX
USB
U (4:0) RX
USB
PLL
M3 MUX
M
8
8
M3 MUX
N
M3 MUX
P
8
M3 MUX
Q
8
M3 MUX
R
8
M3 MUX
S
8
8
XCLKIN
GPIO
(S:A)
IRQ
- MUX
PIN LEVEL
136
32
32
C28 MUX A
32
C28 MUX B
32
C28 MUX C
GPTRIP
(12:1)
8
C28 MUX D
C28 MUX E
GPI
(63:0)
LPM
WAKEUP
C28 PERIPHERAL SIGNAL ROUTING
EPWM (12:1) B
EPWM (12:1) A
ECAP (6:1)
EQEP (3:1) I
EQEP (3:1) S
EQEP (3:1) B
EQEP (3:1) A
SCLA
SDAA
SPISIMO
SPISTE
SPISOMI
SPICLK
SCITXDA
SCIRXDA
MDXA
MFSXA
MDRA
MCLXA
MCLRA
MFSRA
LPM
WAKE
C28x
DMA
McBSP
SCI
2
SPI
IC
EQEP
(3)
ECAP
(6)
GPTRIP (12:7)
EPWM
(12)
GPTRIP (12:1)
XINT
(3)
C28x
CPU
GPTRIP (6:4)
C28 CPU BUS
C28 DMA BUS
Figure 6-15. GPIO_MUX1 Block
Detailed Description
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
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PERIPHERALS 1-15 REPRESENT A SET OF UP TO
15 M3 PERIPHERALS SPECIFIC TO ONE I/O PIN
BLUE REGISTER SET A
REPRESENTS 8 OF 136
GPIOs. REMAINING 128
GPIOs ARE CONTROLLED BY
SIMILAR REGISTER SETS
B, C, D, … Q, R, S
TO/FROM M3 PERIPH 1-11
TO/FROM M3 PERIPH 12-15
GPIO63
ONLY
PRIMARY
GPIOPCTL REG
GPIO (A)
IRQ
XCLKIN
ALT
M3 REG SET A
PRIMARY
AT RESET
GPIOIBE REG
GPIOIS REG
M3 REG SET A
GREY LOGIC IS SPECIFIC TO
ONE DEVICE I/O PIN
A-S INTR REQUESTS TO M3
M3 CLOCKS
GPIOAPSEL REG
GPIOIEV REG
GPIOIM REG
GPIORIS REG
ENB
GPIOPUR REG
PULLUP
DISABLED
ON RESET
GPIOODR REG
GPIOCSEL REG
GPIODEN REG
GPIOAFSEL REG
GPIOLOCK REG
GPIOCR REG
M3 REG SET A
M3 REG SET A
GPIOAMSEL REG
(USB ANALOG SIGNALS)
M3 REG SET A
GPIOMIS REG
GPIODATA REG
GPIOICR REG
GPIODIR REG
M3 REG SET A
NORMAL
AT RESET
‘1’
SELECT M3
AT RESET
I/O DISABLED
AT RESET
GPIO MODE
AT RESET
PULLUP
INPUT
‘0’
(4 PINS ONLY)
ANALOG USB
SIGNALS
ONE OF 136
GPIO_MUX1 PINS
GPIOAMSEL REG
OE
OUTPUT
DISABLED
AFTER RESET
(M3 GPIO)
OUTPUT
OPEN
DRAIN
LOGIC
OE
OE
‘1’
ASYNC INPUT
ORANGE LOGIC SHOWS
USB ANALOG FUNCTIONS
(APPLIES TO 4 PINS ONLY)
OE
XRS
SYNC INPUT
SYNC
GREEN REGISTER SET A
SHOWN REPRESENTS 32
OF 136 GPIOs. THE
REMAINING 104 GPIOs
ARE CONTROLLED BY
SIMILAR REGISTER SETS
B, C, D AND E
C28SYSCLK
C28 REG SET A
GPIO
AT RESET
GPACTRL REG
QUAL
(C28 GPIO)
OUTPUTS
C28 REG SET A
6 SAMPLES
GPASET REG
GPASEL1 REG
3 SAMPLES
GPACLEAR REG
GPASEL2 REG
SYNC INPUT
AT RESET
GPATOGGLE REG
C28 REG SET A
SEL(1:0)
GPADIR REG
EACH I/O PIN HAS A
DEDICATED PAIR OF
BITS FOR MUX SELECT
GPADAT REG
EACH I/O PIN HAS A
DEDICATED PAIR OF
BITS FOR MUX SELECT
GPAMUX1 REG
GPAMUX2 REG
SEL(1:0)
SEL(1:0)
TO C28x CPU WAKE-UP FROM
A LOW POWER MODE
C28 REG SET A
PERIPHERALS 1-3 REPRESENT A SET OF UP TO
THREE C28 PERIPHERALS SPECIFIC TO ONE I/O PIN
FROM C28 PERIPH 1-3
GPI (63:0)
INPUTS
N/C AT RESET
N/C
TO C28 PERIPH 1-3
GPTRIP1SEL REG
…
GPTRIP (12:1)
TO XINT, ECAP, EPWM
GPTRIP12SEL REG
Figure 6-16. GPIO_MUX1 Pin Mapping Through Register Set A
220
Detailed Description
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www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
For each of the 8 pins in set A of the Cortex-M3 GPIO registers, register GPIOPCTL selects between 1 of
11 possible primary Cortex-M3 peripheral signals, or 1 of 4 possible alternate peripheral signals. Register
GPIOAPSEL then picks one output to propagate further along the muxing chain towards a given pin. The
input takes the reverse path. See Table 6-27 and Table 6-28 for the mapping of Cortex-M3 peripheral
signals to GPIO_MUX1 pins.
Similarly, on the C28x side, GPAMUX1 and GPAMUX2 registers select 1 of 4 possible C28x peripheral
signals for each of 32 pins of set A. The selected C28x peripheral output then propagates further along
the muxing chain towards a given pin. The input takes the reverse path. See Table 6-29 for the mapping
of C28x peripheral signals to GPIO_MUX1 pins.
In addition to passing mostly digital signals, four GPIO_MUX1 pins can also be assigned to analog
signals. The GPIO Analog Mode Select (GPIOAMSEL) Register is used to assign four pins to analog USB
signals. PF6_GPIO38 becomes USB0VBUS, PG2_GPIO42 becomes USB0DM, PG5_GPIO45 becomes
USB0DP, and PG6_GPIO46 becomes USB0ID. When analog mode is selected, these four pins are not
available for digital GPIO_MUX1 options as described above.
Another special case is the External Oscillator Input signal (XCLKIN). This signal, available through pin
PJ7_GPIO63, is directly tied to USBPLLCLK (clock input to USB PLL) and two CAN modules. XCLKIN is
always available at these modules where it can be selected through local registers.
NOTE
For GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46, only the corresponding USB function
is available on silicon revision 0 devices (GPIO and other functions listed in Table 4-1 are not
available).
Detailed Description
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Table 6-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes) (1)
ANALOG
MODE
(USB PINS)
DEVICE
PIN NAME
M3
PRIMARY
MODE 1
M3
PRIMARY
MODE 2
M3
PRIMARY
MODE 3
M3
PRIMARY
MODE 4
M3
PRIMARY
MODE 5
M3
PRIMARY
MODE 6
M3
PRIMARY
MODE 7
–
PA0_GPIO0
U0RX
–
–
–
–
–
–
PA1_GPIO1
U0TX
–
–
–
–
–
–
PA2_GPIO2
SSI0CLK
–
MIITXD2
–
–
–
PA3_GPIO3
SSI0FSS
–
MIITXD1
–
–
PA4_GPIO4
SSI0RX
–
MIITXD0
–
PA5_GPIO5
SSI0TX
–
–
PA6_GPIO6
I2C1SCL
–
PA7_GPIO7
–
(1)
(2)
222
M3
PRIMARY
MODE 8
M3
PRIMARY
MODE 9
M3
PRIMARY
MODE 10
M3
PRIMARY
MODE 11
–
I2C1SCL
U1RX
–
–
–
I2C1SDA
U1TX
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CAN0RX
–
–
–
–
–
–
MIIRXDV
–
CAN0TX
–
–
–
–
–
–
CCP1
MIIRXCK
–
–
CAN0RX
–
USB0EPEN
–
–
–
I2C1SDA
CCP4
MIIRXER
–
–
CAN0TX
CCP3
USB0PFLT
–
–
–
PB0_GPIO8
CCP0
–
–
–
U1RX
–
–
–
–
–
–
–
PB1_GPIO9
CCP2
–
–
CCP1
U1TX
–
–
–
–
–
–
–
PB2_GPIO10
I2C0SCL
–
–
CCP3
CCP0
–
–
USB0EPEN
–
–
–
–
PB3_GPIO11
I2C0SDA
–
–
–
–
–
–
USB0PFLT
–
–
–
–
PB4_GPIO12
–
–
–
U2RX
CAN0RX
–
U1RX
EPI0S23
–
–
–
–
PB5_GPIO13
–
CCP5
CCP6
CCP0
CAN0TX
CCP2
U1TX
EPI0S22
–
–
–
–
PB6_GPIO14
CCP1
CCP7
–
–
–
CCP5
–
EPI0S37 (2)
–
–
–
–
PB7_GPIO15
–
–
–
EXTNMI
–
–
MIIRXD1
EPI0S36 (2)
–
–
–
–
PD0_GPIO16
–
CAN0RX
–
U2RX
U1RX
CCP6
MIIRXDV
–
–
–
–
–
PD1_GPIO17
–
CAN0TX
–
U2TX
U1TX
CCP7
MIITXER
–
–
CCP2
–
–
PD2_GPIO18
U1RX
CCP6
–
CCP5
–
–
–
EPI0S20
–
–
–
–
PD3_GPIO19
U1TX
CCP7
–
CCP0
–
–
–
EPI0S21
–
–
–
–
PD4_GPIO20
CCP0
CCP3
–
MIITXD3
–
–
–
–
–
EPI0S19
–
–
PD5_GPIO21
CCP2
CCP4
–
MIITXD2
–
–
–
–
U2RX
EPI0S28
–
–
PD6_GPIO22
–
–
–
MIITXD1
–
–
–
–
U2TX
EPI0S29
–
–
PD7_GPIO23
–
–
CCP1
MIITXD0
–
–
–
–
–
EPI0S30
–
–
PE0_GPIO24
–
SSI1CLK
CCP3
–
–
–
–
EPI0S8
USB0PFLT
–
–
–
PE1_GPIO25
–
SSI1FSS
–
CCP2
CCP6
–
–
EPI0S9
–
–
–
–
PE2_GPIO26
CCP4
SSI1RX
–
–
CCP2
–
–
EPI0S24
–
–
–
–
PE3_GPIO27
CCP1
SSI1TX
–
–
CCP7
–
–
EPI0S25
–
–
–
–
PE4_GPIO28
CCP3
–
–
–
U2TX
CCP2
MIIRXD0
EPI0S34 (2)
–
–
–
–
PE5_GPIO29
CCP5
–
–
–
–
–
–
EPI0S35 (2)
–
–
–
–
PE6_GPIO30
–
–
–
–
–
–
–
–
–
–
–
–
PE7_GPIO31
–
–
–
–
–
–
–
–
–
–
–
Blank fields represent Reserved functions.
This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.
Detailed Description
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 6-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes)(1) (continued)
ANALOG
MODE
(USB PINS)
DEVICE
PIN NAME
M3
PRIMARY
MODE 1
M3
PRIMARY
MODE 2
M3
PRIMARY
MODE 3
M3
PRIMARY
MODE 4
M3
PRIMARY
MODE 5
M3
PRIMARY
MODE 6
M3
PRIMARY
MODE 7
M3
PRIMARY
MODE 8
M3
PRIMARY
MODE 9
M3
PRIMARY
MODE 10
M3
PRIMARY
MODE 11
–
PF0_GPIO32
CAN1RX
–
–
MIIRXCK
–
–
–
–
–
PF1_GPIO33
CAN1TX
–
–
MIIRXER
–
–
–
–
–
–
–
–
CCP3
–
PF2_GPIO34
–
–
MIIPHYINTR
–
–
–
–
–
(2)
SSI1CLK
–
–
(2)
EPI0S32
–
PF3_GPIO35
–
–
MIIMDC
–
–
–
–
SSI1FSS
–
–
–
PF4_GPIO36
CCP0
–
MIIMDIO
–
–
–
–
EPI0S12
SSI1RX
–
–
–
PF5_GPIO37
CCP2
–
MIIRXD3
–
–
–
–
EPI0S15
SSI1TX
–
–
USB0VBUS
PF6_GPIO38
CCP1
–
MIIRXD2
–
–
–
–
EPI0S38(2)
–
–
–
–
PF7_GPIO39
–
–
–
–
–
–
–
–
–
–
–
–
PG0_GPIO40
U2RX
–
I2C1SCL
–
–
–
USB0EPEN
EPI0S13
–
–
–
–
PG1_GPIO41
U2TX
–
I2C1SDA
–
–
–
–
EPI0S14
–
–
–
EPI0S33
(2)
USB0DM
PG2_GPIO42
–
–
MIICOL
–
–
–
–
–
–
–
–
PG3_GPIO43
–
–
MIICRS
–
–
–
–
–
–
–
–
–
PG4_GPIO44
–
–
–
–
–
–
–
–
–
–
–
USB0DP
PG5_GPIO45
CCP5
–
MIITXEN
–
–
–
–
EPI0S40(2)
–
–
–
USB0ID
PG6_GPIO46
–
–
MIITXCK
–
–
–
–
EPI0S41(2)
–
–
–
–
PG7_GPIO47
–
–
MIITXER
–
–
–
–
CCP5
EPI0S31
–
–
–
PH0_GPIO48
CCP6
–
MIIPHYRST
–
–
–
–
EPI0S6
–
–
–
–
PH1_GPIO49
CCP7
–
–
–
–
–
–
EPI0S7
–
–
–
–
PH2_GPIO50
–
–
–
–
–
–
–
EPI0S1
MIITXD3
–
–
–
PH3_GPIO51
–
–
–
USB0EPEN
–
–
–
EPI0S0
MIITXD2
–
–
–
PH4_GPIO52
–
–
–
USB0PFLT
–
–
–
EPI0S10
MIITXD1
–
SSI1CLK
–
PH5_GPIO53
–
–
–
–
–
–
–
EPI0S11
MIITXD0
–
SSI1FSS
–
PH6_GPIO54
–
–
–
–
–
–
–
EPI0S26
MIIRXDV
–
SSI1RX
–
PH7_GPIO55
–
–
MIIRXCK
–
–
–
–
EPI0S27
–
–
SSI1TX
–
PJ0_GPIO56
–
–
MIIRXER
–
–
–
–
EPI0S16
–
–
I2C1SCL
–
PJ1_GPIO57
–
–
–
–
–
–
–
EPI0S17
USB0PFLT
–
I2C1SDA
–
PJ2_GPIO58
–
–
–
–
–
–
–
EPI0S18
CCP0
–
–
–
PJ3_GPIO59
–
–
–
–
–
–
–
EPI0S19
–
CCP6
–
–
PJ4_GPIO60
–
–
–
–
–
–
–
EPI0S28
–
CCP4
–
–
PJ5_GPIO61
–
–
–
–
–
–
–
EPI0S29
–
CCP2
–
–
PJ6_GPIO62
–
–
–
–
–
–
–
EPI0S30
–
CCP1
–
–
PJ7_GPIO63/
XCLKIN
–
–
–
–
–
–
–
–
–
CCP0
–
EPI0S39
Detailed Description
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223
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 6-27. GPIO_MUX1 Pin Assignments (M3 Primary Modes)(1) (continued)
ANALOG
MODE
(USB PINS)
DEVICE
PIN NAME
M3
PRIMARY
MODE 1
M3
PRIMARY
MODE 2
M3
PRIMARY
MODE 3
M3
PRIMARY
MODE 4
M3
PRIMARY
MODE 5
M3
PRIMARY
MODE 6
M3
PRIMARY
MODE 7
M3
PRIMARY
MODE 8
M3
PRIMARY
MODE 9
M3
PRIMARY
MODE 10
M3
PRIMARY
MODE 11
–
PC0_GPIO64
–
–
–
–
–
–
–
EPI0S32(2)
–
–
–
(2)
224
–
PC1_GPIO65
–
–
–
–
–
–
–
EPI0S33
–
–
–
–
PC2_GPIO66
–
–
–
–
–
–
–
EPI0S37(2)
–
–
–
–
PC3_GPIO67
–
–
–
–
–
–
–
EPI0S36(2)
–
–
–
–
PC4_GPIO68
CCP5
–
MIITXD3
–
CCP2
CCP4
–
EPI0S2
CCP1
–
–
–
PC5_GPIO69
CCP1
–
–
–
CCP3
USB0EPEN
–
EPI0S3
–
–
–
–
PC6_GPIO70
CCP3
–
–
–
U1RX
CCP0
USB0PFLT
EPI0S4
–
–
–
–
PC7_GPIO71
CCP4
–
–
CCP0
U1TX
USB0PFLT
–
EPI0S5
–
–
–
Detailed Description
Copyright © 2012–2020, Texas Instruments Incorporated
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F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 6-28. GPIO_MUX1 Pin Assignments (M3 Alternate Modes) (1)
(1)
(2)
ANALOG MODE
(USB PINS)
DEVICE PIN NAME
M3
ALTERNATE
MODE 12
M3
ALTERNATE
MODE 13
M3
ALTERNATE
MODE 14
M3
ALTERNATE
MODE 15
–
PA0_GPIO0
–
–
–
–
–
PA1_GPIO1
–
–
–
SSI1FSS
–
PA2_GPIO2
–
–
–
–
–
PA3_GPIO3
–
–
–
SSI1CLK
–
PA4_GPIO4
–
–
–
–
–
PA5_GPIO5
–
–
–
–
–
PA6_GPIO6
–
–
–
–
–
PA7_GPIO7
MIIRXD1
–
–
–
–
PB0_GPIO8
–
SSI2TX
CAN1TX
U4TX
–
PB1_GPIO9
–
SSI2RX
–
–
–
PB2_GPIO10
–
SSI2CLK
CAN1RX
U4RX
–
PB3_GPIO11
–
SSI2FSS
U1RX
–
–
PB4_GPIO12
–
–
CAN1TX
SSI1TX
–
PB5_GPIO13
–
–
CAN1RX
SSI1RX
–
PB6_GPIO14
MIICRS
I2C0SDA
U1TX
SSI1CLK
–
PB7_GPIO15
–
I2C0SCL
U1RX
SSI1FSS
–
PD0_GPIO16
MIIRXD2
SSI0TX
CAN1TX
USB0EPEN
–
PD1_GPIO17
MIICOL
SSI0RX
CAN1RX
USB0PFLT
–
PD2_GPIO18
–
SSI0CLK
U1TX
CAN0RX
–
PD3_GPIO19
–
SSI0FSS
U1RX
CAN0TX
–
PD4_GPIO20
–
–
U3TX
CAN1TX
–
PD5_GPIO21
–
–
U3RX
CAN1RX
–
PD6_GPIO22
–
–
I2C1SDA
U1TX
–
PD7_GPIO23
–
–
I2C1SCL
U1RX
–
PE0_GPIO24
–
SSI3TX
CAN0RX
SSI1TX
–
PE1_GPIO25
–
SSI3RX
CAN0TX
SSI1RX
–
PE2_GPIO26
–
SSI3CLK
U2RX
SSI1CLK
–
PE3_GPIO27
–
SSI3FSS
U2TX
EPI0S38
SSI1FSS
(2)
–
PE4_GPIO28
–
U0RX
–
PE5_GPIO29
MIITXER
U0TX
–
USB0EPEN
USB0PFLT
–
PE6_GPIO30
MIIMDIO
CAN0RX
–
–
–
PE7_GPIO31
MIIRXD3
CAN0TX
–
–
–
PF0_GPIO32
–
I2C0SDA
TRACED2
–
–
PF1_GPIO33
–
I2C0SCL
TRACED3
–
–
PF2_GPIO34
–
–
TRACECLK
XCLKOUT
–
PF3_GPIO35
–
U0TX
TRACED0
–
–
PF4_GPIO36
–
U0RX
–
–
–
PF5_GPIO37
–
–
–
MIITXEN
USB0VBUS
PF6_GPIO38
–
–
–
–
–
PF7_GPIO39
–
–
CAN1TX
–
Blank fields represent Reserved functions.
This muxing option is only available on silicon Revision A devices; this muxing option is not available on silicon Revision 0 devices.
Detailed Description
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Copyright © 2012–2020, Texas Instruments Incorporated
225
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 6-28. GPIO_MUX1 Pin Assignments (M3 Alternate Modes)(1) (continued)
ANALOG MODE
(USB PINS)
DEVICE PIN NAME
M3
ALTERNATE
MODE 12
M3
ALTERNATE
MODE 13
M3
ALTERNATE
MODE 14
M3
ALTERNATE
MODE 15
–
PG0_GPIO40
MIIRXD2
U4RX
–
MIITXCK
–
PG1_GPIO41
MIIRXD1
U4TX
–
MIITXER
USB0DM
PG2_GPIO42
–
–
–
–
–
PG3_GPIO43
MIIRXDV
–
TRACED1
–
–
PG4_GPIO44
–
–
CAN1RX
–
USB0DP
PG5_GPIO45
–
–
–
–
USB0ID
PG6_GPIO46
–
–
–
–
–
PG7_GPIO47
–
–
–
MIICRS
–
PH0_GPIO48
–
SSI3TX
–
MIITXD3
–
PH1_GPIO49
MIIRXD0
SSI3RX
–
MIITXD2
–
PH2_GPIO50
–
SSI3CLK
–
MIITXD1
–
PH3_GPIO51
–
SSI3FSS
–
MIITXD0
–
PH4_GPIO52
–
U3TX
–
MIICOL
–
PH5_GPIO53
–
U3RX
–
MIIPHYRST
–
PH6_GPIO54
MIITXEN
SSI0TX
–
MIIPHYINTR
–
PH7_GPIO55
MIITXCK
SSI0RX
–
MIIMDC
–
PJ0_GPIO56
–
SSI0CLK
–
MIIMDIO
–
PJ1_GPIO57
MIIRXDV
SSI0FSS
–
MIIRXD3
–
PJ2_GPIO58
MIIRXCK
SSI0CLK
U0TX
MIIRXD2
–
PJ3_GPIO59
MIIMDC
SSI0FSS
U0RX
MIIRXD1
–
PJ4_GPIO60
MIICOL
SSI1CLK
–
MIIRXD0
–
PJ5_GPIO61
MIICRS
SSI1FSS
–
MIIRXDV
–
PJ6_GPIO62
MIIPHYINTR
U2RX
–
MIIRXER
–
PJ7_GPIO63/
XCLKIN
MIIPHYRST
U2TX
–
MIIRXCK
–
PC0_GPIO64
–
–
–
MIIRXD2
–
PC1_GPIO65
–
–
–
MIICOL
–
PC2_GPIO66
–
–
–
MIITXEN
–
PC3_GPIO67
–
–
–
MIITXCK
–
PC4_GPIO68
–
–
–
–
–
PC5_GPIO69
–
–
–
–
–
PC6_GPIO70
–
–
–
–
–
PC7_GPIO71
–
–
–
–
–
PK0_GPIO72
–
SSI0TX
–
–
–
PK1_GPIO73
–
SSI0RX
–
–
–
PK2_GPIO74
–
SSI0CLK
–
–
–
PK3_GPIO75
–
SSI0FSS
–
–
–
PK4_GPIO76
MIITXEN
SSI0TX
–
–
–
PK5_GPIO77
MIITXCK
SSI0RX
–
–
–
PK6_GPIO78
MIITXER
SSI0CLK
–
–
–
PK7_GPIO79
MIICRS
SSI0FSS
–
–
226
Detailed Description
Copyright © 2012–2020, Texas Instruments Incorporated
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Product Folder Links: F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 6-28. GPIO_MUX1 Pin Assignments (M3 Alternate Modes)(1) (continued)
ANALOG MODE
(USB PINS)
DEVICE PIN NAME
M3
ALTERNATE
MODE 12
M3
ALTERNATE
MODE 13
M3
ALTERNATE
MODE 14
M3
ALTERNATE
MODE 15
–
PL0_GPIO80
MIIRXD3
–
–
SSI1TX
–
PL1_GPIO81
MIIRXD2
–
–
SSI1RX
–
PL2_GPIO82
MIIRXD1
–
–
SSI1CLK
–
PL3_GPIO83
MIIRXD0
–
–
SSI1FSS
–
PL4_GPIO84
MIICOL
SSI3TX
–
–
–
PL5_GPIO85
MIIPHYRST
SSI3RX
–
–
–
PL6_GPIO86
MIIPHYINTR
SSI3CLK
–
–
–
PL7_GPIO87
MIIMDC
SSI3FSS
–
–
–
PM0_GPIO88
MIIMDIO
SSI2TX
–
–
–
PM1_GPIO89
MIITXD3
SSI2RX
–
–
–
PM2_GPIO90
MIITXD2
SSI2CLK
–
–
–
PM3_GPIO91
MIITXD1
SSI2FSS
–
–
–
PM4_GPIO92
MIITXD0
–
–
–
–
PM5_GPIO93
MIIRXDV
–
–
–
–
PM6_GPIO94
MIIRXER
–
–
–
–
PM7_GPIO95
MIIRXCK
–
–
–
–
PN0_GPIO96
–
I2C0SCL
–
–
–
PN1_GPIO97
–
I2C0SDA
–
–
–
PN2_GPIO98
–
U1RX
–
–
–
PN3_GPIO99
–
U1TX
–
–
–
PN4_GPIO100
–
U3TX
–
–
–
PN5_GPIO101
–
U3RX
–
–
(2)
–
PN6_GPIO102
–
U4RX
EPI0S42
USB0EPEN
–
PN7_GPIO103
–
U4TX
EPI0S43(2)
USB0PFLT
–
PP0_GPIO104
–
I2C1SCL
–
–
–
PP1_GPIO105
–
I2C1SDA
–
–
–
PP2_GPIO106
–
I2C0SCL
–
–
–
PP3_GPIO107
–
I2C0SDA
–
–
–
PP4_GPIO108
–
I2C1SCL
–
–
–
PP5_GPIO109
–
I2C1SDA
–
–
–
PP6_GPIO110
–
–
–
–
–
PP7_GPIO111
–
–
–
–
–
PQ0_GPIO112
–
–
–
–
–
PQ1_GPIO113
–
–
–
–
–
PQ2_GPIO114
–
–
U0RX
–
–
PQ3_GPIO115
–
–
U0TX
–
–
PQ4_GPIO116
–
SSI1TX
–
–
–
PQ5_GPIO117
–
SSI1RX
–
–
–
PQ6_GPIO118
–
–
–
–
–
PQ7_GPIO119
–
–
–
–
Detailed Description
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Copyright © 2012–2020, Texas Instruments Incorporated
227
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 6-28. GPIO_MUX1 Pin Assignments (M3 Alternate Modes)(1) (continued)
ANALOG MODE
(USB PINS)
DEVICE PIN NAME
M3
ALTERNATE
MODE 12
–
PR0_GPIO120
–
PR1_GPIO121
–
–
228
M3
ALTERNATE
MODE 13
M3
ALTERNATE
MODE 14
M3
ALTERNATE
MODE 15
–
SSI3TX
–
–
–
SSI3RX
–
–
PR2_GPIO122
–
SSI3CLK
–
–
PR3_GPIO123
–
SSI3FSS
–
–
–
PR4_GPIO124
–
–
–
–
–
PR5_GPIO125
–
–
–
–
–
PR6_GPIO126
–
–
–
–
–
PR7_GPIO127
–
–
–
–
–
PS0_GPIO128
–
–
–
–
–
PS1_GPIO129
–
–
–
–
–
PS2_GPIO130
–
–
–
–
–
PS3_GPIO131
–
–
–
–
–
PS4_GPIO132
–
–
–
–
–
PS5_GPIO133
–
–
–
–
–
PS6_GPIO134
–
–
–
–
–
PS7_GPIO135
–
–
–
–
Detailed Description
Copyright © 2012–2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 6-29. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes) (1)
(1)
ANALOG MODE
(USB PINS)
DEVICE PIN NAME
C28x
PERIPHERAL
MODE 0
C28x
PERIPHERAL
MODE 1
C28x
PERIPHERAL
MODE 2
C28x
PERIPHERAL
MODE 3
–
PA0_GPIO0
GPIO0
EPWM1A
–
–
–
PA1_GPIO1
GPIO1
EPWM1B
ECAP6
–
–
PA2_GPIO2
GPIO2
EPWM2A
–
–
–
PA3_GPIO3
GPIO3
EPWM2B
ECAP5
–
–
PA4_GPIO4
GPIO4
EPWM3A
–
–
–
PA5_GPIO5
GPIO5
EPWM3B
MFSRA
ECAP1
–
PA6_GPIO6
GPIO6
EPWM4A
–
EPWMSYNCO
–
PA7_GPIO7
GPIO7
EPWM4B
MCLKRA
ECAP2
–
PB0_GPIO8
GPIO8
EPWM5A
–
ADCSOCAO
–
PB1_GPIO9
GPIO9
EPWM5B
–
ECAP3
–
PB2_GPIO10
GPIO10
EPWM6A
–
ADCSOCBO
–
PB3_GPIO11
GPIO11
EPWM6B
–
ECAP4
–
PB4_GPIO12
GPIO12
EPWM7A
–
–
–
PB5_GPIO13
GPIO13
EPWM7B
–
–
–
PB6_GPIO14
GPIO14
EPWM8A
–
–
–
PB7_GPIO15
GPIO15
EPWM8B
–
–
–
PD0_GPIO16
GPIO16
SPISIMOA
–
–
–
PD1_GPIO17
GPIO17
SPISOMIA
–
–
–
PD2_GPIO18
GPIO18
SPICLKA
–
–
–
PD3_GPIO19
GPIO19
SPISTEA
–
–
–
PD4_GPIO20
GPIO20
EQEP1A
MDXA
–
–
PD5_GPIO21
GPIO21
EQEP1B
MDRA
–
–
PD6_GPIO22
GPIO22
EQEP1S
MCLKXA
–
–
PD7_GPIO23
GPIO23
EQEP1I
MFSXA
–
–
PE0_GPIO24
GPIO24
ECAP1
EQEP2A
–
–
PE1_GPIO25
GPIO25
ECAP2
EQEP2B
–
–
PE2_GPIO26
GPIO26
ECAP3
EQEP2I
–
–
PE3_GPIO27
GPIO27
ECAP4
EQEP2S
–
–
PE4_GPIO28
GPIO28
SCIRXDA
–
–
–
PE5_GPIO29
GPIO29
SCITXDA
–
–
–
PE6_GPIO30
GPIO30
–
–
EPWM9A
–
PE7_GPIO31
GPIO31
–
–
EPWM9B
–
PF0_GPIO32
GPIO32
I2CASDA
SCIRXDA
ADCSOCAO
–
PF1_GPIO33
GPIO33
I2CASCL
EPWMSYNCO
ADCSOCBO
–
PF2_GPIO34
GPIO34
ECAP1
SCIRXDA
XCLKOUT
–
PF3_GPIO35
GPIO35
SCITXDA
–
–
–
PF4_GPIO36
GPIO36
SCIRXDA
–
–
–
PF5_GPIO37
GPIO37
ECAP2
–
–
USB0VBUS
PF6_GPIO38
GPIO38
–
–
–
–
PF7_GPIO39
GPIO39
–
–
–
Blank fields represent Reserved functions.
Detailed Description
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Product Folder Links: F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2
Copyright © 2012–2020, Texas Instruments Incorporated
229
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
www.ti.com
Table 6-29. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)(1) (continued)
ANALOG MODE
(USB PINS)
DEVICE PIN NAME
C28x
PERIPHERAL
MODE 0
C28x
PERIPHERAL
MODE 1
C28x
PERIPHERAL
MODE 2
C28x
PERIPHERAL
MODE 3
–
PG0_GPIO40
GPIO40
–
–
–
–
PG1_GPIO41
GPIO41
–
–
–
USB0DM
PG2_GPIO42
GPIO42
–
–
–
–
PG3_GPIO43
GPIO43
–
–
–
–
PG4_GPIO44
GPIO44
–
–
–
USB0DP
PG5_GPIO45
GPIO45
–
–
–
USB0ID
PG6_GPIO46
GPIO46
–
–
–
–
PG7_GPIO47
GPIO47
–
–
–
–
PH0_GPIO48
GPIO48
ECAP5
–
–
–
PH1_GPIO49
GPIO49
ECAP6
–
–
–
PH2_GPIO50
GPIO50
EQEP1A
–
–
–
PH3_GPIO51
GPIO51
EQEP1B
–
–
–
PH4_GPIO52
GPIO52
EQEP1S
–
–
–
PH5_GPIO53
GPIO53
EQEP1I
–
–
–
PH6_GPIO54
GPIO54
SPISIMOA
–
EQEP3A
–
PH7_GPIO55
GPIO55
SPISOMIA
–
EQEP3B
–
PJ0_GPIO56
GPIO56
SPICLKA
–
EQEP3S
–
PJ1_GPIO57
GPIO57
SPISTEA
–
EQEP3I
–
PJ2_GPIO58
GPIO58
MCLKRA
–
EPWM7A
–
PJ3_GPIO59
GPIO59
MFSRA
–
EPWM7B
–
PJ4_GPIO60
GPIO60
–
–
EPWM8A
–
PJ5_GPIO61
GPIO61
–
–
EPWM8B
–
PJ6_GPIO62
GPIO62
–
–
EPWM9A
–
PJ7_GPIO63/
XCLKIN
GPIO63
–
–
EPWM9B
–
PC0_GPIO64
GPIO64
EQEP1A
EQEP2I
–
–
PC1_GPIO65
GPIO65
EQEP1B
EQEP2S
–
–
PC2_GPIO66
GPIO66
EQEP1S
EQEP2A
–
–
PC3_GPIO67
GPIO67
EQEP1I
EQEP2B
–
–
PC4_GPIO68
GPIO68
–
–
–
–
PC5_GPIO69
GPIO69
–
–
–
–
PC6_GPIO70
GPIO70
–
–
–
–
PC7_GPIO71
GPIO71
–
–
–
–
PK0_GPIO72
GPIO72
SPISIMOA
–
–
–
PK1_GPIO73
GPIO73
SPISOMIA
–
–
–
PK2_GPIO74
GPIO74
SPICLKA
–
–
–
PK3_GPIO75
GPIO75
SPISTEA
–
–
–
PK4_GPIO76
GPIO76
–
–
–
–
PK5_GPIO77
GPIO77
–
–
–
–
PK6_GPIO78
GPIO78
–
–
–
–
PK7_GPIO79
GPIO79
–
–
–
230
Detailed Description
Copyright © 2012–2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: F28M36P63C2 F28M36P53C2 F28M36H53B2 F28M36H33B2
F28M36P63C2, F28M36P53C2
F28M36H53B2, F28M36H33B2
www.ti.com
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Table 6-29. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)(1) (continued)
ANALOG MODE
(USB PINS)
DEVICE PIN NAME
C28x
PERIPHERAL
MODE 0
C28x
PERIPHERAL
MODE 1
C28x
PERIPHERAL
MODE 2
C28x
PERIPHERAL
MODE 3
–
PL0_GPIO80
GPIO80
–
–
–
–
PL1_GPIO81
GPIO81
–
–
–
–
PL2_GPIO82
GPIO82
–
–
–
–
PL3_GPIO83
GPIO83
–
–
–
–
PL4_GPIO84
GPIO84
–
–
–
–
PL5_GPIO85
GPIO85
–
–
–
–
PL6_GPIO86
GPIO86
–
–
–
–
PL7_GPIO87
GPIO87
–
–
–
–
PM0_GPIO88
GPIO88
–
–
–
–
PM1_GPIO89
GPIO89
–
–
–
–
PM2_GPIO90
GPIO90
–
–
–
–
PM3_GPIO91
GPIO91
–
–
–
–
PM4_GPIO92
GPIO92
–
MDXA
–
–
PM5_GPIO93
GPIO93
–
MDRA
–
–
PM6_GPIO94
GPIO94
–
MCLKXA
–
–
PM7_GPIO95
GPIO95
–
MFSXA
–
–
PN0_GPIO96
GPIO96
–
MCLKRA
–
–
PN1_GPIO97
GPIO97
–
MFSRA
–
–
PN2_GPIO98
GPIO98
–
–
–
–
PN3_GPIO99
GPIO99
–
–
–
–
PN4_GPIO100
GPIO100
–
–
–
–
PN5_GPIO101
GPIO101
–
–
–
–
PN6_GPIO102
GPIO102
–
–
–
–
PN7_GPIO103
GPIO103
–
–
–
–
PP0_GPIO104
GPIO104
I2CSDAA
–
–
–
PP1_GPIO105
GPIO105
I2CSCLA
–
–
–
PP2_GPIO106
GPIO106
EQEP1A
–
–
–
PP3_GPIO107
GPIO107
EQEP1B
–
–
–
PP4_GPIO108
GPIO108
EQEP1S
–
–
–
PP5_GPIO109
GPIO109
EQEP1I
–
–
–
PP6_GPIO110
GPIO110
–
EQEP2A
EQEP3S
–
PP7_GPIO111
GPIO111
–
EQEP2B
EQEP3I
–
PQ0_GPIO112
GPIO112
–
EQEP2I
EQEP3A
–
PQ1_GPIO113
GPIO113
–
EQEP2S
EQEP3B
–
PQ2_GPIO114
GPIO114
–
–
–
–
PQ3_GPIO115
GPIO115
–
–
–
–
PQ4_GPIO116
GPIO116
–
–
–
–
PQ5_GPIO117
GPIO117
–
–
–
–
PQ6_GPIO118
GPIO118
–
SCITXDA
–
–
PQ7_GPIO119
GPIO119
–
SCIRXDA
–
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Table 6-29. GPIO_MUX1 Pin Assignments (C28x Peripheral Modes)(1) (continued)
ANALOG MODE
(USB PINS)
DEVICE PIN NAME
C28x
PERIPHERAL
MODE 0
C28x
PERIPHERAL
MODE 1
C28x
PERIPHERAL
MODE 2
C28x
PERIPHERAL
MODE 3
–
PR0_GPIO120
GPIO120
–
–
–
–
PR1_GPIO121
GPIO121
–
–
–
–
PR2_GPIO122
GPIO122
–
–
–
–
PR3_GPIO123
GPIO123
–
–
–
–
PR4_GPIO124
GPIO124
EPWM7A
–
–
–
PR5_GPIO125
GPIO125
EPWM7B
–
–
–
PR6_GPIO126
GPIO126
EPWM8A
–
–
–
PR7_GPIO127
GPIO127
EPWM8B
–
–
–
PS0_GPIO128
GPIO128
EPWM9A
–
–
–
PS1_GPIO129
GPIO129
EPWM9B
–
–
–
PS2_GPIO130
GPIO130
EPWM10A
–
–
–
PS3_GPIO131
GPIO131
EPWM10B
–
–
–
PS4_GPIO132
GPIO132
EPWM11A
–
–
–
PS5_GPIO133
GPIO133
EPWM11B
–
–
–
PS6_GPIO134
GPIO134
EPWM12A
–
–
–
PS7_GPIO135
GPIO135
EPWM12B
–
–
232
Detailed Description
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
6.16.2 GPIO_MUX2
The eight pins of the GPIO_MUX2 block can be selectively mapped to eight General-Purpose Inputs, eight
General-Purpose Outputs, or six COMPOUT outputs from the Analog Comparator peripheral. Each
GPIO_MUX2 pin can have a pullup enabled or disabled. On reset, all pins of the GPIO_MUX2 block are
configured as analog inputs, and the GPIO function is disabled. The GPIO_MUX2 block is programmed
through a separate set of registers from those used to program GPIO_MUX1.
The multiple registers responsible for configuring the GPIO_MUX2 pins are organized in register set G.
They are accessible by the C28x CPU only. The middle portion of Figure 6-17 shows set G of Control
Subsystem registers, plus muxing logic for the associated eight GPIO pins. The GPGMUX1 register
selects one of six possible digital output signals from analog comparators, or one of eight general-purpose
GPIO digital outputs. The GPGPUD register disables pullups for the GPIO_MUX2 pins when a
corresponding bit of that register is set to “1”. Other registers of set G allow reading and writing of the
eight GPIO bits, as well as setting the direction for each of the bits (read or write). See Table 6-30 for the
mapping of comparator outputs and GPIO to the eight pins of GPIO_MUX2.
Peripheral Modes 0, 1, 2, and 3 are chosen by setting selected bit pairs of GPGMUX1 register to “00”,
“01”, “10”, and “11”, respectively. For example, setting bits 5–4 of the GPGMUX1 register to “00”
(Peripheral Mode 0) assigns pin GPIO194 to internal signal GPIO194 (digital GPIO). Setting bits 5–4 of
the GPGMUX1 register to “11” (Peripheral Mode 3) assigns pin GPIO194 to internal signal COMP6OUT
coming from Analog Comparator 6. Peripheral Modes 1 and 2 are reserved and are not currently
available.
Table 6-30. GPIO_MUX2 Pin Assignments (C28x Peripheral Modes) (1)
(1)
DEVICE PIN NAME
C28x
PERIPHERAL
MODE 0
C28x
PERIPHERAL
MODE 1
C28x
PERIPHERAL
MODE 2
C28x
PERIPHERAL
MODE 3
GPIO192
GPIO192
–
–
–
GPIO193
GPIO193
–
–
COMP1OUT
GPIO194
GPIO194
–
–
COMP6OUT
GPIO195
GPIO195
–
–
COMP2OUT
GPIO196
GPIO196
–
–
COMP3OUT
GPIO197
GPIO197
–
–
COMP4OUT
GPIO198
GPIO198
–
–
–
GPIO199
GPIO199
–
–
COMP5OUT
Blank fields represent Reserved functions.
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ADC1INA0
ADC1INA2
ADC1INA3
ADC1INA4
ADC1INA6
ADC1INA7
ONE OF 12
AIO_MUX1
PINS
ADC1INB0
ADC1INB2
ADC1INB3
ADC1INB4
ADC1INB6
ADC1INB7
AIO2
AIO4
AIO6
AIO10
AIO12
AIO14
AIOMUX1 REG
AIODIR REG
ADC
1
AIO_MUX1
AIOSET REG
AIOCLEAR REG
AIOTOGGLE REG
AIODIR REG
AIODAT REG
DIS
COMPOUT1
COMPOUT2
COMPOUT3
COMPOUT4
COMPOUT5
COMPOUT6
GPIOPUR
GPGPUD REG
REG
PULLUP
DISABLED
ON RESET
‘1’
PULLUP
GPGMUX1 REG
GPGDIR REG
ONE OF 8
GPIO_MUX2
PINS
AIOMUX2 REG
AIODIR REG
COMPB1
COMPB2
COMPB3
COMPA4
COMPA5
COMPA6
GPIO192
GPIO193
GPIO194
GPIO195
GPIO196
GPIO197
GPIO198
GPIO199
ADC2INA0
ADC2INA2
ADC2INA3
ADC2INA4
ADC2INA6
ADC2INA7
ONE OF 12
AIO_MUX2
PINS
6
COMPARATOR
+ DAC UNITS
COMPA1
COMPA2
COMPA3
GPIO_MUX2
GPGSET REG
GPGCLEAR REG
ANALOG BUS
COMPB4
COMPB5
COMPB6
ANALOG
COMMON
INTERFACE
BUS
C28
CPU
BUS
C28x
CPU
GPGTOGGLE REG
GPGDIR REG
GPGDAT REG
ADC2INB0
ADC2INB2
ADC2INB3
ADC2INB4
ADC2INB6
ADC2INB7
AIO18
AIO20
AIO22
AIO26
AIO28
AIO30
ADC
2
AIO_MUX2
AIOSET REG
AIOCLEAR REG
AIOTOGGLE REG
AIODIR REG
AIODAT REG
Figure 6-17. Pin Muxing on AIO_MUX1, AIO_MUX2, and GPIO_MUX2
234
Detailed Description
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
6.16.3 AIO_MUX1
The 12 pins of AIO_MUX1 can be selectively mapped through a dedicated set of registers to 12 analog
inputs for ADC1 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or
four General-Purpose Outputs. While AIO_MUX1 has been named after the analog signals passing
through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in the
GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the
AIO_MUX1 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX1
block is programmed through a separate set of registers from those used to program AIO_MUX2.
The multiple registers responsible for configuring the AIO_MUX1 pins are accessible by the C28x CPU
only. The top portion of Figure 6-17 shows Control Subsystem registers and muxing logic for the
associated 12 AIO pins. The AIOMUX1 register selects 1 of 12 possible analog input signals or 1 of 6
general-purpose AIO inputs. Other registers allow reading and writing of the 6 AIO bits, as well as setting
the direction for each of the bits (read or write). See Table 6-31 for the mapping of analog inputs and AIOs
to the 12 pins of AIO_MUX1.
AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX1 register to ‘0’. AIO Mode 1 is chosen
by setting selected odd bits of the AIOMUX1 register to ‘1’. For example, setting bit 5 of the AIOMUX1
register to ‘0’ assigns pin ADC1INA2 to internal signal AIO2 (digital GPIO). Setting bit 5 of the AIOMUX1
register to ‘1’ assigns pin ADC1INA2 to analog inputs ADC1INA2 or COMPA1 (only one should be
enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX1 register are
“don’t cares”.
Table 6-31. AIO_MUX1 Pin Assignments (C28x AIO Modes) (1) (2)
DEVICE PIN NAME
(1)
(2)
(3)
(4)
C28x AIO MODE 0 (3)
C28x AIO MODE 1 (4)
ADC1INA0
–
ADC1INA0
ADC1INA2
AIO2
ADC1INA2, COMPA1
ADC1INA3
–
ADC1INA3
ADC1INA4
AIO4
ADC1INA4, COMPA2
ADC1INA6
AIO6
ADC1INA6, COMPA3
ADC1INA7
–
ADC1INA7
ADC1INB0
–
ADC1INB0
ADC1INB2
AIO10
ADC1INB2, COMPB1
ADC1INB3
–
ADC1INB3
ADC1INB4
AIO12
ADC1INB4, COMPB2
ADC1INB6
AIO14
ADC1INB6, COMPB3
ADC1INB7
–
ADC1INB7
Blank fields represent Reserved functions.
For each field with two pins (for example, ADC1INA2, COMPA1), only one pin should be enabled at a time; the other pin should be
disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs.
AIO Mode 0 represents digital general-purpose inputs or outputs.
AIO Mode 1 represents analog inputs for ADC1 or the Comparator module.
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6.16.4 AIO_MUX2
The 12 pins of AIO_MUX2 can be selectively mapped through a dedicated set of registers to 12 analog
inputs for ADC2 peripheral, six analog inputs for Comparator peripherals, four General-Purpose Inputs, or
four General-Purpose Outputs. While AIO_MUX2 has been named after the analog signals passing
through it, the GPIOs (here called AIOs) are still digital, although with fewer features than those in the
GPIO_MUX1 and GPIO_MUX2 blocks—for example, they do not offer pullups. On reset, all pins of the
AIO_MUX2 block are configured as analog inputs and the GPIO function is disabled. The AIO_MUX2
block is programmed through a separate set of registers from those used to program AIO_MUX1.
The multiple registers responsible for configuring the AIO_MUX2 pins are accessible by the C28x CPU
only. The bottom portion of Figure 6-17 shows Control Subsystem registers and muxing logic for the
associated 12 AIO pins. The AIOMUX2 register selects 1 of 12 possible analog input signals or 1 of 6
general-purpose AIO inputs. Other registers allow reading and writing of the 6 AIO bits, as well as setting
the direction for each of the bits (read or write). See Table 6-32 for the mapping of analog inputs and AIOs
to the 12 pins of AIO_MUX2. Peripheral Modes 1 and 2 are currently not available.
AIO Mode 0 is chosen by setting selected odd bits of the AIOMUX2 register to ‘0’. AIO Mode 1 is chosen
by setting selected odd bits of the AIOMUX2 register to ‘1’. For example, setting bit 9 of the AIOMUX2
register to ‘0’ assigns pin ADC2INA4 to internal signal AIO20 (digital GPIO). Setting bit 9 of the AIOMUX2
register to ‘1’ assigns pin ADC2INA4 to analog inputs ADC2INA4 or COMPA5 (only one should be
enabled at a time in the respective analog module). Currently, all even bits of the AIOMUX2 register are
“don’t cares”.
Table 6-32. AIO_MUX2 Pin Assignments (C28x AIO Modes) (1) (2)
DEVICE PIN NAME
(1)
(2)
(3)
(4)
236
C28x AIO MODE 0 (3)
C28x AIO MODE 1 (4)
ADC2INA0
–
ADC2INA0
ADC2INA2
AIO18
ADC2INA2, COMPA4
ADC2INA3
–
ADC2INA3
ADC2INA4
AIO20
ADC2INA4, COMPA5
ADC2INA6
AIO22
ADC2INA6, COMPA6
ADC2INA7
–
ADC2INA7
ADC2INB0
–
ADC2INB0
ADC2INB2
AIO26
ADC2INB2, COMPB4
ADC2INB3
–
ADC2INB3
ADC2INB4
AIO28
ADC2INB4, COMPB5
ADC2INB6
AIO30
ADC2INB6, COMPB6
ADC2INB7
–
ADC2INB7
Blank fields represent Reserved functions.
For each field with two pins (for example, ADC2INA6, COMPA6), only one pin should be enabled at a time; the other pin should be
disabled. Use registers inside the respective destination analog peripherals to enable or disable these inputs.
AIO Mode 0 represents digital general-purpose inputs or outputs.
AIO Mode 1 represents analog inputs for ADC2 or the Comparator module.
Detailed Description
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
6.17 Emulation/JTAG
Concerto devices have two types of emulation ports to support debug operations: the 7-pin TI JTAG port
and the 5-pin Cortex-M3 Instrumentation Trace Macrocell (ITM) port. The 7-pin TI JTAG port can be used
to connect to debug tools through the TI 14-pin JTAG header or the TI 20-pin JTAG header. The 5-pin
Cortex-M3 ITM port can only be accessed through the TI 20-pin JTAG header.
The JTAG port has seven dedicated pins: TRST, TMS, TDI, TDO, TCK, EMU0, and EMU1. The TRST
signal should always be pulled down through a 2.2-kΩ pulldown resistor on the board. EMU0 and EMU1
signals should be pulled up through a pair of pullups ranging from 2.2 kΩ to 4.7 kΩ (depending on the
drive strength of the debugger ports). The JTAG port is TI’s standard debug port.
The ITM port uses five GPIO pins that can be mapped to internal Cortex-M3 ITM trace signals: TRACE0,
TRACE1, TRACE2, TRACE3, and TRACECLK. This port is typically used for advanced software debug.
TI JTAG debug probes, and those from other manufacturers, can connect to Concerto devices through
TI’s 14-pin JTAG header or 20-pin JTAG header. See Figure 6-18 to see how the 14-pin JTAG header
connects to the JTAG port signals in Concerto. The 14-pin header does not support the ITM debug mode.
Figure 6-19 shows two possible ways to connect the 20-pin header to the emulation pins in Concerto. The
left side of the drawing shows all seven JTAG signals connecting to the 20-pin header similar to the way
the 14-pin header was connected. The JTAG EMU0 and EMU1 signals are mapped to the corresponding
terminals on the 20-pin header. In this mode, header terminals EMU2, EMU3, and EMU4 are left
unconnected and the ITM trace mode is not available.
The right side of the drawing shows the same 20-pin header now connected to five ITM signals and five of
seven JTAG signals. The EMU0 and EMU1 signals in Concerto are left unconnected in this mode; thus,
the emulation functions associated with these two signals are not available when debugging with ITM
trace.
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CONCERTO F28M36x
TRST
N19
2.2K
3.3V
TMS
TDI
M19
1
K19
3
5
TDO
7
T19
4.7K
TCK
EMU0
EMU1
4.7K
9
TMS
nTRST
2
TDI
TDIS
4
PD
KEY
6
TDO
GND
8
RTCK
GND
10
L19
11
TCK
GND
12
P19
13
EMU0
EMU1
14
R19
TI 14-PIN
JTAG HEADER
JTAG
PINS
(A)
GPIO PINS
TRACED0
PF3_GPIO35
TRACED1
PG3_GPIO43
TRACECLK
PF2_GPIO34
TRACED2
PF0_GPIO32
TRACED3
PF1_GPIO33
P17
N17
P16
D19
E17
ITM trace
from M3
PROCESSOR
A.
The GPIO pins (GPIO32–GPIO35 and GPIO43) may be used in the application if ITM trace is not used.
Figure 6-18. Connecting to TI 14-Pin JTAG Debug Probe Header
238
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SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
CONCERTO F28M36x
CONCERTO F28M36x
TRST
N19
TRST
N19
2.2K
2.2K
3.3V
TMS
TDI
3.3V
M19
1
K19
3
5
TDO
7
T19
4.7K
TCK
EMU0
EMU1
9
4.7K
TMS
nTRST
2
TDI
TDIS
4
PD
KEY
6
TDO
GND
8
RTCK
GND
10
L19
11
TCK
GND
12
P19
13
EMU0
EMU1
14
R19
15
RESETn
GND
16
17
EMU2
EMU3
18
NC
JTAG
PINS
NC
19
EMU4
GND
TMS
TDI
M19
1
K19
3
TMS
nTRST
2
TDI
TDIS
4
PD
KEY
6
TDO
GND
8
RTCK
GND
10
11
TCK
GND
12
13
EMU0
EMU1
14
15
RESETn
GND
16
17
EMU2
EMU3
18
19
EMU4
GND
20
5
TDO
7
T19
4.7K
TCK
EMU0
EMU1
L19
P19
R19
NC
JTAG
PINS
20
9
4.7K
NC
NC
TI 20-PIN
JTAG HEADER
TI 20-PIN
JTAG HEADER
(A)
GPIO PINS
TRACED0
PF3_GPIO35
TRACED1
PG3_GPIO43
TRACECLK
PF2_GPIO34
TRACED2
PF0_GPIO32
TRACED3
PF1_GPIO33
GPIO PINS
P17
N17
P16
D19
E17
TRACED0
PF3_GPIO35
TRACED1
PG3_GPIO43
TRACECLK
PF2_GPIO34
TRACED2
PF0_GPIO32
TRACED3
PF1_GPIO33
P17
N17
P16
D19
E17
OPEN
DRAIN
ITM trace
from M3
PROCESSOR
A.
A LOW PULSE FROM THE JTAG DEBUG PROBE CAN BE TIED
WITH OTHER RESET SOURCES TO RESET THE BOARD
OPEN
DRAIN
ITM trace
from M3
PROCESSOR
A LOW PULSE FROM THE JTAG DEBUG PROBE CAN BE TIED
WITH OTHER RESET SOURCES TO RESET THE BOARD
The GPIO pins (GPIO32–GPIO35 and GPIO43) may be used in the application if ITM trace is not used.
Figure 6-19. Connecting to TI 20-Pin JTAG Debug Probe Header
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6.18 Code Security Module
The Code Security Module (CSM) is a security feature incorporated in Concerto devices. The CSM
prevents access and visibility to on-chip secure memories by unauthorized persons—that is, the CSM
prevents duplication and reverse-engineering of proprietary code. The word "secure" means that access to
on-chip secure memories is protected. The word "unsecure" means that access to on-chip secure memory
is not protected—that is, the contents of the memory could be read by any means [for example, by using a
debugging tool such as Code Composer Studio™ Integrated Development Environment (IDE)].
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD
TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR
THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT
AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS
CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY
OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
6.18.1 Functional Description
The security module restricts the CPU access to on-chip secure memory without interrupting or stalling
CPU execution. When a read occurs to a protected memory location, the read returns a zero value and
CPU execution continues with the next instruction. This process, in effect, blocks read and write access to
various memories through the JTAG port or external peripherals. Security is defined with respect to the
access of on-chip secure memories and prevents unauthorized copying of proprietary code or data.
The zone is secure when CPU access to the on-chip secure memories associated with that zone is
restricted. When secure, two levels of protection are possible, depending on where the program counter is
currently pointing. If code is currently running from inside secure memory, only an access through JTAG is
blocked (that is, through the JTAG debug probe). This process allows secure code to access secure data.
Conversely, if code is running from unsecure memory, all accesses to secure memories are blocked. User
code can dynamically jump in and out of secure memory, thereby allowing secure function calls from
unsecure memory. Similarly, interrupt service routines can be placed in secure memory, even if the main
program loop is run from unsecure memory.
The code security mechanism present in this device offers dual-zone security for the Cortex-M3 code and
single-zone security for the C28x code. In case of dual-zone security on the master subsystem, the
different secure memories (RAMs and flash sectors) can be assigned to different security zones by
configuring the GRABRAM and GRABSECT registers associated with each zone. Flash Sector N and
Flash Sector A are dedicated to Zone1 and Zone2, respectively, and cannot be allocated to any other
zone by configuration. Similarly, flash sectors get assigned to different zones based on the setting in the
GRABSECT registers.
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Security is provided by a CSM password of 128 bits of data (four 32-bit words) that is used to secure or
unsecure the zones. Each zone has its own 128-bit CSM password. The zone can be unsecured by
executing the password match flow (PMF).
The CSM password for each zone is stored in its dedicated flash sector. The password storage locations
in the flash sector store the CSM password. The password is selected by the system designer. If the
password locations of a zone have all 128 bits as ones, the zone is considered "unsecure". Because new
flash devices have erased flash (all ones), only a read of the password locations is required to bring any
zone into unsecure mode. If the password locations of a zone have all 128 bits as zeros, the zone is
considered "secure", regardless of the contents of the CSMKEY registers. The user should not use all
zeros as a password or reset the device during an erase of the flash. Resetting the device during an erase
routine can result in either an all-zero or unknown password. If a device is reset when the password
locations are all zeros, the device cannot be unlocked by the password match flow. Using a password of
all zeros will seriously limit the user’s ability to debug secure code or reprogram the flash.
NOTE
If a device is reset while the password locations of a zone contain all zeros or an unknown
value, that zone will be permanently locked unless a method to run the flash erase routine
from secure SARAM is embedded into the flash or OTP. Care must be taken when
implementing this procedure to avoid introducing a security hole.
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6.19 µCRC Module
The µCRC module is part of the master subsystem. This module can be used by Cortex-M3 software to
compute CRC on data and program, which are stored at memory locations that are addressable by
Cortex-M3. On this device, the Cortex-M3 Flash Bank and ROM are mapped to the code space that is
only accessed by the ICODE/DCODE bus of Cortex-M3; and RAMs are mapped on the SRAM space that
is accessible by the SYSTEM bus. Hence, the µCRC module snoops both the DCODE and SYSTEM
buses to support CRC calculation for data and program.
6.19.1 Functional Description
The µCRC module snoops both the DCODE and SYSTEM buses to support CRC calculation for data and
program. To allow interrupts execution in between CRC calculations for a block of data and to discard the
Cortex-M3 literal pool accesses in between executions of the program (which reads data for CRC
calculation), the Cortex-M3 ROM, Flash, and RAMs are mapped to a mirrored memory location. The
µCRC module grabs data from the bus to calculate CRC only if the address of the read data belongs to
mirrored memory space. After grabbing, the µCRC module performs the CRC calculation on the grabbed
data and updates the µCRC Result Register (µCRCRES). This register can be read at any time to get the
calculated CRC for all the previous read data. The µCRC module only supports CRC calculation for byte
accesses. So, in order to calculate the CRC on a block of data, software must perform byte accesses to
all the data. For half-word and word accesses, the µCRC module discards the data and does not update
the µCRCRES register.
NOTE
If a read to a mirrored address space is thrown from the debugger (Code Composer Studio
or any other debug platform), the µCRC module ignores the read data and does not update
the CRC result for that particular read.
6.19.2 CRC Polynomials
The following are the CRC polynomials that are supported by the µCRC module:
• CRC8 Polynomial = 0x07
• CRC16 Polynomial-1 = 0x8005
• CRC16 Polynomial-2 = 0x1021
• CRC32 Polynomial = 0x04C11DB7
6.19.3 CRC Calculation Procedure
The software procedure for calculating CRC for a set of data that is stored in Cortex-M3 addressable
memory space is as follows:
1. Save the current value of the µCRC Result Register (µCRCRES) into the stack to allow calculation of
CRC in nested interrupt
2. Clear the µCRC Result Register (µCRCRES) by setting the CLEAR field of the µCRC Control Register
(µCRCCONTROL) to "1"
3. Configure the µCRC polynomials (CRC8, CRC16-P1, CRC16-P2, or CRC32) in the µCRC
Configuration Register (µCRCCONFIG)
4. Read the data from memory locations for which CRC needs to be calculated using mirrored address
5. Read the µCRCRES register to get the calculated CRC value. Pop the last saved value of the CRC
from the stack and store this value into the µCRC Result Register (uCRCRES)
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6.19.4 CRC Calculation for Data Stored In Secure Memory
This device has dual-zone security for the Cortex-M3 subsystem. Because ZoneX (X → 1/2) software
does not have access to program/data in ZoneY (Y → 2/1), code running from ZoneX cannot calculate
CRC on data stored in ZoneY memory. Similarly, in the case of Exe-Only flash sectors, even though
software is running from same secure zone, the software cannot read the data stored in Exe-Only sectors.
However, hardware does allow CRC computation on data stored in Exe-Only flash sectors as long as the
read access for this data is initiated by code running from same secure zone. These reads are just dummy
reads and, in this case, read data only goes to the µCRC module, not to the CPU.
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7 Applications, Implementation, and Layout
NOTE
Information in the following sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1
TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded
processor, and connectivity. Created by TI experts to help you jump start your system design, all
reference designs include schematic or block diagrams, BOMs, and design files to speed your time to
market. Search and download designs at the Select TI reference designs page.
244
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8 Device and Documentation Support
8.1
Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
Concerto MCU devices and support tools. Each Concerto MCU commercial family member has one of
three prefixes: x, p, or no prefix (for example, xF28M36P63C2ZWTT). Texas Instruments recommends
two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (with prefix x for devices and
TMDX for tools) through fully qualified production devices/tools (with no prefix for devices and TMDS,
instead of TMDX, for tools).
xF28M36...
Experimental device that is not necessarily representative of the final device's
electrical specifications
pF28M36...
Final silicon die that conforms to the device's electrical specifications but has
not completed quality and reliability verification
F28M36...
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS Fully qualified development-support product
Devices with prefix x or p and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices with prefix of x or p have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZWT) and temperature range (for example, T).
For device part numbers and further ordering information of F28M36x devices in the ZWT package type,
see the TI website (www.ti.com) or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the F28M36x Concerto™
MCUs Silicon Errata.
Device and Documentation Support
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F28M3
x
6
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P
6
3
C
2
ZWT
T
PREFIX
TEMPERATURE RANGE
T = −40°C to 105°C (TJ)
S = −40°C to 125°C (TJ)
= experimental device
x
= prototype device
p
no prefix = qualified device
PACKAGE TYPE
289-Ball ZWT New Fine Pitch Ball Grid Array (nFBGA)
DEVICE FAMILY
F28M3 = Concerto
PINS
2 = 289 terminals
SERIES NUMBER
PERFORMANCE
(C28x Speed / Cortex-M3 Speed)
PERIPHERALS
C = Connectivity
B = Base
P = 150/125 MHz
H = 150/100 MHz
RAM
FLASH
(A)
3 = additional 256KB to one core
5 = 512KB each core
6 = 1MB on Cortex-M3 and 512KB on C28x
A.
3 = 168KB + 64KB masterable RAM
The additional 256KB is added to the Cortex-M3 core (connectivity devices) or to the C28x core (base devices).
Figure 8-1. Device Nomenclature
8.2
Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the
performance of the device, generate code, and develop solutions are listed below. To view all available
tools and software for C2000™ real-time control MCUs, visit the C2000 MCU Tools and Software page.
Development Tools
H63C2 Concerto Experimenter Kit
The C2000 Experimenter Kits from Texas Instruments are ideal products for initial device exploration and
testing. The Concerto H63C2 Experimenter Kit has a docking station that features access to all
controlCARD signals, breadboard areas and RS-232 and JTAG connectors. Each kit contains a H63C2
controlCARD. The controlCARD is a complete board level module that utilizes and industry-standard
DIMM form factor to provide a low-profiles single-board controller solution. Kit is complete with Code
Composer StudioTM IDE v5 and USB cable.
F28M36 Concerto Control Card
The C2000 controlCARDs from Texas Instruments are ideal products for initial software development and
short run builds for system prototypes, test stands, and many other projects that require easy access to
high-performance controllers. The controlCARDs are complete board-level modules that utilize an
industry-standard DIMM form factor to provide a low-profile single-board controller solution. The host
system needs to provide only a single 5V power rail to the controlCARD for it to be fully functional.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or
scripting interface.
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Software Tools
controlSUITE™ Software Suite: Essential Software and Development Tools for C2000™ Microcontrollers
controlSUITE™ for C2000™ microcontrollers is a cohesive set of software infrastructure and software
tools designed to minimize software development time.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller
and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop
and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project
build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user
interface taking the user through each step of the application development flow. Familiar tools and
interfaces allow users to get started faster than ever before. Code Composer Studio combines the
advantages of the Eclipse software framework with advanced embedded debug capabilities from TI
resulting in a compelling feature-rich development environment for embedded developers.
F021 Flash API
The F021 Flash Application Programming Interface (API) provides a software library of functions to
program, erase, and verify F021 on-chip Flash memory.
Models
Various models are available for download from the product Tools & Software pages. These include I/O
Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models.
To view all available models, visit the Models section of the Tools & Software page for each device, which
can be found in Table 8-1.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and
performance, TI has developed a variety of training resources. Utilizing the online training materials and
downloadable hands-on workshops provides an easy means for gaining a complete working knowledge of
the C2000 microcontroller family. These training resources have been designed to decrease the learning
curve, while reducing development time, and accelerating product time to market. For more information on
the various training resources, visit the C2000™ real-time control MCUs – Support & training site.
8.3
Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
is listed below.
Errata
F28M36x Concerto™ MCUs Silicon Errata describes known advisories on silicon and provides
workarounds.
Technical Reference Manual
Concerto F28M36x Technical Reference Manual details the integration, the environment, the functional
description, and the programming models for each peripheral and subsystem in the F28M36x
Microcontroller Processors.
Device and Documentation Support
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CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and
the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This
Reference Guide also describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline,
and instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the
28x DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language
tools (assembler and other tools used to develop assembly language code), assembler directives, macros,
common object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts
their application in perspective with respect to system-level junction temperature estimation.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare
semiconductor devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful
lifetime of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at
general engineers who wish to determine if the reliability of the TI EP meets the end system reliability
requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the
input/output structures and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders
for serial programming a device.
8.4
Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 8-1. Related Links
248
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
F28M36P63C2
Click here
Click here
Click here
Click here
Click here
F28M36P53C2
Click here
Click here
Click here
Click here
Click here
F28M36H53B2
Click here
Click here
Click here
Click here
Click here
F28M36H33B2
Click here
Click here
Click here
Click here
Click here
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www.ti.com
8.5
SPRS825F – OCTOBER 2012 – REVISED JUNE 2020
Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help —
straight from the experts. Search existing answers or ask your own question to get the quick design help
you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications
and do not necessarily reflect TI's views; see TI's Terms of Use.
8.6
Trademarks
Concerto, TMS320C2000, controlSUITE, Texas Instruments, Code Composer Studio, C2000, TI E2E are
trademarks of Texas Instruments.
Arm, Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Freescale is a trademark of Freescale Semiconductor, Inc.
NXP is a registered trademark of NXP Semiconductors.
Bosch is a registered trademark of Robert Bosch GmbH Corporation.
All other trademarks are the property of their respective owners.
8.7
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.8
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
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9 Mechanical, Packaging, and Orderable Information
9.1
Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
250
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
F28M36H33B2ZWTT
ACTIVE
NFBGA
ZWT
289
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F28M36
H33B2ZWTT
F28M36H53B2ZWTT
ACTIVE
NFBGA
ZWT
289
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F28M36
H53B2ZWTT
F28M36P53C2ZWTS
ACTIVE
NFBGA
ZWT
289
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 125
F28M36
P53C2ZWTS
F28M36P53C2ZWTT
ACTIVE
NFBGA
ZWT
289
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F28M36
P53C2ZWTT
F28M36P63C2ZWTS
ACTIVE
NFBGA
ZWT
289
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 125
F28M36
P63C2ZWTS
F28M36P63C2ZWTT
ACTIVE
NFBGA
ZWT
289
90
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 105
F28M36
P63C2ZWTT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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