TMP75B-Q1
SBOS721A – OCTOBER 2014 – REVISED JUNE 2022
TMP75B-Q1 1.8-V Digital Temperature Sensor with Two-Wire Interface and Alert
1 Features
3 Description
•
•
The TMP75B-Q1 is an integrated digital temperature
sensor with a 12-bit analog-to-digital converter (ADC)
that can operate at a 1.8-V supply, and is pin
and register compatible with the industry-standard
LM75 and TMP75. This device is available in
SOIC-8 and VSSOP-8 packages, and requires no
external components to sense the temperature. The
TMP75B-Q1 is capable of reading temperatures with
a resolution of 0.0625°C and is specified over a
temperature range of –40°C to 125°C.
•
•
•
•
•
•
•
•
•
•
•
2 Applications
•
•
•
•
•
•
•
Automotive embedded systems
ECU processor temperature monitoring
TCM processor temperature monitoring
BCM processor temperature monitoring
LED headlight thermal control
Battery thermal protection
Electrical motor driver thermal protection
The TMP75B-Q1 features SMBus and two-wire
interface compatibility, and allows up to eight devices
on the same bus with the SMBus overtemperature
alert function. The programmable temperature limits
and the ALERT pin allow the sensor to operate as a
stand-alone thermostat, or an overtemperature alarm
for power throttling or system shutdown.
The factory-calibrated temperature accuracy and the
noise-immune digital interface make the TMP75B-Q1
the preferred solution for temperature compensation
of other sensors and electronic components, without
the need for additional system-level calibration or
elaborate board layout for distributed temperature
sensing.
The TMP75B-Q1 is designed for thermal
management and protection of a variety of automotive
applications, and is a high-performance alternative to
a PCB-mounted NTC thermistor.
Device Information(1)
DEVICE NAME
(1)
0.01 PF
2
Two-Wire
Host Controller
3
4.90 mm × 3.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
3
8
SDA
VS
SCL
A0
ALERT
A1
GND
A2
4
BODY SIZE (NOM)
SOIC (8)
For all available packages, see the package option
addendum at the end of the data sheet.
TMP75B-Q1
1
PACKAGE
TMP75B-Q1
1.4 V to 3.6 V
2
7
6
5
Temperature Error (ƒC)
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Temperature grade 1: –40°C to 125°C
– HBM ESD classification 2
– CDM ESD classification C4B
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Digital output with two-wire serial interface
Up to 8 pin-programmable bus addresses
Programmable overtemperature ALERT
Shutdown mode for power saving
One-shot conversion mode
Operating temperature range: –40°C to 125°C
Operating supply range: 1.4 V to 3.6 V
Quiescent current:
– 45-μA Active (typical)
– 0.3-μA Shutdown (typical)
Accuracy:
– ±0.5°C (typical) from –20°C to 85°C
– ±1°C (typical) from –40°C to 125°C
Resolution: 12 bits (0.0625°C)
Packages: SOIC-8 and VSSOP-8
1
0
±1
Mean
±2
Simplified Schematic
Mean - 61
Mean + 61
±3
±75
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
C005
Temperature Accuracy (Error) vs. Ambient
Temperature
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP75B-Q1
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 6
7 Detailed Description........................................................7
7.1 Overview..................................................................... 7
7.2 Functional Block Diagram........................................... 7
7.3 Feature Description.....................................................8
7.4 Device Functional Modes..........................................16
7.5 Programming............................................................ 17
7.6 Register Map.............................................................19
8 Application and Implementation.................................. 22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 22
9 Power-Supply Recommendations............................... 23
10 Layout...........................................................................24
10.1 Layout Guidelines................................................... 24
10.2 Layout Example...................................................... 24
11 Device and Documentation Support..........................25
11.1 Documentation Support.......................................... 25
11.2 Trademarks............................................................. 25
12 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
Changes from Revision * (October 2014) to Revision A (June 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed all instances of legacy terminology to controller and target where I2C is mentioned.......................... 1
• Added Functional Safety information to the Features section............................................................................ 1
2
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5 Pin Configuration and Functions
SDA
1
8
VS
SCL
2
7
A0
ALERT
3
6
A1
GND
4
5
A2
Figure 5-1. D and DGK Packages 8-Pin SOIC and 8-Pin VSSOP (Top View)
Table 5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
A0
7
I
Address select. Connect to GND or VS.
A1
6
I
Address select. Connect to GND or VS.
A2
5
I
Address select. Connect to GND or VS.
ALERT
3
O
Overtemperature alert. Open-drain output; requires a pullup resistor.
GND
4
—
Ground
SCL
2
I
SDA
1
I/O
VS
8
I
Serial clock
Serial data. Open-drain output; requires a pullup resistor.
Supply voltage, 1.4 V to 3.6 V
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
Supply voltage, VS
MAX
UNIT
4
V
SDA, SCL, ALERT, A2, A1
–0.3
4
V
A0
–0.3
(VS) + 0.3
V
10
mA
Operating junction temperature
–55
150
°C
Tstg
–60
150
°C
Input voltage
Sink current
(1)
SDA, ALERT
Storage temperature range
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
Human body model (HBM), per AEC
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per
AEC Q100-011
Q100-002(1)
MIN
MAX
–2000
2000
Corner pins (1, 4, 5,
and 8)
–1000
1000
Other pins
–1000
1000
UNIT
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
Supply voltage
1.4
1.8
Operating free-air temperature, TA
–40
MAX
UNIT
3.6
V
125
°C
6.4 Thermal Information
TMP75B-Q1
THERMAL
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
125.4
188.1
RθJC(top)
Junction-to-case (top) thermal resistance
71.5
79.1
RθJB
Junction-to-board thermal resistance
65.8
109.6
ψJT
Junction-to-top characterization parameter
21.1
15.3
ψJB
Junction-to-board characterization parameter
65.3
108
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
(1)
4
METRIC(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At TA = –40°C to 125°C and VS = 1.4 V to 3.6 V, unless otherwise noted. Typical values at TA = 25°C and VS = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
125
°C
TEMPERATURE INPUT
Temperature range
–40
Temperature resolution
Temperature accuracy
(error)
0.0625
–20°C to 85°C
–40°C to 125°C
°C
±0.5
±2
°C
±1
±3
°C
DIGITAL INPUT/OUTPUT
VIH
High-level input voltage
0.7(VS)
VS
V
VIL
Low-level input voltage
–0.3
0.3(VS)
V
IIN
Input current
VOL
Low-level output voltage
0 V < VIN < (VS) + 0.3 V
1
μA
VS ≥ 2 V, IOUT = 3 mA
0.4
V
VS < 2 V, IOUT = 3 mA
0.2(VS)
V
ADC resolution
Conversion time
Conversion modes
12
One-shot mode
20
27
Bit
35
ms
CR1 = 0, CR0 = 0 (default)
37
Conv/s
CR1 = 0, CR0 = 1
18
Conv/s
CR1 = 1, CR0 = 0
9
Conv/s
CR1 = 1, CR0 = 1
4
Conv/s
Timeout time
38
54
70
ms
POWER SUPPLY
Operating supply range
IQ
ISD
Quiescent current
Shutdown current
3.6
V
Serial bus inactive, CR1 = 0, CR0 = 0 (default)
1.4
45
89
μA
Serial bus inactive, CR1 = 0, CR0 = 1
22
48
μA
Serial bus inactive, CR1 = 1, CR0 = 0
12
30
μA
Serial bus inactive, CR1 = 1, CR0 = 1
6.5
21
μA
Serial bus inactive
0.3
8
μA
Serial bus active, SCL frequency = 400 kHz
10
μA
Serial bus active, SCL frequency = 3.4 MHz
80
μA
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6.6 Typical Characteristics
At TA = 25°C and VS = 1.8 V (unless otherwise noted).
100
80
70
Vs = 1.8V
8
Vs = 3.6V
7
60
50
40
6
5
4
30
3
20
2
10
1
0
0
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
±75
±50
0
±25
25
50
75
100
125
Temperature (ƒC)
C001
Figure 6-1. Quiescent Current vs. Temperature
150
C002
Figure 6-2. Shutdown Current vs. Temperature
30
200
29
175
28
Ta = 7D
7D
150
27
Û&
Û&
Û&
125
26
IQ ( A)
Conversion Time (ms)
Vs = 1.4V
9
ISD ( A)
IQ ( A)
10
CR = '0h'
CR = '1h'
CR = '2h'
CR = '3h'
90
25
24
100
75
23
22
21
Vs = 1.4V
50
Vs = 1.8V
25
Vs = 3.6V
20
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
0
150
10
Figure 6-3. Conversion Time vs. Temperature
100
1000
Bus Frequency (kHz)
C003
10000
C004
Figure 6-4. Quiescent Current vs. Bus Frequency
3
Population
1
0
±1
Mean
±2
Mean - 61
Mean + 61
±3
±75
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
Temperature Error (ƒC)
C005
Figure 6-5. Temperature Error vs. Temperature
6
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Temperature Error (ƒC)
2
C006
Figure 6-6. Temperature Error at 25°C
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7 Detailed Description
7.1 Overview
The TMP75B-Q1 is a digital temperature sensor optimal for thermal management and thermal protection
applications. The TMP75B-Q1 is two-wire and SMBus interface compatible, and is specified over a temperature
range of –40°C to 125°C.
The temperature sensing device for the TMP75B-Q1 is the chip itself. A bipolar junction transistor (BJT) inside
the chip is used in a band-gap configuration to produce a voltage proportional to the chip temperature. The
voltage is digitized and converted to a 12-bit temperature result in degrees Celsius, with a resolution of
0.0625°C. The package leads provide the primary thermal path because of the lower thermal resistance of
the metal. Thus, the temperature result is equivalent to the local temperature of the printed circuit board (PCB)
where the sensor is mounted.
7.2 Functional Block Diagram
VS
Device
Voltage Regulator
Register Bank
Oscillator
SDA
Serial Interface
Control Logic
SCL
A0
NxI
I
ALERT
A1
A2
ADC
Thermal
BJT
GND
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7.3 Feature Description
7.3.1 Digital Temperature Output
The 12-bit digital output from each temperature measurement conversion is stored in the read-only temperature
register. Two bytes must be read to obtain the data; see Figure 7-9. Note that byte 1 is the most significant byte,
followed by byte 2, the least significant byte. The temperature result is left-justified with the 12 most significant
bits used to indicate the temperature. There is no need to read the second byte if resolution below 1°C is not
required. Table 7-1 summarizes the temperature data format. One LSB equals 0.0625°C. Negative numbers are
represented in binary twos complement format.
Table 7-1. Temperature Data Format(1)
DIGITAL OUTPUT
(1)
TEMPERATURE (°C)
BINARY
HEX
128
0111 1111 1111
7FF
127.9375
0111 1111 1111
7FF
100
0110 0100 0000
640
80
0101 0000 0000
500
75
0100 1011 0000
4B0
50
0011 0010 0000
320
25
0001 1001 0000
190
0.25
0000 0000 0100
004
0
0000 0000 0000
000
–0.25
1111 1111 1100
FFC
–25
1110 0111 0000
E70
–55
1100 1001 0000
C90
The temperature sensor resolution is 0.0625°C/LSB.
Table 7-1 does not supply a full list of all temperatures. Use the following rules to obtain the digital data format
for a given temperature, and vice versa.
To convert positive temperatures to a digital data format:
Divide the temperature by the resolution. Then, convert the result to binary code with a 12-bit, left-justified
format, and MSB = 0 to denote a positive sign.
Example: (50°C) / (0.0625°C / LSB) = 800 = 320h = 0011 0010 0000
To convert a positive digital data format to temperature:
Convert the 12-bit, left-justified binary temperature result, with the MSB = 0 to denote a positive sign, to a
decimal number. Then, multiply the decimal number by the resolution to obtain the positive temperature.
Example: 0011 0010 0000 = 320h = 800 × (0.0625°C / LSB) = 50°C
To convert negative temperatures to a digital data format:
Divide the absolute value of the temperature by the resolution, and convert the result to binary code with a
12-bit, left-justified format. Then, generate the twos complement of the result by complementing the binary
number and adding one. Denote a negative number with MSB = 1.
Example: (|–25°C|) / (0.0625°C / LSB) = 400 = 190h = 0001 1001 0000
Two's complement format: 1110 0110 1111 + 1 = 1110 0111 0000
To convert a negative digital data format to temperature:
Generate the twos compliment of the 12-bit, left-justified binary number of the temperature result (with MSB =
1, denoting negative temperature result) by complementing the binary number and adding one. This represents
8
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the binary number of the absolute value of the temperature. Convert to decimal number and multiply by the
resolution to get the absolute temperature, then multiply by –1 for the negative sign.
Example: 1110 0111 0000 has twos compliment of 0001 1001 0000 = 0001 1000 1111 + 1
Convert to temperature: 0001 1001 0000 = 190h = 400; 400 × (0.0625°C / LSB) = 25°C = (|–25°C|); (|–25°C|) ×
(–1) = –25°C
7.3.2 Temperature Limits and Alert
The temperature limits are stored in the TLOW and THIGH registers (Table 7-8 and Table 7-9) in the same format
as the temperature result, and their values are compared to the temperature result on every conversion. The
outcome of the comparison drives the behavior of the ALERT pin, which can operate as a comparator output or
an interrupt, and is set by the TM bit in the configuration register (Table 7-7).
In comparator mode (TM = 0, default), the ALERT pin becomes active when the temperature is equal to or
exceeds the value in THIGH (fault conditions) for a consecutive number of conversions as set by the FQ bits
of the configuration register. ALERT clears when the temperature falls below TLOW for the same consecutive
number of conversions. The difference between the two limits acts as a hysteresis on the comparator output,
and a fault counter prevents false alerts as a result of environmental noise.
In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds the value
in THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of
any register occurs, or the device successfully responds to the SMBus alert response address. The ALERT pin
is also cleared if the device is placed in shutdown mode (see the Shutdown Mode section for shutdown mode
description). After the ALERT pin is cleared, this pin becomes active again only when the temperature falls
below TLOW for a consecutive number of fault conditions, and remains active until cleared by a read operation
of any register, or a successful response to the SMBus alert response address. After the ALERT pin is cleared,
the cycle repeats with the ALERT pin becoming active when the temperature equals or exceeds THIGH, and so
on. The ALERT pin can also be cleared by resetting the device with the general-call reset command. This action
also clears the state of the internal registers in the device and the fault counter memory, returning the device to
comparator mode (TM = 0).
The active state of the ALERT pin is set by the POL bit in the configuration register. When POL = 0 (default), the
ALERT pin is active low. When POL = 1, the ALERT pin is active high. The operation of the ALERT pin in various
modes is shown in Figure 7-1.
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THIGH
Measured
Temperature
TLOW
Device ALERT PIN
(Comparator Mode)
POL = 0
Device ALERT PIN
(Interrupt Mode)
POL = 0
Device ALERT PIN
(Comparator Mode)
POL = 1
Device ALERT PIN
(Interrupt Mode)
POL = 1
Read
Read
Read
Time
Figure 7-1. ALERT Pin Modes of Operation
10
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7.3.3 Serial Interface
The TMP75B-Q1 operates as a target device only on the two-wire bus and SMBus. Connections to the bus
are made using the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spikesuppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP75B-Q1
supports the transmission protocol for both fast (1 kHz to 400 kHz) and high-speed (1 kHz to 3 MHz) modes. All
data bytes are transmitted MSB first.
7.3.3.1 Bus Overview
The device that initiates the transfer is called a controller, and the devices controlled by the controller are targets.
The bus must be controlled by a controller device that generates the serial clock (SCL), controls the bus access,
and generates the start and stop conditions.
To address a specific device, initiate a start condition by pulling the data line (SDA) from a high to a low logic
level while SCL is high. All targets on the bus shift in the target address byte; the last bit indicates whether
a read or write operation follows. During the ninth clock pulse, the target being addressed responds to the
controller by generating an acknowledge bit and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high because any change in SDA while SCL is high is interpreted
as a start or stop signal.
After all data have been transferred, the controller generates a stop condition indicated by pulling SDA from low
to high, while SCL is high.
7.3.3.2 Serial Bus Address
To communicate with the TMP75B-Q1, the controller must first communicate with target devices using a target
address byte. The target address byte consists of seven address bits, and a direction bit indicating the intent of
executing either a read or write operation. The TMP75B-Q1 features three address pins that allow up to eight
devices to be addressed on a single bus. The TMP75B-Q1 latches the status of the address pins at the start of a
communication. Table 7-2 describes the pin logic levels and the corresponding address values.
Table 7-2. Address Pin Connections and Target Addresses
DEVICE TWO-WIRE ADDRESS
A2
A1
A0
1001000
GND
GND
GND
1001001
GND
GND
VS
1001010
GND
VS
GND
1001011
GND
VS
VS
1001100
VS
GND
GND
1001101
VS
GND
VS
1001110
VS
VS
GND
1001111
VS
VS
VS
7.3.3.3 Writing and Reading Operation
Accessing a particular register on the TMP75B-Q1 is accomplished by writing the appropriate value to the
pointer register. The value for the pointer register is the first byte transferred after the target address byte with
the R/W bit low. Every write operation to the TMP75B-Q1 requires a value for the pointer register (see Figure
7-3).
When reading from the TMP75B-Q1, the last value stored in the pointer register by a write operation is used to
determine which register is read by a read operation. To change the register pointer for a read operation, a new
value must be written to the pointer register. This action is accomplished by issuing a target address byte with
the R/W bit low, followed by the pointer register byte. No additional data are required. The controller can then
generate a start condition and send the target address byte with the R/W bit high to initiate the read command.
See Figure 7-4 for details of this sequence. If repeated reads from the same register are desired, there is no
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need to continually send the pointer register bytes because the TMP75B-Q1 stores the pointer register value
until it is changed by the next write operation.
Note that register bytes are sent with the most significant byte first, followed by the least significant byte.
7.3.3.4 Target-Mode Operations
The TMP75B-Q1 can operate as a target receiver or target transmitter.
7.3.3.4.1 Target Receiver Mode:
The first byte transmitted by the controller is the target address, with the R/W bit low. The TMP75B-Q1 then
acknowledges reception of a valid address. The next byte transmitted by the controller is the pointer register.
The TMP75B-Q1 then acknowledges reception of the pointer register byte. The next byte or bytes are written to
the register addressed by the pointer register. The TMP75B-Q1 acknowledges reception of each data byte. The
controller can terminate data transfer by generating a start or stop condition.
7.3.3.4.2 Target Transmitter Mode:
The first byte transmitted by the controller is the target address, with the R/W bit high. The target acknowledges
reception of a valid target address. The next byte is transmitted by the target and is the most significant byte of
the register indicated by the pointer register. The controller acknowledges reception of the data byte. The next
byte transmitted by the target is the least significant byte. The controller acknowledges reception of the data
byte. The controller can terminate data transfer by generating a not-acknowledge bit on reception of any data
byte, or by generating a start or stop condition.
7.3.3.5 SMBus Alert Function
The TMP75B-Q1 supports the SMBus alert function. When the TMP75B-Q1 operates in interrupt mode (TM = 1),
the ALERT pin may be connected as an SMBus alert signal. When a controller senses that an alert condition is
present on the ALERT line, the controller sends an SMBus alert command (00011001) to the bus. If the ALERT
pin is active, the device acknowledges the SMBus alert command and responds by returning its target address
on the SDA line. The eighth bit (LSB) of the target address byte indicates whether the alert condition is caused
by the temperature exceeding THIGH or falling below TLOW. The LSB is high if the temperature is greater than
THIGH, or low if the temperature is less than TLOW. See Figure 7-5 for details of this sequence.
If multiple devices on the bus respond to the SMBus alert command, arbitration during the target address portion
of the SMBus alert command determines which device clears its alert status first. If the TMP75B-Q1 wins the
arbitration, its ALERT pin becomes inactive at the completion of the SMBus alert command. If the TMP75B-Q1
loses the arbitration, its ALERT pin remains active.
7.3.3.6 General Call
The TMP75B-Q1 responds to a two-wire general call address (0000000) if the eighth bit is 0. The device
acknowledges the general call address and responds to commands in the second byte. If the second byte is
00000100, the TMP75B-Q1 latches the status of the address pin, but does not reset. If the second byte is
00000110, the TMP75B-Q1 internal registers are reset to power-up values.
7.3.3.7 High-Speed (Hs) Mode
In order for the two-wire bus to operate at frequencies above 400 kHz, the controller device must issue an
SMBus Hs-mode controller code (00001xxx) as the first byte after a start condition to switch the bus to highspeed operation. The TMP75B-Q1 does not acknowledge this byte, but does switch its input filters on SDA and
SCL and its output filters on SDA to operate in Hs-mode, allowing transfers at up to 3 MHz. After the Hs-mode
controller code has been issued, the controller transmits a two-wire target address to initiate a data-transfer
operation. The bus continues to operate in Hs-mode until a stop condition occurs on the bus. Upon receiving the
stop condition, the TMP75B-Q1 switches the input and output filters back to fast-mode operation.
7.3.3.8 Timeout Function
The TMP75B-Q1 resets the serial interface if SCL or SDA are held low for 54 ms (typical) between a start and
stop condition. If the TMP75B-Q1 is pulled low, it releases the bus and then waits for a start condition. To avoid
12
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activating the timeout function, it is necessary to maintain a communication speed of at least 1 kHz for the SCL
operating frequency.
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7.3.3.9 Two-Wire Timing
The TMP75B-Q1 is two-wire and SMBus compatible. Figure 7-2 to Figure 7-5 describe the various operations on
the TMP75B-Q1. Parameters for Figure 7-2 are defined in Table 7-3. Bus definitions are:
Bus Idle
Both SDA and SCL lines remain high.
Start Data
Transfer
A change in the state of the SDA line, from high to low, while the SCL line is high defines a
start condition. Each data transfer is initiated with a start condition.
Stop Data
Transfer
A change in the state of the SDA line from low to high while the SCL line is high defines a
stop condition. Each data transfer is terminated with a repeated start or stop condition.
Data Transfer
The number of data bytes transferred between a start and a stop condition is not limited,
and is determined by the controller device.
The receiver acknowledges the transfer of data. It is also possible to use the TMP75B-Q1
for single-byte updates. To update only the MS byte, terminate communication by issuing a
start or stop condition on the bus.
Acknowledge
Each receiving device, when addressed, must generate an acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock
pulse so that the SDA line is stable low during the high period of the acknowledge clock
pulse. Setup and hold times must be taken into account. When a controller receives
data, the termination of the data transfer can be signaled by the controller generating a
not-acknowledge (1) on the last byte transmitted by the target.
Table 7-3. Timing Diagram Requirements
FAST MODE
PARAMETER
HIGH-SPEED MODE
MIN
MAX
MIN
MAX
UNIT
VS ≥ 1.8 V
0.001
0.4
VS < 1.8 V
0.001
0.4
0.001
3
MHz
0.001
2.5
MHz
VS ≥ 1.8 V
1300
160
ns
VS < 1.8 V
1300
260
ns
f(SCL)
SCL operating frequency
t(BUF)
Bus free time between
stop and start conditions
t(HDSTA)
Hold time after repeated start condition.
After this period, the first clock is generated.
600
160
ns
t(SUSTA)
Repeated start condition setup time
600
160
ns
t(SUSTO)
Stop condition setup time
600
160
ns
t(HDDAT)
Data hold time
t(SUDAT)
Data setup time
t(LOW)
SCL clock low period
t(HIGH)
SCL clock high period
tR(SDA), tF(SDA)
Data rise and fall time
tR(SCL), tF(SCL)
Clock rise and fall time
tR
Clock and data rise time for SCLK ≤ 100 kHz
14
VS ≥ 1.8 V
0
900
0
100
ns
VS < 1.8 V
0
900
0
140
ns
VS ≥ 1.8 V
100
10
ns
VS < 1.8 V
100
20
ns
VS ≥ 1.8 V
1300
190
ns
VS < 1.8 V
1300
240
ns
600
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60
ns
300
80
ns
300
40
ns
1000
ns
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7.3.3.10 Two-Wire Timing Diagrams
t(LOW)
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH)
t(SUSTO)
t(SUSTA)
t(HDDAT)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 7-2. Two-Wire Timing Diagram
1
9
1
9
SCL
SDA
¼
1
0
0
1
A2(1)
A1(1)
A0(1)
R/W
Start By
Controller
0
0
0
0
0
0
P1
P0
ACK By
Device
¼
ACK By
Device
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Target Address Byte
9
1
1
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
A.
D0
ACK By
Device
ACK By
Device
Frame 3 Data Byte 1
D1
Stop By
Controller
Frame 4 Data Byte 2
The value of A0, A1, and A2 are determined by the connections of the corresponding pins.
Figure 7-3. Two-Wire Timing Diagram for Write Word Format
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1
9
1
9
SCL
¼
SDA
1
0
0
1
A2
(1)
A1
(1)
(1)
A0
R/W
0
Start By
Controller
0
0
0
0
0
P1
P0
ACK By
Device
ACK By
Device
Frame 1 Two-Wire Target Address Byte
Stop By
Controller
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
¼
SDA
(Continued)
1
0
0
1
A2
(1)
A1
(1)
(1)
A0
R/W
D7
Start By
Controller
D6
D5
D4
D3
D2
ACK By
Device
D0
¼
ACK By
From
Device
Frame 3 Two-Wire Target Address Byte
1
D1
Controller
(2)
Frame 4 Data Byte 1 Read Register
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
From
Device
ACK By
Controller
(3)
Stop By
Controller
Frame 5 Data Byte 2 Read Register
A.
B.
C.
The value of A0, A1, and A2 are determined by the connections of the corresponding pins.
Controller should leave SDA high to terminate a single-byte read operation.
Controller should leave SDA high to terminate a two-byte read operation.
Figure 7-4. Two-Wire Timing Diagram for Read Word Format
ALERT
1
9
1
9
SCL
SDA
0
0
0
1
1
Start By
Controller
0
0
R/W
1
0
1
A2
(1)
ACK By
Device
Frame 1 SMBus ALERT Response Address Byte
A.
0
A1
(1)
A0
From
Device
(1)
Status
NACK By Stop By
Controller Controller
Frame 2 Target Address From Device
The value of A0, A1, and A2 are determined by the connections of the corresponding pins.
Figure 7-5. Timing Diagram for SMBus Alert
7.4 Device Functional Modes
7.4.1 Continuous-Conversion Mode
The default mode of the TMP75B-Q1 is continuous conversion, where the ADC performs continuous
temperature conversions and stores each result to the temperature register, overwriting the result from the
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previous conversion. Conversion rate bits CR1 and CR0 in the configuration register configure the TMP75B-Q1
for typical conversion rates of 37 Hz, 18 Hz, 9 Hz, or 4 Hz. The TMP75B-Q1 has a typical conversion time of
27 ms. To achieve different conversion rates, the TMP75B-Q1 makes a conversion, and then powers down
and waits for the appropriate delay set by CR1 and CR0. The default rate is 37 Hz (no delay between
conversions).Table 7-4 shows the settings for CR1 and CR0.
Table 7-4. Conversion Rate Settings
CR1
CR0
CONVERSION RATE (TYP)
IQ (TYP)
0
0
37 Hz (continuous conversion, default)
45 μA
0
1
18 Hz
22 μA
1
0
9 Hz
12 μA
1
1
4 Hz
6.5 μA
After power-up or a general-call reset, the TMP75B-Q1 immediately starts a conversion, as shown in Figure 7-6.
The first result is available after 27 ms (typical). The active quiescent current during conversion is 45 μA (typical
at 25°C). The quiescent current during delay is 1 μA (typical at 25°C).
Delay
(1)
Delay
(1)
27 ms
27 ms
27 ms
Startup
A.
Start of
Conversion
Start of
Conversion
Delay is set by the CR bits in the configuration register.
Figure 7-6. Conversion Start
7.4.2 Shutdown Mode
Shutdown mode saves maximum power by shutting down all device circuitry other than the serial interface, and
reduces current consumption to typically less than 0.3 μA. Shutdown mode is enabled when the SD bit in the
configuration register is set to 1; the device shuts down after the current conversion is completed. When SD is
equal to 0, the device operates in continuous-conversion mode. When shutdown mode is enabled, the ALERT
pin and fault counter clear in both comparator and interrupt modes; however, this clearing occurs with the rising
edge of the shutdown signal. After shutdown is enabled, reprogramming shutdown does not clear the ALERT pin
and the fault counter until a rising edge is generated on the shutdown signal.
7.4.3 One-Shot Mode
The TMP75B-Q1 features a one-shot temperature measurement mode. When the device is in shutdown mode,
writing a 1 to the OS bit starts a single temperature conversion. The device returns to the shutdown state
at the completion of the single conversion. This mode reduces power consumption in the TMP75B-Q1 when
continuous temperature monitoring is not required. When the configuration register is read, the OS bit always
reads zero.
7.5 Programming
Figure 7-7 shows the internal register structure of the TMP75B-Q1. Use the 8-bit pointer register to address a
given data register. The pointer register uses the two LSBs to identify which of the data registers respond to a
read or write command. Figure 7-8 identifies the bits of the pointer register byte.
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Pointer
Register
Temperature
Register
Configuration
Register
TLOW
Register
SCL
I/O
Control
Interface
SDA
THIGH
Register
Figure 7-7. Internal Register Structure
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7.6 Register Map
Table 7-5 describes the registers available in the TMP75B-Q1 with their pointer addresses, followed by the
description of the bits in each register.
Table 7-5. Register Map and Pointer Addresses
P1
P0
0
0
Temperature register (read only, default)
REGISTER
0
1
Configuration register (read/write)
1
0
TLOW register (read/write)
1
1
THIGH register (read/write)
Figure 7-8. Pointer Register (pointer = N/A) [reset = 00h]
7
6
5
1
0
Reserved
4
3
2
P1
P0
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
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Figure 7-9. Temperature Register (pointer = 0h) [reset = 0000h]
15
14
13
12
11
10
9
8
T11
T10
T9
T8
T7
T6
T5
T4
3
2
1
0
R-0h
7
6
T3
T2
5
4
T1
T0
Reserved
R-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-6. Temperature Register Description
Name
Description
T11 to T4
The 8 MSBs of the temperature result (resolution of 1°C)
T3 to T0
The 4 LSBs of the temperature result (resolution of 0.0625°C)
Figure 7-10. Configuration Register (pointer = 1h) [reset = 00FFh]
15
14
13
12
11
10
9
8
OS
CR
FQ
POL
TM
SD
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
2
1
0
7
6
5
4
3
Reserved
R-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-7. Configuration Register Description
Name
Description
OS
One-shot mode
In shutdown (SD = 1), write 1 to start a conversion. OS always reads back 0.
CR
Conversion rate control
CR = 0h: 37-Hz conversion rate (typ) (default)
CR = 1h: 18-Hz conversion rate (typ)
CR = 2h: 9-Hz conversion rate (typ)
CR = 3h: 4-Hz conversion rate (typ)
FQ
Fault queue to trigger the ALERT pin
FQ = 0h: 1 fault (default)
FQ = 1h: 2 faults
FQ = 2h: 4 faults
FQ = 3h: 6 faults
POL
ALERT polarity control
POL = 0: ALERT is active low (default)
POL = 1: ALERT is active high
TM
ALERT thermostat mode control
TM = 0: ALERT is in comparator mode (default)
TM = 1: ALERT is in interrupt mode
SD
Shutdown control bit
SD = 0: Device is in continuous conversion mode (default)
SD = 1: Device is in shutdown mode
Figure 7-11. TLOW: Temperature Low Limit Register (pointer = 2h) [reset = 4B00h](1)
15
20
14
13
12
11
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9
8
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Figure 7-11. TLOW: Temperature Low Limit Register (pointer = 2h) [reset = 4B00h](1) (continued)
L11
L10
L9
L8
L7
L6
3
2
L5
L4
1
0
R/W-4Bh
7
6
5
4
L3
L2
L1
L0
Reserved
R/W-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
4B00h = 75°C.
Table 7-8. TLOW Register Description
Name
Description
L11 to L4
The 8 MSBs of the temperature low limit (resolution of 1°C)
L3 to L0
The 4 LSBs of the temperature low limit (resolution of 0.0625°C)
Figure 7-12. THIGH: Temperature High Limit Register (pointer = 3h) [reset = 5000h](1)
15
14
13
12
H11
H10
H9
H8
11
10
9
8
H7
H6
H5
H4
3
2
1
0
R/W-50h
7
6
5
4
H3
H2
H1
H0
Reserved
R/W-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1)
5000h = 80°C.
Table 7-9. THIGH Register Description
Name
Description
H11 to H4
The 8 MSBs of the temperature high limit (resolution of 1°C)
H3 to H0
The 4 LSBs of the temperature high limit (resolution of 0.0625°C)
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TMP75B-Q1 is used to measure the PCB temperature of the location it is mounted. The programmable
address options allow up to eight locations on the board to be monitored on a single serial bus. Connecting the
ALERT pins together and programming the temperature limit registers to desired values allows for a temperature
watchdog operation of all devices, interrupting the host controller only if the temperature exceeds the limits.
8.2 Typical Application
1.4 V to 3.6 V
0.01 PF
TMP75B-Q1
1
2
Two-Wire
Host Controller
3
4
SDA
VS
SCL
A0
ALERT
A1
GND
A2
8
7
6
Connect to VS or
GND for up to 8
Address
Combinations
5
1.4 V to 3.6 V
TMP75B-Q1
1
2
3
4
0.01 PF
SDA
VS
SCL
A0
ALERT
A1
GND
A2
8
7
6
Connect to VS or
GND for up to 8
Address
Combinations
5
Additional
Sensor
Locations
Figure 8-1. Temperature Monitoring of Multiple Locations on a PCB
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8.2.1 Design Requirements
The TMP75B-Q1 only requires pullup resistors on SDA and ALERT, although a pullup resistor is typically present
on the SCL as well. A 0.01-μF bypass capacitor on the supply is recommended, as shown in Figure 8-1. The
SCL, SDA, and ALERT lines can be pulled up to a supply that is equal to or higher than VS through the pullup
resistors. To configure one of eight different addresses on the bus, connect A0, A1, and A2 to either VS or GND.
8.2.2 Detailed Design Procedure
The TMP75B-Q1 should be placed in close proximity to the heat source to be monitored, with a proper layout
for good thermal coupling. This ensures that temperature changes are captured within the shortest possible time
interval.
8.2.3 Application Curve
Temperature (ƒC)
Figure 8-2 shows the step response of the TMP75B-Q1 to a submersion in an oil bath of 100°C from room
temperature (27°C). The time-constant, or the time for the output to reach 63% of the input step, is 1.5 seconds.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
±1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Time (s)
C007
Figure 8-2. Temperature Step Response
9 Power-Supply Recommendations
The TMP75B-Q1 operates with power supply in the range of 1.4 V to 3.6 V. It is optimized for operation at 1.8-V
supply but can measure temperature accurately in the full supply range.
A power-supply bypass capacitor is recommended; place this capacitor as close as possible to the supply and
ground pins of the device. A typical value for this supply bypass capacitor is 0.01 μF. Applications with noisy or
high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.
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10 Layout
10.1 Layout Guidelines
Place the temperature sensor as close as possible and run copper planes on the ground or other layers to
ensure good thermal coupling to the heat source for fast settling and accurate measurement of the temperature
of the hot spot.
Place the power-supply bypass capacitor as close as possible to the supply and ground pins.
Pull up the open-drain output pins (SDA and ALERT) to a supply voltage rail (VS or higher but up to 3.6 V)
through 10-kΩ pullup resistors. Smaller values of the resistors can be used to compensate for long bus traces
that can cause an increase in capacitance and slow rise time for the open-drain outputs; the values should not
be less than 1kΩ to avoid self-heating effects due to increased current through the part in the low states of the
outputs.
10.2 Layout Example
Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
Supply Bypass
Capacitor
Supply Voltage
SDA
VS
SCL
A0
ALERT
A1
GND
A2
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 10-1. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
SBOU141 — TMP75xEVM User's Guide
11.2 Trademarks
All trademarks are the property of their respective owners.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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16-May-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TMP75BQDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T75BQ
Samples
TMP75BQDGKTQ1
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
T75BQ
Samples
TMP75BQDQ1
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU-DCC
Level-2-260C-1 YEAR
-40 to 125
T75BQ
Samples
TMP75BQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU-DCC
Level-2-260C-1 YEAR
-40 to 125
T75BQ
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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