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TMUX1104
SCDS392B – NOVEMBER 2018 – REVISED JULY 2019
TMUX1104 5-V, Low-Leakage-Current, 4:1 Precision Multiplexer
1 Features
3 Description
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The TMUX1104 is a precision complementary metaloxide semiconductor (CMOS) multiplexer (MUX). The
TMUX1104 offers a single channel, 4:1 configuration.
Wide operating supply of 1.08 V to 5.5 V allows for
use in a broad array of applications from medical
equipment to industrial systems. The device supports
bidirectional analog and digital signals on the source
(Sx) and drain (D) pins ranging from GND to VDD. All
logic inputs have 1.8 V logic compatible thresholds,
ensuring both TTL and CMOS logic compatibility
when operating in the valid supply voltage range.
Fail-Safe Logic circuitry allows voltages on the control
pins to be applied before the supply pin, protecting
the device from potential damage.
1
Wide supply range: 1.08 V to 5.5 V
Low leakage current: 3 pA
Low charge injection: 1.5 pC
Low on-resistance: 2 Ω
-40°C to +125°C Operating temperature
1.8 V Logic Compatible
Fail-Safe Logic
Rail to Rail Operation
Bidirectional Signal Path
Break-before-make switching
ESD protection HBM: 2000 V
The TMUX1104 is part of the precision switches and
multiplexers family of devices. These devices have
very low on and off leakage currents and low charge
injection, allowing them to be used in high precision
measurement applications. A low supply current of 5
nA and small package options enable use in portable
applications.
2 Applications
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Ultrasound scanners
Patient monitoring & diagnostics
Blood glucose monitors
Optical networking
Optical test equipment
Remote radio units
Wired networking
Data acquisition systems
ATE test equipment
Factory automation and industrial controls
Programmable logic controllers (PLC)
Analog input modules
SONAR receivers
Battery monitoring systems
Device Information(1)
PART NUMBER
TMUX1104
BODY SIZE (NOM)
VSSOP (10) (DGS)
3.00 mm × 3.00 mm
USON (10) (DQA)
2.50 mm x 1.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Simplified Schematic
VDD
PACKAGE
Block Diagram
VDD
TMUX1104
VREF
EN
S1
Bridge Sensor
REF
S1
S2
+
D1
Op Amp
Thermocouple
-
S2
D
S3
+
Op Amp
Current Sensing
Photo
LED Detector
Optical Sensor
Analog Inputs
S3
Precision
ADC
S4
S4
GND
A0
1-of-4
Decoder
A1
1.8V Logic
Signals
TMUX1104
EN
A1
A0
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX1104
SCDS392B – NOVEMBER 2018 – REVISED JULY 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics (VDD = 5 V ±10 %) ............ 5
Electrical Characteristics (VDD = 3.3 V ±10 %) ......... 7
Electrical Characteristics (VDD = 1.8 V ±10 %) ......... 9
Electrical Characteristics (VDD = 1.2 V ±10 %) ....... 11
Typical Characteristics ............................................ 13
Parameter Measurement Information ................ 16
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
On-Resistance ........................................................
Off-Leakage Current ...............................................
On-Leakage Current ...............................................
Transition Time .......................................................
Break-Before-Make .................................................
tON(EN) and tOFF(EN)..................................................
Charge Injection ......................................................
Off Isolation .............................................................
Crosstalk .................................................................
16
16
17
17
18
18
19
19
20
7.10 Bandwidth ............................................................. 20
8
Detailed Description ............................................ 21
8.1
8.2
8.3
8.4
9
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Truth Tables ............................................................
21
21
23
23
Application and Implementation ........................ 24
9.1
9.2
9.3
9.4
9.5
Application Information............................................
Typical Application .................................................
Design Requirements..............................................
Detailed Design Procedure .....................................
Application Curve ....................................................
24
24
24
25
25
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 26
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2018) to Revision B
Page
•
Deleted the Product Preview note from the DQA package in the Device Information table .................................................. 1
•
Deleted the Product Preview note from the DQA package in the Pin Configuration and Functions section ......................... 3
•
Added DQA (USON) thermal values to Thermal Information ................................................................................................ 4
Changes from Original (November 2018) to Revision A
•
2
Page
Changed the document status From: Advanced Information To: Production Mix data.......................................................... 1
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SCDS392B – NOVEMBER 2018 – REVISED JULY 2019
5 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
DQA Package
10-Pin USON
Top View
A0
1
10
A1
S1
2
9
S2
GND
3
8
D
S3
4
7
S4
EN
5
6
VDD
A0
1
10
A1
S1
2
9
S2
GND
3
8
D
S3
4
7
S4
EN
5
6
VDD
Not to scale
Not to scale
Pin Functions
PIN
NAME
DGS, DQA
TYPE (1)
DESCRIPTION
A0
1
I
S1
2
I/O
GND
3
P
S3
4
I/O
EN
5
I
Active high logic enable. When this pin is low, all switches are turned off. When this pin is high, the
A[1:0] logic inputs determine which switch is turned on.
VDD
6
P
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
S4
7
I/O
Source pin 4. Can be an input or output.
D
8
I/O
Drain pin. Can be an input or output.
S2
9
I/O
Source pin 2. Can be an input or output.
A1
10
I
(1)
Address line 0. Controls the switch configuration as shown in Table 1.
Source pin 1. Can be an input or output.
Ground (0 V) reference
Source pin 3. Can be an input or output.
Address line 1. Controls the switch configuration as shown in Table 1.
I = input, O = output, I/O = input and output, P = power
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SCDS392B – NOVEMBER 2018 – REVISED JULY 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
MAX
VDD
Supply voltage
–0.5
6
V
VSEL or VEN
Logic control input pin voltage (EN, A0, A1)
–0.5
6
V
ISEL or IEN
Logic control input pin current (EN, A0, A1)
–30
30
mA
VS or VD
Source or drain voltage (Sx, D)
–0.5
VDD+0.5
IS or ID (CONT)
Source or drain continuous current (Sx, D)
–30
30
mA
Tstg
Storage temperature
–65
150
°C
TJ
Junction temperature
150
°C
(1)
(2)
(3)
UNIT
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD
Positive power supply voltage
VS or VD
VSEL or
VEN
TA
Ambient temperature
NOM
MAX
UNIT
1.08
5.5
V
Signal path input/output voltage (source or drain pin) (Sx, D)
0
VDD
V
Logic control input pin voltage
0
5.5
V
–40
125
°C
6.4 Thermal Information
TMUX1104
THERMAL METRIC
(1)
DGS (VSSOP)
DQA (USON)
10 PINS
10 PINS
UNIT
193.9
173.0
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
83.1
99.7
°C/W
RθJB
Junction-to-board thermal resistance
116.5
73.5
°C/W
ΨJT
Junction-to-top characterization parameter
22.0
8.9
°C/W
ΨJB
Junction-to-board characterization parameter
114.6
73.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SCDS392B – NOVEMBER 2018 – REVISED JULY 2019
6.5 Electrical Characteristics (VDD = 5 V ±10 %)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
RON
On-resistance matching between
channels
On-resistance flatness
FLAT
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
ID(ON)
IS(ON)
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
4
Ω
–40°C to +85°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-Leakage Current
25°C
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-Leakage Current
25°C
VDD = 5 V
Switch On
VD = VS = 2.5 V
Refer to On-Leakage Current
25°C
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1.5 V
Refer to On-Leakage Current
25°C
2
4.5
Ω
–40°C to +125°C
4.9
Ω
0.13
Ω
–40°C to +85°C
0.4
Ω
–40°C to +125°C
0.5
Ω
0.85
Ω
–40°C to +85°C
1.6
Ω
–40°C to +125°C
1.6
Ω
0.08
nA
–40°C to +85°C
–0.08
–0.3
0.3
nA
–40°C to +125°C
–0.9
0.9
nA
–0.1
±0.005
0.1
nA
–40°C to +85°C
–0.75
0.75
nA
–40°C to +125°C
–3.5
3.5
nA
0.025
nA
–0.025
±0.01
±0.003
–40°C to +85°C
–0.3
0.3
nA
–40°C to +125°C
–0.95
0.95
nA
0.1
nA
–40°C to +85°C
–0.75
–0.1
±0.01
0.75
nA
–40°C to +125°C
–3.5
3.5
nA
LOGIC INPUTS (EN, A0, A1)
VIH
Input logic high
–40°C to +125°C
1.49
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.87
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.005
µA
1
µA
When VS is 4.5 V, VD is 1.5 V, and vice versa.
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Electrical Characteristics (VDD = 5 V ±10 %) (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
Enable turn-on time
tOFF(EN) Enable turn-off time
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
14
–40°C to +85°C
–40°C to +125°C
ns
18
ns
19
ns
8
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
12
ns
–40°C to +85°C
17
ns
–40°C to +125°C
18
ns
5
ns
–40°C to +85°C
8
ns
–40°C to +125°C
9
ns
VS = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
1.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–45
dB
155
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
CSOFF
Source off capacitance
f = 1 MHz
25°C
6
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
28
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
35
pF
6
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6.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
3.7
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
RON
On-resistance matching between
channels
On-resistance flatness
FLAT
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
8.8
Ω
–40°C to +85°C
9.5
Ω
–40°C to +125°C
9.8
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
Refer to Off-Leakage Current
25°C
0.13
Ω
–40°C to +85°C
0.4
Ω
–40°C to +125°C
0.5
Ω
–40°C to +85°C
–40°C to +125°C
Ω
2
Ω
2.2
Ω
0.05
nA
–40°C to +85°C
–0.1
0.1
nA
–40°C to +125°C
–0.5
0.5
nA
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
Refer to Off-Leakage Current
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.5
0.5
nA
–2
2
nA
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
Refer to On-Leakage Current
25°C
–0.1
0.1
nA
–40°C to +85°C
–40°C to +125°C
–0.05
1.9
±0.001
±0.005
±0.005
–0.5
0.5
nA
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (EN, A0, A1)
VIH
Input logic high
–40°C to +125°C
1.35
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.8
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.005
µA
1
µA
When VS is 3 V, VD is 1 V, and vice versa.
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Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
Enable turn-on time
tOFF(EN) Enable turn-off time
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
15
–40°C to +85°C
–40°C to +125°C
ns
21
ns
22
ns
9
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
14
ns
–40°C to +85°C
21
ns
–40°C to +125°C
21
ns
7
ns
–40°C to +85°C
9
ns
–40°C to +125°C
10
ns
VS = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
–1.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–45
dB
155
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
CSOFF
Source off capacitance
f = 1 MHz
25°C
6
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
28
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
35
pF
8
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6.7 Electrical Characteristics (VDD = 1.8 V ±10 %)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
On-resistance matching between
channels
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-Leakage Current
25°C
40
Ω
–40°C to +85°C
80
Ω
–40°C to +125°C
80
Ω
0.4
Ω
–40°C to +85°C
1.5
Ω
–40°C to +125°C
1.5
Ω
0.05
nA
–40°C to +85°C
–0.1
0.1
nA
–40°C to +125°C
–0.5
0.5
nA
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-Leakage Current
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.5
0.5
nA
–2
2
nA
VDD = 1.98 V
Switch On
VD = VS = 1.62 V / 1 V
Refer to On-Leakage Current
25°C
–0.1
0.1
nA
–40°C to +85°C
–40°C to +125°C
–0.05
±0.003
±0.005
±0.005
–0.5
0.5
nA
–40°C to +125°C
–2
2
nA
LOGIC INPUTS (EN, A0, A1)
VIH
Input logic high
–40°C to +125°C
1.07
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.68
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.001
µA
0.85
µA
When VS is 1.62 V, VD is 1 V, and vice versa.
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Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
Enable turn-on time
tOFF(EN) Enable turn-off time
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
28
–40°C to +85°C
–40°C to +125°C
ns
44
ns
44
ns
16
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
25
ns
–40°C to +85°C
41
ns
–40°C to +125°C
41
ns
13
ns
–40°C to +85°C
23
ns
–40°C to +125°C
23
ns
VS = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
–0.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–45
dB
140
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
CSOFF
Source off capacitance
f = 1 MHz
25°C
6
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
28
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
35
pF
10
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6.8 Electrical Characteristics (VDD = 1.2 V ±10 %)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
On-resistance matching between
channels
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
25°C
Source off leakage current (1)
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-Leakage Current
On-resistance
ΔRON
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
Drain off leakage current (1)
Channel on leakage current
70
–40°C to +85°C
–40°C to +125°C
Ω
105
Ω
105
Ω
0.4
–40°C to +85°C
Ω
1.5
–40°C to +125°C
–0.05
±0.003
Ω
1.5
Ω
0.05
nA
–40°C to +85°C
–0.1
0.1
nA
–40°C to +125°C
–0.5
0.5
nA
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-Leakage Current
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.5
0.5
nA
–2
2
nA
VDD = 1.32 V
Switch On
VD = VS = 1 V / 0.8 V
Refer to On-Leakage Current
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.5
0.5
nA
–40°C to +125°C
–2
2
nA
–40°C to +125°C
±0.005
±0.005
LOGIC INPUTS (EN, A0, A1)
VIH
Input logic high
–40°C to +125°C
0.96
5.5
V
VIL
Input logic low
–40°C to +125°C
0
0.36
V
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
25°C
CIN
Logic input capacitance
–40°C to +125°C
±0.005
µA
±0.05
1
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.001
µA
0.7
µA
When VS is 1 V, VD is 0.8 V, and vice versa.
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Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
tOFF(EN) Enable turn-off time
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
QC
VS = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
–0.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–45
dB
MHz
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
OISO
XTALK
Enable turn-on time
Charge Injection
Off Isolation
Crosstalk
55
ns
–40°C to +85°C
190
ns
–40°C to +125°C
190
ns
28
–40°C to +85°C
1
–40°C to +125°C
1
ns
ns
ns
50
–40°C to +85°C
–40°C to +125°C
ns
175
ns
175
ns
35
ns
–40°C to +85°C
135
ns
–40°C to +125°C
135
ns
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
125
CSOFF
Source off capacitance
f = 1 MHz
25°C
7
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
32
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
40
pF
12
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6.9 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
5
6
VDD = 3 V
4.5
5
4
4
VDD = 4.5 V
3
3.5
On Resistance (:)
On Resistance (:)
VDD = 3.63 V
VDD = 5.5 V
2
TA = 85qC
TA = 125qC
TA = -40qC
TA = 25qC
3
2.5
2
1.5
1
1
0.5
0
0
0
1
2
3
4
VS or VD - Source or Drain Voltage (V)
5
5.5
0
1
2
3
4
VS or VD - Source or Drain Voltage (V)
D001
TA = 25°C
Figure 2. On-Resistance vs Temperature
8
80
7
VDD = 1.08 V
70
TA = 85qC TA = 125qC
60
On Resistance (:)
6
On Resistance (:)
D002
VDD = 5 V
Figure 1. On-Resistance vs Source or Drain Voltage
5
4
3
2
VDD = 1.32 V
50
40
VDD = 1.62 V
30
20
1
TA = -40qC
VDD = 1.98 V
10
TA = 25qC
0
0
0
0.5
1
1.5
2
2.5
3
VS or VD - Source or Drain Voltage (V)
3.5
0
0.2
D003
VDD = 3.3 V
0.4 0.6 0.8
1
1.2 1.4 1.6
VS or VD - Source or Drain Voltage (V)
1.8
2
D004
TA = 25°C
Figure 3. On-Resistance vs Temperature
Figure 4. On-Resistance vs Source or Drain Voltage
40
400
30
300
20
200
VDD = 1.32 V
VDD = 1.98 V
VDD = 3.63 V
On-Leakage (pA)
On-Leakage (pA)
5
10
0
-10
100
0
-100
-20
-200
-30
-300
-40
-400
0
0.5
1
1.5
2
2.5
3
VS or VD - Source or Drain Voltage (V)
3.5
4
0
1
2
3
4
VS or VD - Source or Drain Voltage (V)
D005
TA = 25°C
5
D006
VDD = 5 V
Figure 5. On-Leakage vs Source or Drain Voltage
Figure 6. On-Leakage vs Source or Drain Voltage
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1
3.5
0.75
2.5
0.5
Leakage Current (nA)
Leakage Current (nA)
Typical Characteristics (continued)
IS(OFF)
0.25
0
-0.25
ID(OFF)
-0.5
-20
0
20
40
60
Temperature (qC)
80
IS(OFF)
0.5
-0.5
ID(OFF)
-1.5
I(ON)
I(ON)
-2.5
-0.75
-1
-40
1.5
100
-3.5
-40
120
-20
0
20
40
60
Temperature (qC)
D007
VDD = 3.3 V
80
100
120
D008
VDD = 5 V
Figure 7. Leakage Current vs Temperature
Figure 8. Leakage Current vs Temperature
0.4
1400
VDD = 5 V
1200
Supply Current (PA)
Supply Current (PA)
0.3
VDD = 3.3 V
0.2
VDD = 1.8 V
0.1
1000
800
600
VDD = 3.3 V
VDD = 5 V
400
0
200
VDD = 1.2 V
-0.1
-40
0
-20
0
20
40
60
80
Temperature (qC)
100
120
140
0
0.5
1
D009
VSEL = 5.5 V
1.5
2
2.5
3
3.5
Logic Voltage (V)
4
4.5
5
D010
TA = 25°C
Figure 9. Supply Current vs Temperature
Figure 10. Supply Current vs Logic Voltage
20
5
15
Charge Injection (pC)
Charge Injection (pC)
3
10
VDD = 5 V
5
0
-5
-10
VDD = 1.2 V
1
-1
VDD = 1.8 V
-3
VDD = 3.3 V
-15
-20
-5
0
1
2
3
VS - Source Voltage (V)
4
5
0
0.5
D011
TA = -40°C to 125°C
2
D012
TA = -40°C to 125°C
Figure 11. Charge Injection vs Source Voltage
14
1
1.5
VS - Source Voltage (V)
Figure 12. Charge Injection vs Source Voltage
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Typical Characteristics (continued)
30
20
27
16
24
TON(EN)
18
Time (ns)
Time (ns)
21
TON(EN)
15
12
8
TOFF(EN)
12
9
4
TOFF(EN)
6
3
1.5
2
2.5
3
3.5
4
4.5
VDD - Supply Voltage (V)
5
0
-60
5.5
-30
0
30
60
Temperature (qC)
D013
TA = 25°C
90
120
150
D014
VDD = 5 V
Figure 13. TON (EN) and TOFF (EN) vs Supply Voltage
Figure 14. TON (EN) and TOFF (EN) vs Temperature
0
30
-10
25
-20
Magnitude (dB)
Time (ns)
20
RISING
15
10
-30
-40
-50
-60
FALLING
-70
5
0
0.5
-80
1.5
2.5
3.5
VDD - Supply Voltage (V)
4.5
-90
100k
5.5
1M
D015
10M
Frequency (Hz)
100M
D016
TA = 25°C
TA = 25°C
Figure 16. Xtalk and Off-Isolation vs Frequency
Figure 15. Output TTRANSITION vs Supply Voltage
0
-1
Gain (dB)
-2
-3
-4
-5
-6
1M
10M
Frequency (Hz)
100M
D017
TA = 25°C
Figure 17. On Response vs Frequency
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in Figure 18. Voltage (V) and current (ISD) are measured
using this setup, and RON is computed with RON = V / ISD:
V
ISD
Sx
D
VS
Figure 18. On-Resistance Measurement Setup
7.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 19.
Is (OFF)
VDD
VDD
VDD
VDD
S1
S1
A
ID (OFF)
S2
S2
VS
D
D
S3
A
S3
S4
S4
VS
VD
VD
GND
GND
Figure 19. Off-Leakage Measurement Setup
16
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON).
Either the source pin or drain pin is left floating during the measurement. Figure 20 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).
VDD
VDD
VDD
S1
N.C.
VDD
IS (ON)
S1
A
ID (ON)
S2
S2
D
S3
D
A
N.C.
S4
S8
Vs
VS
VS
VD
GND
GND
Figure 20. On-Leakage Measurement Setup
7.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device. System level timing can then account for the time constant added from the load resistance and load
capacitance. Figure 21 shows the setup used to measure transition time, denoted by the symbol tTRANSITION.
VDD
0.1…F
VDD
VDD
ADDRESS
DRIVE
(VSEL)
S1
tf < 5ns
tr < 5ns
VS
VIH
VIL
S2
0V
D
OUTPUT
S3
RL
S4
CL
tTRANSITION
tTRANSITION
A0
90%
A1
OUTPUT
VSEL
10%
GND
0V
Figure 21. Transition-Time Measurement Setup
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7.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 22 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM).
VDD
0.1…F
VDD
VDD
VS
ADDRESS
DRIVE
(VSEL)
tr < 5ns
S2
tf < 5ns
D
OUTPUT
S3
0V
RL
S4
CL
90%
Output
tBBM 1
A0
tBBM 2
0V
A1
VSEL
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
GND
Figure 22. Break-Before-Make Delay Measurement Setup
7.6 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. Figure 23
shows the setup used to measure turn-on time, denoted by the symbol tON(EN).
Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. Figure 23
shows the setup used to measure turn-off time, denoted by the symbol tOFF(EN).
VDD
0.1…F
VDD
VDD
ENABLE
DRIVE
(VEN)
tf < 5ns
tr < 5ns
VS
VIH
S2
VIL
D
OUTPUT
S3
0V
RL
S4
CL
tOFF (EN)
tON (EN)
EN
A0
90%
A1
OUTPUT
VEN
10%
GND
0V
Figure 23. Turn-On and Turn-Off Time Measurement Setup
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7.7 Charge Injection
The TMUX1104 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted
by the symbol QC. Figure 24 shows the setup used to measure charge injection from source (Sx) to drain (D).
VDD
0.1…F
VDD
VDD
VS
VEN
S2
OUTPUT
D
0V
S3
CL
S4
Output
VOUT
VOUT
VS
QC = CL ×
VOUT
A0
EN
A1
VEN
GND
Figure 24. Charge-Injection Measurement Setup
7.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. Figure 25 shows the setup used to measure, and the equation used to
calculate off isolation.
0.1µF
NETWORK
VDD
VS
ANALYZER
50Q
S
VSIG
D
VOUT
RL
50Q
SX
GND
RL
50Q
Figure 25. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(1)
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7.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. Figure 26 shows the setup used to measure, and the equation used to
calculate crosstalk.
0.1µF
NETWORK
VDD
ANALYZER
S1
VOUT
RL
D
50Q
VS
RL
S2
50Q
50Q
VSIG
SX
RL
GND
50Q
Figure 26. Crosstalk Measurement Setup
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
Channel-to-Channel Crosstalk
(2)
7.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure 27
shows the setup used to measure bandwidth.
0.1µF
NETWORK
VDD
VS
ANALYZER
50Q
S
VSIG
D
VOUT
RL
SX
50Q
GND
RL
50Q
Figure 27. Bandwidth Measurement Setup
20
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8 Detailed Description
8.1 Functional Block Diagram
The TMUX1104 is an 4:1, 1-channel (single-ended) multiplexer or demultiplexer. Each input is turned on or
turned off based on the state of the address lines and enable pin.
TMUX1104
S1
S2
D1
S3
S4
1-of-4
Decoder
EN
A1
A0
Figure 28. TMUX1104 Functional Block Diagram
8.2 Feature Description
8.2.1 Bidirectional Operation
The TMUX1104 conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
8.2.2 Rail to Rail Operation
The valid signal path input/output voltage for TMUX1104 ranges from GND to VDD.
8.2.3 1.8 V Logic Compatible Inputs
The TMUX1104 has 1.8-V logic compatible control for all logic control inputs. The logic input thresholds scale
with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level inputs
allows the TMUX1104 to interface with processors that have lower logic I/O rails and eliminates the need for an
external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches
8.2.4 Fail-Safe Logic
The TMUX1104 supports Fail-Safe Logic on the control input pins (EN, A0, A1) allowing for operation up to 5.5
V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before
the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by
removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX1104 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX1104 with VDD = 1.2 V while allowing the select pins to interface with a logic level
of another device up to 5.5 V.
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Feature Description (continued)
8.2.5 Ultra-low Leakage Current
The TMUX1104 provides extremely low on-leakage and off-leakage currents. The TMUX1104 is capable of
switching signals from high source-impedance inputs into a high input-impedance op amp with minimal offset
error because of the ultra-low leakage currents. Figure 29 shows typical leakage currents of the TMUX1104
versus temperature.
3.5
Leakage Current (nA)
2.5
1.5
IS(OFF)
0.5
-0.5
ID(OFF)
-1.5
I(ON)
-2.5
-3.5
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
D008
Figure 29. Leakage Current vs Temperature
8.2.6 Ultra-low Charge Injection
The TMUX1104 has a transmission gate topology, as shown in Figure 30. Any mismatch in the stray capacitance
associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
Figure 30. Transmission Gate Topology
22
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Feature Description (continued)
The TMUX1104 has special charge-injection cancellation circuitry that reduces the source-to-drain charge
injection to 1.5 pC at VS = 1 V as shown in Figure 31.
20
Charge Injection (pC)
15
10
VDD = 5 V
5
0
-5
-10
VDD = 3.3 V
-15
-20
0
1
2
3
VS - Source Voltage (V)
4
5
D011
Figure 31. Charge Injection vs Source Voltage
8.3 Device Functional Modes
When the EN pin of the TMUX1104 is pulled high, one of the switches is closed based on the state of the
address lines. When the EN pin is pulled low, all the switches are in an open state regardless of the state of the
address lines. The control pins can be as high as 5.5 V.
8.4 Truth Tables
Table 1 show the truth tables for the TMUX1104.
Table 1. TMUX1104 Truth Table
EN
A1
A0
Selected Input Connected To Drain (D) Pin
0
X (1)
X (1)
All channels are off
1
0
0
S1
1
0
1
S2
1
1
0
S3
1
1
1
S4
(1)
X denotes don't care.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMUX11xx family offers ulta-low input/output leakage currents and low charge injection. These devices
operate up to 5.5 V, and offer true rail-to-rail input and output of both analog and digital signals. The TMUX1104
has a low on-capacitance which allows faster settling time when multiplexing inputs in the time domain. These
features make the TMUX11xx devices a family of precision, high-performance switches and multiplexers for lowvoltage applications.
9.2 Typical Application
Figure 32 shows a 16-bit, 4 input, multiplexed, data-acquisition system. This example is typical in industrial
applications that require low distortion for precision measurements. The circuit uses the ADS8864, a 16-bit, 400kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a precision
amplifier, and a 4 input mux.
VDD
Bridge Sensor
VDD
EN
S1
3.3V
+
REF
OPA333
-
S2
Thermocouple
D
...
S3
+
OPA333
Gain / Filter
Network
ADS8864
S4
Current
Sensing
GND
Photo
LED Detector
Optical Sensor
A0
A1
1.8V Logic
Signals
TMUX1104
Analog Inputs
Figure 32. Multiplexing Signals to External ADC
9.3 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
PARAMETERS
24
VALUES
Supply (VDD)
3.3 V
I/O signal range
0 V to VDD (Rail to Rail)
Control logic thresholds
1.8 V compatible
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9.4 Detailed Design Procedure
The TMUX1104 can be operated without any external components except for the supply decoupling capacitors. If
the desired power-up state is disabled, the enable pin should have a weak pull-down resistor and be controlled
by the MCU via GPIO. All inputs being muxed to the ADC must fall within the recommend operating conditions of
the TMUX1104, including signal range and continuous current. For this design with a supply of 3.3V the signal
range can be 0 V to 3.3 V, and the max continuous current can be 30 mA.
The design example highlights a multiplexed data-acquisition system for highest system linearity and fast settling.
The overall system block diagram is illustrated in Figure 32. The circuit is a multichannel data-acquisition signal
chain consisting of an input low-pass filter, mux, mux output buffer, SAR ADC driver, and a reference buffer. The
architecture provides a cost-effective solution for fast sampling of multiple channels using a single ADC.
9.5 Application Curve
The TMUX1104 is capable of switching signals from high source-impedance inputs into a high input-impedance
op amp with minimal offset error because of the ultra-low leakage currents.
40
30
On-Leakage (pA)
20
VDD = 1.32 V
VDD = 1.98 V
VDD = 3.63 V
10
0
-10
-20
-30
-40
0
0.5
1
1.5
2
2.5
3
VS or VD - Source or Drain Voltage (V)
3.5
4
D005
TA = 25°C
Figure 33. On-Leakage vs Source or Drain Voltage
10 Power Supply Recommendations
The TMUX1104 operates across a wide supply range of 1.08 V to 5.5 V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply to
other components. Good power-supply decoupling is important to achieve optimum performance. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to ground.
Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes.
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11 Layout
11.1 Layout Guidelines
11.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners.Figure 34 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
BETTER
BEST
2W
WORST
1W min.
W
Figure 34. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, throughhole pins are not recommended at high frequencies.
Figure 35 illustrates an example of a PCB layout with the TMUX1104. Some key considerations are:
•
•
•
•
Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
A0
A1
TMUX1104
S1
S2
GND
D
S3
S4
EN
VDD
Via to
GND plane
C
Wide (low inductance)
trace for power
Figure 35. TMUX1104 Layout Example
26
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit.
Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.
Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX1104DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1D7
TMUX1104DQAR
ACTIVE
USON
DQA
10
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
104
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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