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TPA2005D1-Q1
SLOS474E – AUGUST 2005 – REVISED MARCH 2016
TPA2005D1-Q1 1.4-W Mono Filter-Free Class-D Audio Power Amplifier
1 Features
•
•
1
•
•
•
•
– 3 mm × 3 mm SON package (DRB)
– 3 mm × 5 mm MSOP-PowerPAD™ Package
(DGN)
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 3 (DRB and DGN
package non T-suffix): –40°C to +85°C
Ambient Operating Temperature Range
– Device Temperature Grade 2 (DGN package
T-suffix): –40°C to +105°C Ambient Operating
Temperature Range
– Device HBM Classification Level 2
– Device CDM Classification Level C5
1.4 W Into 8 Ω From a 5-V Supply at
THD = 10% (Typical)
Maximum Battery Life and Minimum Heat
– Efficiency With an 8-Ω Speaker:
– 84% at 400 mW
– 79% at 100 mW
– 2.8-mA Quiescent Current
– 0.5-μA Shutdown Current
Only Three External Components
– Optimized PWM Output Stage Eliminates LC
Output Filter
– Internally Generated 250-kHz Switching
Frequency Eliminates Capacitor and Resistor
– Improved PSRR (–71 dB at 217 Hz) and Wide
Supply Voltage (2.5 V to 5.5 V) Eliminates
Need for a Voltage Regulator
– Fully Differential Design Reduces RF
Rectification and Eliminates Bypass Capacitor
– Improved CMRR Eliminates Two Input
Coupling Capacitors
Space-Saving Packages
2 Applications
•
•
•
•
•
Cluster
Head Unit
Telematics
Emergency Call (eCall)
Noise Generator
3 Description
The TPA2005D1-Q1 device is a 1.4-W high-efficiency
filter-free class-D audio power amplifier in a SON or
MSOP-PowerPAD package that requires only three
external components.
Features like 84% efficiency, –71-dB PSRR at
217 Hz, improved RF-rectification immunity, and 15mm2 total PCB area make TPA2005D1-Q1 ideal for
low-power audio applications in infotainment and
cluster.
The device allows for independent gain control by
summing the signals from each function while
minimizing noise to only 48 µVRMS. Additionally, the
TPA2005D1-Q1 device offers fast start-up time of 9
ms with minimal pop and has short circuit and
thermal protection.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
MSOP-PowerPAD (8) 3.00 mm × 3.00 mm
TPA2005D1-Q1
SON (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Application Circuit
To Battery
Internal
Oscillator
+
RI
–
RI
CS
IN–
_
Differential
Input
VDD
PWM
VO+
H–
Bridge
VO–
+
IN+
GND
SHUTDOWN
Bias
Circuitry
TPA2005D1
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA2005D1-Q1
SLOS474E – AUGUST 2005 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 16
10 Application and Implementation........................ 19
10.1 Application Information.......................................... 19
10.2 Typical Application ................................................ 19
11 Power Supply Recommendations ..................... 22
11.1 Power Supply Decoupling Capacitors................... 22
12 Layout................................................................... 23
12.1 Layout Guidelines ................................................. 23
12.2 Layout Example .................................................... 24
13 Device and Documentation Support ................. 25
13.1
13.2
13.3
13.4
13.5
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
14 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2015) to Revision E
•
Page
Changed the θJA value and resulting value maximum ambient-temperature equation in the Efficiency and Thermal
Information section ............................................................................................................................................................... 13
Changes from Revision C (March 2010) to Revision D
Page
•
Added Applications, ESD Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1
•
Deleted Ordering Information table. See POA in the back of document. .............................................................................. 1
•
Added RL Load resistance, to the Abs Max Ratings Table .................................................................................................... 4
•
Changed Storage temperature From: -65°C to 85°C To: -65°C to 150°C ............................................................................. 4
•
Deleted Dissipation Ratings table and added Thermal Information table. ............................................................................ 4
•
Updated Efficiency and Thermal Information ...................................................................................................................... 13
2
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SLOS474E – AUGUST 2005 – REVISED MARCH 2016
5 Device Comparison Table
DEVICE
NUMBER
SPEAKER
CHANNELS
SPEAKER AMP
TYPE
OUTPUT POWER
(W)
PSRR (dB)
SUPPLY MIN (V)
SUPPLY MAX (V)
TPA2005D1-Q1
Mono
Class D
1.4
75
2.5
5.5
TPA2000D1-Q1
Mono
Class D
2
77
2.7
5.5
6 Pin Configuration and Functions
DRB Package
8-Pin SON With Exposed Thermal Pad
Top View
DGN Package
8-Pin MSOP-PowerPAD
Top View
SHUTDOWN
1
8
V
NC
2
7
GND
IN+
3
6
V
IN–
4
5
V
SHUTDOWN
1
NC
2
Thermal
Pad
8
V
7
GND
6
V
5
V
O–
DD
O–
Thermal
IN+
3
IN–
4
Pad
DD
O+
O+
The thermal pad of the DRB and DGN
packages must be electrically and thermally
connected to a ground plane.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
IN–
4
I
Negative differential input
IN+
3
I
Positive differential input
VDD
6
I
Power supply
VO+
5
O
Positive BTL output
GND
7
I
High-current ground
VO–
8
O
Negative BTL output
SHUTDOWN
1
I
Shutdown terminal (active low logic)
NC
2
—
No internal connection
—
Must be soldered to a grounded pad on the PCB.
Thermal Pad
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VDD
Supply voltage (2)
VI
Input voltage
RL
MIN
MAX
UNIT
In active mode
–0.3
6
V
In SHUTDOWN mode
–0.3
7
V
–0.3
VDD + 0.3 V
2.5 ≤ VDD ≤ 4.2 V
Load resistance
V
Ω
3.2
4.2 < VDD ≤ 6 V
6.4
Non T-suffix
–40
85
Ω
T-suffix
–40
105
TA
Operating free-air
temperature
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For the MSOP (DGN) package option, the maximum VDD should be limited to 5 V if short-circuit protection is desired.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
MAX
2.5
5.5
V
SHUTDOWN
2
VDD
V
Low-level input voltage
SHUTDOWN
0
0.7
V
RI
Input resistor
Gain ≤ 20 V/V (26 dB)
15
VIC
Common-mode input voltage
VDD = 2.5 V, 5.5 V, CMRR ≤ –49 dB
0.5
VDD – 0.8
Non T-suffix
–40
85
T-suffix
–40
105
VDD
Supply voltage
VIH
High-level input voltage
VIL
TA
Operating free-air temperature
UNIT
kΩ
V
°C
7.4 Thermal Information
TPA2005D1-Q1
THERMAL METRIC (1)
DRB (SON)
DGN
(MSOP
PowerPAD)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
49.5
57
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
62.1
53.8
°C/W
RθJB
Junction-to-board thermal resistance
24.8
33.7
°C/W
ψJT
Junction-to-top characterization parameter
1.3
1.9
°C/W
ψJB
Junction-to-board characterization parameter
24.9
33.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.9
6.4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLOS474E – AUGUST 2005 – REVISED MARCH 2016
7.5 Electrical Characteristics
TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
|VOS|
Output offset voltage (measured
differentially)
VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V
PSRR
Power-supply rejection ratio
VDD = 2.5 V to 5.5 V
CMRR
Common-mode rejection ratio
VDD = 2.5 V to 5.5 V,
VIC = VDD / 2 to 0.5 V,
VIC = VDD / 2 to VDD – 0.8 V
|IIH|
High-level input current
VDD = 5.5 V, VI = 5.8 V
|IIL|
Low-level input current
I(Q)
Quiescent current
I(SD)
Shutdown current
rDS(on)
Static drain-source on-state
resistance
f(sw)
MIN
TYP
TA = 25°C
MAX
25
mV
–75
–55
dB
–68
–49
TA = –40°C to 85°C
–35
50
VDD = 5.5 V, VI = 0.3 V
TA = –40°C to 85°C
4
TA = –40°C to 105°C
12
VDD = 5.5 V, no load
3.4
VDD = 3.6 V, no load
2.8
VDD = 2.5 V, no load
2.2
3.2
0.5
2
TA = –40°C to 85°C
V (SHUTDOWN) = 0.8 V,
VDD = 2.5 V to 5.5 V
770
590
VDD = 5.5 V
500
V (SHUTDOWN) = 0.8 V
Switching frequency
VDD = 2.5 V to 5.5 V
Gain
2´
μA
μA
mΩ
>1
200
μA
mA
2.5
VDD = 3.6 V
dB
4.5
TA = –40°C to 105°C
VDD = 2.5 V
Output impedance in SHUTDOWN
UNIT
kΩ
250
300
142 kW
150 kW
158 kW
2´
2´
RI
RI
RI
kHz
V
V
7.6 Operating Characteristics
TA = 25°C, Gain = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
THD + N= 1%, f = 1 kHz,
RL = 8 Ω
PO
Output power
THD + N= 10%, f = 1 kHz,
RL = 8 Ω
MIN
1.18
VDD = 3.6 V
0.58
VDD = 2.5 V
0.26
VDD = 5 V
1.45
VDD = 3.6 V
0.75
VDD = 2.5 V
THD+N
Total harmonic distortion plus noise
TYP
VDD = 5 V
MAX
UNIT
W
0.35
PO = 1 W, f = 1 kHz, RL = 8 Ω
VDD = 5 V
0.18%
PO = 0.5 W, f = 1 kHz, RL = 8 Ω
VDD = 3.6 V
0.19%
PO = 200 mW, f = 1 kHz, RL = 8 Ω
VDD = 2.5 V
0.20%
VDD = 3.6 V
–71
dB
dB
kSVR
Supply ripple rejection ratio
f = 217 Hz, V(RIPPLE) = 200 mVpp,
Inputs ac-grounded with Ci = 2 μF
SNR
Signal-to-noise ratio
PO= 1 W, RL = 8 Ω
VDD = 5 V
97
48
A weighting
36
Vn
Output voltage noise
VDD = 3.6 V, f = 20 Hz to 20 kHz,
Inputs ac-grounded with Ci = 2 μF
No weighting
CMRR
Common-mode rejection ratio
VIC = 1 Vpp , f = 217 Hz
VDD = 3.6 V
ZI
Input impedance
Start-up time from shutdown
–63
142
VDD = 3.6 V
μVRMS
150
dB
158
9
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ms
5
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7.7 Typical Characteristics
100
90
RL = 32 W, 33 mH
90
80
RL = 8 W, 33 mH
RL = 16 W, 33 mH
60
Efficiency - %
Efficiency - %
70
50
40
30
Class-AB,
RL = 8 Ω
20
VDD = 5 V,
80
10
RL = 8W, 33mH
70
VDD = 2.5 V,
60
RL = 8W, 33mH
50
40
Class-AB,
VDD = 5 V,
RL = 8 W
30
20
10
VDD = 3.6
0
0
0
0.1
0.2
0.3
0.4
0.5
0
0.6
0.2
0.4
0.6
0.8
1
1.2
PO - Output Power - W
PO - Output Power - W
Figure 2. Efficiency vs Output Power
Figure 1. Efficiency vs Output Power
90
0.7
Class-AB, V DD = 5 V, RL = 8 W
80
0.6
70
60
PD - Power Dissipation - W
Efficiency - %
VDD = 4.2 V,
RL = 4 W, 33 mH
50
40
30
20
10
Class-AB,
VDD = 3.6 V,
RL = 8 W
0.5
0.4
0.5
1
1.5
RL = 4 W, 33 mH
0.3
VDD = 3.6 V,
RL = 8 W, 33 mH
0.2
0.1
VDD = 5 V,
RL = 8 W, 33 mH
0
0
0
VDD = 4.2 V,
0
0.2
0.4
0.6
0.8
1
1.2
PO - Output Power - W
PO - Output Power - W
Figure 4. Power Dissipation vs Output Power
Figure 3. Efficiency vs Output Power
250
300
VDD = 3.6 V
250
Supply Current - mA
Supply Current - mA
200
RL = 8 W, 33 mH
150
100
50
150
VDD = 5 V,
RL = 8 W, 33 mH
100
VDD = 3.6 V,
RL = 8 W, 33 mH
50
RL = 32 W, 33 mH
0
0
0.1
0.2
0.3
0.4
PO - Output Power - W
VDD = 2.5 V,
RL = 8 W, 33 mH
0
0.5
0.6
0
0.2
0.4
0.6
0.8
1
1.2
PO - Output Power - W
Figure 5. Supply Current vs Output Power
6
200
Figure 6. Supply Current vs Output Power
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SLOS474E – AUGUST 2005 – REVISED MARCH 2016
3.8
1
3.6
0.9
I (SD) - Shutdown Current - m A
I (Q) − Quiescent Current − mA
Typical Characteristics (continued)
3.4
RL = 8 W, 33 mH
3.2
3
2.8
No Load
2.6
2.4
0.8
0.7
0.6
0.4
VDD = 3.6 V
0.3
VDD = 5 V
0.2
2.2
0.1
0
2
2.5
3
3.5
4
4.5
5
0
5.5
0.1
0.3
0.4
0.5
0.6
0.7
0.8
Shutdown Voltage - V
Figure 7. Quiescent Current vs Supply Voltage
Figure 8. Shutdown Current vs Shutdown Voltage
1.6
RL = 8 W
f = 1 kHz
Gain = 2 V/V
1.4
1.4
1.2
RL = 4 W,
f = 1kHz,
Gain = 2 V/V
1
PO - Output Power - W
1.2
THD+N = 10%
0.8
THD+N = 10%
1
0.8
0.6
THD+N = 1%
0.6
THD+N = 1%
0.4
0.4
0.2
0.2
0
2.5
3
3.5
4
4.5
0
2.5
5
3
VDD - Supply Voltage - V
3.5
4
4.5
VDD - Supply Voltage - V
Figure 9. Output Power vs Supply Voltage
Figure 10. Output Power vs Supply Voltage
1.8
1.4
f = 1 kHz,
THD+N = 1%,
Gain = 2 V/V
1
1.4
VDD = 3.6 V
VDD = 4.2 V
0.8
VDD = 5 V
0.6
f = 1 kHz,
THD+N = 10%,
Gain = 2 V/V
1.6
PO - Output Power - W
1.2
PO - Output Power - W
0.2
VDD − Supply Voltage − V
1.6
PO - Output Power - W
VDD = 2.5 V
0.5
0.4
VDD = 5 V
1.2
VDD = 4.2 V
1
VDD = 3.6 V
0.8
0.6
0.4
0.2
0.2
VDD = 2.5 V
0
VDD = 2.5 V
0
4
RL - Load Resistance - W
12
16
20
24
RL - Load Resistance - W
Figure 11. Output Power vs Load Resistance
Figure 12. Output Power vs Load Resistance
4
8
12
16
20
24
28
32
8
28
32
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THD+N − Total Harmonic Distortion + Noise − %
30
20
RL = 4 W,
f = 1 kHz,
Gain = 2 V/V
10
VDD = 2.5 V
5
VDD = 3.6 V
2
VDD = 4.2 V
1
0.5
0.2
0.1
0.01
0.1
1
2
THD+N − Total Harmonic Distortion + Noise − %
Figure 13. Total Harmonic Distortion + Noise vs Output
Power
30
20
RL = 16 W,
f = 1 kHz,
Gain = 2 V/V
10
5
2.5 V
2
3.6 V
1
5V
0.5
0.2
0.1
0.01
30
20
10
RL = 8 W,
f = 1 kHz,
Gain = 2 V/V
5
2.5 V
2
3.6 V
1
5V
0.5
0.2
0.1
0.01
0.1
0.1
1
2
10
VDD = 5 V
CI = 2 mF
RL = 8 W
Gain = 2 V/V
5
2
1
0.5
0.2
50 mW
0.1
1W
0.05
0.02
250 mW
0.008
20
100
10
VDD = 3.6 V
CI = 2 mF
RL = 8 W
Gain = 2 V/V
1
0.5
0.2
500 mW
25 mW
0.1
0.05
125 mW
0.02
0.01
20
100
1k
20 k
20 k
10
VDD = 2.5 V
CI = 2 mF
RL = 8 W
Gain = 2 V/V
5
2
1
15 mW
75 mW
0.5
0.2
0.1
200 mW
0.05
0.02
0.01
20
f − Frequency − Hz
100
1k
20 k
f − Frequency − Hz
Figure 17. Total Harmonic Distortion + Noise vs Frequency
8
1k
f − Frequency − Hz
Figure 16. Total Harmonic Distortion + Noise vs Frequency
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
Figure 15. Total Harmonic Distortion + Noise vs Output
Power
2
2
Figure 14. Total Harmonic Distortion + Noise vs Output
Power
PO − Output Power − W
5
1
PO − Output Power − W
PO - Output Power - W
THD+N − Total Harmonic Distortion + Noise − %
THD+N - Total Harmonic Distortion + Noise - %
Typical Characteristics (continued)
Figure 18. Total Harmonic Distortion + Noise vs Frequency
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10
VDD = 3.6 V
CI = 2 mF
RL = 16 W
Gain = 2 V/V
5
2
1
0.5
0.2
15 mW
0.1
75 mW
0.05
0.02
200 mW
0.01
20
100
1k
20 k
THD+N - Total Harmonic Distortion + Noise - %
THD+N − Total Harmonic Distortion + Noise − %
Typical Characteristics (continued)
10
5
VDD = 4.2 V,
2
R L = 4 W,
Gain = 2 V/V
500 mW
1
0.5
250 mW
1W
0.2
0.1
0.05
0.02
0.01
20
100
1k
f - Frequency - Hz
f − Frequency − Hz
5
VDD = 3.6 V,
2
R L = 4 W,
Gain = 2V/V
1
250 mW
0.5
775 mW
500 mW
0.2
0.1
0.05
0.02
0.01
20
100
1k
f-Frequency-Hz
20k
f = 1 kHz
PO = 200 mW
1
VDD = 2.5 V
VDD = 3.6 V
0.1
0
0.5
1
1.5
2
2.5
3
3.5
VIC - Common Mode Input Voltage - V
Figure 23. Total Harmonic Distortion + Noise vs
Common Mode Input Voltage
10
5
VDD = 2.5 V,
2
RL = 4 W,
Gain = 2V/V
75 mW
15 mW
1
0.5
200 mW
0.2
0.1
0.05
0.02
0.01
20
100
1k
f - Frequency - Hz
20k
Figure 22. Total Harmonic Distortion + Noise vs Frequency
10
k
THD+N - Total Harmonic Distortion + Noise - %
Figure 21. Total Harmonic Distortion + Noise vs Frequency
THD+N - Total Harmonic Distortion + Noise - %
10
Figure 20. Total Harmonic Distortion + Noise vs Frequency
− Supply Voltage Rejection Ratio − dB
SVR
THD+N - Total Harmonic Distortion + Noise - %
Figure 19. Total Harmonic Distortion + Noise vs Frequency
20k
0
CI = 2 mF
RL = 8 W
Vp-p = 200 mV
Inputs ac-Grounded
Gain = 2 V/V
−10
−20
−30
−40
VDD = 3.6 V
−50
VDD =2. 5 V
−60
−70
VDD = 5 V
−80
20
100
1k
f − Frequency − Hz
20 k
Figure 24. Supply Voltage Rejection Ratio vs Frequency
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− Supply Voltage Rejection Ratio − dB
SVR
0
Gain = 5 V/V
CI = 2 mF
RL = 8 W
Vp-p = 200 mV
Inputs ac-Grounded
−10
−20
−30
VDD = 2. 5 V
−40
−50
VDD = 5 V
−60
−70
VDD = 3.6 V
−80
k
k
− Supply Voltage Rejection Ratio − dB
SVR
Typical Characteristics (continued)
20
100
1k
f − Frequency − Hz
20 k
Figure 25. Supply Voltage Rejection Ratio vs Frequency 25
f = 217 Hz
RL = 8 W
Gain = 2 V/V
-10
-20
-30
-40
VDD = 2.5 V
-50
VDD = 3.6 V
-60
-70
-80
VDD = 5 V
-90
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIC - Common Mode Input Voltage - V
Figure 27. Supply Voltage Rejection Ratio vs
Common-Mode Input Voltage
−10
−20
−30
CI = 2 mF
RL = 8 W
Inputs Floating
Gain = 2 V/V
−40
−50
−60
VDD = 3.6 V
−70
−80
−90
−100
20
100
1k
f − Frequency − Hz
20 k
Figure 26. Supply Voltage Rejection Ratio vs Frequency
CMRR − Common Mode Rejection Ratio − dB
k
SVR
- Supply Voltage Rejection Ratio - dB
0
0
0
−10
−20
VDD = 2.5 V to 5 V
VIC = 1 Vp−p
RL = 8 W
Gain = 2 V/V
−30
−40
−50
−60
−70
20
100
1k
f − Frequency − Hz
20 k
Figure 28. Common-Mode Rejection Ratio vs Frequency
CMRR - Common Mode Rejection Ratio - dB
0
RL = 8W
Gain = 2 V/V
-10
-20
-30
-40
VDD = 2.5 V
VDD = 3.6 V
-50
-60
-70
-80
VDD = 5 V
-90
-100
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
VIC - Common Mode Input Voltage - V
5
Figure 29. Common-Mode Rejection Ratio vs
Common-Mode Input Voltage
10
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8 Parameter Measurement Information
TPA2005D1
CI
+
Measurement
Output
CI
±
RI
IN+
OUT+
Load
RI
IN±
OUT±
VDD
+
30 kHz
Low Pass
Filter
+
Measurement
Input
±
GND
1 mF
VDD
±
Copyright © 2016, Texas Instruments Incorporated
A.
CI was shorted for any common-mode input voltage measurement.
B.
A 33-μH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.
C.
The 30-kHz low-pass filter is required, even if the analyzer has a low-pass filter. An RC filter (100 Ω, 47 nF) is used
on each output for the data sheet graphs.
Figure 30. Test Setup For Graphs
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9 Detailed Description
9.1 Overview
The TPA2005D1-Q1 device is a high-efficiency filter-free Class-D audio amplifier capable of delivering up to 1.4
W into 8-Ω loads with a 5-V power supply. The fully-differential design of this amplifier avoids the usage of
bypass capacitors and the improved CMRR eliminates the usage of input-coupling capacitors. This makes the
device size a perfect choice for small, space constrained applications as only three external components are
required. The advanced modulation used in the TPA2005D1-Q1 PWM output stage eliminates the need for an
output filter.
9.2 Functional Block Diagram
Gain = 2 V/V
VDD
B4, C4
VDD
150 kW
IN− D1
_
+
+
_
Deglitch
Logic
Gate
Drive
+
_
Deglitch
Logic
Gate
Drive
A4
VO−
_
+
_
+
+
_
IN+ C1
150 kW
SHUTDOWN
A1
TTL
SD Input
Buffer
Biases
and
References
Ramp
Generator
Startup
& Thermal
Protection
Logic
D4
VO+
Short
Circuit
Detect
GND
Copyright © 2016, Texas Instruments Incorporated
9.3 Feature Description
9.3.1 Fully Differential Amplifier
The TPA2005D1-Q1 device is a fully differential amplifier with differential inputs and outputs. The fully differential
amplifier consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that
the amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The
common-mode feedback ensures that the common-mode voltage at the output is biased around VDD / 2,
regardless of the common-mode voltage at the input. The fully differential TPA2005D1-Q1 device can still be
used with a single-ended input; however, the TPA2005D1-Q1 device should be used with differential inputs when
in a noisy environment to ensure maximum noise rejection.
9.3.1.1 Advantages Of Fully Differential Amplifiers
Fully differential amplifiers have the following advantages:
• Input-coupling capacitors not required:
– The fully differential amplifier allows the inputs to be biased at a voltage other than mid-supply. For
example, if a codec has a mid-supply lower than the mid-supply of the TPA2005D1-Q1 device, the
common-mode feedback circuit adjusts, and the TPA2005D1-Q1 outputs still is biased at mid-supply of
the TPA2005D1-Q1 device. The inputs of the TPA2005D1-Q1 device can be biased from 0.5 V to VDD –
0.8 V. If the inputs are biased outside of that range, input-coupling capacitors are required.
• Mid-supply bypass capacitor, C(BYPASS), not required:
– The fully differential amplifier does not require a bypass capacitor. This is because any shift in the midsupply affects both positive and negative channels equally and cancels at the differential output.
12
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Feature Description (continued)
•
Better RF immunity:
– The fully differential amplifier cancels noise from RF interference much better than the typical audio
amplifier.
9.3.2 Efficiency and Thermal Information
As an example, the DRB package has a RθJA of 49.5°C/W, the maximum allowable junction temperature of
150°C, and a maximum internal dissipation of 0.2 W (worst case 5-V supply and 8-Ω load). Use Equation 1 to
calculate the maximum ambient temperature.
TAMax = TJMax – RθJAPDmax = 150 – 49.5(0.2) = 140.1°C
(1)
Equation 1 shows that the calculated maximum ambient temperature is 140.1°C at maximum power dissipation
with a 5-V supply; however, the maximum ambient temperature of the package is limited to 85°C (note that the
TPA2005D1TDGNRQ1 supports up to 105°C). Because of the efficiency of the TPA2005D1-Q1, it can operate
under all conditions to an ambient temperature of 85°C. The TPA2005D1-Q1 is designed with thermal protection
that turns the device off when the junction temperature surpasses 150°C to prevent damage to the IC. Also,
using speakers more resistive than 8 Ω dramatically increases the thermal performance by reducing the output
current and increasing the efficiency of the amplifier.
9.3.3 Eliminating the Output Filter With the TPA2005D1-Q1
This section focuses on why the user can eliminate the output filter with the TPA2005D1-Q1.
9.3.3.1 Effect On Audio
The class-D amplifier outputs a pulse-width modulated (PWM) square wave, which is the sum of the switching
waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the
frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are
much greater than 20 kHz, so the only signal heard is the amplified input audio signal.
9.3.3.2 Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme has a differential output in which each output is 180 degrees out of
phase and changes from ground to the supply voltage, VDD. Therefore, the differential pre-filtered output varies
between positive and negative VDD, where filtered 50% duty cycle yields 0 V across the load. The traditional
class-D modulation scheme with voltage and current waveforms is shown in Figure 31. Note that, even at an
average of 0 V across the load (50% duty cycle), the current to the load is high, causing a high loss and thus
causing a high supply current.
OUT+
OUT–
+5 V
Differential Voltage
Across Load
0V
–5 V
Current
Figure 31. Traditional Class-D Modulation Scheme Output Voltage and Current Waveforms Into an
Inductive Load With No Input
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Feature Description (continued)
9.3.3.3 TPA2005D1-Q1 Modulation Scheme
The TPA2005D1-Q1 device uses a modulation scheme that still has each output switching from 0 to the supply
voltage. However, OUT+ and OUT– are now in phase with each other, with no input. The duty cycle of OUT+ is
greater than 50% and OUT– is less than 50% for positive voltages. The duty cycle of OUT+ is less than 50% and
OUT– is greater than 50% for negative voltages. The voltage across the load remains at 0 V throughout most of
the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
OUT+
OUT–
Differential
Voltage
Across
Load
Output = 0 V
+5 V
0V
–5 V
Current
OUT+
OUT–
Differential
+5 V
Voltage
Across
0V
Load
Output > 0 V
–5 V
Current
Figure 32. TPA2005D1-Q1 Output Voltage and Current Waveforms Into an Inductive Load
9.3.3.4 Efficiency: Why You Must Use a Filter With The Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VDD, and the time at each voltage is one-half the period
for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half-cycle
for the next half-cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA2005D1-Q1 modulation scheme has very little loss in the load without a filter because the pulses are
very short and the change in voltage is VDD instead of 2 × VDD. As the output power increases, the pulses widen,
making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for
most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance than the speaker, resulting in less power
dissipation, which increases efficiency.
14
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Feature Description (continued)
9.3.3.5 Effects Of Applying a Square Wave Into a Speaker
If the amplitude of a square wave is high enough and the frequency of the square wave is within the bandwidth
of the speaker, a square wave could cause the voice coil to jump out of the air gap, scar the voice coil, or both. A
250-kHz switching frequency, however, is not significant because the speaker cone movement is proportional to
1/f2 for frequencies beyond the audio band. Therefore, the amount of cone movement at the switching frequency
is very small. However, damage could occur to the speaker if the voice coil is not designed to handle the
additional power. To size the speaker for added power, the ripple current dissipated in the load must be
calculated by subtracting the theoretical supplied power, PSUP THEORETICAL, from the actual supply power, PSUP, at
maximum output power, POUT. The switching power dissipated in the speaker is the inverse of the measured
efficiency, ηMEASURED, minus the theoretical efficiency, ηTHEORETICAL.
P
+P
–P
(at max output power)
SPKR
SUP SUP THEORETICAL
(2)
P
P
P
+ SUP – SUP THEORETICAL (at max output power)
SPKR
P
P
OUT
OUT
(3)
Ǔ
ǒ
1
1
(at max output power)
*
OUT h MEASURED h THEORETICAL
R
L
hTHEORETICAL +
(at max output power)
R ) 2r
L
DS(on)
P
SPKR
+P
(4)
(5)
The maximum efficiency of the TPA2005D1-Q1 device with a 3.6-V supply and an 8-Ω load is 86% from
Equation 5. Using Equation 4 with the efficiency at maximum power (84%). An additional 17 mW is dissipated in
the speaker. The added power dissipated in the speaker is not an issue as long as it is taken into account when
choosing the speaker.
9.3.3.6 When to Use an Output Filter
Design the TPA2005D1-Q1 device without an output filter if the traces from amplifier to speaker are short. The
TPA2005D1-Q1device passed FCC and CE radiated emissions with no shielding and with speaker trace wires
100 mm long or less.
A ferrite bead filter often can be used if the design is failing radiated emissions without an LC filter, and the
frequency-sensitive circuit is greater than 1 MHz. If choosing a ferrite bead, choose one with high impedance at
high frequencies, but very low impedance at low frequencies.
Use an LC output filter if there are low-frequency (
(2p 150 kW 20 Hz )
(11)
CI2 > 53 pF
(12)
RI1
Differential
Input 1
Single-Ended
Input 2
RI1
CI2 R
I2
To Battery
Internal
Oscillator
IN–
_
RI2
VDD
PWM
H–
Bridge
CS
VO+
VO–
+
IN+
CI2
GND
SHUTDOWN
Bias
Circuitry
Filter-Free Class D
Copyright © 2016, Texas Instruments Incorporated
Figure 36. Application Schematic With TPA2005D1-Q1 Summing Differential Input And
Single-Ended Input Signals
9.4.1.3 Summing Two Single-Ended Input Signals
Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner
frequencies (fc1 and fc2) for each input source can be set independently (see Equation 13 through Equation 16
and Figure 37). Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the
IN– terminal. The single-ended inputs must be driven by low-impedance sources, even if one of the inputs is not
outputting an AC signal.
V
150 kW æ V ö
Gain 1 = O = 2 ´
çV÷
VI1
RI1
è ø
(13)
VO
150 kW æ V ö
=2´
çV÷
VI2
RI2
è ø
1
CI1 =
(2p RI1 fc1 )
Gain 2 =
(14)
(15)
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Device Functional Modes (continued)
CI2 =
1
2
p
R
( I2 fc2 )
(16)
CP = CI1 + CI2
(17)
R ´ RI2
RP = I1
(RI1 + RI2 )
(18)
Single-Ended
Input 1
Single-Ended
Input 2
CI1 R
I1
To Battery
CI2 R
I2
Internal
Oscillator
CS
IN–
_
RP
VDD
PWM
H–
Bridge
VO+
VO–
+
IN+
CP
GND
SHUTDOWN
Bias
Circuitry
Filter-Free Class D
Copyright © 2016, Texas Instruments Incorporated
Figure 37. Application Schematic With TPA2005D1-Q1 Summing Two Single-Ended Inputs
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device in several popular use cases.
Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible
modules allow full evaluation of the device in the most common modes of operation. Any design variation can be
supported by TI through schematic and layout reviews. Visit http://e2e.ti.com for design assistance.
10.2 Typical Application
10.2.1 TPA2005D1-Q1 With Differential Input
To Battery
Internal
Oscillator
+
RI
IN–
_
Differential
Input
–
RI
VDD
PWM
H–
Bridge
CS
VO+
VO–
+
IN+
GND
SHUTDOWN
Bias
Circuitry
TPA2005D1
Filter-Free Class D
Copyright © 2016, Texas Instruments Incorporated
Figure 38. Typical TPA2005D1-Q1 Application Schematic With Differential Input
10.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1
Table 1. Design Requirements
PARAMETER
EXAMPLE
Power Supply
5V
High > 2 V
Shutdown Input
Low < 0.8 V
8Ω
Speaker
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10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Component Selection
Figure 38 shows the TPA2005D1-Q1 typical schematic with differential inputs, and Figure 40 shows the
TPA2005D1-Q1 device with differential inputs and input capacitors, and Figure 41 shows the TPA2005D1-Q1
device with single-ended inputs. Differential inputs should be used whenever possible, because the single-ended
inputs are much more susceptible to noise.
Table 2. Typical Component Values
REF DES
VALUE
EIA SIZE
MANUFACTURER
PART NUMBER
RI
150 kΩ (±0.5%)
0402
Panasonic
ERJ2RHD154V
CS
1 μF (+22%, –80%)
0402
Murata
GRP155F50J105Z
3.3 nF (±10%)
0201
Murata
GRP033B10J332K
CI
(1)
(1)
CI is needed only for single-ended input or if VICM is not between 0.5 V and VDD – 0.8 V. CI = 3.3 nF (with RI = 150 kΩ) gives a highpass corner frequency of 321 Hz.
10.2.1.2.2 Input Resistors (RI)
The input resistors (RI) set the gain of the amplifier according to equation Equation 19.
150 kW
Gain = 2 ´
RI
(19)
Resistor matching is very important in fully differential amplifiers. The balance of the output on the
reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second
harmonic distortion diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance
resistors, or better, to keep the performance optimized. Matching is more important than overall tolerance.
Resistor arrays with 1% matching can be used with a tolerance greater than 1%.
Place the input resistors very close to the TPA2005D1-Q1 to limit noise injection on the high-impedance nodes.
For optimal performance, the gain should be set to 2 V/V or lower. Lower gain allows the TPA2005D1-Q1 to
operate at its best and keeps a high voltage at the input, making the inputs less susceptible to noise.
10.2.1.2.3 Decoupling Capacitor (CS)
The TPA2005D1-Q1 is a high-performance class-D audio amplifier that requires adequate power-supply
decoupling to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency
transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor,
typically 1 μF, placed as close as possible to the device VDD lead, works best. Placing this decoupling capacitor
close to the TPA2005D1-Q1 is very important for the efficiency of the class-D amplifier, because any resistance
or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lowerfrequency noise signals, a 10-μF, or greater, capacitor placed near the audio power amplifier also helps, but it is
not required in most applications because of the high PSRR of this device.
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10.2.1.3 Application Curve
1.6
RL = 8 W
f = 1 kHz
Gain = 2 V/V
PO - Output Power - W
1.4
1.2
1
THD+N = 10%
0.8
0.6
THD+N = 1%
0.4
0.2
0
2.5
3
3.5
4
4.5
5
VDD - Supply Voltage - V
Figure 39. Output Power vs Supply Voltage
10.2.2 TPA2005D1-Q1 With Differential Input and Input Capacitors
To Battery
CI
Differential
Input
Internal
Oscillator
RI
IN–
_
CI
VDD
PWM
H–
Bridge
VO+
VO–
+
RI
CS
IN+
GND
Bias
Circuitry
SHUTDOWN
TPA2005D1
Filter-Free Class D
Copyright © 2016, Texas Instruments Incorporated
Figure 40. TPA2005D1-Q1 Application Schematic With Differential Input And Input Capacitors
10.2.2.1 Detailed Design Requirements
10.2.2.1.1 Input Capacitors (CI)
The TPA2005D1-Q1device does not require input coupling capacitors if the design uses a differential source that
is biased from 0.5 V to VDD – 0.8 V (shown in Figure 38). If the input signal is not biased within the
recommended common-mode input range, if needing to use the input as a high pass filter (shown in Figure 40),
or if using a single-ended source (shown in Figure 41), input coupling capacitors are required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in
Equation 20.
1
fC =
(2p RI CI )
(20)
The value of the input capacitor is important to consider, as it directly affects the bass (low frequency)
performance of the circuit.
Equation 21 is reconfigured to solve for the input coupling capacitance.
1
CI =
(2p RI fC )
(21)
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If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better,
because any mismatch in capacitance causes an impedance mismatch at frequencies lower than the corner
frequency.
For a flat low-frequency response, use large input coupling capacitors (1 μF).
10.2.3 TPA2005D1-Q1 With Single-Ended Input
To Battery
CI
Single-ended
Input
Internal
Oscillator
RI
IN–
_
RI
VDD
PWM
H–
Bridge
CS
VO+
VO–
+
IN+
CI
GND
Bias
Circuitry
SHUTDOWN
TPA2005D1
Filter-Free Class D
Copyright © 2016, Texas Instruments Incorporated
Figure 41. TPA2005D1-Q1 Application Schematic With Single-Ended Input
11 Power Supply Recommendations
The TPA2005D1-Q1 device is designed to operate from an input voltage supply range between 2.5-V and 5.5-V.
Therefore, the output voltage range of power supply should be within this range and well regulated. The current
capability of upper power should not exceed the maximum current limit of the power switch.
11.1 Power Supply Decoupling Capacitors
The TPA2005D1-Q1 device requires adequate power supply decoupling to ensure a high efficiency operation
with low total harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor,
typically 0.1 µF, within 2 mm of the VDD pin. This choice of capacitor and placement helps with higher frequency
transients, spikes, or digital hash on the line. In addition to the 0.1 μF ceramic capacitor, TI recommends to place
a 2.2-µF to 10-µF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir, providing
energy faster than the board supply, thus helping to prevent any droop in the supply voltage.
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12 Layout
12.1 Layout Guidelines
12.1.1 Component Location
Place all the external components very close to the TPA2005D1-Q1 device. The input resistors need to be very
close to the TPA2005D1-Q1 input pins so noise does not couple on the high-impedance nodes between the
input resistors and the input amplifier of the TPA2005D1-Q1 device. Placing the decoupling capacitor, CS, close
to the TPA2005D1-Q1 device is important for the efficiency of the class-D amplifier. Any resistance or inductance
in the trace between the device and the capacitor can cause a loss in efficiency.
12.1.2 Trace Width
Make the high current traces going to pins VDD, GND, VO+ and VO– of the TPA2005D1-Q1 device have a
minimum width of 0.7 mm. If these traces are too thin, the TPA2005D1-Q1 performance and output power will
decrease. The input traces do not need to be wide, but do need to run side-by-side to enable common-mode
noise cancellation.
12.1.3 8-Pin QFN (DRB) Layout
Use the following land pattern for board layout with the 8-pin QFN (DRB) package. Note that the solder paste
should use a hatch pattern to fill solder paste at 50% to ensure that there is not too much solder paste under the
package.
0,7 mm
0,33 mm plugged vias (5 places)
1,4 mm
0,38 mm
0,65 mm
1,95 mm
Solder Mask: 1,4 mm × 1,85 mm centered in package
Make solder paste a hatch pattern to fill 50%
3,3 mm
Figure 42. TPA2005D1-Q1 8-Pin QFN (DRB) Board Layout (Top View)
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TPA2005D1-Q1
SLOS474E – AUGUST 2005 – REVISED MARCH 2016
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12.2 Layout Example
Decoupling capacitor
placed as close as
possible to the device
1
8
2
7
IN +
3
6
-
4
5
SHUTDOWN
IN
OUT 0.1µF
OUT +
TPA2005D1
Input Resistors
placed as close as
possible to the device
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Thermal Pad
Via to Bottom Ground Plane
Via to Power Supply
Figure 43. TPA2005D1-Q1 DRB Package Layout Example
Decoupling capacitor
placed as close as
possible to the device
SHUTDOWN
1
8
2
7
IN +
3
6
-
4
5
IN
OUT 0.1µF
OUT +
TPA2005D1
Input Resistors
placed as close as
possible to the device
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Thermal Pad
Via to Bottom Ground Plane
Via to Power Supply
Figure 44. TPA2005D1-Q1 DGN Package Layout Example
24
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Product Folder Links: TPA2005D1-Q1
TPA2005D1-Q1
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SLOS474E – AUGUST 2005 – REVISED MARCH 2016
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• AN-1737 Managing EMI in Class D Audio Applications, SNAA050
• AN-1849 An Audio Amplifier Power Supply Design, SNAA057
• Guidelines for Measuring Audio Power Amplifier Performance, SLOA068
• Measuring Class-D Amplifiers for Audio Speaker Overstress Testing, SLOA116
• Power Rating in Audio Amplifiers, SLEA047
• TPA2005D1 Audio Power Amplifier Evaluation Module, SLOU134
13.2 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPA2005D1DGNRQ1
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
2005I
TPA2005D1DRBQ1
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BIQ
TPA2005D1TDGNRQ1
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
2005T
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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