TPA3106D1
HLQFP
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SLOS516C – OCTOBER 2007 – REVISED AUGUST 2010
40-W MONO CLASS-D AUDIO POWER AMPLIFIER
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FEATURES
APPLICATIONS
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1
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40-W Into an 8-Ω Load From a 25-V Supply
Operates From 10 V to 26 V
Efficient Class-D Operation Eliminates the
Need for Heat Sinks
Four Selectable, Fixed Gain Settings
Differential Inputs
Thermal and Short-Circuit Protection With
Auto Recovery Feature
Clock Output for Synchronization With
Multiple Class-D Devices
Surface Mount 7×7, 32-pin HLQFP Package
Televisions
Powered Speakers
DESCRIPTION
The TPA3106D1 is a 40-W efficient, Class-D audio
power amplifier for driving bridged-tied stereo
speakers. The TPA3106D1 can drive stereo speakers
as low as 4Ω. The high efficiency, ~92%, of the
TPA3106D1 eliminates the need for an external heat
sink when playing music.
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 20, 26, 32, 36 dB.
The outputs are fully protected against shorts to
GND, VCC, and output-to-output shorts with an auto
recovery feature and monitor output.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2010, Texas Instruments Incorporated
TPA3106D1
SLOS516C – OCTOBER 2007 – REVISED AUGUST 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC
Supply voltage
VI
Input voltage
AVCC, PVCC
–0.3 V to 30 V
SHUTDOWN, MUTE
–0.3 V to VCC + 0.3 V
GAIN0, GAIN1, INN, INP, MSTR/SLV, SYNC
–0.3 V to VREG + 0.5 V
Continuous total power dissipation
TA
See Thermal Information Table
Operating free-air temperature range
TJ
Operating junction temperature range
Tstg
Storage temperature range
RLoad
Load resistance
Electrostatic discharge
(1)
(2)
(3)
(4)
–40°C to 85°C
(2)
–40°C to 150°C
–65°C to 150°C
3.2 Ω Minimum
Human body model
(3)
(all pins)
Charged-device model
(4)
±2 kV
(all pins)
±500 V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The TPA3106D1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical
Briefs SLMA002 for more information about using the HTQFP thermal pad.
In accordance with JEDEC Standard 22, Test Method A114-B.
In accordance with JEDEC Standard 22, Test Method C101-A
THERMAL INFORMATION
THERMAL METRIC (1)
TPA3106D1
(2)
VFP (32 PINS)
qJA
Junction-to-ambient thermal resistance
28.23
qJCtop
Junction-to-case (top) thermal resistance
32.4
qJB
Junction-to-board thermal resistance
16.6
yJT
Junction-to-top characterization parameter
yJB
Junction-to-board characterization parameter
6.7
qJCbot
Junction-to-case (bottom) thermal resistance
1.1
(1)
(2)
1
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
10
26
VCC
Supply voltage
PVCC, AVCC
VIH
High-level input voltage
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, SYNC
VIL
Low-level input voltage
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, SYNC
0.8
SHUTDOWN, VI = VCC, VCC = 24 V
125
IIH
High-level input current
MUTE, VI = VCC, VCC = 24 V
75
2
SHUTDOWN, VI = 0, VCC = 24 V
2
SYNC, MUTE, GAIN0, GAIN1, MSTR/SLV, VI = 0 V, VCC = 24 V
1
Low-level input current
VOH
High-level output voltage
FAULT, IOH = 1 mA
VOL
Low-level output voltage
FAULT, IOL = -1 mA
fOSC
Oscillator frequency
ROSC resistor = 100 kΩ
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VREG – 0.6
V
µA
µA
V
AGND + 0.4
200
V
V
GAIN0, GAIN1, MSTR/SLV, SYNC, VI = VREG, VCC = 24 V
IIL
2
2
UNIT
300
V
kHz
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RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TA
TEST CONDITIONS
Operating free-air temperature
MIN
MAX
–40
85
UNIT
°C
DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Class-D output offset voltage (measured
differentially)
VI = 0 V, Gain = 36 dB
Bypass reference for input amplifier
VBYP, no load
4-V internal supply voltage
VREG, no load, VCC = 10 V to 26 V
PSRR
DC Power supply rejection ratio
VCC = 12 V to 24 V, inputs ac coupled to
AGND, Gain = 36 dB
ICC
Quiescent supply current
SHUTDOWN = 2 V, MUTE = 0 V, no load
ICC(SD)
Quiescent supply current in shutdown mode
SHUTDOWN = 0.8 V, no load
ICC(MUTE)
Quiescent supply current in mute mode
MUTE = 2 V, no load
| VOS |
rDS(on)
VCC = 12 V, IO = 500 mA,
TJ = 25°C
Drain-source on-state resistance
G
Gain
GAIN1 = 2 V
UNIT
5
50
1.2
1.35
1.55
V
3.8
4.1
4.4
V
–70
mV
dB
14
17
mA
215
250
µA
6
9
mA
High Side
200
Low side
200
Total
GAIN1 = 0.8 V
TYP MAX
mΩ
400
500
GAIN0 = 0.8 V
19
20
21
GAIN0 = 2 V
25
26
27
GAIN0 = 0.8 V
31
32
33
GAIN0 = 2 V
35
36
37
dB
dB
tON
Turn-on time
C(VBYP) = 1 µF, SHUTDOWN = 2 V
25
ms
tOFF
Turn-off time
C(VBYP) = 1 µF, SHUTDOWN = 0.8 V
0.1
ms
DC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Class-D output offset voltage (measured
differentially)
VI = 0 V, Gain = 36 dB
Bypass reference for input amplifier
VBYP, no load
4-V internal supply voltage
VREG, no load
PSRR
DC Power supply rejection ratio
VCC = 12 V to 24 V, Inputs ac coupled to
AGND, Gain = 36 dB
ICC
Quiescent supply current
SHUTDOWN = 2 V, MUTE = 0 V, no load
ICC(SD)
Quiescent supply current in shutdown mode
SHUTDOWN = 0.8 V, no load
ICC(MITE)
Quiescent supply current in mute mode
MUTE = 2 V, no load
rDS(on)
Drain-source on-state resistance
VCC = 12 V, IO = 500 mA,
TJ = 25°C
| VOS |
GAIN1 = 0.8 V
G
Gain
GAIN1 = 2 V
TYP MAX
UNIT
5
50
1.2
1.35
1.55
V
3.8
4.1
4.4
V
–70
mV
dB
10
14
130
180
µA
5
7
mA
High Side
200
Low side
200
Total
400
500
mA
mΩ
GAIN0 = 0.8 V
19
20
21
GAIN0 = 2 V
25
26
27
GAIN0 = 0.8 V
31
32
33
GAIN0 = 2 V
35
36
37
dB
dB
tON
Turn-on time
C(VBYP) = 1 µF, SHUTDOWN = 2 V
25
ms
tOFF
Turn-off time
C(VBYP) = 1 µF, SHUTDOWN = 0.8 V
0.1
ms
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AC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
KSVR
PO
Supply ripple rejection
Continuous output power
TEST CONDITIONS
MI
N
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
TYP MAX
–88
THD+N = 7%, f = 1 kHz, VCC = 24 V
32
THD+N = 10%, f = 1 kHz, VCC = 24 V
40
THD+N < 7%, f = 1 kHz, VCC = 24 V, RL = 4 Ω, Thermally limited
by package
25
THD+N
Total harmonic distortion +
noise
f = 1 kHz, PO = 20 W (half-power)
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
SNR
Signal-to-noise ratio
Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB,
A-weighted
UNIT
dB
W
0.2%
Thermal trip point
Thermal hysteresis
125
µV
–80
dBV
102
dB
150
°C
30
°C
AC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
KSVR
PO
Supply ripple rejection
Continuous output power
TEST CONDITIONS
MIN
200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs ac-coupled to AGND
–88
THD+N = 7%, f = 1 kHz
8.7
THD+N = 10%, f = 1 kHz
9.2
THD+N = 7%, f = 1 kHz, RL = 4 Ω
15.6
THD+N = 10%, f = 1 kHz, RL = 4 Ω
16.4
RL = 8 Ω, f = 1 kHz, PO = 5 W
0.11%
RL = 4 Ω, f = 1 kHz, PO = 8 W
0.15%
THD+N
Total harmonic distortion + noise
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
SNR
Signal-to-noise ratio
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted
Thermal trip point
Thermal hysteresis
4
TYP
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MAX
UNIT
dB
W
100
µV
–80
dBV
98
dB
150
°C
30
°C
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SLOS516C – OCTOBER 2007 – REVISED AUGUST 2010
32-PIN HTQFP (VFP)
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O
DESCRIPTION
SHUTDOWN
29
I
Active low. Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic levels with
compliance to AVCC.
INP
1
I
Positive audio input
INN
2
I
Negative audio input
GAIN0
5
I
Gain select least significant bit. TTL logic levels with compliance to VREG.
GAIN1
6
I
Gain select most significant bit. TTL logic levels with compliance to VREG.
MUTE
30
I
Active high. Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z, LOW = outputs
enabled). TTL logic levels with compliance to AVCC.
FAULT
31
O
TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only reports short-circuit faults.
Thermal faults are not reported on this terminal.
23
I/O
Bootstrap I/O for left channel, positive high-side FET.
BSP
PVCC
14, 15,
26–28
Power supply for left channel H-bridge, not internally connected to AVCC.
OUTP
21, 22
PGND
16, 17,
24, 25
OUTN
19, 20
O
Class-D 1/2-H-bridge negative output
BSN
18
I/O
Bootstrap I/O for left channel, negative high-side FET.
VCLAMP
13
AGND
3, 4, 12
ROSC
9
O
Class-D 1/2-H-bridge positive output
Power ground for H-bridge.
Internally generated voltage supply forbootstrap capacitor.
Analog ground for digital/analog cells in core.
I/O
I/O for current setting resistor of ramp generator.
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Master/Slave select for determining direction of SYNC terminal. HIGH=Master mode, SYNC terminal is
an output; LOW = slave mode, SYNC terminal accepts a clock input. TTL logic levels with compliance to
VREG.
MSTR/SLV
7
I
SYNC
8
I/O
Clock input/output for synchronizing multiple class-D devices. Direction determined by MSTR/SLV
terminal. Input signal not to exceed VREG.
VBYP
11
O
Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up time via external capacitor
sizing.
VREG
10
O
4-V regulated output for use by internal cells, GAINx, MUTE, and MSTR/SLV pins only. Not specified for
driving other external circuitry.
AVCC
32
Thermal Pad
—
High-voltage analog power supply. Not internally connected to PVCCL.
—
Connect to AGND and PGND – should be star point for both grounds. Internal resistive connection to
AGND and PGND. Thermal vias on the PCB should connect this pad to a large copper area on an
internal or bottom layer for the best thermal performance. The Thermal Pad must be soldered to the
PCB for mechanical reliability.
FUNCTIONAL BLOCK DIAGRAM
PVCC
PVCC
PVCC
VBYP
VCLAMP
BSN
VBYP
AVCC
AVCC
Gain Control
INN
Gate
Drive
Gain
Control
INP
OUTN
VClamp
Gen
PWM
Logic
VBYP
GAIN0
GAIN1
BSP
Gain
Control
To Gain Adj.
Blocks &
Startup Logic
4
Gate
Drive
OUTP
Gain Control
FAULT
PGND
SC
Detect
ROSC
SYNC
PVCC
VBYP AVCC
Thermal
Biases
&
References
VREGok
VREG
Ramp
Generator
MSTR/SLV
Startup
Protection
Logic
AVCC
VCCok
VREG
VREG
4V Reg
SHUTDOWN
TTL Input Buffer
(VCC Compliant)
MUTE
TTL Input Buffer
(VREG
Compliant)
AGND
6
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TYPICAL CHARACTERISTICS
Table 1. TABLE OF GRAPHS
Y-AXIS
X-AXIS
FIGURE
Total Harmonic Distortion + N (%)
Frequency (Hz) (BTL)
Figure 1
Total Harmonic Distortion + N (%)
Frequency (Hz) (BTL)
Figure 2
Total Harmonic Distortion + N (%)
Frequency (Hz) (BTL)
Figure 3
Total Harmonic Distortion + N (%)
Frequency (Hz) (BTL)
Figure 4
Total Harmonic Distortion + N (%)
Frequency (Hz) (BTL)
Figure 5
Total Harmonic Distortion + N (%)
Frequency (Hz) (BTL)
Figure 6
Total Harmonic Distortion + N (%)
Output Power (W) (BTL)
Figure 7
Total Harmonic Distortion + N (%)
Output Power (W) (BTL)
Figure 8
Total Harmonic Distortion + N (%)
Output Power (W) (BTL)
Figure 9
Total Harmonic Distortion + N (%)
Output Power (W) (BTL)
Figure 10
Total Harmonic Distortion + N (%)
Output Power (W) (BTL)
Figure 11
Total Harmonic Distortion + N (%)
Output Power (W) (BTL)
Figure 12
Closed Loop Response
Frequency (Hz) (BTL)
Figure 13
Closed Loop Response
Frequency (Hz) (BTL)
Figure 14
PO – Output Power (W)
Supply Voltage (V) (BTL)
Figure 15
PO – Output Power (W)
Supply Voltage (V) (BTL)
Figure 16
Efficiency (%)
Output Power (W) (BTL)
Figure 16
Efficiency (%)
Output Power (W) (BTL)
Figure 18
Efficiency (%)
Output Power (W) (BTL)
Figure 19
ICC – Supply Current (A)
PO – Total Output Power (W) (BTL)
Figure 20
ICC – Supply Current (A)
PO – Total Output Power (W) (BTL)
Figure 21
kSVR – Supply Rejection Ratio (dB)
Frequency (Hz) (BTL)
Figure 22
kSVR – Supply Rejection Ratio (dB)
Frequency (Hz) (BTL)
Figure 23
kSVR – Supply Rejection Ratio (dB)
Frequency (Hz) (BTL)
Figure 24
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
VCC = 12 V,
RL = 8W,
Gain = 20 dB
PO = 2.5 W
1
0.1
PO = 5 W
PO = 0.5 W
0.01
0.003
20
100
1k
f - Frequency - Hz
10k
20k
VCC = 18 V,
RL = 8W,
Gain = 20 dB
PO = 5 W
1
0.1
PO = 10 W
PO = 1 W
0.01
0.003
20
Figure 1.
100
1k
f - Frequency - Hz
10k 20k
Figure 2.
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TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10
VCC = 24 V,
RL = 8 W,
Gain = 20 dB
PO = 5 W
1
0.1
PO = 10 W
PO = 1 W
0.01
0.003
20
100
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
VCC = 18 V,
L = 22 mH,
C = 1 mF,
Gain = 20 dB
PO = 5 W
0.2
0.05
PO = 10 W
PO = 1 W
0.02
0.01
0.005
0.002
0.001
20
0.5
0.2
0.1
PO = 1 W
0.05
0.02
0.01
0.005
0.002
100
200
1k 2k
f - Frequency - Hz
10k 20k
100 200
1k 2k
f - Frequency - Hz
10k 20k
10
5
2
1
VCC = 12 V,
RL = 4 W,
L = 15 mH,
C = 2 mF,
Gain = 20 dB
PO = 5 W
0.5
0.2
0.1
PO = 1 W
0.05
0.02
0.01
0.005
0.002
0.001
20
100 200
1k
2k
10k 20k
f - Frequency - Hz
Figure 5.
8
PO = 5 W
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
0.5
0.1
L = 15 mH,
C = 2 mF,
Gain = 20 dB
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
1
1
RL = 6 W,
Figure 4.
RL = 6 W,
2
2
VCC = 12 V,
Figure 3.
10
5
5
0.001
20
10k 20k
1k
f - Frequency - Hz
10
Figure 6.
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TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
20
VCC = 12 V,
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
20
RL = 8 W,
Gain = 20 dB
1
1 kHz
10 kHz
0.1
20 Hz
0.01
10m
100m
1
10
VCC = 18 V,
RL = 8 W,
Gain = 20 dB
1
10 kHz
20 Hz
0.1
1 kHz
0.01
10m
10 20 40
100m
PO - Output Power - W
Figure 8.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
VCC = 24 V,
RL = 8 W,
Gain = 20 dB
1
10 kHz
20 Hz
0.1
1 kHz
0.01
10m
100m
1
10 20 40
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %
10 20 40
Figure 7.
20
10
1
PO - Output Power - W
VCC = 12 V,
RL = 6 W,
L = 22 mH,
C = 1 mF,
Gain = 20 dB
1
1 kHz
10 kHz
0.1
20 Hz
0.01
10m
PO - Output Power - W
Figure 9.
100m
1
10
PO - Output Power - W
50
Figure 10.
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TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
10
THD+N - Total Harmonic Distortion + Noise - %
RL = 6 W,
L = 22 mH,
C = 1 mF,
Gain = 20 dB
1
1 kHz
10 kHz
0.1
20 Hz
0.01
10m
1
100m
PO - Output Power - W
10
VCC = 12 V,
RL = 4 W,
L = 15 mH,
C = 2 mF,
Gain = 20 dB
1
1 kHz
10 kHz
0.1
20 Hz
0.01
10m
50
100m
1
Figure 11.
Figure 12.
CLOSED LOOP RESPONSE
vs
FREQUENCY
CLOSED LOOP RESPONSE
vs
FREQUENCY
+200
20
VCC = 24 V, VI = 100 mVrms
+100
+100
1
+0
100m
-100
10m
100
1k
10k
f - Frequency - Hz
-200
100k
Voltage - V
Measurement Low-Pass Filter:
R = 100 W, C = 10 nF
Deg - °
Voltage - V
1
Measurement Low-Pass Filter:
R = 100 W, C = 10 nF
+0
100m
-100
10m
1m
20
Figure 13.
10
50
+200
20
VCC = 12 V, VI = 100 mVrms
1m
20
10
PO - Output Power - W
Deg - °
THD+N - Total Harmonic Distortion + Noise - %
VCC = 18 V,
100
10k
1k
f - Frequency - Hz
-200
100k
Figure 14.
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OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
SUPPLY VOLTAGE
45
25
RL = 8 W
Gain = 20 dB
40
20
PO − Output Power − W
Power Out – W
THD+N=10%
15
10
THD+N=1%
35
30
THD+N = 10%
25
THD+N = 1%
20
15
5
10
RL = 4 W
Gain = 20 dB
0
10
11
12
13
Supply Voltage – V
5
14
10
12
16
14
18
20
22
24
26
VCC - Supply Voltage - V
Figure 15.
Figure 16.
EFFICIENCY
vs
OUTPUT POWER (BTL)
EFFICIENCY
vs
OUTPUT POWER (BTL)
90
100
80
90
VCC = 12 V
70
70
Efficiency –%
Efficiency –%
60
50
40
30
60
50
40
30
20
20
10
10
0
0.1
VCC = 18 V
80
RL = 4 W
VCC = 12 V
3
7
11
15
Power Out – W
PLACE HOLDER
Figure 17.
19
23
0
0.1
RL = 6 W
3
7
11
15 19 23
Power
Out – W
PLACE HOLDER
Figure 18.
27
31
35
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EFFICIENCY
vs
OUTPUT POWER (BTL)
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
100
2.5
VCC = 18 V
VCC = 12 V
RL = 8 Ω
Gain = 32 dB
90
VCC = 24 V
70
Efficiency –%
2
ICC − Supply Current − A
80
60
50
40
30
20
10
0
0.1
VCC = 18 V
VCC = 12 V
1.5
VCC = 24 V
1
0.5
RL = 8 W
3
7
11
15
19
23
27
31
0
35 39
0
10
Power
Out – W
PLACE
HOLDER
Figure 20.
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
+0
1.5
VIN = 12 V
RL = 4 W
Gain = 20 dB
1
0.5
1
3
5
7
9 11 13
Power
Out – W
PLACE
HOLDER
15
17
19
PSRR - Power Supply Rejection Ratio - dB
ICC Supply Current – A
40
PO − Total Output Power − W
2
VCC = 12 V,
Vripple = 200 mVp-p
-20
RL = 8 W
-40
-60
-80
-100
20
Figure 21.
12
30
Figure 19.
2.5
0
0.1
20
100
1k
f - Frequency - Hz
10k 20k
Figure 22.
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SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
+0
VCC = 18 V,
Vripple = 200 mVp-p
-20
PSRR - Power Supply Rejection Ratio - dB
PSRR - Power Supply Rejection Ratio - dB
+0
RL = 8 W
-40
-60
-80
-100
VCC = 24 V,
Vripple = 200 mVp-p
RL = 8 W
-20
-40
-60
-80
-100
20
100
1k
f - Frequency - Hz
10k 20k
20
Figure 23.
100
1k
f - Frequency - Hz
10k 20k
Figure 24.
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APPLICATION INFORMATION
1 mF
220 mF
SDZ
MUTE
FAULT
PGND
PVCC
SDZ
PVCC
MUTE
AVCC
FAULT
Analog
Audio In
PVCC
VCC
1 mF
10 mF
VCC
INP
PGND
INN
BSP
1.0 mF
1.0 mF
AGND
GAIN0
OUTN
GAIN1
GAIN1
OUTN
VCC
220 mF
1 mF
1 mF
1 mF
1nF
1μF
1μF
33 mH
20 Ω
PGND
PVCC
PVCC
AGND
10nF
VCLAMP
PGND
VBYP
BSN
SYNC
ROSC
MSTR/SLV
VREG
C17
1nF
OUTP
TPA3106D1
GAIN0
SYNC
33 mH
OUTP
AGND
MSTR/SLV
20 Ω
0.22 μF
Connected at PowerPad
with single point
connection
PGND
AGND
Figure 25. TPA3106D1 Application Circuit With Single-Ended Inputs
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CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3106D1.
Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out-of-phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0
V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 26. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss and thus causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
Across Load
0V
-12 V
Current
Figure 26. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an
Inductive Load With No Input
TPA3106D1 Modulation Scheme
The TPA3106D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and
OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most
of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
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OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+12 V
0V
-12 V
Current
OUTP
OUTN
Differential
Voltage
Across
Load
Output > 0 V
+12 V
0V
-12 V
Current
Figure 27. The TPA3100D2 Output Voltage and Current Waveforms Into an Inductive Load
Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3106D1 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
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When to Use an Output Filter for EMI Suppression
Design the TPA3106D1 without the filter if the traces from amplifier to speaker are short (< 10 cm). Powered
speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without
a filter.
Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and
CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high
impedance at high frequencies, but low impedance at low frequencies.
Use an LC output filter if there are low frequency (
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