TPD6F002DSVR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPD6F002 SLLS876B – AUGUST 2008 – REVISED MAY 2016 TPD6F002 Six-Channel EMI Filter for LCD Display and FPD-Link 1 Features 3 Description • The TPD6F002 device is a highly-integrated device that provides a six-channel Electromagnetic Interference (EMI) filter and a TVS based ESD protection diode array. The low-pass filter array suppresses EMI/RFI emissions for data ports subject to electromagnetic interference. The TVS diode array is rated to dissipate ESD strikes above the maximum level specified in the IEC 61000-4-2 international standard. The high level of integration, combined with its small easy-to-route DSV package, allows this device to provide great circuit protection for LCD displays, memory interfaces, GPIO lines, and FPDLink. 1 • • • • Six-Channel EMI Filtering for Data Ports – –57-dB Crosstalk Attenuation at 100 MHz – –35-dB Insertion Loss at 800 MHz – –3-dB Bandwidth at 100 MHz Robust ESD Protection Exceeds IEC 61000-4-2 (Level 4) – ±20-kV IEC 61000-4-2 Contact Discharge – ±30-kV IEC 61000-4-2 Air-Gap Discharge Pi-Style (C-R-C) Filter Configuration (R = 100 Ω, CTOTAL = 34 pF) Low Leakage Current: 20 nA (Maximum) Space-Saving WSON Package (3 mm × 1.35 mm) Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) 2 Applications TPD6F002 • • • • • (1) For all available packages, see the orderable addendum at the end of the data sheet. LCD Display Interface GPIO Memory Interface Data Lines at Flex Cables FPD-Link WSON (12) 3.00 mm × 1.35 mm Equivalent Schematic Representation 100 Ω Ch_In C1 = 17 pF Ch_Out C2 = 17 pF GND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPD6F002 SLLS876B – AUGUST 2008 – REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 3 3 4 4 5 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 6 7.1 Overview ................................................................... 6 7.2 Functional Block Diagram ......................................... 6 7.3 Feature Description................................................... 6 7.4 Device Functional Modes.......................................... 6 8 Application and Implementation .......................... 7 8.1 Application Information.............................................. 7 8.2 Typical Application ................................................... 7 9 Power Supply Recommendations........................ 9 10 Layout..................................................................... 9 10.1 Layout Guidelines ................................................... 9 10.2 Layout Example ...................................................... 9 11 Device and Documentation Support ................. 10 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 10 10 10 10 12 Mechanical, Packaging, and Orderable Information ........................................................... 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (November 2009) to Revision B Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 • Removed Ordering Information table .................................................................................................................................... 1 2 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6F002 TPD6F002 www.ti.com SLLS876B – AUGUST 2008 – REVISED MAY 2016 5 Pin Configuration and Functions DSV Package 12-Pin WSON Top View Ch1_Out Ch2_In Ch2_Out Ch3_In Ch3_Out GND Ch1_In Ch4_In Ch4_Out Ch5_In Ch5_Out Ch6_In Ch6_Out Pin Functions PIN TYPE DESCRIPTION NAME NO. ChX_In 1, 2, 3, 4, 5, 6 I/O ESD-protected channel, connected to corresponding ChX_Out 7, 8, 9, 10, 11, 12 I/O ESD-protected channel, connected to corresponding ChX_Inx GND G Ground ChX_Out GND 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN VIO MAX UNIT 6 V Lead temperature (soldering, 10 s) 300 °C TJ Junction temperature 150 °C Tstg Storage temperature 150 °C (1) I/O to GND –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Human-body model V(ESD) (1) Electrostatic discharge (1) UNIT ±15000 IEC 61000-4-2 contact discharge ±20000 IEC 61000-4-2 air-gap discharge ±30000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VIO Input pin voltage TA Operating free-air temperature MIN MAX 0 5.5 UNIT V –40 85 °C Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6F002 3 TPD6F002 SLLS876B – AUGUST 2008 – REVISED MAY 2016 www.ti.com 6.4 Thermal Information TPD6F002 THERMAL METRIC (1) DSV (WSON) UNIT 12 PINS RθJA Junction-to-ambient thermal resistance 120.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 104.4 °C/W RθJB Junction-to-board thermal resistance 78.5 °C/W ψJT Junction-to-top characterization parameter 13 °C/W ψJB Junction-to-board characterization parameter 77.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 66.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics TA = –40°C to 85°C (Unless otherwise noted) PARAMETER TEST CONDITIONS IIO = 10 μA MIN TYP (1) VBR DC breakdown voltage R Resistance C Capacitance (C1 or C2) VIO = 2.5 V 17 IIO Channel leakage current VIO = 3.3 V 1 fC Cutoff frequency ZSOURCE = 50 Ω, ZLOAD = 50 Ω (1) 4 MAX 6 85 UNIT V 100 100 115 Ω pF 20 nA MHz Typical values are at TA = 25°C. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6F002 TPD6F002 www.ti.com SLLS876B – AUGUST 2008 – REVISED MAY 2016 6.6 Typical Characteristics 150 1.00E-05 8.00E-06 6.00E-06 -40C 25C 85C 4.00E-06 R e s is t a n c e ( o h m s ) 100 C u r re n t ( µ A ) 2.00E-06 0.00E+00 -2.00E-06 50 -4.00E-06 -6.00E-06 -8.00E-06 0 -1.00E-05 -40 -7 -5 -3 -1 1 3 5 25 7 85 Temp (C) Voltage (V) Figure 2. Series Resistance vs Temperature Figure 1. DC Voltage-Current Sweep Across Input, Output Pins 30 0 C1 -5 C2 25 -10 20 C a p a c i ta n c e (p F ) I n s e rt io n L o s s ( d B ) -15 -20 -25 15 10 -30 5 -35 -40 0 0 0.5 -45 1 1.5 2 2.5 3 3.5 4 4.5 Voltage Bias (V) 1.00E+06 1.00E+07 1.00E+08 1.00E+09 Frequency (Hz) TA = 25°C, DC Bias = 0 V, 50 Ω Environment Figure 3. TPD6F002 Typical Insertion-Loss Characteristics Figure 4. Capacitance (C1 or C2) vs Bias Voltage Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6F002 5 TPD6F002 SLLS876B – AUGUST 2008 – REVISED MAY 2016 www.ti.com 7 Detailed Description 7.1 Overview The TPD6F002 is a highly-integrated ESD protection and EMI filtering device intended for use where small size and ease of routing are important. Common applications include LCD display interfaces, memory interfaces, GPIO lines, and FPD-Link. 7.2 Functional Block Diagram 100 Ω Ch_In C1 = 17 pF Ch_Out C2 = 17 pF GND Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Six-Channel EMI Filtering This device provides six channels for EMI filtering of data lines with the following parameters: • –57-dB Crosstalk Attenuation at 100 MHz • –35-dB Insertion Loss at 800 MHz • –3-dB Bandwidth at 100 MHz 7.3.2 Pi-Style Filter Configuration This device has a pi-style filtering configuration composed of a series resistor and two capacitors in parallel with the I/O pins. The typical resistor value is 100 Ω and the typical capacitor values are 17 pF each. 7.3.3 Robust ESD Protection The ESD protection on all pins exceeds the IEC 61000-4-2 level 4 standard. Contact ESD is rated at ±20 kV and Air-gap ESD is rated at ±30 kV. 7.3.4 Low Leakage Current The I/O pins feature an ultra-low leakage current of 20 nA (maximum) with a bias of 3.3 V 7.3.5 Space-Saving WSON Package The layout of this device makes it easy to add protection to existing layouts. The packages offer flow-through routing which requires minimal changes to existing layout for addition of these devices. Additionally, the device offers a small, space-saving package that takes a minimal footprint on the board. 7.4 Device Functional Modes The TPD6F002 is a passive integrated circuit that passively filters EMI and triggers when voltages are above VBR or below the lower diode voltage (–0.6 V). During ESD events, voltages as high as ±30 kV (air) can be directed to ground through the internal diode network. Once the voltages on the protected line fall below the trigger levels, the device reverts to passive. 6 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6F002 TPD6F002 www.ti.com SLLS876B – AUGUST 2008 – REVISED MAY 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPD6F002 offers highly-integrated ESD protection and EMI filtering for 6 channels per device. Take care during implementation to make sure that this device fits the application appropriately. 8.2 Typical Application TPD6F002 R0 1 12 R1 2 11 R2 3 10 R3 4 9 R4 5 8 R5 6 7 Display Panel Connector G0 1 12 G1 2 11 G2 3 10 G3 4 9 G4 5 8 6 7 G5 TPD6F002 Connector TPD6F002 GND GND B0 1 12 B1 2 11 B2 3 10 B3 4 9 B4 5 8 B5 6 7 GND Copyright © 2016, Texas Instruments Incorporated Figure 5. Display Panel Schematic 8.2.1 Design Requirements For this design example, three TPD6F002 devices are being used in an 18-bit display panel application. This provides a complete ESD and EMI protection solution for the display connector. Table 1 lists the parameters for this display panel application. Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6F002 7 TPD6F002 SLLS876B – AUGUST 2008 – REVISED MAY 2016 www.ti.com Table 1. Design Parameters DESIGN PARAMETER VALUE Signal range on all pins except GND 0 V to 5 V Operating Frequency 50 MHz 8.2.2 Detailed Design Procedure To • • • begin the design process, some design parameters must be decided; the designer must know the following: Signal range of all the protected lines Operating frequency Crosstalk response 8.2.2.1 Signal Range on All Protected Lines The TPD6F002 has 6 identical protection channels for signal lines. All I/O pins support a signal range from 0 to 5.5 V. 8.2.2.2 Operating Frequency The TPD6F002 has a 100-MHz, –3-dB bandwidth, which supports the operating frequency for this display. 8.2.2.3 Crosstalk Response The TPD6F002 has a –57-dB crosstalk attenuation at 100 MHz, sufficient for this display. 8.2.3 Application Curve 0 -10 -20 -30 S 4 1 (d B ) -40 -50 -60 -70 -80 -90 -100 1.00E+06 1.00E+07 1.00E+08 1.00E+09 frequency (Hz) Figure 6. Channel-to-Channel Crosstalk 8 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6F002 TPD6F002 www.ti.com SLLS876B – AUGUST 2008 – REVISED MAY 2016 9 Power Supply Recommendations This device is a passive EMI and ESD device so there is no need to power it. Take care not to violate the recommended VIO specification (5.5 V) to ensure the device functions properly. 10 Layout 10.1 Layout Guidelines • • • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 10.2 Layout Example This application is typical of an 18-bit RGB display panel layout. VIA to GND Plane B5 B4 B3 B2 B1 B0 G5 G4 G3 G2 G1 G0 R5 R4 R3 R2 R1 R0 6 5 4 3 2 1 6 5 4 3 2 1 6 5 4 3 2 1 11 12 GND GND GND 10 9 8 7 12 11 10 9 8 7 12 11 10 9 8 7 Figure 7. Typical RGB Display Layout Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6F002 9 TPD6F002 SLLS876B – AUGUST 2008 – REVISED MAY 2016 www.ti.com 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 10 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: TPD6F002 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPD6F002DSVR ACTIVE SON DSV 12 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3NS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of