TPIC6259DWRG4

TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 • • • • • • • Low rDS(on) . . . 1.3 Ω Typical Avalanche Energy . . . 75 mJ Eight Power DMOS Transistor Outputs of 250-mA Continuous Current 1.5-A Pulsed Current Per Output Output Clamp Voltage at 45 V Four Distinct Function Modes Low Power Consumption DW OR N PACKAGE (TOP VIEW) PGND VCC S0 DRAIN0 DRAIN1 DRAIN2 DRAIN3 S1 LGND PGND description This power logic 8-bit addressable latch controls open-drain DMOS transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multifunctional device capable of storing single-line data in eight addressable latches with 3-to-8 decoding or demultiplexing mode active-low DMOS outputs. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 PGND CLR D DRAIN7 DRAIN6 DRAIN5 DRAIN4 G S2 PGND FUNCTION TABLE H L OUTPUT OF ADDRESSED DRAIN L H INPUTS CLR G H H L L D EACH OTHER DRAIN Qio Qio H H X Qio Qio L L L L H L L H H H FUNCTION Addressable Latch Memory 8-Line Demultiplexer Four distinct modes of operation are selectable by L H X H H Clear controlling the clear (CLR) and enable (G) inputs as enumerated in the function table. In the LATCH SELECTION TABLE addressable-latch mode, data at the data-in (D) SELECT INPUTS DRAIN terminal is written into the addressed latch. The ADDRESSED S2 S1 S0 addressed DMOS transistor output inverts the L L L 0 data input with all unaddressed DMOS-transistor L L H 1 outputs remaining in their previous states. In the L H L 2 memory mode, all DMOS-transistor outputs L H H 3 remain in their previous states and are unaffected H L L 4 by the data or address inputs. To eliminate the H L H 5 possibility of entering erroneous data in the latch, H H L 6 H H H 7 enable G should be held high (inactive) while the address lines are changing. In the 3-to-8 decoding or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are high. In the clear mode, all outputs are high and unaffected by the address and data inputs. Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 9, logic ground (LGND), and pins 1, 10, 11, and 20, power ground (PGND) must be externally made in a manner that reduces crosstalk between the logic and load circuits. The TPIC6259 is characterized for operation over the operating case temperature range of – 40°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251–1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 logic symbol† S0 S1 S2 G D CLR 3 0 8 12 13 18 19 8M 0/7 2 G8 Z9 Z10 9,0D 4 DRAIN0 10,0R 9,1D 5 DRAIN1 10,1R 9,2D 6 DRAIN2 10,2R 9,3D 7 DRAIN3 10,3R 9,4D 14 DRAIN4 10,4R 9,5D 15 DRAIN5 10,5R 9,6D 16 DRAIN6 10,6R 9,7D 17 10,7R † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • DRAIN7 TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 logic diagram (positive logic) 4 DRAIN0 S0 3 D C1 CLR 5 DRAIN1 D C1 CLR 6 DRAIN2 D S1 C1 8 CLR 7 DRAIN3 D C1 CLR S2 14 12 DRAIN4 D C1 CLR 15 DRAIN5 D C1 CLR 16 DRAIN6 D C1 CLR D 18 17 DRAIN7 D G CLR C1 13 CLR 1,10,11, 20 19 PGND • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 3 TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 45 V Input 25 V 12 V 12 V LGND PGND LGND absolute maximum ratings over the recommended operating case temperature range (unless otherwise noted)† Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 V Continuous source-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Pulsed source-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Pulsed drain current, each output, all outputs on, IDn, TA = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . 750 mA Continuous drain current, each output, all outputs on, IDn, TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA Peak drain current single output, IDM, TA = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Single-pulse avalanche energy, EAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mJ Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to LGND and PGND. 2. Each power DMOS source is internally connected to PGND. 3. Pulse duration ≤ 100 µs, duty cycle ≤ 2% 4. DRAIN supply voltage = 15 V, starting junction temperature, (TJS) = 25°C, L = 100 mH, IAS = 1 A (see Figure 4). DISSIPATION RATING TABLE 4 PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 125°C POWER RATING DW 1125 mW 9.0 mW/°C 225 mW N 1150 mW 9.2 mW/°C 230 mW • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 recommended operating conditions over recommended operating temperature range (unless otherwise noted) Logic supply voltage, VCC High-level input voltage, VIH MIN MAX 4.5 5.5 UNIT V 0.85 VCC Low-level input voltage, VIL V 0.15 VCC Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) – 1.8 Setup time, D high before G↑, tsu (see Figure 2) 1.5 V A 10 ns 5 ns Hold time, D high after G↑, th (see Figure 2) Pulse duration, tw (see Figure 2) 15 Operating case temperature, TC – 40 ns °C 125 electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted) PARAMETER V(BR)DSX VSD Drain-source breakdown voltage IIH IIL High-level input current ICC Logic supply current IN Nominal current IDSX Off state drain current Off-state rDS(on) Static drain-source on-state resistance TEST CONDITIONS Source-drain diode forward voltage Low-level input current ID = 1 mA IF = 250 mA, See Note 3 VCC = 5.5 V, VCC = 5.5 V, VI = VCC VI = 0 MIN TYP MAX 45 VDS = 40 V VDS = 40 V, V 0.85 IO = 0, All inputs low VDS(on) = 0.5 V, IN = ID, TC = 85°C, See Notes 5, 6, and 7 15 ID = 250 mA, ID = 250 mA, VCC = 4.5 V VCC = 4.5 V TC = 125°C, ID = 500 mA, VCC = 4.5 V 1 V 1 µA –1 µA 100 µA 250 TC = 125°C See Notes 5 and 6 and Figures 8 and 9 UNIT mA 0.05 1 0.15 5 1.3 2 2 3.2 1.3 2 TYP MAX µA Ω switching characteristics, VCC = 5 V, TC = 25°C PARAMETER TEST CONDITIONS MIN UNIT tPLH tPHL Propagation delay time, low-to-high-level output from D 625 ns Propagation delay time, high-to-low-level output from D 140 ns tr tf Rise time, drain output 650 ns 400 ns ta trr Reverse-recovery-current rise time CL = 30 pF,, ID = 250 mA,, See Figures 1, 2, and 10 Fall time, drain output IF = 250 mA, di/dt = 20 A/µs, µ See Notes 5 and 6 and Figure 3 Reverse-recovery time NOTES: 3. 5. 6. 7. 100 ns 300 Pulse duration ≤ 100 µs, duty cycle ≤ 2% Technique should limit TJ – TC to 10°C maximum. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at TC = 85°C. thermal resistance PARAMETER RθJA TEST CONDITIONS Thermal resistance junction-to-ambient junction to ambient DW package All 8 outputs with equal power N package • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • MIN MAX 111 108 UNIT °C/W 5 TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION 5V CLR 0V 5V S0 5V 24 V 0V 5V 2 3 8 S1 ID VCC S0 0V RL = 95 Ω S1 12 Word S2 DUT Generator 4 –7, 13 (see Note A) G 14 –17 19 DRAIN CLR 18 D LGND PGND 9 1, 10, 11, 20 5V S2 Output 0V 5V G 0V 5V CL = 30 pF (see Note B) D 0V 24 V TEST CIRCUIT DRAIN5 0.5 V 24 V DRAIN3 0.5 V VOLTAGE WAVEFORMS Figure 1. Typical Operation Mode 5V G 5V 2 VCC Word Generator (see Note A) 18 24 V 19 13 50% 0V ID 4 –7, 14 –17 1, 10, 11, 20 tPHL 90% Output 95 Ω DRAIN LGND PGND 9 50% tPLH D G D CLR DUT Word Generator (see Note A) 0V 5V 10% 10% tr Output 24 V 90% 0.5 V tf SWITCHING TIMES CL = 30 pF (see Note B) 5V G 50% 0V tsu th TEST CIRCUIT 5V D 50% 50% 0V tw INPUT SETUP AND HOLD WAVEFORMS Figure 2. Test Circuit, Switching Times, and Voltage Waveforms NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION TP K DRAIN 0.25 A 2500 µF 250 V Circuit Under Test dl/dt = 20 A/µs + 25 V L = 1 mH IF (see Note B) IF – 0 TP A 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note A) ta 50 Ω trr TEST CIRCUIT CURRENT WAVEFORM NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.25 A, where t1 = 10 µs, t2 = 7 µs, and t3 = 3 µs. B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-Drain Diode 5V 15 V tw 2 12 8 Word Generator (see Note A) 3 13 18 VCC S2 S1 S0 5V Input 0.11 Ω See Note B ID DUT G D DRAIN 19 4 –7, 14 –17 0V IAS = 1 A L = 100 mH ID VDS CLR V(BR)DSX = 45 V MIN VDS LGND PGND 9 tav 1, 10, 11, 20 VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω . B. Input pulse duration, tw, is increased until peak current IAS = 1 A. Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 75 mJ. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 7 TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 800 10 I D – Maximum Continuous Drain Current of Each Output – mA IAS – Peak Avalanche Current – A TJS = 25°C 4 2 1 0.4 0.2 0.1 0.1 0.2 0.4 1 2 4 VCC = 5 V 700 600 500 TA = 25°C 400 300 TA = 100°C 200 TA = 125°C 100 0 10 0 1 2 3 4 5 6 7 8 N – Number of Outputs Conducting Simultaneously tav – Time Duration of Avalanche – ms Figure 5 Figure 6 MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY I D – Maximum Peak Drain Current of Each Output – A 2 VCC = 5 V TA = 25°C d = tw/tperiod = 1 ms/tperiod 1.5 d = 5% 1 d = 50% d = 10% 0.5 d = 80% 0 0 1 2 3 4 5 6 7 8 N – Number of Outputs Conducting Simultaneously Figure 7 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE r DS(on) – Static Drain-Source On-State Resistance – Ω r DS(on) – Static Drain-Source On-State Resistance – Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 4 3.5 VCC = 5 V See Note A 3 TC = 125°C 2.5 2 TC = 25°C 1.5 1 TC = – 40°C 0.5 0 0.25 0.5 0.75 1 1.25 1.5 3 ID = 250 mA See Note A TC = 125°C 2.5 2 TC = 25°C 1.5 1 TC = – 40°C 0.5 0 3 4 5 6 7 VCC – Logic Supply Voltage – V ID – Drain Current – A Figure 8 Figure 9 SWITCHING TIME vs FREE-AIR TEMPERATURE 700 tr Switching Time – ns 600 tPLH ID = 250 mA See Note A 500 tf 400 300 200 tPHL 100 – 50 0 50 100 150 TA – Free-Air Temperature – °C Figure 10 NOTE A: Technique should limit TJ – TC to 10°C maximum. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPIC6259DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM TPIC6259DWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM TPIC6259DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM TPIC6259DWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM TPIC6259N ACTIVE PDIP N 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -40 to 125 TPIC6259 TPIC6259 -40 to 125 TPIC6259 TPIC6259 -40 to 125 TPIC6259N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of