TPIC6A259DWG4

    
 
   SLIS004B − APRIL 1993 − REVISED SEPTEMBER 1995 • • • • • • • Low rDS(on) . . . 1 Ω Typ Output Short-Circuit Protection Avalanche Energy . . . 75 mJ Eight 350-mA DMOS Outputs 50-V Switching Capability Four Distinct Function Modes Low Power Consumption NE PACKAGE (TOP VIEW) DRAIN2 DRAIN3 S1 LGND PGND PGND S2 G DRAIN4 DRAIN5 description This power logic 8-bit addressable latch controls open-drain DMOS-transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multifunctional device capable of operating as eight addressable latches or an 8-line demultiplexer with active-low DMOS outputs. Each open-drain DMOS transistor features an independent chopping current-limiting circuit to prevent damage in the case of a short circuit. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 DRAIN1 DRAIN0 S0 VCC PGND PGND CLR D DRAIN7 DRAIN6 DW PACKAGE (TOP VIEW) DRAIN2 DRAIN3 S1 LGND PGND PGND PGND PGND S2 G DRAIN4 DRAIN5 Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) terminal is written into the addressed latch. The addressed DMOS-transistor output inverts the data input with all unaddressed DMOS-transistor outputs remaining in their previous states. In the memory mode, all DMOS-transistor outputs remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latch, enable G should be held high (inactive) while the address lines are changing. In the 8-line demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are high. In the clear mode, all outputs are high and unaffected by the address and data inputs. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DRAIN1 DRAIN0 S0 VCC PGND PGND PGND PGND CLR D DRAIN7 DRAIN6 FUNCTION TABLE OUTPUT OF ADDRESSED DRAIN L H Qio INPUTS CLR H H H L L L G D L H L L H X L L H H L X L H H EACH OTHER DRAIN Qio Qio Qio H H H FUNCTION Addressable Latch Memory 8-Line Demultiplexer Clear LATCH SELECTION TABLE SELECT INPUTS S2 S1 S0 L L L L H L L L H L H H H L L H H L L H H H H H Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits. DRAIN ADDRESSED 0 1 2 3 4 5 6 7 Copyright  1995, Texas Instruments Incorporated  
  
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   SLIS004B − APRIL 1993 − REVISED SEPTEMBER 1995 description (continued) The TPIC6A259 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body, surface-mount (DW) package. The TPIC6A259 is characterized for operation over the operating case temperature range of −40°C to 125°C. logic symbol† S0 0 8M 0 7 S1 S2 2 G G8 D Z9 CLR Z10 9,0D DRAIN0 10,0R 9,1D DRAIN1 10,1R 9,2D DRAIN2 10,2R 9,3D DRAIN3 10,3R 9,4D DRAIN4 10,4R 9,5D DRAIN5 10,5R 9,6D DRAIN6 10,6R 9,7D DRAIN7 10,7R † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
    
 
   SLIS004B − APRIL 1993 − REVISED SEPTEMBER 1995 logic diagram (positive logic) D CLR G DRAIN0 D C1 S0 CLR DRAIN1 D C1 CLR DRAIN2 S1 D D C1 CLR S2 D C1 Current Limit and Charge Pump C1 CLR DRAIN3 DRAIN4 CLR DRAIN5 D C1 CLR DRAIN6 D C1 CLR DRAIN7 D C1 CLR • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • PGND 3 
    
 
   SLIS004B − APRIL 1993 − REVISED SEPTEMBER 1995 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN Input 25 V 12 V RSENSE LGND LGND PGND absolute maximum ratings over the recommended operating case temperature range (unless otherwise noted)† Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Pulsed drain current, each output, all outputs on, ID, TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . 1.1 A Continuous drain current, each output, all outputs on, ID, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mA Peak drain current single output, TC = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 A Single-pulse avalanche energy, EAS (see Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mJ Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mA Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to LGND and PGND. 2. Each power DMOS source is internally connected to PGND. 3. Pulse duration ≤ 100 µs, and duty cycle ≤ 2%. 4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 210 mH, and IAS = 600 mA (see Figure 6). DISSIPATION RATING TABLE 4 PACKAGE TC ≤ 25°C POWER RATING DERATING FACTOR ABOVE TC = 25°C TC = 125°C POWER RATING DW 1750 mW 14 mW/°C 350 mW NE 2500 mW 20 mW/°C 500 mW • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
    
 
   SLIS004B − APRIL 1993 − REVISED SEPTEMBER 1995 recommended operating conditions MIN Logic supply voltage, VCC MAX 4.5 High-level input voltage, VIH 0.85 VCC Low-level input voltage, VIL 0 Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) 5.5 Hold time, D high before G↑, th (see Figure 2) V VCC 0.15 VCC −1.8 Setup time, D high before G↑,tsu (see Figure 2) UNIT 0.6 V V A 10 ns 5 ns Pulse duration, tw (see Figure 2) 15 ns Operating case temperature, TC −40 °C 125 electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS V(BR)DSX Drain-to-source breakdown voltage ID = 1 mA VSD Source-to-drain diode forward voltage IF = 350 mA, MIN TYP MAX 50 See Note 3 High-level input current Low-level input current VI = VCC VI = 0 ICC Logic supply current IO = 0, VI = VCC or 0 IOK Output current at which chopping starts TC = 25°C, See Note 5 and Figures 3 and 4 I(nom) Nominal current ID Off-state drain current rDS(on) Static drain-to-source on-state resistance 0.6 VDS(on) = 0.5 V, I(nom) = ID, TC = 85°C, VCC = 5 V, See Notes 5, 6, and 7 VDS = 40 V, TC = 25°C VDS = 40 V, TC = 125°C ID = 350 mA, ID = 350 mA, TC = 25°C TC = 125°C V 0.8 IIH IIL 1.1 V 1 µA −1 µA 0.5 5 mA 0.8 1.1 350 See Notes 5 and 6 and Figures 9 and 10 UNIT A mA 0.1 1 0.2 5 1 1.5 1.7 2.5 TYP MAX µA A Ω switching characteristics, VCC = 5 V, TC = 25°C PARAMETER TEST CONDITIONS tPHL tPLH Propagation delay time, high- to low-level output from D tr tf Rise time, drain output ta trr Reverse-recovery-current rise time Propagation delay time, low- to high-level output from D NOTES: 3. 5. 6. 7. UNIT 30 ns CL = 30 pF, ID = 350 mA, See Figures 1, 2, and 11 125 ns 60 ns 30 ns IF = 350 mA, di/dt = 20 A/µs, See Notes 5 and 6 and Figure 5 100 ns 300 ns Fall time, drain output Reverse-recovery time MIN Pulse duration ≤ 100 µs and duty cycle ≤ 2%. Technique should limit TJ − TC to 10°C maximum. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at TC = 85°C. thermal resistance PARAMETER TEST CONDITIONS DW RθJC JC Thermal resistance, junction-to-case RθJA JA Thermal resistance, junction-to-ambient NE MAX 10 All eight outputs with equal power DW NE MIN 10 50 All eight outputs with equal power • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 50 UNIT °C/W °C/W 5 
    
 
   SLIS004B − APRIL 1993 − REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION 5V 0V 5V RL = 68 Ω S1 Word Generator (see Note A) S2 0V 5V S0 ID VCC S0 5V CLR 24 V DUT S1 0V 5V Output G S2 DRAIN CLR 0V 5V CL = 30 pF (see Note B) D LGND PGND G 0V 5V D TEST CIRCUIT 0V 24 V DRAIN5 0.5 V 24 V DRAIN3 0.5 V VOLTAGE WAVEFORMS Figure 1. Typical Operation Mode 5V G 5V 5V 24 V VCC Word Generator (see Note A) D 50% tPLH ID D 68 Ω LGND tPHL 90% Output 24 V 90% 10% 10% tr Output G 50% 0V CLR DUT Word Generator (see Note A) 0V 0.5 V tf SWITCHING TIMES DRAIN PGND CL = 30 pF (see Note B) 5V G 50% 0V tsu th TEST CIRCUIT 5V D 50% 50% 0V tw INPUT SETUP AND HOLD WAVEFORMS Figure 2. Test Circuit, Switching Times, and Voltage Waveforms NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
    
 
   SLIS004B − APRIL 1993 − REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION OUTPUT CURRENT vs TIME FOR INCREASING LOAD RESISTANCE REGION 1 CURRENT WAVEFORM 1.5 IOK IOK (see Notes A and B) 1 I O − Output Current I O − Output Current − A 1.25 0.75 0.5 0 0.25 t1 t2 t1 t2 t1 t1 ≈ 40 µs t2 ≈ 2.5 ms 0 Region 2 Region 1 Time Time First output current pulses after turn-on in chopping mode with resistive load. NOTES: A. Figure 3 illustrates the output current characteristics of the device energizing a load having initially low, increasing resistance, e.g., an incandescent lamp. In region 1, chopping occurs and the peak current is limited to IOK. In region 2, output current is continuous. The same characteristics occur in reverse order when the device energizes a load having an initially high, decreasing resistance. B. Region 1 duty cycle is approximately 2%. Figure 3. Chopping-Mode Characteristics OUTPUT CURRENT LIMIT vs CASE TEMPERATURE 1.5 I O − Output Current Limit − A VCC = 5.5 V 1.2 0.9 VCC = 4.5 V 0.6 0.3 0 − 50 − 25 0 25 50 75 100 125 150 TC − Case Temperature − °C Figure 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 7 
    
 
   SLIS004B − APRIL 1993 − REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION TP K DRAIN Circuit Under Test 0.35 A 2500 µF 250 V di/dt = 20 A/µs + 24 V L = 1 mH IF (see Note B) IF − 0 TP A 25% of IRM t2 t1 t3 Driver IRM (see Note C) RG VGG (see Note A) ta 50 Ω trr CURRENT WAVEFORM TEST CIRCUIT NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.35 A, where t1 = 10 µs, t2 = 7 µs, and t3 = 3 µs. B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. C. IRM = maximum recovery current Figure 5. Reverse-Recovery-Current Test Circuit and Waveforms of Source-Drain Diode 5V 15 V tw S2 S1 Word Generator (see Note A) S0 G D Input 1Ω See Note B ID DUT DRAIN tav† 5V VCC 0V IAS = 600 mA L = 210 mH ID VDS CLR VDS LGND PGND V(BR)DSX = 50 V MIN VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT † Non-JEDEC symbol for avalanche time. NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. Input pulse duration, tw, is increased until peak current IAS = 600 mA. Energy test level is defined as EAS = (IAS × V(BR)DSX × tav)/2 = 75 mJ. Figure 6. Single-Pulse Avalanche Energy Test Circuit and Waveforms 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 
    
 
   SLIS004B − APRIL 1993 − REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS IDM − Maximum Peak Drain Current of Each Output − A MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY ID − Maximum Continuous Drain Current of Each Output − A 0.7 VCC = 5 V 0.6 TA = 25°C 0.5 0.4 TA = 100°C 0.3 0.2 TA = 125°C 0.1 0 1 2 3 4 5 6 7 8 N − Number of Outputs Conducting Simultaneously MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 0.9 0.8 d = 50% 0.6 0.5 d = 80% 0.4 0.3 VCC = 5 V TA = 25°C d = tw/tperiod d = 1 ms/tperiod 0.2 0.1 0 1 2 3 4 5 6 7 8 N − Number of Outputs Conducting Simultaneously Figure 7 Figure 8 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE r DS(on) − Static Drain-Source On-State Resistance − Ω r DS(on) − Static Drain-Source On-State Resistance − Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 2 VCC = 5 V See Note A 1.75 TC = 125°C 1.5 Current Limit 1.25 TC = 25°C 1 0.75 TC = − 40°C 0.5 0.25 0 0 0.2 0.4 d = 20% 0.7 0.6 0.8 1 1.2 2 1.75 TC = 125°C 1.5 1.25 TC = 25°C 1 0.75 TC = − 40°C 0.5 0.25 ID = 350 mA See Note A 0 4 5 6 7 VCC − Logic Supply Voltage − V ID − Drain Current − A Figure 9 Figure 10 NOTE A: Technique should limit TJ − TC to 10°C maximum. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 9 
    
 
   SLIS004B − APRIL 1993 − REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS SWITCHING TIME vs CASE TEMPERATURE 140 ID = 350 mA See Note A Switching Time − ns 120 tPLH 100 80 tr 60 tPHL 40 tf 20 − 50 0 50 100 150 TC − Case Temperature − °C NOTE A: Technique should limit TJ − TC to 10°C maximum. Figure 11 THERMAL INFORMATION NE PACKAGE TRANSIENT THERMAL IMPEDANCE vs ON TIME The single-pulse curve represents measured data. The curves for various pulse durations are based on the following equation: Z θJA− Transient Thermal Impedance − ° C /W 100 Zq d = 50% Where: d = 20% 10 JA + Ť tt Ť Rq JA ) Ť 1 – tw tc Ť Z q ǒt w ) t c Ǔ ) Z qǒt wǓ–Z qǒt cǓ Z qǒt wǓ = the single-pulse thermal impedance for t = tw seconds d = 10% d = 5% Z qǒt cǓ = the single-pulse thermal impedance for t = tc seconds d = 2% Z qǒt w ) t cǓ = the single-pulse thermal impedance for t = tw + tc seconds 1 d = tw/tc tc Single Pulse 0.1 0.001 0.01 tw 0.1 1 10 100 1000 Figure 12 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • ID 0 t − On Time − s 10 w c PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPIC6A259DW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC6A259 TPIC6A259DWG4 ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC6A259 TPIC6A259DWRG4 ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC6A259 TPIC6A259NE ACTIVE PDIP NE 20 20 RoHS & Non-Green NIPDAU N / A for Pkg Type -40 to 125 TPIC6A259NE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of