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SLIS115D – APRIL 2005–REVISED FEBRUARY 2008
FEATURES
APPLICATIONS
Eight Low-Side Drivers With Internal Clamp for
Inductive Loads and Current Limiting for Self
Protection
– Seven Outputs Rated at 150 mA and
Controlled Through Serial Interface
– One Output Rated at 150 mA and
Controlled Through Serial Interface and
Dedicated Enable Pin
5-V ± 5% Regulated Power Supply With
200-mA Load Capability at VIN Max of 18 V
Internal Voltage Supervisory for Regulated
Output
Serial Communications for Control of Eight
Low-Side Drivers
Enable/Disable Input for OUT1
5-V or 3.3-V I/O Tolerant for Interface to
Microcontroller
Programmable Power-On Reset Delay Before
RST Asserted High, Once 5 V Is Within
Specified Range (6 ms Typ)
Programmable Deglitch Timer Before RST
Asserted Low (40 Qs Typ)
Zero-Voltage Detection Signal
Thermal Shutdown for Self Protection
1
2
Electrical Appliances
– Air Conditioning Units
– Ranges
– Dishwashers
– Refrigerators
– Microwaves
– Washing Machines
General-Purpose Interface Circuits, Allowing
Microcontroller Interface to Relays, Electric
Motors, LEDs, and Buzzers
>:7
398
398
398
398
398
398
398
398
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7=2
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DESCRIPTION/ORDERING INFORMATION
The power supply provides regulated 5-V output to power the system microcontroller and drive eight low-side
switches. The ac zero-detect circuitry is monitoring the crossover voltage of the mains ac supply. The resultant
signal is a low-frequency clock output on the ZVS terminal, based on the ac-line cycle. This information allows
the microcontroller to reduce in-rush current by powering loads on the ac-line peak voltage.
A serial communications interface controls the eight low-side outputs; each output has an internal snubber circuit
to absorb the energy in the inductor at turn OFF. Alternatively, the system can use a fly-back diode to V IN to help
recirculate the energy in an inductive load at turn OFF.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
PDIP – N
–40C to 125C
(1)
(2)
PowerPAD™ – PWP
ORDERABLE PART NUMBER
Tube of 20
TPIC9201N
Reel of 2000
TPIC9201PWPR
Tube of 70
TPIC9201PWP
TOP-SIDE MARKING
TPIC9201N
IC9201
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2008, Texas Instruments Incorporated
[[[XMGSQ
SLIS115D – APRIL 2005– REVISED FEBRUARY 2008
PINOUT CONFIGURATION
NO.
NAME
I/O
1
ZVS
O
Zero-voltage synchronization
2
OUT1
O
Low-side output 1
3
OUT2
O
Low-side output 2
4
OUT3
O
Low-side output 3
5
OUT4
O
Low-side output 4
6
OUT5
O
Low-side output 5
7
OUT6
O
Low-side output 6
8
OUT7
O
Low-side output 7
9
OUT8
O
Low-side output 8
(1)
GND
I
Ground
11 (1)
GND
I
Ground
12
EN1
I
Enable/disable for OUT1
10
(1)
(2)
2
DESCRIPTION
13
RDELAY
O
Power-up reset delay
14 (2)
RST
I/O
Power-on reset output (open drain, active low)
15
MOSI
I
Serial data input
Chip select
16
NCS
I
17
SCLK
I
Serial clock for data synchronization
18
5VOUT
O
Regulated output
19
VIN
I
Unregulated input voltage source
20
SYN
I
AC zero detect input
Terminals 10 and 11 are fused internally in the lead frame for the 20-pin PDIP package.
Terminal 14 can be used as an input or an output.
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[[[XMGSQ
SLIS115D – APRIL 2005–REVISED FEBRUARY 2008
FUNCTIONAL BLOCK DIAGRAM
A.
The resistor and Zener diode are required if there is insufficient thermal-management allocation.
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3
[[[XMGSQ
SLIS115D – APRIL 2005– REVISED FEBRUARY 2008
DETAILED DESCRIPTION
The 5-V regulator is powered from VIN, and the regulated output is within 5 V ± 5% over the operating conditions.
The open-drain power-on reset (RST) pin remains low until the regulator exceeds the set threshold, and the timer
value set by the capacitor on the reset delay (RDELAY) pin expires. If both of these conditions are satisfied, RST is
asserted high. This signifies to the microcontroller that serial communications can be initiated to the TPIC9201.
The serial communications is an 8-bit format, with data transfer synchronized using a serial clock from the
microcontroller. A single register controls all the outputs (one bit per output). The default value is zero (OFF). If
an output requires pulse width modulation (PWM) function, the register must be updated at a rate faster than the
desired PWM frequency. OUT1 can be controlled by serial input from the microcontroller or with the dedicated
enable (EN1) pin. If EN1 is pulled low or left open, the serial input through the shift register controls OUT1. If
EN1 is pulled high, OUT1 always is turned on, and the serial input for OUT1 is ignored.
The SYN input translates the image of the mains voltage through the secondary of the transformer. The SYN
input has a resistor to protect from high currents into the IC. The zero-voltage synchronization output translates
the ac-line cycle frequency into a low-frequency clock, which can be used for a timing reference and to help
power loads on the ac-line peak voltage (to reduce in-rush currents).
If RST is asserted, all outputs are turned OFF internally, and the input register is reset to all zeroes. The
microcontroller must write to the register to turn the outputs ON again.
4
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[[[XMGSQ
SLIS115D – APRIL 2005–REVISED FEBRUARY 2008
Absolute Maximum Ratings (1)
MIN
(3)
VIN
24
SYN
24
VI(unreg)
Unregulated input voltage (2)
VI(logic)
Logic input voltage (2)
VO
Low-side output voltage
OUT1–OUT8
ILIMIT
Output current limit (4)
OUTn = ON and shorted to VIN
with low impedance
UJA
Thermal impedance, junction to ambient (5)
UJC
Thermal impedance, junction to case (5)
UJP
Thermal impedance, junction to thermal pad (5)
(3)
PD
Continuous power dissipation (6)
ESD
Electrostatic discharge (7)
TA
Operating ambient temperature range
Tstg
Storage temperature range
Tlead
Lead temperature
(1)
(2)
(3)
(4)
(5)
(6)
(7)
MAX
EN1, MOSI, SCLK, and NCS
7
RST and RDELAY
7
UNIT
V
V
16.5
V
350
mA
N package
69
PWP package
33
N package
54
PWP package
20
PWP package
1.4
N package
1.8
PWP package
3.7
C/W
C/W
C/W
W
2
kV
–40
125
C
–65
125
C
260
C
Soldering, 10 s
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND.
Absolute negative voltage on these pins must not go below –0.5 V.
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed 1 ms.
The thermal data is based on using 1-oz copper trace with JEDEC 51-5 test board for PWP and JEDEC 51-7 test board for N.
The data is based on ambient temperature of 25C max.
The Human-Body Model is a 100-pF capacitor discharged through a 1.5-k resistor into each pin.
Dissipation Ratings
PACKAGE
TA 25C
POWER RATING
DERATING FACTOR
ABOVE TA = 25C
TA = 125C
POWER RATING
N
PWP
1812 mW
14.5 mW/C
362 mW
3787 mW
30.3 mW/C
757 mW
Recommended Operating Conditions
VI(unreg)
Unregulated input voltage
VI(logic)
Logic input voltage
TA
Operating ambient temperature
MIN
MAX
VIN
7
18
SYN
0
18
0
5.25
V
–40
125
C
EN1, MOSI, SCLK, NCS, RST, and RDELAY
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UNIT
V
5
[[[XMGSQ
SLIS115D – APRIL 2005– REVISED FEBRUARY 2008
Electrical Characteristics
TA = –40C to 125C, VIN = 7 V to 18 V (unless otherwise noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
MAX
UNIT
Supply Voltage and Current
VIN (2)
Input voltage
IVIN
Input supply current
7
18
Enable = ON, OUT1–OUT8 = Off
3
Enable = ON, OUT1–OUT8 = On
5
V
mA
Logic Inputs (MOSI, NCS, SCLK, and EN1)
VIL
Logic input low level
IIL = 100 QA
VIH
Logic input high level
IIL = 100 QA
Low-level logic output
IOL = 1.6 mA
0.8
2.4
V
Reset (RST)
VOL
(3)
High-level logic output
5-k
VH
Disabling reset threshold
5-V regulator ramps up
VL
Enabling reset threshold
5-V regulator ramps down
VHYS
Threshold hysteresis
VOH
pullup to VCC
0.4
V
4.5
V
VCC – 0.8
V
4.25
3.3
3.75
V
0.12
0.5
V
18
28
Reset Delay (RDELAY)
IOUT
Output current
TDW
Reset delay timer
C = 47 nF
6
ms
TUP
Reset capacitor to low level
C = 47 nF
45
Qs
0.4
3
48
QA
Output (OUT1–OUT8)
VOL
Output ON
IOUTn = 150 mA
IOH
Output leakage
VOH = Max of 16.5 V
0.7
V
2
QA
5.25
V
Regulator Output (5VOUT)
5VOUT
Output supply
I5VOUT = 5 mA to 200 mA, VIN = 7 V to 18 V,
C5VOUT = 1 QF
4.75
I5VOUT limit
Output short-circuit current
5VOUT = 0 V
200
5
mA
Thermal Shutdown
TSD
Thermal shutdown
THYS
Hysteresis
150
C
20
C
Zero Voltage Synchronization (ZVS)
VSYNTH
Transition threshold
ISYN
Input activating current
RZV = 10 k , VSYN = 24 V
tD
Transition time
Rising and falling
(1)
(2)
(3)
6
0.4
0.75
1.1
2
10
V
mA
Qs
All typical values are at TA = 25C.
There are external high-frequency noise-suppression capacitors and filter capacitors on VIN.
VCC is the pullup resistor voltage.
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[[[XMGSQ
SLIS115D – APRIL 2005–REVISED FEBRUARY 2008
Output Control Register
MSB
LSB
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
0
0
0
0
0
0
0
0
INn = 0: Output OFF
INn = 1: Output ON
To operate the output in PWM mode, the output control register must be updated at a rate twice the desired
PWM frequency of the output. Maximum PWM frequency is 5 kHz. The register is updated every 100 Qs.
ENABLE TRUTH TABLE
EN1
SERIAL INPUT
FOR OUT1
OUT1
Open
H
On
Open
L
Off
L
H
On
L
L
Off
H
H
On
H
L
On
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7
[[[XMGSQ
SLIS115D – APRIL 2005– REVISED FEBRUARY 2008
Serial Communications Interface
The serial communications is an 8-bit format, with data transfer synchronized using a serial clock from the
microcontroller (see Figure 1). A single register controls all the outputs. The signal gives the instruction to control
the output of TPIC9201.
The NCS signal enables the SCLK and MOSI data when it is low. After NCS is set low for T 1, synchronization
clock and data begin to transmit and, after the 8-bit data has been transmitted, NCS is set high again to disable
SCLK and MOSI and transfer the serial data to the control register. SCLK must be held low when NCS is in the
high state.
Figure 1. Serial Communications
8
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[[[XMGSQ
SLIS115D – APRIL 2005–REVISED FEBRUARY 2008
Timing Requirements
TA = –40C to 125C, VIN = 7 V to 18 V (unless otherwise noted)
MIN
TYP
MAX
4
UNIT
fSPI
SPI frequency
T1
Delay time, NCS falling edge to SCLK rising edge
10
MHz
ns
T2
Delay time, NCS falling edge to SCLK falling edge
80
ns
T3
Pulse duration, SCLK high
60
ns
T4
Pulse duration, SCLK low
60
ns
T5
Delay time, last SCLK falling edge to NCS rising edge
80
ns
T6
Setup time, MOSI valid before SCLK edge
10
ns
T7
Hold time, MOSI valid after SCLK edge
10
ns
T8
Time between two words for transmitting
170
ns
Reset Delay (RDELAY)
The RDELAY output provides a constant current source to charge an external capacitor to approximately 6.5 V.
The external capacitor is selected to provide a delay time, based on the current equation for a capacitor,
I = C( v/ t) and a 28-QA typical output current.
Therefore, the user should select a 47-nF capacitor to provide a 6-ms delay at 3.55 V.
I = C( v/ t)
28 QA = C (3.55 V/6 ms)
C = 47 nF
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9
[[[XMGSQ
SLIS115D – APRIL 2005– REVISED FEBRUARY 2008
APPLICATION INFORMATION
Figure 2. Typical Application
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0)( 0)(
;EXIV
7YTTP]
:EPZI
*MPXIVW
;EXIV
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7YTTP]
:SPYQI
7IRWSV
1
4S[IV
7[MXGL
'SRXVSPPIV
;EXIV0IZIP
7IRWSV
(VMZIV
3TXMGEP
7IRWSV
7=2
:-2
b
>:7
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(IXIGXMSR
6IKYPEXSV
b
4367=7
8IQTIVEXYVI
7IRWSV
3TXMSREP
:398
678
'SZIV
7[MXGL
84-'
Figure 3. Washing-Machine Application
10
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[[[XMGSQ
SLIS115D – APRIL 2005–REVISED FEBRUARY 2008
PCB Layout
To maximize the efficiency of this package for application on a single-layer or multilayer PCB, certain guidelines
must be followed when laying out this part on the PCB.
The following information is to be used as a guideline only.
For further information, see the PowerPAD concept implementation document.
Application Using a Multilayer PCB
In a multilayer board application, the thermal vias are the primary method of heat transfer from the package
thermal pad to the internal ground plane (see Figure 4 and Figure 5).
The efficiency of this method depends on several factors: die area, number of thermal vias, thickness of copper,
etc. (see the PowerPAD™ Thermally Enhanced Package Technical Brief, literature number SLMA002).
Figure 4. Package and PCB Land Configuration for a Multilayer PCB
Figure 5. Multilayer Board (Side View)
Application Using a Single-Layer PCB
In a single-layer board application, the thermal pad is attached to a heat spreader (copper area) by using the low
thermal-impedance attachment method (solder paste or thermal-conductive epoxy). With either method, it is
advisable to use as much copper trace area as possible to dissipate the heat.
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11
[[[XMGSQ
SLIS115D – APRIL 2005– REVISED FEBRUARY 2008
CAUTION:
If the attachment method is not implemented correctly, the functionality of the
product cannot be ensured. Power-dissipation capability is adversely affected if
the device is incorrectly mounted onto the circuit board.
Figure 6. Layout Recommendations for a Single-Layer PCB
12
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[[[XMGSQ
SLIS115D – APRIL 2005–REVISED FEBRUARY 2008
Recommended Board Layout
Figure 7. Recommended Board Layout for PWP
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13
PACKAGE OPTION ADDENDUM
10-Jan-2008
www.ti.com
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPIC9201N
NRND
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPIC9201NE4
NRND
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPIC9201PWP
NRND
HTSSOP
PWP
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPIC9201PWPG4
NRND
HTSSOP
PWP
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPIC9201PWPR
NRND
HTSSOP
PWP
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPIC9201PWPRG4
NRND
HTSSOP
PWP
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
11-Mar-2008
www.ti.com
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPIC9201PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
20
Reel
Reel
Diameter Width
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
6.95
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
11-Mar-2008
www.ti.com
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPIC9201PWPR
HTSSOP
PWP
20
2000
346.0
346.0
33.0
Pack Materials-Page 2
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