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TPL7407LA-Q1
SLRS074 – MAY 2018
TPL7407LA-Q1 30-V 7-Channel Low Side Driver
1 Features
2 Applications
•
•
•
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
600-mA Rated Drain Current (Per Channel)
CMOS Pin-to-Pin Improvement of 7-channel
Darlington Array (For Example: ULN2003A)
Power Efficient (Very low VOL)
– Less Than 4 Times Lower VOL at 100 mA Than
Darlington Array
Very Low Output Leakage < 10 nA Per Channel
High-Voltage Outputs 30 V
Compatible with 1.8-V to 5-V Microcontroller and
Logic Interface
Internal Free-wheeling Diodes for Inductive Kickback Protection
Input Pull-down Resistors Allows Tri-stating the
Input Driver
Input RC-Snubber to Eliminate Spurious
Operation in Noisy Environment
ESD Protection Exceeds JESD 22
– 2-kV HBM, 500-V CDM
•
•
•
Inductive Loads
– Relays
– Unipolar Stepper and Brushed DC Motors
– Solenoids and Valves
LEDs
Logic Level Shifting
Gate and IGBT Drive
3 Description
The TPL7407LA-Q1 is a high-voltage, high-current
NMOS transistor array. This device consists of seven
NMOS transistors that feature high-voltage outputs
with common-cathode clamp diodes for switching
inductive loads. The maximum drain-current rating of
a single NMOS channel is 600 mA. New regulation
and drive circuitry added to give maximum drive
strength across all GPIO ranges (1.8 V–5 V).The
transistors can be paralleled for higher current
capability.
The TPL7407LA-Q1 key benefit is its improved power
efficiency and lower leakage than a Bipolar Darlington
Implementation. With the lower VOL the user is
dissipating less than half the power than traditional
relay drivers with currents less than 250 mA per
channel.
Device Information(1)
PART NUMBER
TPL7407LA-Q1
PACKAGE (PINS)
TSSOP (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simple Application Schematic
VSUP
M
TPL7407LA-Q1
1.8 V Logic
1.8 V Logic
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
24 V
COM
CCOM
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPL7407LA-Q1
SLRS074 – MAY 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes.......................................... 7
8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application .................................................. 11
9 Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
10.3 Thermal Considerations ........................................ 14
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
May 2018
*
Initial release.
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5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
IN1 1
EMF
Clamp
16 OUT1
IN2 2
EMF
Clamp
15 OUT2
IN3 3
EMF
Clamp
14 OUT3
IN4 4
EMF
Clamp
13 OUT4
IN5 5
EMF
Clamp
12 OUT5
IN6 6
EMF
Clamp
11 OUT6
IN7 7
EMF
Clamp
10 OUT7
GND 8
LDO
9 COM
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
COM
9
—
Supply pin that must be tied to 6.5 V or higher for proper operation (see
the Power Supply Recommendations section for more information)
GND
8
—
Ground pin
1
2
3
IN(X)
4
I
GPIO inputs that drives the outputs "low" (or sink current) when driven
"high"
O
Driver output that sinks currents after input is driven "high"
5
6
7
10
11
12
OUT(X)
13
14
15
16
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6 Specifications
6.1 Absolute Maximum Ratings
at 25°C free-air temperature (unless otherwise noted)
VOUT
(1)
Pins OUT1-OUT7 to GND voltage
VOK
Output clamp diode reverse voltage
VCOM
COM pin voltage (2)
VIN
Pins IN1-IN7 to GND voltage
(2)
(2)
MIN
MAX
UNIT
–0.3
32
V
–0.3
32
V
–0.3
32
V
–0.3
30
V
(3) (4)
IDS
Continuous drain current per channel
600
mA
IOK
Output clamp current
500
mA
IGND
Total continuous GND-pin current
–2
A
TJ
Operating virtual junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
(4)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND/substrate pin, unless otherwise noted.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 8, 9, 16)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating temperature range
MIN
MAX
UNIT
0
30
V
6.5
30
V
0.9
V
VOUT
OUT1 – OUT7 pin voltage for recommended operation
VCOM
COM pin voltage range for full output drive
VIL
IN1- IN7 input low voltage ("Off" high impedance output)
VIH
IN1- IN7 input high voltage ("Full Drive" low impedance output)
1.5
TA
Operating free-air temperature
–40
125
°C
IDS
Continuous drain current
0
500
mA
V
6.4 Thermal Information
TPL7407LA-Q1
THERMAL METRIC (1)
TSSOP (PW)
UNIT
16 PINS
θJA
Junction-to-ambient thermal resistance
113.1
°C/W
θJCtop
Junction-to-case (top) thermal resistance
46.5
°C/W
θJB
Junction-to-board thermal resistance
58.6
°C/W
ψJT
Junction-to-top characterization parameter
7
°C/W
ψJB
Junction-to-board characterization parameter
58
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
TJ= –40°C to +125°C; Typical Values at TA= 25°C
PARAMETER
(1)
TEST CONDITIONS
TYP
MAX
ID = 100 mA
210
450
ID = 200 mA
430
900
VOL (VDS)
OUT1- OUT7 low-level output
voltage
VIN ≥ 1.5 V
VIL
IN1- IN7 low-level input voltage
ID = 5 µA
VIH
IN1- IN7 high-level input voltage
ID = 100 mA
IOUT(OFF)
(IDS_OFF)
OUT1- OUT7 OFF-state leakage
current
VOUT = 30 V, VIN ≤ 0.9 V
VF
Clamp forward voltage
IF = 200 mA
IIN(off)
IN1- IN7 Off-state input current
VINX = 0 V
IIN(ON)
IN1- IN7 ON state input current
VINX = 1.5 V – 5 V
ICOM
Static current flowing through
COM pin
VCOM = 6.5 V – 30 V
(1)
MIN
UNIT
mV
0.9
V
1.5
V
10
VOUT = 30 V
17
500
nA
1.4
V
500
nA
10
μA
30
μA
During production testing, device is tested under short duration, therefore TA = TJ.
6.6 Switching Characteristics
Typical Values at TA= 25°C
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low- to high-level output
VINX ≥ 1.65 V, Vpull-up = 30 V, Rpull-up =
48 Ω
tPHL
Propagation delay time, high- to low-level output
VINX ≥ 1.65 V, Vpull-up = 30 V, Rpull-up =
48 Ω
Ci
Input capacitance
VI = 0,
f = 100 kHz
MIN
TYP
MAX
UNIT
350
ns
350
ns
5
pF
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6.7 Typical Characteristics
2.4
500
-40°C
25°C
125°C
2
450
400
350
IF (mA)
VOL (V)
1.6
1.2
300
250
200
0.8
150
100
0.4
50
0
0
100
200
300
400
Output Drain Current IDS (mA)
0
500
0
Figure 1. VOL (VDS)
0.6
0.8
VF (V)
1
1.2
1.4
D002
0.55
N
N
N
N
N
N
N
0.5
0.45
0.4
0.35
0.3
=1
=2
=3
=4
=5
=6
=7
0.25
0.2
0.15
0.1
0.05
0
Maximum Current Per Channel (A)
Maximum Current Per Channel (A)
0.4
Figure 2. Flyback Diode Forward Voltage at 25°C
0.55
N
N
N
N
N
N
N
0.5
0.45
0.4
0.35
0.3
=1
=2
=3
=4
=5
=6
=7
0.25
0.2
0.15
0.1
0.05
0
0
20%
40%
60%
Duty Cycle
80%
100%
0
20%
D007
Figure 3. Maximum Collector Current vs Duty Cycle at 25°C
6
0.2
D001
40%
60%
Duty Cycle
80%
100%
D008
Figure 4. Maximum Collector Current vs Duty Cycle at 70°C
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7 Detailed Description
7.1 Overview
The TPL740LA-Q1 integrates seven low side NMOS transistors that are capable of sinking up to 600 mA and
wide GPIO range capability.
The TPL7407LA-Q1 comprises seven high voltage, high current NMOS transistors tied to a common ground
driven by internal level shifting and gate drive circuitry. The TPL7407LA-Q1 offers solutions to many interface
needs, including solenoids, relays, lamps, small motors, and LEDs. Applications requiring sink currents beyond
the capability of a single output may be accommodated by paralleling the outputs.
The TPL7407LA-Q1 also enables pin to pin replacement with legacy 7 channel darlington pair implementations.
This device can operate over a wide temperature range (–40°C to +125°C).
7.2 Functional Block Diagram
COM
Regulation
Circuitry
OUT(1-7)
50 k
DRIVER
IN(1-7)
1M
OVP
7.3 Feature Description
Each channel of the TPL7407LA-Q1 consists of high power low side NMOS transistors driven by level shifting
and gate driving circuitry. The gate drivers allow for high output current drive with a very low input voltage,
meaning full operation with low GPIO voltages.
In order to enable floating inputs a 1-MΩ pull-down resistor exists on each channel. Another 50-kΩ resistor exists
between the input and gate driving circuitry. This exists to limit the input current whenever there is an over
voltage and the internal Zener clamps. It also interacts with the inherent capacitance of the gate driving circuitry
to behave as an RC snubber to help prevent spurious switching in noisy environment.
In order to power the gate driving circuitry an LDO exists. See the Power Supply Recommendations section for
further detail on this circuitry.
The diodes connected between the output and COM pin is used to suppress kick-back voltage from an inductive
load that is excited when the NMOS drivers are turned off (stop sinking) and the stored energy in the coils
causes a reverse current to flow into the coil supply.
7.4 Device Functional Modes
7.4.1 Inductive Load Drive
When the COM pin is tied to the coil supply voltage, the TPL7407LA-Q1 is able to drive inductive loads and
suppress the kick-back voltage via the internal free wheeling diodes.
7.4.2 Resistive Load Drive
When driving a resistive load, a pull-up resistor is needed in order for the TPL7407LA-Q1 to sink current and for
there to be a logic high level. The COM pin must be supplied ≥ 6.5 V for full functionality.
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Device Functional Modes (continued)
7.4.3 ON State Input Current
The current into the INx pins is defined in the electrical characteristics table for input voltages from 1.5 V to 5 V.
At higher voltages, this leakage increases, and the input current can be estimated using the approximate clamp
voltage for the OVP diode, 6.4 V. Equation 1 shows how to approximate input current for input voltages greater
than 6.4 V:
IIN(ON) = VIN / 1 MΩ + (VIN - 6.4 V) / 50 kΩ
where
•
•
•
•
8
VIN is the input voltage
1 MΩ is the input pull-down resistance
50 kΩ is the input series resistance
6.8 V is the approximate clamp voltage for the OVP diode
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPL7407LA-Q1 is typically used to drive a high voltage and/or current peripheral from an MCU or logic
device that cannot tolerate these conditions. The following design is a common application of the TPL7407LAQ1, driving inductive loads. This includes motors, solenoids and relays. Each load type can be modeled by
what's seen in Figure 7.
8.1.1 Unipolar Stepper Motor Driver
Motor
VSUP
Motor Control Pulses
(1.8 V to 5 V)
TPL7407LA-Q1
IN1
OUT1
Phase_A
IN2
OUT2
Phase_C
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
Phase_B
Optional
Phase_D
COM
CCOM
Figure 5. Stepper Motor Driver Schematic
Figure 5 shows an implementation of the TPL7407LA-Q1 for driving a uniploar stepper motor. The unconnected
input channels can be used for other functions. When an input pin is left open the internal 1-MΩ pull down
resistor pulls the respective input pin to GND potential. For higher noise immunity use an external short across
an unconnected input and GND pins. The COM pin must be tied to the supply of whichever inductive load is
being driven for the driver to be protected by the free-wheeling diode.
For more information on this application, see the Stepper Motor Driving With Peripheral Drivers (Driver ICs)
application report.
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Application Information (continued)
8.1.2 Multi-Purpose Sink Driver
VSUP
M
TPL7407LA-Q1
1.8 V Logic
1.8 V Logic
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
24 V
COM
CCOM
Figure 6. Multi-Purpose Sink Driver Schematic
When configured as per Figure 6, the TPL7407LA-Q1 may be used as a multi-purpose driver. The output
channels may be tied together to sink more current. The TPL7407LA-Q1 can easily drive motors, relays and
LEDs with little power dissipation. COM must be tied to highest load voltage, which may or may not be same as
inductive load supply.
10
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8.2 Typical Application
A common application for the TPL7407LA-Q1 is driving inductive loads such as relays, solenoids, and unipolar
stepper motors.
12 V
TPL7407LA-Q1
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
1.8 V Logic
Simultaneous operation
is limited or enabled by
relay resistance, coil
voltage and temperature
1.8 V Logic
GND
12 V
COM
CCOM
Figure 7. Inductive Load Driver Schematic
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
GPIO Voltage
1.8 V, 3.3 V or 5 V
Coil supply voltage
6.5 V to 30 V
Number of channels
7
Output current (RCOIL)
20 mA to 300 mA per channel
CCOM
0.1 µF
Duty cycle
100%
8.2.2 Detailed Design Procedure
When using the TPL7407LA-Q1 in a coil driving application, determine the following:
• Input Voltage Range
• Temperature Range
• Output & Drive Current
• Power Dissipation
8.2.2.1 TTL and other Logic Inputs
The TPL7407LA-Q1 input interface is specified for standard 1.8 V through 5 V CMOS logic interface and can
tolerate up to 30 V. At any input voltage the output drivers is going to be driven at its maximum when VCOM is
greater than or equal to 6.5 V.
8.2.2.2 Input RC Snubber
The TPL7407LA-Q1 features an input RC snubber that helps prevent spurious switching in noisy environments.
Connect an external 1 kΩ to 5 kΩ resistor in series with the input to further enhance the TPL7407LA-Q1’s noise
tolerance.
8.2.2.3 High-Impedance Input Drivers
The TPL7407LA-Q1 features a 1-MΩ input pull-down resistor. The presence of this resistor allows the input
drivers to be tri-stated. When a high-impedance driver is connected to a channel input the TPL7407LA-Q1
detects the channel input as a low level input and remains in the OFF position. The input RC snubber helps
improve noise tolerance when input drivers are in the high-impedance state.
8.2.2.4 Drive Current
The coil current is determined by the coil voltage (VSUP), coil resistance & output low voltage (VOL) as shown in
Equation 2.
ICOIL= (VSUP - VOL)/RCOIL
(2)
8.2.2.5 Output Low Voltage
The output low voltage (VOL) is drain to source (VDS) voltage of the output NMOS transistors when the input is
driven high and it is sinking current and can be determined by the Electrical Characteristics section or Figure 1.
12
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8.2.3 Application Curve
Figure 8 was generated with TPL7407LA-Q1 driving an OMRON G5NB relay -- Vin = 5 V; Vsup = 12 V & RCOIL =
2.8 kΩ
Figure 8. Output Response With De-Activation of Coil (Turnoff)
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9 Power Supply Recommendations
The COM pin is the power supply pin of this device to power the gate drive circuitry. While a bypass capacitor on
this pin is recommended for sensitive power supplies, it is not required for proper operation of the device. The
COM pin supply ensures full drive potential with any GPIO above 1.5 V. The gate drive circuitry is based on low
voltage CMOS transistors that can only handle a max gate voltage of 7 V. An integrated LDO reduces the COM
voltage of 6.5 V to 30 V to a regulated voltage of 5.3 V. Though 6.5 V minimum is recommended for VCOM, the
part still functions with a reduced COM voltage that has a reduced gate drive voltage and a resulting higher
Rdson.
10 Layout
10.1 Layout Guidelines
Thin traces can be used on the input due to the low current logic that is typically used to drive the TPL7407LAQ1. Care must be taken to separate the input channels as much as possible, as to eliminate cross-talk. Thick
traces are recommended for the output, in order to drive whatever high currents that may be needed. Wire
thickness can be determined by the trace material's current density and desired drive current.
Since all of the channels currents return to a common ground, it is best to size that trace width to be very wide.
Some applications require up to 2 A.
Since the COM pin only draws up to 30 µA, thick traces are not necessary.
10.2 Layout Example
TPL7407LA-Q1
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN4
OUT4
IN5
OUT5
IN6
OUT6
IN7
OUT7
GND
COM
GND
CCOM
Only needed
for fluctuating
supplies
GND
Figure 9. Package Layout
10.3 Thermal Considerations
The number of coils driven is dependent on the coil current and on-chip power dissipation. The number of coils
driven can be determined by Figure 3 or Figure 4.
14
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Thermal Considerations (continued)
For a more accurate determination of number of coils possible, use Equation 3 to calculate TPL7407LA-Q1 onchip power dissipation PD:
N
PD = å VOLi ´ ILi
i=1
where
•
•
N is the number of channels active together
VOLi is the OUTi pin voltage for the load current ILi. This is the same as VCE(SAT)
(3)
In order to guarantee reliability of TPL7407LA-Q1 and the system, the on-chip power dissipation must be lower
than or equal to the maximum allowable power dissipation (PD(MAX)) dictated by below equation Equation 4.
PD MAX
TJ MAX
TA
TJA
where
•
•
•
TJ(MAX) is the target maximum junction temperature
TA is the operating ambient temperature
θJA is the package junction to ambient thermal resistance
(4)
It is recommended to limit rhe TPL7407LA-Q1 IC’s die junction temperature to less than 125°C. The IC junction
temperature is directly proportional to the on-chip power dissipation.
10.3.1 Improving Package Thermal Performance
θJA value depends on the PC board layout. An external heat sink and/or a cooling mechanism, like a cold air fan,
can help reduce θJA and thus improve device thermal capabilities. Refer to TI’s design support web page at
www.ti.com/thermal for a general guidance on improving device thermal performance.
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TPL7407LA-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPL7407LAQPWRQ1
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
TPL747LAQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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