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TPS2041B, TPS2042B, TPS2043B, TPS2044B
TPS2051B, TPS2052B, TPS2053B, TPS2054B
SLVS514M – JUNE 2010 – REVISED JUNE 2016
TPS20xxB Current-Limited, Power-Distribution Switches
1 Features
3 Description
•
•
•
•
The TPS20xxB power-distribution switches are
intended for applications where heavy capacitive
loads and short circuits are likely to be encountered.
These devices incorporates 70-mΩ N-channel
MOSFET power switches for power-distribution
systems that require multiple power switches in a
single package. Each switch is controlled by a logic
enable input. Gate drive is provided by an internal
charge pump designed to control the power-switch
rise times and fall times to minimize current surges
during switching. The charge pump requires no
external components and allows operation from
supplies as low as 2.7 V.
1
•
•
•
•
•
•
•
•
•
70-mΩ High-Side MOSFET
500-mA Continuous Current
Thermal and Short-Circuit Protection
Accurate Current Limit
(0.75 A Minimum, 1.25 A Maximum)
Operating Range: 2.7 V to 5.5 V
0.6-ms Typical Rise Time
Undervoltage Lockout
Deglitched Fault Report (OC)
No OC Glitch During Power Up
Maximum Standby Supply Current:
1-μA (Single, Dual) or 2-μA (Triple, Quad)
Ambient Temperature Range: –40°C to 85°C
UL Recognized, File Number E169910
Additional UL Recognition for TPS2042B and
TPS2052B for Ganged Configuration
When the output load exceeds the current-limit
threshold or a short is present, the device limits the
output current to a safe level by switching into a
constant-current mode, pulling the overcurrent (OCx)
logic output low. When continuous heavy overloads
and short circuits increase the power dissipation in
the switch, causing the junction temperature to rise, a
thermal protection circuit shuts off the switch to
prevent damage. Recovery from a thermal shutdown
is automatic once the device has cooled sufficiently.
Internal circuitry ensures that the switch remains off
until valid input voltage is present. This powerdistribution switch is designed to set current limit at 1
A (typical).
2 Applications
•
•
Heavy Capacitive Loads
Short-Circuit Protections
Device Information(1)
PART NUMBER
TPS20xxB
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
SOIC (16)
9.90 mm × 3.91 mm
SOT-23 (5)
2.90 mm × 1.60 mm
HVSSOP (8)
3.00 mm × 3.00 mm
SON (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
TPS2042B
2
Power Supply
2.7 V to 5.5 V
IN
OUT1
0.1 µF
8
3
5
4
7
Load
0.1 µF
22 µF
0.1 µF
22 µF
OC1
EN1
OUT2
OC2
6
Load
EN2
GND
1
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2041B, TPS2042B, TPS2043B, TPS2044B
TPS2051B, TPS2052B, TPS2053B, TPS2054B
SLVS514M – JUNE 2010 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
General Switch Catalog.........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
1
1
1
2
4
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings ............................................................ 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Dissipation Ratings ................................................... 9
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 14
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
9.2 Functional Block Diagrams ..................................... 15
9.3 Feature Description................................................. 19
9.4 Device Functional Modes........................................ 20
10 Application and Implementation........................ 21
10.1 Application Information.......................................... 21
10.2 Typical Application ................................................ 21
11 Power Supply Recommendations ..................... 35
11.1 Undervoltage Lockout (UVLO) .............................. 35
12 Layout................................................................... 35
12.1
12.2
12.3
12.4
Layout Guidelines .................................................
Layout Example ....................................................
Power Dissipation .................................................
Thermal Protection................................................
35
35
35
36
13 Device and Documentation Support ................. 37
13.1
13.2
13.3
13.4
13.5
13.6
Receiving Notification of Documentation Updates
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
37
37
14 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (June 2011) to Revision M
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 7
Changes from Revision K (June 2010) to Revision L
Page
•
Added note to General Switch Catalog link at www.ti.com .................................................................................................... 4
•
Added IOC spec to the ELEC CHARA TABLE ........................................................................................................................ 8
•
Deleted Not tested in production, specified by design. note 2 in ELECTRICAL CHARA TABLE.......................................... 8
Changes from Revision J (December 2008) to Revision K
•
Page
Deleted Electrical Char Table note - Estimated value. Final value pending characterization................................................ 9
Changes from Revision I (October 2008) to Revision J
Page
•
Deleted Product Preview from the DRB package .................................................................................................................. 1
•
Deleted Electrical Char Table note - This configuration has not been tested for UL certification.......................................... 9
Changes from Revision H (September 2007) to Revision I
Page
•
Added Featured Bullet: Additional UL Recognition.. .............................................................................................................. 1
•
Added DRB-8 pinout package. ............................................................................................................................................... 1
•
Added DRB-8 to the Dissipation Rating Table. ...................................................................................................................... 9
2
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B, TPS2043B, TPS2044B
TPS2051B, TPS2052B, TPS2053B, TPS2054B
www.ti.com
SLVS514M – JUNE 2010 – REVISED JUNE 2016
Changes from Revision G (OCTOBER 2006) to Revision H
•
Page
Updated the General Switch Catalog table ............................................................................................................................ 4
Changes from Revision F (June 2006) to Revision G
Page
•
Deleted Product Preview from the DBV package................................................................................................................... 1
•
Added TPS2060 1.5 A and TPS2064 1.5 A to the General Switch Catalog table ................................................................. 4
•
Added the DBV PACKAGE to the Terminal Functions table.................................................................................................. 5
•
Added D, DGN and DBV package options to the rDS(on) Test Condition ............................................................................... 8
Copyright © 2010–2016, Texas Instruments Incorporated
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Product Folder Links: TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
3
TPS2041B, TPS2042B, TPS2043B, TPS2044B
TPS2051B, TPS2052B, TPS2053B, TPS2054B
SLVS514M – JUNE 2010 – REVISED JUNE 2016
www.ti.com
5 General Switch Catalog
GENERAL SWITCH CATALOG
33 mW, Single
TPS201xA
TPS202x
TPS203x
80 mW, Single
TPS2014
TPS2015
TPS2041B
TPS2051B
TPS2045A
TPS2049
TPS2055A
TPS2061
TPS2065
TPS2068
TPS2069
0.2 A to 2 A
0.2 A to 2 A
0.2 A to 2 A
600 mA
1A
500 mA
500 mA
250 mA
100 mA
250 mA
1A
1A
1.5 A
1.5 A
80 mW, Dual
TPS2042B
TPS2052B
TPS2046B
TPS2056
TPS2062
TPS2066
TPS2060
TPS2064
500 mA
500 mA
250 mA
250 mA
1A
1A
1.5 A
1.5 A
80 mW, Dual
TPS2080
TPS2081
TPS2082
TPS2090
TPS2091
TPS2092
500 mA
500 mA
500 mA
250 mA
250 mA
250 mA
80 mW, Triple
TPS2043B
TPS2053B
TPS2047B
TPS2057A
TPS2063
TPS2067
500 mA
500 mA
250 mA
250 mA
1A
1A
80 mW, Quad
TPS2044B
TPS2054B
TPS2048A
TPS2058
80 mW, Quad
500 mA
500 mA
250 mA
250 mA
TPS2085
TPS2086
TPS2087
TPS2095
TPS2096
TPS2097
500 mA
500 mA
500 mA
250 mA
250 mA
250 mA
See TI Switch Portfolio at http://www.ti.com/usbpower
6 Pin Configuration and Functions
TPS2041B and TPS2051B: DBV Package
5-Pin SOT-23
Top View
OUT
IN
GND
OC
EN
†
† All enable outputs are active high for the
TPS205xB series.
TPS2041B and TPS2051B: D and DGN Packages
8-Pin SOIC and HVSSOP
Top View
GND
IN
IN
EN†
1
8
2
7
3
6
4
5
OUT
OUT
OUT
OC
† All enable outputs are active high for the
TPS205xB series.
TPS2042B and TPS2052B: D and DGN Packages
8-Pin SOIC and HVSSOP
Top View
GND
IN
TPS2042B and TPS2052B: DRB Package
8-Pin SON
Top View
1
8
2
7
EN1†
3
6
EN2†
4
5
OC1
OUT1
OUT2
OC2
† All enable outputs are active high for the
TPS205xB series.
GND
1
8
OC1
IN
2
7
OUT1
EN1†
3
6
OUT2
EN2†
4
5
OC2
† All enable outputs are active high for the
TPS205xB series.
TPS2043B and TPS2053B: D Package
16-Pin SOIC
Top View
GND
IN1
EN1†
1
16
2
15
3
14
EN2†
GND
IN2
EN3†
4
13
5
12
NC
6
11
7
10
8
9
OC1
OUT1
OUT2
OC2
OC3
OUT3
NC
NC
† All enable outputs are active high for the
TPS205xB series.
TPS2044B and TPS2054B: D Package
16-Pin SOIC
Top View
GND
IN1
EN1†
1
16
2
15
3
14
EN2†
GND
IN2
EN3†
4
13
5
12
EN4†
6
11
7
10
8
9
OC1
OUT1
OUT2
OC2
OC3
OUT3
OUT4
OC4
† All enable outputs are active high for the
TPS205xB series.
4
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Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B, TPS2043B, TPS2044B
TPS2051B, TPS2052B, TPS2053B, TPS2054B
www.ti.com
SLVS514M – JUNE 2010 – REVISED JUNE 2016
Pin Functions (TPS2041B and TPS2051B)
PIN
NAME
TPS2041B
TPS2051B
TPS2041B
SOIC AND DGN
TPS2051B
EN
4
—
4
—
EN
—
4
—
GND
1
1
2
IN
2, 3
2, 3
OC
5
6, 7, 8
OUT
I/O
DESCRIPTION
SOT-23
I
Enable input, logic low turns on power switch
4
I
Enable input, logic high turns on power switch
2
—
5
5
I
Input voltage
5
3
3
O
Overcurrent open-drain output, active-low
6, 7, 8
1
1
O
Power-switch output
Ground
Pin Functions (TPS2042B and TPS2052B)
PIN
NAME
EN1
TPS2042B
TPS2052B
I/O
DESCRIPTION
SOIC, HVSSOP, SON
3
—
I
Enable input, logic low turns on power switch IN-OUT1
EN2
4
—
I
Enable input, logic low turns on power switch IN-OUT2
EN1
—
3
I
Enable input, logic high turns on power switch IN-OUT1
EN2
—
4
I
Enable input, logic high turns on power switch IN-OUT2
GND
1
1
—
IN
2
2
I
Input voltage
OC1
8
8
O
Overcurrent, open-drain output, active low, IN-OUT1
OC2
5
5
O
Overcurrent, open-drain output, active low, IN-OUT2
OUT1
7
7
O
Power-switch output, IN-OUT1
OUT2
6
6
O
Power-switch output, IN-OUT2
PowerPAD
™
—
—
—
Internally connected to GND; used to heat-sink the part to the circuit board
traces. Should be connected to GND pin.
Ground
Pin Functions (TPS2043B and TPS2053B)
PIN
TPS2043B
TPS2053B
SOIC
SOIC
EN1
3
—
I
Enable input, logic low turns on power switch IN1-OUT1
EN2
4
—
I
Enable input, logic low turns on power switch IN1-OUT2
EN3
7
—
I
Enable input, logic low turns on power switch IN2-OUT3
EN1
—
3
I
Enable input, logic high turns on power switch IN1-OUT1
EN2
—
4
I
Enable input, logic high turns on power switch IN1-OUT2
Enable input, logic high turns on power switch IN2-OUT3
NAME
I/O
DESCRIPTION
EN3
—
7
I
GND
1, 5
1, 5
—
2
2
I
Input voltage for OUT1 and OUT2
Input voltage for OUT3
IN1
Ground
IN2
6
6
I
NC
8, 9, 10
8, 9, 10
—
No connection
OC1
16
16
O
Overcurrent, open-drain output, active low, IN1-OUT1
OC2
13
13
O
Overcurrent, open-drain output, active low, IN1-OUT2
OC3
12
12
O
Overcurrent, open-drain output, active low, IN2-OUT3
OUT1
15
15
O
Power-switch output, IN1-OUT1
OUT2
14
14
O
Power-switch output, IN1-OUT2
OUT3
11
11
O
Power-switch output, IN2-OUT3
Copyright © 2010–2016, Texas Instruments Incorporated
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TPS2041B, TPS2042B, TPS2043B, TPS2044B
TPS2051B, TPS2052B, TPS2053B, TPS2054B
SLVS514M – JUNE 2010 – REVISED JUNE 2016
www.ti.com
Pin Functions (TPS2044B and TPS2054B)
PIN
TPS2044B
TPS2054B
SOIC
SOIC
EN1
3
—
I
Enable input, logic low turns on power switch IN1-OUT1
EN2
4
—
I
Enable input, logic low turns on power switch IN1-OUT2
EN3
7
—
I
Enable input, logic low turns on power switch IN2-OUT3
EN4
8
—
I
Enable input, logic low turns on power switch IN2-OUT4
EN1
—
3
I
Enable input, logic high turns on power switch IN1-OUT1
EN2
—
4
I
Enable input, logic high turns on power switch IN1-OUT2
EN3
—
7
I
Enable input, logic high turns on power switch IN2-OUT3
EN4
—
8
I
Enable input, logic high turns on power switch IN2-OUT4
GND
NAME
I/O
DESCRIPTION
1, 5
1, 5
—
IN1
2
2
I
Input voltage for OUT1 and OUT2
IN2
6
6
I
Input voltage for OUT3 and OUT4
OC1
16
16
O
Overcurrent, open-drain output, active low, IN1-OUT1
OC2
13
13
O
Overcurrent, open-drain output, active low, IN1-OUT2
OC3
12
12
O
Overcurrent, open-drain output, active low, IN2-OUT3
OC4
9
9
O
Overcurrent, open-drain output, active low, IN2-OUT4
OUT1
15
15
O
Power-switch output, IN1-OUT1
OUT2
14
14
O
Power-switch output, IN1-OUT2
OUT3
11
11
O
Power-switch output, IN2-OUT3
OUT4
10
10
O
Power-switch output, IN2-OUT4
6
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Ground
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: TPS2041B TPS2042B TPS2043B TPS2044B TPS2051B TPS2052B TPS2053B TPS2054B
TPS2041B, TPS2042B, TPS2043B, TPS2044B
TPS2051B, TPS2052B, TPS2053B, TPS2054B
www.ti.com
SLVS514M – JUNE 2010 – REVISED JUNE 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VI(IN), VI(INx)
Input voltage
VO(OUT), VO(OUTx)
(2)
(1)
(2)
MIN
MAX
UNIT
–0.3
6
V
Output voltage
–0.3
6
V
VI(EN), VI(ENx), VI(EN),
VI(ENx)
Input voltage
–0.3
6
V
VI(/OC), VI(OCx)
Voltage range
–0.3
6
V
IO(OUT), IO(OUTx)
Continuous output current
Internally limited
Continuous total power dissipation
See Dissipation Ratings
TJ
Operating virtual junction temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VI(IN), VI(INx)
Input voltage
2.7
5.5
V
VI(EN), VI(ENx), VI(EN),
VI(ENx)
Input voltage
0
5.5
V
IO(OUT), IO(OUTx)
Continuous output current
0
500
mA
TJ
Operating virtual junction temperature
–40
125
°C
7.4 Thermal Information
TPS2042xx and TPS2053xx
D
(SOIC)
THERMAL METRIC (1)
DBV
(SOT-23)
DGN
(HVSSOP)
DRB
(SON)
UNIT
8 PINS
16 PINS
5 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
119.3
81.6
208.6
53.6
47.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
67.6
42.7
122.9
58.7
53
°C/W
RθJB
Junction-to-board thermal resistance
59.6
39.1
37.8
35.5
14.2
°C/W
ψJT
Junction-to-top characterization parameter
20.3
10.4
14.6
2.7
1.2
°C/W
ψJB
Junction-to-board characterization
parameter
59.1
38.8
36.9
35.3
14.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
N/A
N/A
N/A
6.7
7.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2010–2016, Texas Instruments Incorporated
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TPS2041B, TPS2042B, TPS2043B, TPS2044B
TPS2051B, TPS2052B, TPS2053B, TPS2054B
SLVS514M – JUNE 2010 – REVISED JUNE 2016
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7.5 Electrical Characteristics
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.5 A, VI(/ENx) = 0 V (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP MAX
UNIT
POWER SWITCH
Static drain-source on-state
VI(IN) = 5 V or 3.3 V, IO = 0.5 A,
resistance, 5-V operation
-40°C ≤ TJ ≤ 125°C
and 3.3-V operation
rDS(on)
tr
tf
D and DGN packages
70
135
DBV package only
95
140
Static drain-source on-state VI(IN) = 2.7 V, IO = 0.5 A,
resistance, 2.7-V operation –40°C ≤ TJ ≤ 125°C
D and DGN packages
75
150
mΩ
Static drain-source on-state VI(IN) = 5 V, IO = 1 A, OUT1 and OUT2
resistance, 5-V operation
connected, 0°C ≤ TJ ≤ 70°C
DGN package,
TPS2042B/52B
49
mΩ
Rise time, output
Fall time, output
VI(IN) = 5.5 V
0.6
VI(IN) = 2.7 V
0.4
VI(IN) = 5.5 V
CL = 1 μF,
RL = 10 Ω
TJ = 25°C
VI(IN) = 2.7 V
mΩ
1.5
1
0.05
0.5
0.05
0.5
ms
ENABLE INPUT EN AND ENx
VIH
High-level input voltage
2.7 V ≤ VI(IN) ≤ 5.5 V
VIL
Low-level input voltage
2.7 V ≤ VI(IN) ≤ 5.5 V
II
Input current
VI(ENx) = 0 V or 5.5 V
ton
Turnon time
CL = 100 μF, RL = 10 Ω
3
toff
Turnoff time
CL = 100 μF, RL = 10 Ω
10
2
0.8
–0.5
0.5
V
μA
ms
CURRENT LIMIT
VI(IN) = 5 V, OUT connected to GND,
device enabled into short-circuit
IOS
IOC
Short-circuit output current
Overcurrent trip threshold
VI(IN) = 5 V, OUT1 and OUT2 connected to
GND, device enabled into short-circuit,
measure at IN
VIN = 5 V, 100 A/s
TJ = 25°C
0.75
1
1.25
–40°C ≤ TJ ≤ 125°C
0.7
1
1.3
0°C ≤ TJ ≤ 70°C
TPS2042B/52B
1.5
A
TPS2041B/51B
IOS
1.5
1.9
TPS2042B/52B
IOS
1.55
2
A
SUPPLY CURRENT (TPS2041B, TPS2051B)
Supply current, low-level output
No load on OUT, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
TJ = 25°C
0.5
1
-40°°C ≤ TJ ≤ 125°C
0.5
5
Supply current, high-level output
No load on OUT, VI(ENx) = 0 V,
or VI(ENx) = 5.5 V
TJ = 25°C
43
60
–40°C ≤ TJ ≤ 125°C
43
70
Leakage current
OUT connected to ground, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
–40°C ≤ TJ ≤ 125°C
1
μA
Reverse leakage current
VI(OUTx) = 5.5 V, IN = ground
TJ = 25°C
0
μA
(1)
8
μA
μA
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
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SLVS514M – JUNE 2010 – REVISED JUNE 2016
Electrical Characteristics (continued)
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = 0.5 A, VI(/ENx) = 0 V (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP MAX
UNIT
SUPPLY CURRENT (TPS2042B, TPS2052B)
TJ = 25°C
0.5
1
–40°C ≤ TJ ≤ 125°C
0.5
5
TJ = 25°C
50
70
–40°C ≤ TJ ≤ 125°C
50
90
Supply current, low-level output
No load on OUT, VI(ENx) = 5.5 V
Supply current, high-level output
No load on OUT, VI(ENx) = 0 V
Leakage current
OUT connected to ground, VI(ENx) = 5.5 V
–40°C ≤ TJ ≤ 125°C
1
μA
Reverse leakage current
VI(OUTx) = 5.5 V, IN = ground
TJ = 25°C
0.2
μA
TJ = 25°C
0.5
2
–40°C ≤ TJ ≤ 125°C
0.5
10
TJ = 25°C
65
90
–40°C ≤ TJ ≤ 125°C
65
110
1
μA
μA
μA
μA
SUPPLY CURRENT (TPS2043B, TPS2053B)
Supply current, low-level output
No load on OUT, VI(ENx) = 0 V
Supply current, high-level output
No load on OUT, VI(ENx) = 5.5 V
Leakage current
OUT connected to ground, VI(ENx) = 0 V
–40°C≤ TJ ≤ 125°C
Reverse leakage current
VI(OUTx) = 5.5 V, INx = ground
TJ = 25°C
0.2
μA
μA
SUPPLY CURRENT (TPS2044B, TPS2054B)
Supply current, low-level output
No load on OUT, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
TJ = 25°C
0.5
2
–40°C ≤ TJ ≤ 125°C
0.5
10
Supply current, high-level output
No load on OUT, VI(ENx) = 0 V,
or VI(ENx) = 5.5 V
TJ = 25°C
75
110
–40°C ≤ TJ ≤ 125°C
75
140
Leakage current
OUT connected to ground, VI(ENx) = 5.5 V,
or VI(ENx) = 0 V
–40°C≤ TJ ≤ 125°C
1
μA
Reverse leakage current
VI(OUTx) = 5.5 V, INx = ground
TJ = 25°C
0.2
μA
μA
μA
UNDERVOLTAGE LOCKOUT
Low-level input voltage, IN, INx
Hysteresis, IN, INx
2
TJ = 25°C
2.5
75
V
mV
OVERCURRENT OC and OCx
Output low voltage, VOL(/OCx)
IO(OCx) = 5 mA
Off-state current
VO(OCx) = 5 V or 3.3 V
OC deglitch
OCx assertion or deassertion
0.4
4
8
V
1
μA
15
ms
THERMAL SHUTDOWN (2)
Thermal shutdown threshold
135
Recovery from thermal shutdown
125
Hysteresis
(2)
°C
°C
10
°C
The thermal shutdown only reacts under overcurrent conditions.
7.6 Dissipation Ratings
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGN-8
1712.3 mW
17.123 mW/°C
941.78 mW
684.93 mW
D-8
585.82 mW
5.8582 mW/°C
322.20 mW
234.32 mW
D-16
898.47 mW
8.9847 mW/°C
494.15 mW
359.38 mW
PACKAGE
THERMAL
RESISTANCE, θJA
285 mW
2.85 mW/°C
155 mW
114 mW
DRB-8 (Low-K) (1)
DBV-5
270 °CW
370 mW
3.71 mW/°C
203 mW
148 mW
DRB-8 (High-K) (2)
60 °CW
1600 mW
16.67 mW/°C
916 mW
866 mW
(1)
(2)
Soldered PowerPAD on a standard 2-layer PCB without vias for thermal pad. See TI application note SLMA002 for further details.
Soldered PowerPAD on a standard 4-layer PCB with vias for thermal pad. See TI application note SLMA002 for further details.
Copyright © 2010–2016, Texas Instruments Incorporated
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7.7 Typical Characteristics
1.0
3.3
0.8
3.2
0.7
Turnoff Time − ms
Turnon Time − ms
CL = 100 µF,
RL = 10 Ω,
TA = 25°C
CL = 100 µF,
RL = 10 Ω,
TA = 25°C
0.9
0.6
0.5
0.4
3.1
3
0.3
0.2
2.9
0.1
0
2
3
4
5
VI − Input Voltage − V
2.8
6
3
4
5
6
VI − Input Voltage − V
Figure 1. Turnon Time vs Input Voltage
Figure 2. Turnoff Time vs Input Voltage
0.6
0.25
CL = 1 µF,
RL = 10 Ω,
TA = 25°C
CL = 1 µF,
RL = 10 Ω,
TA = 25°C
0.5
0.2
0.4
Fall Time − ms
Rise Time − ms
2
0.3
0.15
0.1
0.2
0.05
0.1
0
2
3
4
5
VI − Input Voltage − V
0
6
2
3
4
5
VI − Input Voltage − V
6
\
Figure 4. Fall Time vs Input Voltage
Figure 3. Rise Time vs Input Voltage
70
VI = 5.5 V
50
VI = 5 V
40
30
VI = 2.7 V
20
VI = 3.3 V
10
0
−50
10
I I (IN) − Supply Current, Output Enabled − µ A
I I (IN) − Supply Current, Output Enabled − µA
60
0
50
100
150
VI = 5.5 V
60
50
VI = 5 V
VI = 3.3 V
40
30
VI = 2.7 V
20
10
0
−50
0
50
100
150
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
Figure 5. TPS2041B and TPS2051B Supply Current, Output
Enabled vs Junction Temperature
Figure 6. TPS2042B and TPS2052B Supply Current, Output
Enabled vs Junction Temperature
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Typical Characteristics (continued)
120
80
I I (IN) − Supply Current, Output Enabled − µ A
I I (IN) − Supply Current, Output Enabled −µ A
90
VI = 5.5 V
70
VI = 5 V
60
VI = 3.3 V
50
40
VI = 2.7 V
30
20
10
0
−50
80
60
VI = 2.7 V
40
VI = 3.3 V
20
0.35
0.3
VI = 2.7 V
VI = 3.3 V
0.25
0.2
0.15
0.1
0.05
0
50
100
VI = 5 V
0.35
0.3
VI = 3.3 V
VI = 2.7 V
0.25
0.2
0.15
0.1
0.05
0
50
100
150
Figure 10. TPS2042B and TPS2052B Supply Current, Output
Disabled vs Junction Temperature
0.5
I I (IN) − Supply Current, Output Disabled − µ A
I I (IN) − Supply Current, Output Disabled − µ A
VI = 5.5 V
TJ − Junction Temperature − °C
0.5
VI = 5.5 V
VI = 5 V
0.4
0.35
VI = 3.3 V
VI = 2.7 V
0.25
0.2
0.15
0.1
0.05
0
−50
150
0.4
0
−50
150
Figure 9. TPS2041B TPS2051B Supply Current, Output
Disabled vs Junction Temperature
0.3
100
0.5
0.45
TJ − Junction Temperature − °C
0.45
50
Figure 8. TPS2044B TPS2054B Supply Current, Output
Enabled vs Junction Temperature
I I (IN) − Supply Current, Output Disabled − µ A
VI = 5 V
0.4
0
TJ − Junction Temperature − °C
VI = 5.5 V
0.45
−50
150
0.5
I I (IN) − Supply Current, Output Disabled − µ A
VI = 5 V
0
0
50
100
TJ − Junction Temperature − °C
Figure 7. TPS2043B and TPS2053B Supply Current, Output
Enabled vs Junction Temperature
0
−50
VI = 5.5 V
100
0
50
100
TJ − Junction Temperature − °C
150
Figure 11. TPS2043B and TPS2053B Supply Current, Output
Disabled vs Junction Temperature
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0.45
VI = 5.5 V
VI = 5 V
0.4
0.35
0.3
VI = 2.7 V
VI = 3.3 V
0.25
0.2
0.15
0.1
0.05
0
−50
0
50
100
TJ − Junction Temperature − °C
150
Figure 12. TPS2044B and TPS2054B Supply Current, Output
Disabled vs Junction Temperature
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1.08
120
IO = 0.5 A
I OS − Short-Circuit Output Current − A
r DS(on) − Static Drain-Source On-State Resistance − m Ω
Typical Characteristics (continued)
VI = 2.7 V
100
80
VI = 3.3 V
60
VI = 5 V
40
20
0
−50
0
50
100
1.04
1.02
1.0
0.98
VI = 5 V
0.96
VI = 5.5 V
0.94
0.92
0
50
100
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
2
TPS2041B,
TPS2042B,
TPS2051B,
TPS2052B
1.8
TA = 25 °C
Load Ramp = 1A/10 ms
Threshold Trip Current − A
TA = 25°C
Load Ramp = 1A/10 ms
1.6
1.4
1.2
1
2.5
150
Figure 14. Short-Circuit Output Current vs Junction
Temperature
2
Threshold Trip Current − A
VI = 3.3 V
0.9
−50
150
Figure 13. Static Drain-Source on-State Resistance vs
Junction Temperature
1.8
1.6
1.4
TPS2043B,
TPS2044B,
TPS2053B,
TPS2054B
1.2
3
3.5
4
4.5
5
5.5
1
2.5
6
VI − Input Voltage − V
3.5
4
4.5
5
VI − Input Voltage − V
Figure 15. Threshold Trip Current vs Input Voltage
Figure 16. Threshold Trip Current vs Input Voltage
2.26
Current-Limit Response − µs
UVLO − Undervoltage Lockout − V
5.5
6
VI = 5 V,
TA = 25°C
UVLO Rising
2.22
UVLO Falling
2.18
80
60
40
20
2.14
2.1
−50
3
100
2.3
0
0
50
100
TJ − Junction Temperature − °C
150
Figure 17. Undervoltage Lockout vs Junction Temperature
12
VI = 2.7 V
1.06
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0
2.5
5
7.5
Peak Current − A
10
12.5
Figure 18. Current-Limit Response vs Peak Current
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SLVS514M – JUNE 2010 – REVISED JUNE 2016
Typical Characteristics (continued)
VI(EN)
VI(EN)
5 V/div
RL = 10 Ω,
CL = 1 µF
TA = 25°C
VI(EN)
VI(EN)
5 V/div
t − Time − 500 µs/div
t − Time − 500 µs/div
Figure 19. Turnon Delay and Rise Time With 1-µF Load
VI(EN)
VI(EN)
5 V/div
RL = 10 Ω,
CL = 1 µF
TA = 25°C
VO(OUT)
2 V/div
VO(OUT)
2 V/div
RL = 10 Ω,
CL = 100 µF
TA = 25°C
Figure 20. Turnoff Delay and Fall Time With 1-µF Load
VI(EN)
VI(EN)
5 V/div
RL = 10 Ω,
CL = 100 µF
TA = 25°C
VO(OUT)
2 V/div
VO(OUT)
2 V/div
t − Time − 500 µs/div
t − Time − 500 µs/div
Figure 21. Turnon Delay and Rise Time With 100-µF Load
Figure 22. Turnoff Delay and Fall Time With 100-µF Load
VI = 5 V,
RL = 10 Ω,
TA = 25°C
VI(EN)
VI(EN)
5 V/div
VI(EN)
VI(EN)
5 V/div
220 µF
470 µF
IO(OUT)
500 mA/div
IO(OUT)
500 mA/div
100 µF
t − Time − 500 µs/div
Figure 23. Short-Circuit Current,
Device Enabled Into Short
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t − Time − 500 µs/div
Figure 24. Inrush Current With Different
Load Capacitance
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Typical Characteristics (continued)
VO(OC)
2 V/div
VO(OC)
2 V/div
IO(OUT)
500 mA/div
IO(OUT)
500 mA/div
t − Time − 2 ms/div
t − Time − 2 ms/div
Figure 25. 3-Ω Load Connected to Enabled Device
Figure 26. 2-Ω Load Connected to Enabled Device
8 Parameter Measurement Information
OUT
RL
tf
tr
CL
VO(OUT)
90%
10%
90%
10%
TEST CIRCUIT
50%
VI(EN)
50%
toff
ton
VO(OUT)
50%
VI(EN)
90%
50%
toff
ton
90%
VO(OUT)
10%
10%
VOLTAGE WAVEFORMS
Figure 27. Test Circuit and Voltage Waveforms
14
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SLVS514M – JUNE 2010 – REVISED JUNE 2016
9 Detailed Description
9.1 Overview
The TPS20xxB are current-limited, power-distribution switches providing 0.5-A continuous load current. These
devices incorporates 70-mΩ N-channel MOSFET power switches for power-distribution systems that require
multiple power switches in a single package. Gate driver is provided by an internal charge pump designed to
minimize current surges during switching. The charge pump requires no external components and allows
operation supplies as low as 2.7 V.
9.2 Functional Block Diagrams
(See Note A)
CS
IN
OUT
Charge
Pump
EN
(See Note B)
Driver
Current
Limit
OC
UVLO
Thermal
Sense
GND
Deglitch
Note A: Current sense
Note B: Active low (EN) for TPS2041B; Active high (EN) for TPS2051B
Figure 28. Functional Block Diagram (TPS2041B and TPS2051B)
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TPS2051B, TPS2052B, TPS2053B, TPS2054B
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Functional Block Diagrams (continued)
OC1
Thermal
Sense
GND
Deglitch
EN1
(See Note B)
Driver
Current
Limit
Charge
Pump
(See Note A)
CS
OUT1
UVLO
(See Note A)
IN
OUT2
CS
Charge
Pump
Driver
Current
Limit
OC2
EN2
(See Note B)
Thermal
Sense
Deglitch
Note A: Current sense
Note B: Active low (ENx) for TPS2042B; Active high (ENx) for TPS2052B
Figure 29. Functional Block Diagram (TPS2042B and TPS2052B)
16
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TPS2051B, TPS2052B, TPS2053B, TPS2054B
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SLVS514M – JUNE 2010 – REVISED JUNE 2016
Functional Block Diagrams (continued)
OC1
Thermal
Sense
GND
Deglitch
EN1
(See Note B)
Driver
Current
Limit
(See Note A)
CS
OUT1
UVLO
(See Note A)
CS
IN1
Driver
OUT2
Current
Limit
OC2
EN2
(See Note B)
VCC
Selector
Thermal
Sense
Deglitch
Charge
Pump
(See Note A)
IN2
OUT3
CS
EN3
Driver
Current
Limit
(See Note B)
OC3
UVLO
GND
Thermal
Sense
Deglitch
Note A: Current sense
Note B: Active low (ENx) for TPS2043B; Active high (ENx) for TPS2053B
Figure 30. Functional Block Diagram (TPS2043B and TPS2053B)
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TPS2051B, TPS2052B, TPS2053B, TPS2054B
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Functional Block Diagrams (continued)
OC1
Thermal
Sense
GND
Deglitch
EN1
(See Note B)
Driver
Current
Limit
(See Note A)
CS
OUT1
UVLO
Power Switch
(See Note A)
IN1
CS
Driver
OUT2
Current
Limit
OC2
EN2
(See Note B)
Thermal
Sense
VCC
Selector
Deglitch
Charge
Pump
OC3
Thermal
Sense
Deglitch
EN3
(See Note B)
Driver
Current
Limit
(See Note A)
CS
OUT3
UVLO
Power Switch
(See Note A)
IN2
CS
Driver
OUT4
Current
Limit
OC4
EN4
(See Note B)
GND
Thermal
Sense
Deglitch
Note A: Current sense
Note B: Active low (ENx) for TPS2044B; Active high (ENx) for TPS2054B
Figure 31. Functional Block Diagram (TPS2044B and TPS2054B)
18
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SLVS514M – JUNE 2010 – REVISED JUNE 2016
9.3 Feature Description
9.3.1 Power Switch
The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the
power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a
minimum current of 500 mA.
9.3.2 Charge Pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
little supply current.
9.3.3 Driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage.
9.3.4 Enable (ENx)
The logic enable pin disables the power switch and the bias for the charge pump, driver, and other circuitry to
reduce the supply current. The supply current is reduced to less than 1 µA or 2 µA when a logic high is present
on EN. A logic zero input on EN restores bias to the drive and control circuits and turns the switch on. The
enable input is compatible with both TTL and CMOS logic levels.
9.3.5 Enable (ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current. The supply current is reduced to less than 1 μA or 2 μA when a logic low is present on ENx. A
logic high input on ENx restores bias to the drive and control circuits and turns the switch on. The enable input is
compatible with both TTL and CMOS logic levels.
9.3.6 Overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A 10ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown
occurs, the OCx is asserted instantaneously.
9.3.7 Current Sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its
saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.
9.3.8 Thermal Sense
The TPS20xxB implements a thermal sensing to monitor the operating temperature of the power distribution
switch. In an overcurrent or short-circuit condition, the junction temperature rises. When the die temperature rises
to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch,
thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device has
cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until the
fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an overtemperature
shutdown or overcurrent occurs.
9.3.9 Undervoltage Lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
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9.4 Device Functional Modes
There are no other functional modes for TPS20xxB devices.
20
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TPS2051B, TPS2052B, TPS2053B, TPS2054B
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SLVS514M – JUNE 2010 – REVISED JUNE 2016
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Universal Serial Bus (USB) Applications
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-tomedium bandwidth PC peripherals (for example, keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
• Hosts and self-powered hubs (SPH)
• Bus-powered hubs (BPH)
• Low-power, bus-powered functions
• High-power, bus-powered functions
• Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS20xxB can
provide power-distribution solutions to many of these classes of devices.
10.2 Typical Application
10.2.1 Typical Application (TPS2042B)
TPS2042B
2
Power Supply
2.7 V to 5.5 V
IN
OUT1
0.1 µF
8
3
5
4
7
Load
0.1 µF
22 µF
0.1 µF
22 µF
OC1
EN1
OUT2
OC2
6
Load
EN2
GND
1
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Figure 32. Typical Application (Example, TPS2042B)
10.2.1.1 Design Requirements
Table 1 shows the design parameters for this application.
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TPS2051B, TPS2052B, TPS2053B, TPS2054B
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Table 1. Design Parameters
DESIGN PARAMETER
VALUE
Input voltage
5V
Output1 voltage
5V
Output2 voltage
5V
Output1 current
0.5 A
Output2 current
0.5 A
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Power-Supply Considerations
TI recommends placing a 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device.
When the output load is heavy, TI recommends placing a high-value electrolytic capacitor on the necessary
output pins. This precaution reduces power-supply transients that may cause ringing on the input. Additionally,
bypassing the output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to shortcircuit transients.
10.2.1.2.2 Overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 23 through Figure 26). The TPS20xxB senses the
short and immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current
mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 9 through Figure 12). The TPS20xxB is capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
10.2.1.2.3 OC Response
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition
is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or
overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a
momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit.
The TPS20xxB is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates
the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned
off due to an overtemperature shutdown.
V+
TPS2042B
GND
Rpullup
OC1
IN
OUT1
EN1
OUT2
EN2
OC2
Figure 33. Typical Circuit for the OC Pin (Example, TPS2042B)
22
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SLVS514M – JUNE 2010 – REVISED JUNE 2016
10.2.1.3 Application Curves
VI(EN)
VI(EN)
5 V/div
RL = 10 Ω,
CL = 1 µF
TA = 25°C
VI(EN)
VI(EN)
5 V/div
t − Time − 500 µs/div
t − Time − 500 µs/div
Figure 34. Turnon Delay and Rise Time With 1-µF Load
VI(EN)
VI(EN)
5 V/div
RL = 10 Ω,
CL = 1 µF
TA = 25°C
VO(OUT)
2 V/div
VO(OUT)
2 V/div
RL = 10 Ω,
CL = 100 µF
TA = 25°C
Figure 35. Turnoff Delay and Fall Time With 1-µF Load
VI(EN)
VI(EN)
5 V/div
RL = 10 Ω,
CL = 100 µF
TA = 25°C
VO(OUT)
2 V/div
VO(OUT)
2 V/div
t − Time − 500 µs/div
t − Time − 500 µs/div
Figure 36. Turnon Delay and Rise Time With 100-µF Load
VI(EN)
VI(EN)
5 V/div
Figure 37. Turnoff Delay and Fall Time With 100-µF Load
VI = 5 V,
RL = 10 Ω,
TA = 25°C
VI(EN)
VI(EN)
5 V/div
220 µF
470 µF
IO(OUT)
500 mA/div
IO(OUT)
500 mA/div
100 µF
t − Time − 500 µs/div
Figure 38. Short-Circuit Current,
Device Enabled Into Short
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t − Time − 500 µs/div
Figure 39. Inrush Current With Different
Load Capacitance
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TPS2051B, TPS2052B, TPS2053B, TPS2054B
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VO(OC)
2 V/div
VO(OC)
2 V/div
IO(OUT)
500 mA/div
IO(OUT)
500 mA/div
t − Time − 2 ms/div
t − Time − 2 ms/div
Figure 41. 2-Ω Load Connected to Enabled Device
Figure 40. 3-Ω Load Connected to Enabled Device
10.2.2 Host and Self-Powered and Bus-Powered Hubs
Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports (see Figure 42 and Figure 43). This power supply must provide from 5.25 V to 4.75 V to the
board side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to
have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are
desktop PCs, monitors, printers, and stand-alone hubs.
Power Supply
3.3 V
Downstream
USB Ports
5V
TPS2041B
2, 3
IN
D+
D−
6, 7, 8
VBUS
OUT
0.1 µF
0.1 µF
5
USB
Control
4
120 µF
GND
OC
EN
GND
1
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Figure 42. Typical One-Port USB Host and Self-Powered Hub
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TPS2051B, TPS2052B, TPS2053B, TPS2054B
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SLVS514M – JUNE 2010 – REVISED JUNE 2016
Downstream
USB Ports
D+
Power Supply
D−
3.3 V
5V
+
TPS2044B
2
6
IN1
OUT1
IN2
VBUS
33 µF
15
D+
0.1 µF
D−
14
OUT2
16
3
13
4
USB
Controller
12
7
9
8
OC1
OUT3
GND
+
VBUS
33 µF
GND
11
EN1
D+
OC2
D−
EN2
+
10
OC3
VBUS
33 µF
GND
OUT4
EN3
OC4
D+
EN4
D−
GND GND
1
5
+
VBUS
33 µF
GND
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Figure 43. Typical Four-Port USB Host and Self-Powered Hub
10.2.2.1 Design Requirements
10.2.2.1.1 USB Power-Distribution Requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
• Hosts and self-powered hubs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB VBUS
• Bus-powered hubs must:
– Enable/disable power to downstream ports
– Power up at
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