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SLVS245C – SEPTEMBER 2000 – REVISED OCTOBER 2007
POWER-DISTRIBUTION SWITCHES
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
80-mΩ High-Side MOSFET Switch
250 mA Continuous Current per Channel
Independent Thermal and Short-Circuit
Protection With Overcurrent Logic Output
Operating Range: 2.7-V to 5.5-V
CMOS- and TTL-Compatible Enable Inputs
2.5-ms Typical Rise Time
Undervoltage Lockout
10 μA Maximum Standby Supply Current
Bidirectional Switch
Available in 8-Pin and 16-Pin SOIC Packages
Ambient Temperature Range, 0°C to 85°C
ESD Protection
DESCRIPTION
The TPS2090, TPS2091, and TPS2092 dual and the
TPS2095,
TPS2096
and
TPS2097
quad
power-distribution switches are intended for
applications where heavy capacitive loads and short
circuits are likely to be encountered. The TPS209x
devices incorporate 80-mΩ N-channel MOSFET
high-side power switches for power-distribution
systems that require multiple power switches in a
single package. Each switch is controlled by an
independent logic enable input. Gate drive is provided
by an internal charge pump designed to control the
power-switch rise times and fall times to minimize
current surges during switching. The charge pump
requires no external components and allows
operation from supplies as low as 2.7 V.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2007, Texas Instruments Incorporated
TPS2090, TPS2091, TPS2092 DUAL
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SLVS245C – SEPTEMBER 2000 – REVISED OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
When the output load exceeds the current-limit threshold or a short is present, the TPS209x limits the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low.
When continuous heavy overloads and short circuits increase the power dissipation in the switch causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a
thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present. The TPS209x devices are designed to current limit at 0.5-A load.
AVAILABLE OPTIONS (1)
DUAL POWER DISTRIBUTION SWITCHES
ENABLE
TA
0°C to 85°C
EN1
EN2
Active high
Active high
Active high
Active low
Active low
RECOMMENDED
MAXIMUM
CONTINUOUS LOAD
CURRENT
(A)
TYPICAL
SHORT-CIRCUIT
CURRENT LIMIT
AT 25°C
(A)
0.25
0.5
PACKAGED
DEVICES
SMALL
OUTLINE
(D) (2)
TPS2090D
Active low
TPS2091D
TPS2092D
QUAD POWER DISTRIBUTION SWITCHES
ENABLE
TA
0°C to 85°C
(1)
(2)
2
EN1
EN2
EN3
DN4
Active high
Active high
Active high
Active high
Active high
Active low
Active high
Active low
Active low
Active low
Active low
Active low
RECOMMENDED
MAXIMUM
CONTINUOUS LOAD
CURRENT
(A)
TYPICAL
SHORT-CIRCUIT
CURRENT LIMIT
AT 25°C
(A)
0.25
0.5
PACKAGED
DEVICES
SMALL
OUTLINE
(D) (2)
TPS2095D
TPS2096D
TPS2097D
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2091DR).
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TPS2092 FUNCTIONAL BLOCK DIAGRAM
Copyright © 2000–2007, Texas Instruments Incorporated
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SLVS245C – SEPTEMBER 2000 – REVISED OCTOBER 2007
TPS2097 FUNCTIONAL BLOCK DIAGRAM
4
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SLVS245C – SEPTEMBER 2000 – REVISED OCTOBER 2007
TERMINAL FUNCTIONS
DUAL POWER-DISTRIBUTION SWITCHES
TERMINAL
NAME
NO.
TPS2090
TPS2091
EN1
EN2
5
I/O
DESCRIPTION
TPS2092
4
I
Enable input. Active low turns on power switch.
5
I
Enable input. Active low turns on power switch.
I
Enable input. Active high turns on power switch.
I
Enable input. Active high turns on power switch.
EN1
4
4
EN2
5
GND
1
1
1
I
Ground
IN1
2
2
2
I
N-Channel MOSFET Drain
IN2
3
3
3
I
N-Channel MOSFET Drain
OC
8
8
8
O
Overcurrent. Open drain output active low
OUT1
7
7
7
O
Power-switch output
OUT2
6
6
6
O
Power-switch output
QUAD POWER-DISTRIBUTION SWITCHES
TERMINAL
NAME
NO.
TPS2095
4
I
Enable input. Active low turns on power switch.
13
13
I
Enable input. Active low turns on power switch.
8
I
Enable input. Active low turns on power switch.
9
I
Enable input. Active low turns on power switch.
I
Enable input. Active high turns on power switch.
I
Enable input. Active high turns on power switch.
I
Enable input. Active high turns on power switch.
I
Enable input. Active high turns on power switch.
EN3
EN4
DESCRIPTION
TPS2097
EN1
EN2
I/O
TPS2096
9
EN1
4
4
EN2
13
EN3
8
EN4
9
GNDA
1
1
1
Ground for IN1 and IN2 switch and circuitry
GNDB
5
5
5
Ground for IN3 and IN4 switch and circuitry
IN1
2
2
2
I
N-channel MOSFET drain
IN2
3
3
3
I
N-channel MOSFET drain
IN3
6
6
6
I
N-channel MOSFET drain
8
IN4
7
7
7
I
N-channel MOSFET drain
OCA
16
16
16
O
Overcurrent indicator for switch 1 and switch 2. Active-low open drain output.
OCB
12
12
12
O
Overcurrent indicator for switch 3 and switch 4. Active low open drain output
OUT1
15
15
15
O
Power-switch output
OUT2
14
14
14
O
Power-switch output
OUT3
11
11
11
O
Power-switch output
OUT4
10
10
10
O
Power-switch output
Copyright © 2000–2007, Texas Instruments Incorporated
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SLVS245C – SEPTEMBER 2000 – REVISED OCTOBER 2007
DETAILED DESCRIPTION
POWER SWITCH
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (VI(IN) = 5V).
Configured as a high-side switch, the power switch prevents current flow from OUTx to IN and IN to OUTx when
disabled. The power switch supplies a minimum of 250mA per switch.
CHARGE PUMP
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7V and requires
very little supply current.
DRIVER
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
ENABLE (ENx or ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 10 μA when a logic high is present on ENx or a logic low is present on ENx. A
logic low input on ENx or logic high on ENx restores bias to the drive and control circuits and turns the power on.
The enable input is compatible with both TTL and CMOS logic levels.
OVERCURRENT (OCx)
The OCx open drain output is asserted (active low) when an overcurrent or over temperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
CURRENT SENSE
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its
saturation region, which switches the output into a constant current mode and holds the current constant while
varying the voltage on the load.
THERMAL SENSE
The TPS209x implements a dual thermal trip to allow fully independent operation of the power distribution
switches. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature
rises to approximately 140°C, the internal thermal sense circuitry checks to determine which power switch is in
an overcurrent condition and turns off that switch, thus isolating the fault without interrupting operation of the
adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled approximately
20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The
(OCx) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.
UNDERVOLTAGE LOCKOUT
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
6
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VI(IN)
Input voltage range (2)
VO(OUTx)
Output voltage range (2)
VI(ENx) or VI(ENx)
Input voltage range
IO(OUTx)
Continuous output current
(1)
VALUE
UNIT
–0.3 to 6
V
–0.3 to VI(IN) + 0.3
V
–0.3 to 6
V
Internally Limited
Continuous total power dissipation
See Dissipation Rating Table
TJ
Operating virtual junction temperature range
Tstg
Storage temperature range
°C
2
kV
Machine model
200
V
Charged device model (CDM)
750
V
Human body model
ESD
(1)
(2)
Electrostatic discharge protection
°C
0 to 125
–65 to 150
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND.
DISSIPATION RATINGS TABLE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING=
D-8
725 mW
5.8 mW/°C
464 mW
377 mW
D-16
1123 mW
9 mW/°C
719 mW
584 mW
PACKAGE
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
VI(IN)
Input voltage
2.7
5.5
UNIT
V
VI(ENx) or VI(ENx)
Input voltage
0
5.5
V
IO
Continuous output current (per switch)
0
250
mA
TJ
Operating virtual junction temperature
0
125
°C
TYP
MAX
UNIT
0.02
5
1
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, VI(ENx) = 0 V,
VI(ENx) = VI(INx) (unless otherwise noted)
SUPPLY CURRENT
PARAMETER
Supply current, low-level output
TEST CONDITIONS
No Load on OUT
VI(ENx) = VI(IN),
VI(ENx) = 0 V
MIN
TJ = 25°C
–40°C ≤ TJ ≤ 125°C
Supply current, high-level
output
No Load on OUT
VI(ENx) = 0 V,
VI(ENx) = VI(IN)
Leakage current
OUT connected to
ground
Reverse leakage current
INx = high impedance
Copyright © 2000–2007, Texas Instruments Incorporated
TJ = 25°C
μA
10
85
110
μA
–40°C ≤ TJ ≤ 125°C
100
VI(ENx) = VI(IN),
VI(ENx) = 0 V
–40°C ≤ TJ ≤ 125°C
100
μA
VI(ENx) = 0 V,
VI(ENx) = VI(IN)
TJ = 25°C
0.3
μA
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SLVS245C – SEPTEMBER 2000 – REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (Continued)
over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, VI(ENx) = 0 V, VI(ENx) = VI(INx) (unless
otherwise noted)
POWER SWITCH
TEST CONDITIONS (1)
PARAMETER
rDS(on)
MAX
TJ = 25°C,
IO = 0.25 A
80
100
VI(IN) = 5 V,
TJ = 85°C,
IO = 0.25 A
90
120
TJ = 125°C,
IO = 0.25 A
100
135
TJ = 25°C,
IO = 0.25 A
90
125
VI(IN) = 3.3 V,
TJ = 85°C,
IO = 0.25 A
110
145
VI(IN) = 3.3 V,
TJ = 125°C,
IO = 0.25 A
120
165
VI(IN) = 5.5 V, RL = 20 Ω,
TJ = 125°C,
CL = 1 μF
2.5
VI(IN) = 2.7 V, RL = 20 Ω,
TJ = 125°C,
CL = 1 μF
3
VI(IN) = 5.5 V, RL = 20 Ω,
TJ = 125°C,
CL = 1 μF
4.4
VI(IN) = 2.7 V, RL = 20 Ω,
TJ = 125°C,
CL = 1 μF
2.5
Static drain-source on-state VI(IN) = 5 V,
resistance
VI(IN) = 3.3 V,
tr
Rise time, output
tf
Fall time, output
(1)
TYP
VI(IN) = 5 V,
MIN
UNIT
mΩ
ms
ms
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
ENABLE INPUT VI(ENx) or VI(ENx)
PARAMETER
VIH
TEST CONDITIONS
MIN
High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V
TYP
MAX
UNIT
2
V
4.5 V ≤ VI(IN) ≤ 5.5 V
0.8
2.7 V ≤ VI(IN) ≤ 4.5 V
0.4
VIL
Low-level input voltage
II
Input current
VI(ENx) = 0 V and VI(ENx) = VI(IN), or VI(ENx) = VI(IN) and VI(ENx) = 0 V
0.5
μA
ton
Turnon time
CL = 100 μF,
RL = 20 μF
20
ms
toff
Turnon time
CL = 100 μF,
RL = 20 μF
40
ms
–0.5
V
CURRENT LIMIT
PARAMETER
IOS
(1)
TEST CONDITIONS (1)
Short-circuit output current VI(IN) = 5 V, OUT connected to GND, Device enabled into short circuit
MIN
TYP
MAX
0.3
0.5
0.7
UNIT
A
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
UNDERVOLTAGE LOCKOUT
PARAMETER
TEST CONDITIONS
Low-level input voltage
Hysteresis
MIN
TYP
2
TJ = 25°C
MAX
2.5
100
UNIT
V
mV
OVERCURRENT OCx
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Sink current (1)
VO = 5 V
10
Output low voltage
IO = 5 mA, VOL(OCx)
0.5
V
Off-state current (1)
VO = 5 V, VO = 3.3 V
1
μA
(1)
8
mA
Specified by design, not production tested.
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PARAMETER MEASUREMENT INFORMATION
Figure 1. Test Circuit and Voltage Waveforms
Figure 2. Turnon Delay and Rise Time With 0.1-μF Load
Copyright © 2000–2007, Texas Instruments Incorporated
Figure 3. Turnoff Delay and Fall Time With 0.1-μF Load
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SLVS245C – SEPTEMBER 2000 – REVISED OCTOBER 2007
PARAMETER MEASUREMENT INFORMATION (continued)
10
Figure 4. Turnon Delay and Rise Time With 1-μF Load
Figure 5. Turnoff Delay and Fall Time With 1-μF Load
Figure 6. TPS2090, Short-Circuit Current, Device
Enabled Into Short
Figure 7. TPS2090, Threshold Trip Current With Ramped
Load on Enabled Device
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Ramped Load on Enabled Device
Figure 9. Inrush Current With 47-μF, 100-μF and 220-μF
Load Capacitance
Figure 10. 4-Ω Load Connected to Enabled Device
Figure 11. 1-Ω Load Connected to Enabled Device
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SLVS245C – SEPTEMBER 2000 – REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS
12
TURNON DELAY TIME
vs
INPUT VOLTAGE
TURNOFF DELAY TIME
vs
INPUT VOLTAGE
Figure 12.
Figure 13.
RISE TIME
vs
INPUT VOLTAGE
FALL TIME
vs
INPUT VOLTAGE
Figure 14.
Figure 15.
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SLVS245C – SEPTEMBER 2000 – REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT, OUTPUT ENABLED
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT, OUTPUT DISABLED
vs
JUNCTION TEMPERATURE
Figure 16.
Figure 17.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
INPUT-TO-OUTPUT VOLTAGE
vs
LOAD CURRENT
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
14
SHORT-CIRCUIT OUTPUT CURRENT
vs
JUNCTION TEMPERATURE
THRESHOLD TRIP CURRENT
vs
INPUT VOLTAGE
Figure 20.
Figure 21.
UNDERVOLTAGE LOCKOUT
vs
JUNCTION TEMPERATURE
CURRENT LIMIT RESPONSE
vs
PEAK CURRENT
Figure 22.
Figure 23.
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SLVS245C – SEPTEMBER 2000 – REVISED OCTOBER 2007
APPLICATION INFORMATION
Figure 24. Typical Application
POWER-SUPPLY CONSIDERATIONS
A 0.01-μF to 0.1-μF ceramic bypass capacitor between INx and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the
output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients.
OVERCURRENT
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(IN) has been applied (see Figure 6). The TPS209x senses the short and
immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figure 10 and
Figure 11). After the current-limit circuit has tripped (reached the overcurrent trip threshold) the device switches
into constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 8). The TPS209x is capable of delivering current up to the current-limit threshold without
damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.
OC RESPONSES
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. The TPS209x devices are
designed to reduce false overcurrent reporting. An internal overcurrent transient filter eliminates the need to use
external components to remove unwanted pulses. Using low-ESR electrolytic capacitors on the output lowers the
inrush current flow through the device during hot-plug events by providing a low impedance energy source,
thereby reducing erroneous overcurrent reporting.
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Figure 25. Typical Circuit for OC Pin
POWER DISSIPATION AND JUNCTION TEMPERATURE
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to that of power packages; it is
good design practice to check power dissipation and junction temperature. Begin by determining the rDS(on) of the
N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read rDS(on) from Figure 18. Using this value, the power
dissipation per switch can be calculated by:
PD = rDS(on) × I2
Multiply this number by the total number of switches being used, to get the total power dissipation coming from
the N-channel MOSFETs.
Finally, calculate the junction temperature:
TJ = PD × RθJA + TA
Where:
TA = Ambient Temperature °C
RθJA = Thermal resistance SOIC = 172°C/W (for 8 pin), 111°C/W (for 16 pin)
PD = Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
THERMAL PROTECTION
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS209x into constant current mode, which causes the voltage
across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to
the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection
circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense
circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues
to cycle in this manner until the load fault or input power is removed.
The TPS209x implements a dual thermal trip to allow fully independent operation of the power distribution
switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die temperature
rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is in an overcurrent
condition and turns that power switch off, thus isolating the fault without interrupting operation of the adjacent
power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach 160°C, both
switches turn off. The OC open-drain output is asserted (active low) when overtemperature or overcurrent
occurs.
16
Submit Documentation Feedback
Copyright © 2000–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS2090, TPS2091, TPS2092 DUAL TPS2095, TPS2096, TPS2097 QUAD
TPS2090, TPS2091, TPS2092 DUAL
TPS2095, TPS2096, TPS2097 QUAD
www.ti.com
SLVS245C – SEPTEMBER 2000 – REVISED OCTOBER 2007
UNDERVOLTAGE LOCKOUT (UVLO)l
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input
voltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if the
switch is enabled. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce EMI
and voltage overshoots.
GENERIC HOT-PLUG APPLICATIONS (see Figure 26)
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS209x, these devices can be used to
provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS209x
also ensures the switch will be off after the card has been removed, and the switch will be off during the next
insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card or
module.
Figure 26. Typical Hot-Plug Implementation
By placing the TPS209x between the VCC input and the rest of the circuitry, the input power will reach these
devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing a slow voltage
ramp at the output of the device. This implementation controls system surge currents and provides a
hot-plugging mechanism for any device.
Copyright © 2000–2007, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TPS2090, TPS2091, TPS2092 DUAL TPS2095, TPS2096, TPS2097 QUAD
17
PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS2090D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2090
TPS2090DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2090
TPS2090DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2090
TPS2091D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2091
TPS2091DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2091
TPS2092D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2092
TPS2092DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2092
TPS2092DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2092
TPS2095D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2095
TPS2095DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2095
TPS2095DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2095
TPS2096D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2096
TPS2096DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2096
TPS2097D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2097
TPS2097DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
2097
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2016
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Apr-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS2090DR
SOIC
D
TPS2092DR
SOIC
TPS2095DR
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
5.2
2.1
8.0
12.0
Q1
8
2500
330.0
12.4
6.4
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Apr-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS2090DR
SOIC
D
8
2500
340.5
338.1
20.6
TPS2092DR
SOIC
D
8
2500
340.5
338.1
20.6
TPS2095DR
SOIC
D
16
2500
333.2
345.9
28.6
Pack Materials-Page 2
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