TPS2105MDBVREP

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS2105-EP SLVSCH2 – JULY 2014 TPS2105-EP VAUX Power-Distribution Switch 1 Features 2 Applications • • • • 1 • • • • • • • • • Dual-Input, Single-Output MOSFET Switch With No Reverse Current Flow (No Parasitic Diodes) IN1: 250-mΩ, 500-mA N-Channel; 18-µA Supply Current IN2: 1.3-mΩ, 100-mA P-Channel; 0.75-µA Supply Current (VAUX Mode) Advanced Switch Control Logic CMOS and TTL Compatible Enable Input Controlled Rise, Fall, and Transition Times 2.7-V to 5.5-V Operating Range SOT-23-5 Package 2-kV Human Body Model, 750-V Charged Device Model, 200-V Machine-Model ESD Protection Supports Defense, Aerospace, and Medical Applications – Controlled Baseline – One Assembly and Test Site – One Fabrication Site – Available in Military (–55°C to 125°C) Temperature Range – Extended Product Life Cycle – Extended Product-Change Notification – Product Traceability Notebook and Desktop PCs Cell phone, Palmtops, and PDAs Battery Management 3 Description The TPS2105 is a dual-input, single-output power switch designed to provide uninterrupted output voltage when transitioning between two independent power supplies. Both devices combine one N-channel (250 mΩ) and one P-channel (1.3-Ω) MOSFET with a single output. The P-channel MOSFET (IN2) is used with auxiliary power supplies that deliver lower current for standby modes. The N-channel MOSFET (IN1) is used with a main power supply that delivers higher current required for normal operation. Low onresistance makes the N-channel the ideal path for higher main supply current when power-supply regulation and system voltage drops are critical. When using the P-channel MOSFET, quiescent current is reduced to 0.75 µA to decrease the demand on the standby power supply. The MOSFETs in the TPS2105 do not have the parasitic diodes, typically found in discrete MOSFETs, thereby preventing back-flow current when the switch is off. Device Information(1) ORDER NUMBER PACKAGE TPS2105MDBVREP SOT-23 (5) BODY SIZE (NOM) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic TPS2105 5 V VCC 5 V VAUX IN1 5V LOAD IN2 EN Control Signal Holdup Capacitor 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS2105-EP SLVSCH2 – JULY 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................... 9 7.4 Device Functional Modes ....................................... 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application .................................................. 11 9 Power Supply Recommendations...................... 14 10 Layout................................................................... 14 10.1 Layout Guidelines ................................................. 14 10.2 Layout Examples................................................... 15 11 Device and Documentation Support ................. 17 11.1 Trademarks ........................................................... 17 11.2 Electrostatic Discharge Caution ............................ 17 11.3 Glossary ................................................................ 17 Detailed Description .............................................. 9 12 Mechanical, Packaging, and Orderable Information ........................................................... 17 7.1 Overview ................................................................... 9 4 Revision History 2 DATE VERSION NOTES July 2014 * Initial Release Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS2105-EP www.ti.com SLVSCH2 – JULY 2014 5 Pin Configuration and Functions 5-Pin SOT DBV Package (Top View) TPS2105 EN 1 GND 2 IN2 3 5 IN1 4 OUT Pin Functions PIN NAME NO. I/O DESCRIPTION EN 1 I Active-high enable for IN1-OUT switch GND 2 I Ground IN1 (1) 5 I Main input voltage, NMOS drain (250 mΩ), requires 0.22-µF bypass (1) 3 I Auxiliary input voltage, PMOS drain (1.3 Ω), requires 0.22-µF bypass 4 O Power switch output IN2 OUT (1) Unused INx should not be grounded. Table 1. Function Table TPS2105 (1) VIN1 VIN2 EN OUT 0V 0V XX (1) GND 0V 5V h GND 5V 0V h VIN1 5V 5V h VIN1 0V 5V l VIN2 5V 0V l VIN2 5V 5V l VIN2 XX = Don't care Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS2105-EP SLVSCH2 – JULY 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX VI(IN1) Input voltage (2) –0.3 6 V VI(IN2) (2) Input voltage UNIT –0.3 6 V Input voltage, VI at EN (2) –0.3 6 V VO Output voltage (2) –0.3 6 V IO(IN1) Continuous output current 700 mA IO(IN2) Continuous output current 140 mA Continuous total power dissipation TJ See Thermal Information Operating virtual junction temperature –55 Lead temperature soldering 1.6 mm (1/16 inch) from case for 10 s (1) (2) 150 °C 260 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. 6.2 Handling Ratings Tstg Electrostatic discharge V(ESD) (1) (2) MIN MAX UNIT –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) –2000 2000 Machine model (MM) ESD stress voltage –200 200 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) –750 750 Storage temperature range V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VI(INx) Input voltage MIN MAX 2.7 5.5 Input voltage, VI at EN V 5.5 V IO(IN1) Continuous output current 500 mA IO(IN2) Continuous output current 100 (1) mA TJ Operating virtual junction temperature 125 °C (1) 0 UNIT –55 The device can deliver up to 220 mA at IO(IN2). However, operation at the higher current levels results in greater voltage drop across the device, and greater voltage droop when switching between IN1 and IN2. 6.4 Thermal Information THERMAL METRIC (1) TPS2105-EP DBV (5 PINS) RθJA Junction-to-ambient thermal resistance 208.7 RθJC(top) Junction-to-case (top) thermal resistance 122.9 RθJB Junction-to-board thermal resistance 36.7 ψJT Junction-to-top characterization parameter 14.2 ψJB Junction-to-board characterization parameter 35.8 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A (1) 4 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS2105-EP www.ti.com SLVSCH2 – JULY 2014 6.5 Electrical Characteristics Over recommended operating range (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IN1-OUT, VI(IN1) = 5.5 V, VI(IN2) = 0 V 250 435 mΩ IN2-OUT, VI(IN2) = 5.5 V, VI(IN1) = 0 V 1.3 2.4 Ω POWER SWITCH rDS(on) On-state resistance ENABLE INPUT VIH High-level input voltage 2.7 V ≤ VI(INx) ≤ 5.5 V VIL Low-level input voltage 2.7 V ≤ VI(INx) ≤ 5.5 V II Input current EN = 0 V or EN = VI(INx) 2 V –0.65 0.8 V 0.65 µA SUPPLY CURRENT II Supply current EN = L, IN2 selected 0.75 1.5 µA EN = H, IN1 selected 18 35 µA SPACE 100 Electromigration IN1 (500 mA) Electromigration IN2 (100 mA) WB Failure Mode 70 50 40 Estimated Life (Years) 30 20 10 7 5 4 3 2 1 80 85 90 95 100 105 110 115 120 125 Continuous Juction Temperature, T J (°C) 130 135 140 145 150 D013 (1) Wirebond life = Time at temperature with or without bias (2) Electromigration fail mode = Time at temperature with bias (3) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). (4) The predicted operating lifetime versus junction temperature is based on reliability modeling and available qualification data. Figure 1. Predicted Lifetime Derating Chart for TPS2105-EP Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS2105-EP SLVSCH2 – JULY 2014 www.ti.com 6.6 Switching Characteristics TJ = 25°C, VI(IN1) = VI(IN2) = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS IN1-OUT tr VI(IN2) = 0 Output rise time IN2-OUT VI(IN1) = 0 MIN TYP CL = 1 µF, IL = 500 mA 340 CL = 10 µF, IL = 500 mA 340 CL = 1 µF, IL = 100 mA 312 CL = 1 µF, IL = 100 mA 3.4 CL = 10 µF, IL = 100 mA 34 CL = 1 µF, 3.5 IL = 10 mA CL = 1 µF, IL = 500 mA IN1-OUT tf VI(IN2) = 0 Output fall time IN2-OUT VI(IN1) = 0 Propagation delay time, low-to-high output IN1-OUT VI(IN2) = 0 IN2-OUT VI(IN1) = 0 tPHL Propagation delay time, high-to-low output IN1-OUT VI(IN2) = 0 IN2-OUT VI(IN1) = 0 UNIT µs 6 CL = 10 µF, IL = 500 mA 108 CL = 1 µF, IL = 100 mA 8 CL = 1 µF, IL = 100 mA 100 CL = 10 µF, IL = 100 mA µs 990 CL = 1 µF, IL = 10 mA tPLH MAX 1000 55 CL = 10 µF, IL = 100 mA µs 1 1.5 CL = 10 µF, IL = 100 mA µs 50 OUT IO CL LOAD CIRCUIT 50% EN 50% EN t PHL VI t PLH VI 90% VO GND GND VO 10% Propagation Delay Time, Low-to-High-Level Output Propagation Delay Time, High-to–Low-Level Output tr tf VI 90% VO 10% GND Rise/Fall Time 50% EN 50% EN t on t off VI VI 90% VO VO GND Turnon Transition Time 10% GND Turnoff Transition Time Figure 2. Test Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS2105-EP www.ti.com SLVSCH2 – JULY 2014 6.7 Typical Characteristics 1000 400 CL = 100 F CL = 100 F 340 CL = 47 F 310 CL = 10 F CL = 47 F 100 Rise Time (s) Rise Time (s) 370 CL = 10 F 10 280 CL = 1 F CL = 1 F 1 250 0.01 0.1 1 10 100 Output Current (mA) VI(IN1) = 5 V 0 1000 10 20 30 VI(IN2) = 0 V 40 50 60 70 VI(IN1) = 0 V TJ = 25°C 90 100 C002 VI(IN2) = 5 V TJ = 25°C Figure 4. IN2 Switch Rise Time vs Output Current Figure 3. IN1 Switch Rise Time vs Output Current 10000 1000 CL = 100 F CL = 100 F 1000 100 Fall Time (s) CL = 47 F Fall Time (s) 80 Output Current (mA) C001 CL = 10 F 100 10 CL = 10 F 10 CL = 1 F CL = 47 F 1 CL = 1 F 1 0.01 0.1 1 10 100 Output Current (mA) VI(IN1) = 5 V 0.1 0.01 1000 VI(IN2) = 0 V TJ = 25°C VI(IN1) = 0 V 10 100 C004 VI(IN2) = 5 V TJ = 25°C Figure 6. IN2 Switch Fall Time vs Output Current 1 3.5 CL = 1 F 3.0 0.8 CL = 10 F Inrush Current (A) Output Voltage Droop (V) 1 Output Current (mA) Figure 5. IN1 Switch Fall Time vs Output Current 0.6 0.1 C003 CL = 47 F CL = 100 F 0.4 CL = 220 F 2.5 2.0 1.5 1.0 0.2 0.5 0 0.01 0.0 0.1 1 Output Current (mA) 10 100 VI(IN1) = 5 V VI(IN2) = 5 V TJ = 25°C If switching from IN1 to IN2, the voltage droop is much smaller. Thus, choose the load capacitance according to Figure 6. Figure 7. Output Voltage Droop vs Output Current When Output is Switched from IN2 to IN1 Copyright © 2014, Texas Instruments Incorporated 0 100 200 300 400 500 Output Capacitance (F) C005 VI(IN1) = 5 V TJ = 25°C VI(IN2) = 0 V C006 RL = 10 Ω Figure 8. Inrush Current vs Output Capacitance Submit Documentation Feedback 7 TPS2105-EP SLVSCH2 – JULY 2014 www.ti.com Typical Characteristics (continued) 30 27.5 Supply Current (µA) 25 22.5 Supply Current (µA) 2.7 V 3.3 V 4.0 V 5.0 V 5.5 V 20 17.5 15 12.5 10 7.5 5 -75 -50 -25 0 25 50 75 100 Junction Temperature (°C) 125 150 175 0.34 Supply Current (µA) 0.32 0.3 Supply Current (µA) 2.7 V 3.3 V 4.0 V 5.0 V 5.5 V 0.28 0.26 0.24 0.22 0.2 -25 0 25 50 75 100 Junction Temperature (°C) 125 150 175 0 25 50 75 100 Junction Temperature (°C) 125 150 175 D005 0.5 0.475 0.45 0.425 0.4 0.375 0.35 0.325 0.3 0.275 0.25 0.225 0.2 0.175 0.15 -75 2.7 V 3.3 V 4.0 V 5.0 V 5.5 V -50 -25 0 25 50 75 100 Junction Temperature (°C) 125 150 175 D006 Figure 12. IN2 Supply Current vs Junction Temperature (IN2 Disabled) 3.5 280 2.7 V 3.3 V 4.0 V 5.0 V 5.5 V 270 260 250 240 IN2-OUT On-State Resistance (Ω) IN1-OUT On-State Resistance (mΩ) -25 D004 Figure 11. IN2 Supply Current vs Junction Temperature (IN2 Enabled) 230 220 210 200 190 180 2.7 V 3.3 V 4.0 V 5.0 V 5.5 V 3.25 3 2.75 2.5 2.25 2 1.75 1.5 1.25 1 0.75 170 160 -75 -50 -25 0 25 50 75 100 Junction Temperature (°C) 125 150 175 D008 Figure 13. IN1-Out On-State Resistance vs Junction Temperature 8 -50 Figure 10. IN1 Supply Current vs Junction Temperature (IN1 Disabled) 0.36 -50 2.7 V 3.3 V 4.0 V 5.0 V 5.5 V D003 Figure 9. IN1 Supply Current vs Junction Temperature (IN1 Enabled) 0.18 -75 0.35 0.34 0.33 0.32 0.31 0.3 0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.2 -75 Submit Documentation Feedback 0.5 -75 -50 -25 0 25 50 75 100 Junction Temperature (°C) 125 150 175 D007 Figure 14. IN2-Out On-State Resistance vs Junction Temperature Copyright © 2014, Texas Instruments Incorporated TPS2105-EP www.ti.com SLVSCH2 – JULY 2014 7 Detailed Description 7.1 Overview The TPS2105 is a dual-input, single-output power switch designed to provide uninterrupted output voltage when transitioning between two independent power supplies. The device combines one N-channel (250-m) MOSFET with a single output. The P-channel MOSFET (IN2) is used with auxiliary power supplies that deliver lower current for standby modes. The N-channel MOSFET (IN1) is used with a main power supply that delivers higher current required for normal operation. The low on-resistance makes the N-channel the ideal path for higher main supply current when power-supply regulation and system voltage drops are critical. When using the P-channel MOSFET, quiescent current is reduced to 0.75 µA to decrease the demand on the standby power supply. The MOSFETs in the device do not have the parasitic diodes, typically found in discrete MOSFETs, thereby preventing back-flow current when the switch is off. 7.2 Functional Block Diagram SW1 250 mΩ IN1 OUT Charge Pump VCC Select EN Discharge Circuit Driver IN2 Pulldown Circuit SW2 1.3 Ω GND Driver 7.3 Feature Description 7.3.1 Power Switches 7.3.1.1 N-Channel MOSFET The IN1-OUT N-channel MOSFET power switch has a typical on-resistance of 250 mΩ at 5-V input voltage and is configured as a high-side switch. 7.3.1.2 P-Channel MOSFET The IN2-OUT P-channel MOSFET power switch has a typical on-resistance of 1.3 Ω at 5-V input voltage and is configured as a high-side switch. When operating, the P-channel MOSFET quiescent current is reduced to typically 0.75 µA. 7.3.1.3 Charge Pump An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires very little supply current. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 9 TPS2105-EP SLVSCH2 – JULY 2014 www.ti.com Feature Description (continued) 7.3.1.4 Driver The driver controls the gate voltage of the IN1-OUT and IN2-OUT power switches. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the drivers incorporate circuitry that controls the rise times and fall times of the output voltage. 7.3.1.5 Enable The logic enable turns on the IN2-OUT power switch when a logic low is present on EN. A logic high on EN restores bias to the drive and control circuits and turns on the IN1-OUT power switch. The enable input is compatible with both TTL and CMOS logic levels. 7.4 Device Functional Modes 7.4.1 Operation With EN Control The logic enable turns on the IN1-OUT power switch when a logic high is present on EN. Also, a logic low present on EN turns off the IN1-OUT and turns on the IN2-OUT power switch. 10 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS2105-EP www.ti.com SLVSCH2 – JULY 2014 8 Application and Implementation 8.1 Application Information The TPS2105 is a dual-input, single-output power switch designed to provide uninterrupted output voltage when transitioning between two independent power supplies. 8.2 Typical Application TPS2105 CardBus or System Controller 5 V VCC 5 V VAUX 0.22 µF EN 1 µF IN1 IN2 5V OUT xx µF GND 0.22 µF Figure 15. Typical Application Schematic 8.2.1 Design Requirements For this design example, use the following as the input parameters. Table 2. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage range, VI(IN1) 5V Input voltage range, VI(IN2) 5V Output voltage 5V Continuous output current, IO 100 mA Output capacitor, CL 220 µF 8.2.2 Detailed Design Procedure 8.2.2.1 Step-by-Step Design Procedure To begin the design process, the designer must decide upon a few parameters. The designer needs to know the following: • Input voltage range, VI(IN1) • Input voltage range, VI(IN2) • Output voltage • Continuous output current • Output capacitance 8.2.2.2 Power-Supply Considerations TI recommends a 0.22-µF ceramic bypass capacitor between IN and GND, close to the device. The output capacitor should be chosen based on the size of the load during the transition of the switch. TI recommends a 220-µF capacitor for 100-mA loads. Typical output capacitors (xx µF, shown in Figure 15) required for a given load can be determined from Figure 7, which shows the output voltage droop when output is switched from IN2 to IN1. The output voltage droop is insignificant when output is switched from IN1 to IN2. Additionally, bypassing the output with a 1-µF ceramic capacitor improves the immunity of the device to short-circuit transients. 8.2.2.3 Switch Transition The N-channel MOSFET on IN1 uses a charge pump to create the gate-drive voltage, which gives the IN1 switch a rise time of approximately 0.4 ms. The P-channel MOSFET on IN2 has a simpler drive circuit that allows a rise time of approximately 4 µs. Because the device has two switches and a single enable pin, these rise times are seen as transition times, from IN1 to IN2, or IN2 to IN1, by the output. The controlled transition times help limit the surge currents seen by the power supply during switching. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 11 TPS2105-EP SLVSCH2 – JULY 2014 www.ti.com 8.2.2.4 Thermal Protection Thermal protection provided on the IN1 switch prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The increased dissipation causes the junction temperature to rise to dangerously high levels. The protection circuit senses the junction temperature of the switch and shuts it off at approximately 145°C (TJ). The switch remains off until the junction temperature has dropped approximately 10°C. The switch continues to cycle in this manner until the load fault or input power is removed. 8.2.2.5 Undervoltage Lockout An undervoltage lockout function is provided to ensure that the power switch is in the off state at power-up. Whenever the input voltage falls below approximately 2 V, the power switch quickly turns off. This function facilitates the design of hot-insertion systems that may not have the capability to turn off the power switch before input power is removed. Upon reinsertion, the power switch is turned on with a controlled rise time to reduce EMI and voltage overshoots. 8.2.2.6 Power Dissipation and Junction Temperature The low on-resistance on the N-channel MOSFET allows small surface-mount packages, such as SOIC, to pass large currents. The thermal resistances of these packages are high compared to those of power packages; it is a good design practice to check power dissipation and junction temperature. First, find ron at the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read ron from Figure 13 or Figure 14. Next calculate the power dissipation using: PD = ron × I2 (1) Finally, calculate the junction temperature: TJ = PD × RθJA + TA where • • TA = Ambient temperature RθJA = Thermal resistance (2) Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation using the calculated value as the new estimate. Two or three iterations are generally sufficient to obtain a reasonable answer. 8.2.2.7 ESD Protection All TPS2105 pins incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model, 750-V CDM, and 200-V machine-model discharge as defined in MIL-STD-883C. 12 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS2105-EP www.ti.com SLVSCH2 – JULY 2014 8.2.3 Application Curves EN (2 V/div) EN (2 V/div) VO (2 V/div) VO (2 V/div) Time = 200 s/div Time = 2 s/div C013 VI(IN1) = 0 V RL = 50 Ω VI(IN2) = 5 V CL = 1 µF Figure 16. Propagation Delay and Rise Time With 1-µF Load, IN2 Turnon C014 VI(IN1) = 5 V RL = 50 Ω VI(IN2) = 0 V CL = 1 µF Figure 17. Propagation Delay and Rise Time With 1-µF Load, IN1 Turnon EN (2 V/div) EN (2 V/div) VO (2 V/div) VO (2 V/div) Time = 10 s/div Time = 50 s/div C015 VI(IN1) = 0 V RL = 50 Ω VI(IN2) = 5 V CL = 1 µF Figure 18. Propagation Delay and Fall Time With 1-µF Load, IN2 Turnoff Copyright © 2014, Texas Instruments Incorporated C016 VI(IN1) = 5 V RL = 50 Ω VI(IN2) = 0 V CL = 1 µF Figure 19. Propagation Delay and Fall Time With 1-µF Load, IN1 Turnoff Submit Documentation Feedback 13 TPS2105-EP SLVSCH2 – JULY 2014 www.ti.com 9 Power Supply Recommendations The device is designed to operate from an input voltage supply range from 2.7 to 5.5 V. A 0.22-μF ceramic bypass capacitor is needed between IN and GND; TI recommends placing the capacitor close to the device. The output capacitor should be chosen based on the size of the load during the transition of the switch. TI recommends a 220-μF capacitor for 100-mA loads. Adding a 1-μF ceramic bypass capacitor at the output can help to improve the immunity of the device to short-circuit transients. TPS2105-EP requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. Ceramic capacitors lose capacitance when a DC bias is applied across the capacitor. This capacitance loss is due to the polarization of the ceramic material. The capacitance loss is not permanent; after a large DC bias is applied, reducing the DC bias reduces the degree of polarization and capacitance increases. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. All tantalum capacitors have tantalum (Ta) particles sintered together to form an anode. The cathode material can either be the traditional MnO2 or a conductive polymer. Because MnO2 is actually a semiconductor, it has a very high amount of resistance associated with it. A characteristic of this material is that as temperature changes, so does its conductivity. So MnO2-based Tantalum capacitors have relatively high ESR and that ESR shifts significantly across the operational temperature range. However, polymer-based cathodes use a highly-conductive polymer material. Because the material is inherently conductive, tantalum-polymers have a relatively-low ESR compared to their MnO2 counterparts in the same voltage and capacitance ranges. All tantalum capacitors have a voltage derating factor associated with them. Because the polymer material puts less stress on the tantalum-pentoxide dielectric during reflow soldering, more voltage can be applied compared to a MnO2-based tantalum. For polymer-based capacitors, TI recommends 20% derating. Whereas the MnO2based tantalum capacitors require 50% or higher derating. Refer to the capacitor vendor data sheet for more details regarding the derating guidelines. 10 Layout 10.1 Layout Guidelines • • • • • • 14 The IN1 and OUT pins of the TPS2105-EP can carry up to 500 mA, so trace to these pins should have short length and wider traces to minimize the voltage drop to the load. Both the IN1 and IN2 pins should be bypassed to ground with a low-ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 0.22-µF ceramic capacitor. A bypass capacitor and a load capacitor are needed on the output terminal. TI recommends a 220-µF output load capacitor for 100-mA loads. Locating the 1-µF ceramic bypass capacitor at the output can improve the immunity of the device to shortcircuit transients. The GND terminal should be tied to the PCB ground plane at the terminal of the DUT. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS2105-EP www.ti.com SLVSCH2 – JULY 2014 10.2 Layout Examples Output Capacitors C3 and C4 Bypass Capacitors C1 and C2 DUT Area, Pin 1 located on top left. EN IN1 GND IN2 OUT Figure 20. Input and Output Capacitors and DUT Area Enable Main Input, Input 1 Auxiliary Input, Input 2 Output Ground Figure 21. Enable, Input, Output, and Ground Pins Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 15 TPS2105-EP SLVSCH2 – JULY 2014 www.ti.com Layout Examples (continued) Figure 22. Schematics Diagram Table 3. Component Descriptions 16 PART DESCRIPTION C1, C2 0.22 µF, size 0805 C3 1 µF, size 0805 C4 220 µF, tantalum capacitors U1 TPS2105MDBVREP TP_EN, TP_IN1, TP_IN2, TP_OUT, TP_GND Test point, through hole Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS2105-EP www.ti.com SLVSCH2 – JULY 2014 11 Device and Documentation Support 11.1 Trademarks All trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 17 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS2105MDBVREP ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 PD9M V62/14616-01XE ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 PD9M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of