TPS2231
TPS2236
www.ti.com
SLVS536A – JULY 2004 – REVISED NOVEMBER 2004
ExpressCard™ POWER INTERFACE SWITCH
•
FEATURES
•
•
•
•
•
•
•
Meets the ExpressCard™ Standard
(ExpressCard|34 or ExpressCard|54)
Compliant with the ExpressCard™
Compliance Checklists
Fully Satisfies the ExpressCard™
Implementation Guidelines
Supports Systems with WAKE Function
TTL-Logic Compatible Inputs
Short Circuit and Thermal Protection
–40°C to 85°C Ambient Operating
Temperature Range
•
Available in a 20-pin TSSOP or 24-pin
PowerPAD™ HTSSOP (Single)
Available in a 32-pin PowerPAD™ HTSSOP
(Dual)
APPLICATIONS
•
•
•
•
•
Notebook Computers
Desktop Computers
Personal Digital Assistants (PDAs)
Digital Cameras
TV and Set Top Boxes
DESCRIPTION
The TPS2231 and TPS2236 ExpressCard power interface switches provide the total power management solution
required by the ExpressCard specification. The TPS2231 and TPS2236 ExpressCard power interface switches
distribute 3.3 V, AUX, and 1.5 V to the ExpressCard socket. Each voltage rail is protected with integrated
current-limiting circuitry.
The TPS2231 supports systems with single-slot ExpressCard|34 or ExpressCard|54 sockets. The TPS2236
supports systems with dual-slot ExpressCard sockets.
End equipment for the TPS2231 and TPS2236 include notebook computers, desktop computers, personal digital
assistants (PDAs), and digital cameras.
Host
Power
Source
3.3VIN
3.3VOUT
1.5VIN
1.5VOUT
TPS2231
SHDN
STBY
Host
Chip
Set/Lock
Circuits
SYSRST
PERST
CPPE
CPUSB
ExpressCard Connector
AUXOUT
Host Connector
AUXIN
Express Card
OC
GND
RCLKEN
REFCLK+
REFCLK-
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ExpressCard is a trademark of Personal Computer Memory Card International Association.
PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
TPS2231
TPS2236
www.ti.com
SLVS536A – JULY 2004 – REVISED NOVEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
TA
Single
–40°C to 85°C
(1)
(2)
PACKAGED DEVICES (1)
NUMBER OF CHANNELS
TSSOP
PowerPAD HTSSOP
TPS2231PW (2)
TPS2231PWP
Dual
TPS2236DAP
The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2231PWPR).
Product preview stage of development
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage range for card
power
VI
TPS223x
UNIT
VI(3.3VIN)
–0.3 to 6
V
VI(1.5VIN)
–0.3 to 6
V
VI(AUXIN)
–0.3 to 6
V
Logic input/output voltage
VO
Output voltage range
–0.3 to 6
V
VO(3.3VOUT)
–0.3 to 6
V
VO(1.5VOUT)
–0.3 to 6
V
–0.3 to 6
V
VO(AUXOUT)
Continuous total power dissipation
IO
Output current
See Dissipation Rating Table
IO(3.3VOUT)
Internally limited
IO(AUXOUT)
Internally limited
IO(1.5VOUT)
Internally limited
OC sink current
10
mA
PERST sink/source current
10
mA
TJ
Operating virtual junction temperature range
–40 to 120
°C
Tstg
Storage temperature range
–55 to 150
°C
260
°C
2
kV
1.5
kV
500
V
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
TPS2231
ESD
Electrostatic discharge
protection
Human body model
(HBM) MIL-STD-883C
TPS2236, all pins except
PERSTx and OCx
TPS2236, PERSTx and OCx
Charge device model (CDM)
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS (Thermal Resistance = °C/W)
(1)
2
PACKAGE (1)
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PW (20)
704.2 mW
7.41 mW/°C
370.6 mW
259.5 mW
PWP (24)
3153 mW
33.19 mW/°C
1659.5 mW
1161.6 mW
DAP (32)
PowerPAD not soldered down
993.4 mW
10.46 mW/°C
522.8 mW
366 mW
DAP (32)
4040.8 mW
42.55 mW/°C
2126.8 mW
1488.7 mW
These devices are mounted on an JEDEC low-k board (2-oz. traces on surface), (The table is assuming that the maximum junction
temperature is 120°C). The power pad on the device must be soldered down to the power pad on the board if best thermal performance
is needed.
TPS2231
TPS2236
www.ti.com
SLVS536A – JULY 2004 – REVISED NOVEMBER 2004
RECOMMENDED OPERATING CONDITIONS
VI(3.3VIN)
VI(1.5VIN)
Input voltage
VI(AUXIN)
MIN
MAX
3.3VIN is only required for its respective functions
3
3.6
1.5VIN is only required for its respective functions
1.35
1.65
3
3.6
AUXIN is required for all circuit operations
IO(3.3VOUT)
IO(1.5VOUT)
Continuous output current
TJ = 120°C
IO(AUXOUT)
TJ
Operating virtual junction temperature
UNIT
V
0
1.3
A
0
650
mA
0
275
mA
–40
120
°C
ELECTRICAL CHARACTERISTICS
TJ = 25°C, VI(3.3VIN) = VI(AUXIN) = 3.3 V, VI(1.5VIN) = 1.5 V, VI(/SHDNx), VI(/STBYx) = 3.3 V, VI(/CPPEx) = VI(/CPUSBx) = 0 V,
VI(/SYSRST) = 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SWITCH
Power switch
resistance
R(DIS_FET)
IOS
3.3VIN to 3.3VOUT with two
switches on for dual
TJ = 25°C, I = 1300 mA each
1.5VIN to 1.5VOUT With two
switches on for dual
TJ = 25°C, I = 650 mA each
AUXIN to AUXOUT with two
switches on for dual
TJ = 25°C, I = 275 mA each
Discharge resistance on 3.3V/1.5V/AUX outputs
Short-circuit output current (1)
IOS(3.3VOUT) (steady-state value)
IOS(1.5VOUT) (steady-state value)
TJ = 100°C, I = 1300 mA each
Thermal
shutdown
VI(/SHDNx) = 0 V, I(discharge) = 1 mA
Normal operation
of TPS2231
100
TJ (–40, 120°C]. Output powered into
a short
2
mΩ
mΩ
500
Ω
2.5
A
0.67
1
1.3
A
275
450
600
mA
Rising temperature, not in
overcurrent condition
155
165
Overcurrent condition
120
130
°C
VO(3.3VOUT) with 100-mΩ short
43
100
VO(1.5VOUT) with 100-mΩ short,
TPS2231
100
140
VO(1.5VOUT) with 100-mΩ short,
TPS2236
110
150
µs
38
100
125
200
II(3.3VIN)
17.5
25
II(AUXIN)
II(3.3VIN)
II(1.5VIN)
(1)
200
II(AUXIN)
II(1.5VIN)
Operation input
quiescent current
120
1.35
VO(AUXOUT) with 100-mΩ short
II
70
mΩ
10
From short to the 1st threshold
within 1.1 times of final current
limit, TJ = 25°C
Normal operation
of TPS2236
46
TJ = 100°C, I = 275 mA each
Hysteresis
Current-limit
response time
68
TJ = 100°C, I = 650 mA each
IOS(AUXOUT)(steady-state value)
Trip point, TJ
45
Outputs are unloaded,
TJ [–40, 120°C] (does not include
CPPEx and CPUSBx logic pullup
currents)
5.5
15
85
150
10
15
2.5
10
µA
µA
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
3
TPS2231
TPS2236
www.ti.com
SLVS536A – JULY 2004 – REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
TJ = 25°C, VI(3.3VIN) = VI(AUXIN) = 3.3 V, VI(1.5VIN) = 1.5 V, VI(/SHDNx), VI(/STBYx) = 3.3 V, VI(/CPPEx) = VI(/CPUSBx) = 0 V,
VI(/SYSRST) = 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)
PARAMETER
Normal operation
of TPS2236
TEST CONDITIONS
II(3.3VIN)
II(1.5VIN)
Normal operation
of TPS2231
II
Total input
quiescent current
MIN
II(AUXIN)
II(AUXIN)
Outputs are unloaded, TJ[–40,
120°C] (include CPPEx and CPUSBx
logic pullup currents)
II(3.3VIN)
Ilkg(RVS)
II(1.5VOUT)
15
210
10
15
10
3.5
20
II(3.3VIN)
II(AUXIN)
Reverse leakage
current (TPS2236 II(3.3VOUT)
and TPS2231)
5.5
120
440
II(1.5VIN)
II(AUXOUT)
25
2.5
CPUSB = CPPE = 0 V SHDN = 0 V
(discharge FETs are on) (include
CPPEx and CPUSBx logic pullup
currents and SHDN pullup current) TJ
[–40, 120°C]
II(AUXIN)
TPS2231
17.5
250
Shutdown mode of
II(3.3VIN)
TPS2231
II(1.5VIN)
Forward leakage
current
320
II(AUXIN)
II(AUXIN)
Ilkg(FWD)
MAX
200
II(1.5VIN)
Shutdown mode of
II(3.3VIN)
TPS2236
II(1.5VIN)
TPS2236
TYP
SHDN = 3.3 V,
CPUSB = CPPE = 3.3 V (no card
present, discharge FETs are on);
current measured at input pins
TJ = 120°C, includes RCLKEN
pullup current
0.1
20
144
270
3.5
10
0.5
10
40
100
0.1
100
0.1
100
20
50
0.1
50
II(1.5VIN)
0.1
50
TJ = 25°C
0.1
10
II(3.3VIN)
TJ = 120°C
TJ = 25°C
TJ = 120°C
TJ = 25°C
50
VO(AUXOUT) = VO(3.3VOUT)= 3.3 V;
VO(1.5VOUT) = 1.5 V; All voltage inputs
are grounded (current measured
from output pins going in)
0.1
10
50
0.1
TJ = 120°C
10
50
UNIT
µA
µA
µA
µA
µA
µA
µA
µA
µA
LOGIC SECTION (SYSRST, SHDNx, STBYx, PERSTx, RCLKENx, OCx, CPUSBx, CPPEx)
Logic input
supply current
Logic input
voltage
I(/SYSRST)
Input
I(/SHDNx)
Input
I(/STBYx)
Input
I(RCLKENx)
Input
I(/CPUSBx) or
I(/CPPEx)
Inputs
SYSRST = 0 V, sourcing
0
10
SHDNx = 3.6 V, sinking
SHDNx = 0 V, sourcing
1
30
0
10
STBYx = 3.6 V, sinking
1
30
0
1
STBYx = 0 V, sourcing
10
30
RCLKENx = 0 V, sourcing
10
30
CPUSB or CPPE = 0 V, sinking
CPUSB or CPPE = 3.6 V, sourcing
High level
0
10
1
30
2
Low level
RCLEN output low voltage
0.8
Output
PERST assertion threshold of output voltage (PERST
asserted when any output voltage falls below the
threshold)
4
SYSRST = 3.6 V, sinking
IO(RCLKEN) = 60 µA
0.4
3.3VOUT falling
2.7
AUXOUT falling
2.7
3
1.5VOUT falling
1.2
1.35
PERST assertion delay from output voltage
3.3VOUT, AUXOUT, or 1.5VOUT
falling
PERST de-assertion delay from output voltage
3.3VOUT, AUXOUT, and 1.5VOUT
rising within tolerance
PERST assertion delay from SYSRST
Max time from SYSRST asserted or
de-asserted
4
µA
µA
µA
µA
µA
V
V
3
10
V
500
ns
20
ms
500
ns
TPS2231
TPS2236
www.ti.com
SLVS536A – JULY 2004 – REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
TJ = 25°C, VI(3.3VIN) = VI(AUXIN) = 3.3 V, VI(1.5VIN) = 1.5 V, VI(/SHDNx), VI(/STBYx) = 3.3 V, VI(/CPPEx) = VI(/CPUSBx) = 0 V,
VI(/SYSRST) = 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)
PARAMETER
tW(PERST)
PERST minimum pulse width
PERST output low voltage
PERST output high voltage
TEST CONDITIONS
MIN
TYP
3.3VOUT, AUXOUT, or 1.5VOUT
falling out of tolerance or triggered by
SYSRST
100
250
IO(PERST) = 500 µA
OC output low voltage
IO(/OC) = 2 mA
OC leakage current
VO(/OC) = 3.6 V
OC deglitch
Falling into or out of an overcurrent
condition
MAX
UNIT
µs
0.4
2.4
V
V
0.4
V
1
µA
6
20
mS
UNDERVOLTAGE LOCKOUT (UVLO)
3.3VIN UVLO
3.3VIN level, below which 3.3VIN
and 1.5VIN switches are off
2.6
2.9
1.5VIN UVLO
1.5VIN level, below which 3.3VIN
and 1.5VIN switches are off
1
1.25
AUXIN UVLO
AUXIN level, below which all
switches are off
2.6
2.9
UVLO hysteresis
100
V
mV
SWITCHING CHARACTERISTICS
TJ = 25°C, VI(3.3VIN) = VI(AUXIN) = 3.3 V, VI(1.5VIN) = 1.5 V, VI(/SHDNx), VI(/STBYx) = 3.3 V, VI(/CPPEx) = VI(/CPUSBx) = 0 V,
VI(/SYSRST) = 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)
PARAMETER
tr
tf
tf
tpd(on)
Output rise times
Output fall times
when card removed
(both CPUSB and
CPPE de-asserted)
Output fall times
when SHDN
asserted (card is
present)
Turn-on propagation
delay
TEST CONDITIONS
MIN
TYP
MAX
3.3VIN to 3.3VOUT
CL(3.3VOUT) = 0.1 µF, IO(3.3VOUT) = 0 A
0.1
3
AUXIN to AUXOUT
CL(AUXOUT) = 0.1 µF, IO(AUXOUT) = 0 A
0.1
3
1.5VIN to 1.5VOUT
CL(1.5VOUT) = 0.1 µF, IO(1.5VOUT) = 0 A
0.1
3
3.3VIN to 3.3VOUT
CL(3.3VOUT) = 100 µF, RL = VI(3.3VIN)/1 A
0.1
6
AUXIN to AUXOUT
CL(AUXOUT) = 100 µF, RL = VI(AUXIN)/0.250 A
0.1
6
1.5VIN to 1.5VOUT
CL(1.5VOUT) = 100 µF, RL = VI(1.5VIN)/0.500 A
0.1
6
3.3VIN to 3.3VOUT
CL(3.3VOUT) = 0.1 µF, IO(3.3VOUT) = 0 A
10
150
AUXIN to VAUXOUT
CL(AUXOUT) = 0.1 µF, IO(AUXOUT) = 0 A
10
150
1.5VIN to 1.5VOUT
CL(1.5VOUT) = 0.1 µF, IO(1.5VOUT) = 0 A
10
150
3.3VIN to 3.3VOUT
CL(3.3VOUT) = 20 µF, IO(3.3VOUT) = 0 A
2
30
AUXIN to VAUXOUT
CL(AUXOUT) = 20 µF, IO(AUXOUT) = 0 A
2
30
1.5VIN to 1.5VOUT
CL(1.5VOUT) = 20 µF, IO(1.5VOUT) = 0 A
2
30
3.3VIN to 3.3VOUT
CL(3.3VOUT) = 0.1 µF, IO(3.3VOUT) = 0 A
10
150
AUXIN to VAUXOUT
CL(AUXOUT) = 0.1 µF, IO(AUXOUT) = 0 A
10
150
1.5VIN to 1.5VOUT
CL(1.5VOUT) = 0.1 µF, IO(1.5VOUT) = 0 A
10
150
3.3VIN to 3.3VOUT
CL(3.3VOUT) = 100 µF, RL = VI(3.3VIN)/1 A
0.1
5
AUXIN to VAUXOUT
CL(AUXOUT) = 100 µF RL = VI(AUXIN)/0.250 A
0.1
5
1.5VIN to 1.5VOUT
CL(1.5VOUT) = 100 µF, RL = VI(1.5VIN)/0.500 A
0.1
5
3.3VIN to 3.3VOUT
CL(3.3VOUT) = 0.1 µF, IO(3.3VOUT) = 0 A
0.1
1
AUXIN to VAUXOUT
CL(AUXOUT) = 0.1 µF, IO(AUXOUT) = 0A
0.05
0.5
1.5VIN to 1.5VOUT
CL(1.5VOUT) = 0.1 µF, IO(1.5VOUT) = 0 A
0.1
1
3.3VIN to 3.3VOUT
CL(3.3VOUT) = 100 µF, RL = VI(3.3VIN)/1 A
0.1
1.5
AUXIN to VAUXOUT
CL(AUXOUT) = 100 µF, RL = VI(AUXIN)/0.250 A
0.05
1
1.5VIN to 1.5VOUT
CL(1.5VOUT) = 100 µF, RL = VI(1.5VIN)/0.500 A
0.1
1.5
UNIT
ms
µs
ms
µs
ms
ms
5
TPS2231
TPS2236
www.ti.com
SLVS536A – JULY 2004 – REVISED NOVEMBER 2004
SWITCHING CHARACTERISTICS (continued)
TJ = 25°C, VI(3.3VIN) = VI(AUXIN) = 3.3 V, VI(1.5VIN) = 1.5 V, VI(/SHDNx), VI(/STBYx) = 3.3 V, VI(/CPPEx) = VI(/CPUSBx) = 0 V,
VI(/SYSRST) = 3.3 V, OCx and RCLKENx and PERSTx are open, all voltage outputs unloaded (unless otherwise noted)
PARAMETER
tpd(off)
Turn-off propagation
delay
TEST CONDITIONS
MIN
TYP
MAX
3.3VIN to 3.3VOUT
CL(3.3VOUT) = 0.1 µF, IO(3.3VOUT) = 0 A
0.1
1.5
AUXIN to VAUXOUT
CL(AUXOUT) = 0.1 µF, IO(AUXOUT) = 0 A
0.05
0.5
1.5VIN to 1.5VOUT
CL(1.5VOUT) = 0.1 µF, IO(1.5VOUT) = 0 A
0.1
1.5
3.3VIN to 3.3VOUT
CL(3.3VOUT) = 100 µF, RL = VI(3.3VIN)/1 A
0.1
1.5
AUXIN to VAUXOUT
CL(AUXOUT) = 100 µF, RL = VI(AUXIN)/0.250 A
0.05
0.5
1.5VIN to 1.5VOUT
CL(1.5VOUT) = 100 µF, RL = VI(1.5VIN)/0.500 A
0.1
1
PIN ASSIGNMENTS
TPS2231
PW PACKAGE
(TOP VIEW)
SYSRST
SHDN
STBY
3.3VIN
3.3VIN
3.3VOUT
3.3VOUT
PERST
NC
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TPS2231
PWP PACKAGE
(TOP VIEW)
OC
RCLKEN
AUXIN
AUXOUT
1.5VIN
1.5VIN
1.5VOUT
1.5VOUT
CPPE
CPUSB
NC
SYSRST
SHDN
STBY
3.3VIN
3.3VIN
3.3VOUT
3.3VOUT
PERST
NC
GND
NC
1
2
3
4
5
6
7
8
9
10
11
12
TPS2236
DAP PACKAGE
(TOP VIEW)
CPPE1
CPPE2
CPUSB1
NC
NC
CPUSB2
3.3VOUT1
3.3VIN
3.3VIN
3.3VOUT2
PERST2
NC
PERST1
AUXOUT1
AUXIN
AUXOUT2
NC − No internal connection
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RCLKEN1
RCLKEN2
SYSRST
NC
STBY1
STBY2
1.5VOUT1
1.5VIN
1.5VIN
1.5VOUT2
NC
GND
OC2
OC1
SHDN2
SHDN1
24
23
22
21
20
19
18
17
16
15
14
13
NC
OC
RCLKEN
AUXIN
AUXOUT
1.5VIN
1.5VIN
1.5VOUT
1.5VOUT
CPPE
CPUSB
NC
UNIT
ms
TPS2231
TPS2236
www.ti.com
SLVS536A – JULY 2004 – REVISED NOVEMBER 2004
TERMINAL FUNCTIONS
TERMINAL
TPS2231
NAME
TPS2236
NO.
NAME
NO.
I/O
DESCRIPTION
PW
PWP
3.3VIN
4, 5
5, 6
3.3VIN
DAP
8, 9
I
3.3-V input for 3.3VOUT
1.5VIN
15, 16
18, 19
1.5VIN
24, 25
I
1.5-V input for 1.5VOUT
AUXIN
18
21
AUXIN
15
I
AUX input for AUXOUT and chip power
GND
10
11
GND
21
3.3VOUT
6, 7
7, 8
3.3VOUT1
7
O
Ground
Switched output that delivers 0 V, 3.3 V or high impedance to card
1.5VOUT
13, 14
16, 17
1.5VOUT1
26
O
Switched output that delivers 0 V, 1.5 V or high impedance to card
AUXOUT
17
20
AUXOUT1
14
O
Switched output that delivers 0 V, AUX or high impedance to card
3.3VOUT2
10
O
Switched output that delivers 0 V, 3.3 V or high impedance to card
1.5VOUT2
23
O
Switched output that delivers 0 V, 1.5 V or high impedance to card
AUXOUT2
16
O
Switched output that delivers 0 V, AUX or high impedance to card
SYSRST
1
2
SYSRST
30
I
System Reset input – active low, logic level signal. Internally pulled up
to AUXIN.
CPPE
12
15
CPPE1
1
I
Card Present input for PCI Express cards. Internally pulled up to AUXIN
CPUSB
11
14
CPUSB1
3
I
Card Present input for USB cards. Internally pulled up to AUXIN.
CPPE2
2
I
Card Present input for PCI Express cards. Internally pulled up to
AUXIN.
PERST
SHDN
STBY
RCLKEN
OC
NC
8
2
3
19
20
9
9
3
4
22
23
1, 10,
12, 13,
24
CPUSB2
6
I
Card Present input for USB cards. Internally pulled up to AUXIN.
PERST1
13
O
A logic level power good to slot 0 (with delay)
PERST2
11
O
A logic level power good to slot 1 (with delay)
SHDN1
17
I
Shutdown input – active low, logic level signal. Internally pulled up to
AUXIN.
SHDN2
18
I
Shutdown input – active low, logic level signal. Internally pulled up to
AUXIN.
STBY1
28
I
Standby input – active low, logic level signal. Internally pulled up to
AUXIN.
STBY2
27
I
Standby input – active low, logic level signal. Internally pulled up to
AUXIN.
RCLKEN1
32
I/O
Reference Clock Enable signal. As an output, a logic level power good
to host for slot 0 (no delay – open drain). As an input, if kept inactive
(low) by the host, prevents PERST from being de-asserted. Internally
pulled up to AUXIN.
RCLKEN2
31
I/O
Reference Clock Enable signal. As an output, a logic level power good
to host for slot 1 (no delay – open drain). As an input, if kept inactive
(low) by the host, prevents PERST from being de-asserted. Internally
pulled up to AUXIN.
OC1
19
O
Overcurrent status output for slot 0 (open drain)
OC2
20
O
Overcurrent status output for slot 1 (open drain)
NC
4, 5, 12,
22, 29
No connection
7
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SLVS536A – JULY 2004 – REVISED NOVEMBER 2004
FUNCTIONAL BLOCK DIAGRAM
Single ExpressCard Power Switch
3.3VIN
PG
S1
(Note A)
AUXIN
3.3VOUT
CS
(Note B)
PG
S4
CS
AUXOUT
S2
S5
1.5VIN
PG
1.5VOUT
CS
S3
S6
Current Limit
CPUSB
Thermal Limit
CPPE
OC
STBY
SHDN
UVLO
POR
GND
FAULT
PWR_GOOD_ALL
Control
Logic
AUXIN
Delay
RCLKEN
AUXIN
PERST
SYSRST
Note A: PG = power good
Note B: CS = current sense
8
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SLVS536A – JULY 2004 – REVISED NOVEMBER 2004
FUNCTIONAL BLOCK DIAGRAM (continued)
Dual ExpressCard Power Switch
3.3VIN
S1
PG1
CS
3.3VOUT1
S4
PG1
AUXIN
CS
AUXOUT1
S2
S5
1.5VIN
S3
PG1
1.5 VOUT1
CS
S6
PG2
CS
3.3VOUT2
S7
S10
PG2
CS
AUXOUT2
S8
S11
PG2
CS
1.5VOUT2
S9
S12
Current Limit
CPUSB1
Thermal Limit
CPPE1
OC1
PWR_GOOD_ALL_1
CHANNEL-1
FAULT
STBY1
Control
Logic
PWR_GOOD_ALL_2
SHDN1
CPUSB2
CPPE2
AUXIN
Delay
RCLKEN1
PERST1
SYSRST
Delay
RCLKEN2
STBY2
PERST2
UVLO
SHDN2
GND
POR
CHANNEL-2
FAULT
OC2
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DETAILED PIN DESCRIPTIONS
CPPE
A logic low level on this input indicates that the card present supports PCI Express functions. CPPE connects to
the AUXIN input through an internal pullup. When a card is inserted, CPPE is physically connected to ground if
the card supports PCI Express functions.
CPUSB
A logic low level on this input indicates that the card present supports USB functions. CPUSB connects to the
AUXIN input through an internal pullup. When a card is inserted, CPUSB is physically connected to ground if the
card supports USB functions.
SHDN
When asserted (logic low), this input instructs the power switch to turn off all voltage outputs and the discharge
FETs are activated. SHDN has an internal pullup connected to AUXIN.
STBY
When asserted (logic low) after the card is inserted, this input places the power switch in standby mode by
turning off the 3.3-V and 1.5-V power switches and keeping the AUX switch on. If asserted prior to the card being
present, STBY places the power switch in OFF Mode by turning off the AUX, 3.3-V, and 1.5-V power switches.
STBY has an internal pullup connected to AUXIN.
RCLKEN
This pin serves as both an input and an output. On power up, a discharge FET keeps this signal at a low state as
long as any of the output power rails are out of their tolerance range. Once all output power rails are within
tolerance, the switch releases RCLKEN allowing it to transition to a high state (internally pulled up to AUXIN).
The transition of RCLKEN from a low to a high state starts an internal timer for the purpose of deasserting
PERST. As an input, RCLKEN can be kept low to delay the start of the PERST internal timer.
Because RCLKEN is internally connected to a discharge FET, this pin can only be driven low and should never
be driven high as a logic input. When an external circuit drives this pin low, RCLKEN becomes an input;
otherwise, this pin is an output.
RCLKEN can be used by the host system to enable a clock driver.
PERST
On power up, this output remains asserted (logic level low) until all power rails are within tolerance. Once all
power rails are within tolerance and RCLKEN has been released (logic high), PERST is deasserted (logic high)
after a time delay as shown in the parametric table. On power down, this output is asserted whenever any of the
power rails drop below their voltage tolerance.
The PERST signal is an output from the host system and an input to the ExpressCard module. This signal is only
used by PCI Express-based modules and its function is to place the ExpressCard module in a reset state.
During power up, power down, or whenever power to the ExpressCard module is not stable or not within voltage
tolerance limits, the ExpressCard standard requires that PERST be asserted. As a result, this signal also serves
as a power-good indicator to the ExpressCard module, and the relationship between the power rails and PERST
are explicitly defined in the ExpressCard standard.
The host can also place the ExpressCard module in a reset state by asserting a system reset SYSRST. This
system reset generates a PERST to the ExpressCard module without disrupting the voltage rails. This is what is
normally called a warm reset. However, in a cold start situation, the system reset can also be used to extend the
length of time that PERST is asserted.
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Detailed Pin Descriptions (continued)
SYSRST
This input is driven by the host system and directly affects PERST. Asserting SYSRST (logic low) forces PERST
to assert. RCLKEN is not affected by the assertion of SYSRST. SYSRST has an internal pullup connected to
AUXIN.
OC
This pin is an open-drain output. When any of the three power switches (AUX, 3.3V, and 1.5V) is in an
overcurrent condition, OC is asserted (logic low) by an internal discharge FET with a deglitch delay. Otherwise,
the discharge FET is open, and the pin can be pulled up to a power supply through an external resistor.
FUNCTIONAL TRUTH TABLES
Truth Table for Voltage Outputs
VOLTAGE
INPUTS (1)
AUXIN
3.3VIN
1.5VIN
SHDN
STBY
Off
x
x
x
x
On
x
x
0
On
x
x
1
On
On
On
On
On
On
(1)
(2)
(3)
(4)
VOLTAGE OUTPUTS (2)
LOGIC INPUTS
CP
(4)
MODE (3)
AUXOUT
3.3VOUT
1.5VOUT
x
Off
Off
Off
OFF
x
x
GND
GND
GND
Shutdown
x
1
GND
GND
GND
No Card
1
0
0
On
Off
Off
Standby
1
1
0
On
On
On
Card Inserted
For input voltages, On means the respective input voltage is higher than its turnon threshold voltage; otherwise, the voltage is Off (for
AUX input,Off means the voltage is close to zero volt).
For output voltages, On means the respective power switch is turned on so the input voltage is connected to the output; Off means the
power switch and its output discharge FET are both off; GND means the power switch is off but the output discharge FET is on so the
voltage on the output is pulled down to 0 V.
Mode assigns each set of input conditions and respective output voltage results to a different name. These modes are referred to as
input conditions in the following Truth Table for Logic Outputs.
CP = CPUSB and CPPE– equal to 1 when both CPUSB and CPPE signals are logic high, or equal to 0 when either CPUSB or CPPE is
low.
Truth Table for Logic Outputs
INPUT CONDITIONS
MODE
LOGIC OUTPUTS
SYSRST
RCLKEN (1)
PERST
RCLKEN (2)
X
X
0
0
0
Hi-Z
0
1
0
0
0
0
1
Hi-Z
1
1
1
0
0
0
OFF
Shutdown
No Card
Standby
Card Inserted
(1)
(2)
RCLKEN as a logic input in this column. RCLKEN is an I/O pin and it can be driven low externally, left open, or connected to
high-impedance terminals, such as the gate of a MOSFET. It must not be driven high externally.
RCLKEN as a logic output in this column.
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POWER STATES
If AUXIN is not present, then all input-to-output power switches are kept off (OFF mode).
If AUXIN is present and SHDN is asserted (logic low), then all input-to-output power switches are kept off and the
output discharge FETs are turned on (Shutdown mode). If SHDN is asserted and then de-asserted, the state on
the outputs is restored to the state prior to SHDN assertion.
If 3.3VIN, AUXIN and 1.5VIN are present at the input of the power switch and no card is inserted, then all
input-to-output power switches are kept off and the output discharge FETs are turned on (No Card mode).
If 3.3VIN, AUXIN and 1.5VIN are present at the input of the power switch prior to a card being inserted, then all
input-to-output power switches are turned on once a card-present signal (CPUSB and/or CPPE) is detected
(Card Inserted mode).
If a card is present and all output voltages are being applied, then the STBY is asserted (logic low); the AUXOUT
voltage is provided to the card, and the 3.3VOUT and 1.5VOUT switches are turned off (Standby mode).
If a card is present and all output voltages are being applied, then the 1.5VIN, or 3.3VIN is removed from the
input of the power switch; the AUXOUT voltage is provided to the card and the 3.3VOUT and 1.5VOUT switches
are turned off (Standby mode).
If prior to the insertion of a card, the AUXIN is available at the input of the power switch and 3.3VIN and/or
1.5VIN are not, or if STBY is asserted (logic low), then no power is made available to the card (OFF mode). If
1.5VIN and 3.3VIN are made available at the input of the power switch after the card is inserted and STBY is not
asserted, all the output voltages are made available to the card (Card Inserted mode).
DISCHARGE FETs
The discharge FETs on the outputs are activated whenever the device detects that a card is not present (No
Card mode). Activation occurs after the input-to-output power switches are turned off (break before make). The
discharge FETs de-activate if either of the card-present lines go active low, unless the SHDN pin is asserted.
The discharge FETs are also activated whenever the SHDN input is asserted and stay asserted until SHDN is
de-asserted.
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PARAMETER MEASUREMENT INFORMATION
VIN
IO(3.3VOUT/AUXOUT)
RL
CL
VIN
IO(1.5VOUT)
RL
CL
LOAD CIRCUIT
LOAD CIRCUIT
VOLTAGE WAVEFORMS
VIN
VI(3.3V/AUXIN)
50%
VIN
VI(1.5V)
50%
GND
GND
tpd(off)
tpd(on)
VO(3.3VOUT/AUXOUT)
tpd(off)
tpd(on)
VI(3.3V)
90%
10%
90%
10%
VO(1.5VOUT)
GND
VI(3.3V)
50%
tf
tr
VI(3.3V)
Rise/Fall Time (3.3VOUT/AUXOUT)
VIN
GND
Propagation Delay (1.5VOUT)
tf
tr
VO(3.3VOUT/AUXOUT)
10%
GND
Propagation Delay (3.3VOUT/AUXOUT)
VI(1.5V)
90%
VO(1.5VOUT)
90%
10%
VI(1.5V)
GND
Rise/Fall Time (1.5VOUT)
VIN
VI(1.5V)
50%
GND
GND
toff
toff
ton
VO(3.3VOUT/AUXOUT)
ton
VI(3.3V)
90%
10%
VO(1.5VOUT)
GND
Turn On/Off Time (3.3VOUT/AUXOUT)
VI(1.5V)
90%
10%
GND
Turn On/Off Time (1.5VOUT)
Figure 1. Test Circuits and Voltage Waveforms
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Output voltage when card is inserted
vs Time
2
RCLKEN and PERST voltage during power up
vs Time
3
RCLKEN and PERST voltage during power down
vs Time
4
PERST asserted by SYSRST when power is on
vs Time
5
PERST de-asserted by SYSRST when power is on
vs Time
6
Output voltage when 3.3VIN is removed
vs Time
7
Output voltage when 1.5VIN is removed
vs Time
8
OC response when powered into a short (3.3VOUT)
vs Time
9
Supply current of AUXIN
vs Junction temperature
10
Static drain-source on-state resistance
vs Junction temperature
11
3.3-V power switch current limit
vs Junction temperature
12
1.5-V power switch current limit
vs Junction temperature
13
AUX power switch current limit
vs Junction temperature
14
3.3-V power switch current limit trip
vs Junction temperature
15
1.5-V power switch current limit trip
vs Junction temperature
16
AUX power switch current limit trip
vs Junction temperature
17
OUTPUT VOLTAGE WHEN CARD IS INSERTED
vs
TIME
RCLKEN AND PERST VOLTAGE DURING POWER UP
vs
TIME
VI(CPxx)
2 V/div
VO(3.3VOUT)
2 V/div
VO(3.3VOUT)
2 V/div
2 V/div
VO(RCLKEN)
2 V/div
VO(AUXOUT)
2 V/div
VO(PERST)
2 V/div
VO(1.5VOUT)
t − Time − 1 ms/div
Figure 2.
14
t − Time − 5 ms/div
Figure 3.
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RCLKEN AND PERST VOLTAGE DURING POWER DOWN
vs
TIME
PERST ASSERTED BY SYSRST WHEN POWER IS ON
vs
TIME
VO(AUXOUT)
2 V/div
VI(SYSRST)
2 V/div
VO(RCLKEN)
2 V/div
VO(PERST)
2 V/div
VO(PERST)
2 V/div
t − Time − 1 ms/div
t − Time − 500 ns/div
Figure 4.
Figure 5.
PERST DE-ASSERTED BY SYSRST WHEN POWER IS ON
vs
TIME
OUTPUT VOLTAGE WHEN 3.3VIN IS REMOVED
vs
TIME
VI(3.3VIN)
2 V/div
VI(SYSRST)
2 V/div
VO(3.3VOUT)
2 V/div
VO(1.5VOUT)
2 V/div
VO(PERST)
2 V/div
VO(AUXOUT)
2 V/div
RL(3.3VOUT) = 3.6
RL(1.5VOUT) = 2.7
RL(AUXOUT) = 12
CL(3.3V/1.5V/AUXOUT) = 68 F
t − Time − 100 s/div
Figure 6.
t − Time − 500 s/div
Figure 7.
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OC RESPONSE WHEN POWERED INTO A SHORT
(3.3VOUT)
vs
TIME
OUTPUT VOLTAGE WHEN 1.5VIN IS REMOVED
vs
TIME
VI(1.5VIN)
2 V/div
VO(OC)
2 V/div
VO(3.3VOUT)
2 V/div
VO(1.5VOUT)
2 V/div
RL(3.3VOUT) = 3.6
RL(1.5VOUT) = 2.7
VO(AUXVOUT)
2 V/div
IO(3.3VOUT)
0.5 A/div
RL(AUXOUT) = 12
CL(3.3V/1.5V/AUXOUT) = 68 F
t − Time − 500 s/div
t − Time − 5 ms/div
Figure 8.
Figure 9.
SUPPLY CURRENT OF AUXIN
vs
JUNCTION TEMPERATURE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
180
250
AUXIN + CPxx
150
AUXIN
50
On−State Resistance − m Ω
rDS(on) − Static Drain-Source
ICC − Supply Current − µ A
200
100
140
120
100
80
40
20
−20
0
20
40
60
80
100
120
1.5VIN
60
0
−40
0
−40
3.3V_AUX
160
AUXIN + CPxx + SHDN+ RCLKEN
3.3VIN
−20
0
20
40
60
80
100
TJ − Junction Temperature − C
TJ − Junction Temperature − C
Figure 10.
16
Figure 11.
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3.3-V POWER SWITCH CURRENT LIMIT
vs
JUNCTION TEMPERATURE
1.5-V POWER SWITCH CURRENT LIMIT
vs
JUNCTION TEMPERATURE
2.10
1000
990
980
Current Limit − mA
Current Limit − A
2.05
2
970
960
950
940
930
1.95
920
910
1.90
−40
−20
0
20
40
60
80
100
900
−40
120
−20
TJ − Junction Temperature − C
0
20
40
60
80
100
120
TJ − Junction Temperature − C
Figure 12.
Figure 13.
AUX POWER SWITCH CURRENT LIMIT
vs
JUNCTION TEMPERATURE
3.3-V POWER SWITCH CURRENT LIMIT TRIP
vs
JUNCTION TEMPERATURE
500
3.20
490
3.10
Current Limit Trip Threshold − A
480
Current Limit − mA
470
460
450
440
430
420
410
3
2.90
2.80
2.70
2.60
400
390
−40
−20
0
20
40
60
80
100
TJ − Junction Temperature − C
Figure 14.
120
2.50
−40
−20
0
20
40
60
80
100
120
TJ − Junction Temperature − C
Figure 15.
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SLVS536A – JULY 2004 – REVISED NOVEMBER 2004
1.5-V POWER SWITCH CURRENT LIMIT TRIP
vs
JUNCTION TEMPERATURE
AUX POWER SWITCH CURRENT LIMIT TRIP
vs
JUNCTION TEMPERATURE
800
2000
Current Limit Trip Threshold − mA
Current Limit Trip Threshold − mA
1900
1800
1700
1600
1500
1400
1300
1200
760
720
680
640
1100
1000
−40
−20
0
20
40
60
80
100
TJ − Junction Temperature − C
Figure 16.
18
120
600
−40
−20
0
20
40
60
80
TJ − Junction Temperature − C
Figure 17.
100
120
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APPLICATION INFORMATION
INTRODUCTION TO ExpressCard
An ExpressCard module is an add-in card with a serial interface based on PCI Express and/or Universal Serial
Bus (USB) technologies. An ExpressCard comes in two form factors defined as ExpressCard|34 or
ExpressCard|54. The difference, as defined by the name, is the width of the module, 34 mm or 54 mm,
respectively. Host systems supporting the ExpressCard module can support either the ExpressCard|34 or
ExpressCard|54 or both.
ExpressCard POWER REQUIREMENTS
Regardless of which ExpressCard module is used, the power requirements as defined in the ExpressCard
Standard apply to both on an individual slot basis. The host system is required to supply 3.3 V, 1.5 V, and AUX
to each of the ExpressCard slots. However, the voltage is only applied after an ExpressCard is inserted into the
slot.
The ExpressCard connector has two pins, CPPE and CPUSB, that are used to signal the host when a card is
inserted. If the ExpressCard module itself connects the CPPE to ground, the logic low level on that signal
indicates to the host that a card supporting PCI Express has been inserted. If CPUSB is connected to ground,
then the ExpressCard module supports the USB interface. If both PCI Express and USB are supported by the
ExpressCard module, then both signals, CPPE and CPUSB, must be connected to ground.
In addition to the Card Present signals (CPPE and CPUSB), the host system determines when to apply power to
the ExpressCard module based on the state of the system. The state of the system is defined by the state of the
3.3 V, 1.5 V, and AUX input voltage rails. For the sake of simplicity, the 3.3-V and 1.5-V rails are defined as the
primary voltage rails as oppose to the auxiliary voltage rail, AUX.
ExpressCard POWER SWITCH OPERATION
The ExpressCard power switch resides on the host, and its main function is to control when to send power to the
ExpressCard slot. The ExpressCard power switch makes decisions based on the Card Present inputs and on the
state of the host system as defined by the primary and auxiliary voltage rails.
The following conditions define the operation of the host power controller:
1. When both primary power and auxiliary power at the input of the ExpressCard power switch are off, then all
power to the ExpressCard connector is off regardless of whether a card is present.
2. When both primary power and auxiliary power at the input of the ExpressCard power switch are on, then
power is only applied to the ExpressCard after the ExpressCard power switch detects that a card is present.
3. When primary power (either +3.3 V or +1.5 V) at the input of the ExpressCard power switch is off and
auxiliary power at the input of the ExpressCard power switch is on, then the ExpressCard power switch
behaves in the following manner:
a. If neither of the Card Present inputs is detected (no card inserted), then no power is applied to the
ExpressCard slot.
b. If the card is inserted after the system has entered this power state, then no power is applied to the
ExpressCard slot.
c. If the card is inserted prior to the removal of the primary power (either +3.3 V or +1.5 V or both) at the
input of the ExpressCard power switch, then only the primary power (both +3.3 V and +1.5 V) is removed
and the auxiliary power is sent to the ExpressCard slot.
Figure 18 through Figure 23 illustrate the timing relationships between power/logic inputs and outputs of
ExpressCard.
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APPLICATION INFORMATION (continued)
EXPRESS CARD TIMING DIAGRAMS
Host Power
(AUXIN, 3.3VIN,
and 1.5VIN)
SYSRST
CPxx
a
Card Power
(AUXIN, 3.3VOUT,
and 1.5VOUT)
RCLKEN
b
PERST
Tpd
REFCLK
g
c
d
e
a
b
c
d
e
f
g
Min
Max
System Dependent
100
System Dependent
System Dependent
100
4
Units
s
s
20
ms
10
ms
Max
Units
f
Figure 18. Timing Signals - Card Present Before Host Power Is On
Host Power
(AUXIN, 3.3VIN,
and 1.5VIN)
SYSRST
CPxx
Card Power
(AUXIN, 3.3VOUT,
and 1.5VOUT)
RCLKEN
a
PERST
Tpd
REFCLK
b
c
d
a
b
c
d
e
Min
100
10
System Dependent
System Dependent
20
4
e
Figure 19. Timing Signals - Host Power Is On Prior to Card Insertion
20
s
ms
ms
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APPLICATION INFORMATION (continued)
Host Power
(AUXIN)
Host Power
(3.3VIN and 1.5VIN)
SYSRST
CPxx
Card Power
(AUXIN, 3.3VOUT,
and 1.5VOUT)
RCLKEN
PERST
REFCLK
(Either Tri-Stated or Off)
Note: Once 3.3 V and 1.5 V are applied, the power switch follows the power-up sequence of Figure 18 or Figure 19.
Figure 20. Timing Signals - Host System In Standby Prior to Card Insertion
Host Power
(AUXIN, 3.3VIN, and 1.5VIN)
c
SYSRST
CPxx
Card Power
(AUXOUT, 3.3VOUT, and 1.5VOUT)
RCLKEN
d
a
e
PERST
REFCLK
a
Tpd
a
b
c
d
e
Min
Max
500
System Dependent
System Dependent
Load Dependent
500
Units
ns
ns
Figure 21. Timing Signals - Host-Controlled Power Down
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APPLICATION INFORMATION (continued)
Host Power
(AUXIN, 3.3VIN, and 1.5VIN)
e
SHDN
CPxx
f
Card Power
(AUXOUT, 3.3VOUT, and 1.5VOUT)
RCLKEN
a
d
Tpd
PERST
f
c
REFCLK
a
b
c
d
e
f
Min
Max
Units
Load Dependent
System Dependent
500
500
System Dependent
System Dependent
ns
ns
Figure 22. Timing Signals - Controlled Power Down When SHDN Asserted
Host Power
(AUXIN, 3.3VIN, and 1.5VIN)
SYSRST
CPxx
Card Power
(AUXOUT, 3.3VOUT, and 1.5VOUT)
a
RCLKEN
d
Tpd
a
PERST
b
REFCLK
b
c
d
c
Figure 23. Timing Signals - Suprise Card Removal
22
Min
Max
Load Dependent
500
System Dependent
500
Units
ns
ns
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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• DALLAS, TEXAS 75265
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