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TPS22810
SLVSDH0C – DECEMBER 2016 – REVISED JANUARY 2018
TPS22810, 2.7-18-V, 79-mΩ On-Resistance Load Switch With Thermal Protection
1 Features
3 Description
•
•
The TPS22810 is a single channel load switch with
configurable rise time and with an integrated quick
output discharge (QOD). In addition, the device
features thermal shutdown to protect the device
against high junction temperature. Because of this,
safe operating area of the device is inherently
ensured. The device contains an N-channel MOSFET
that can operate over an input voltage range of 2.7 V
to 18 V. SOT23-5 (DBV) package can support a
maximum current of 2 A. WSON (DRV) package can
support a maximum current of 3 A. The switch is
controlled by an on and off input, which is capable of
interfacing directly with low-voltage control signals.
1
•
•
•
•
•
•
•
•
•
•
•
•
(1)
Integrated Single Channel Load Switch
Ambient Operating Temperature:
–40°C to +105°C
– SOT23-6 (DBV): 2-A Maximum Continuous
Current 1
– WSON (DRV): 3-A Maximum Continuous
Current 1
Input Voltage Range: 2.7 V to 18 V
Absolute Maximum Input Voltage: 20 V
On-Resistance (RON)
– RON = 79 mΩ (typical) at VIN = 12 V
Quiescent Current
– 62 µA (typical) at VIN = 12 V
Shutdown Current
– 500 nA (typical) at VIN = 12 V
Thermal Shutdown
Undervoltage Lock-Out (UVLO)
Adjustable Quick Output Discharge (QOD)
Configurable Rise Time With CT Pin
SOT23-6 Package
– 2.9-mm × 2.8-mm, 0.95-mm Pitch
1.45-mm Height (DBV)
WSON Package
– 2-mm × 2-mm, 0.65-mm Pitch
0.75-mm Height (DRV)
ESD Performance Tested per JESD 22
– ±2-kV HBM and ±1-kV CDM
The TPS22810 is available in a leaded, SOT-23
package (DBV) which allows to visually inspect solder
joints, as well as a WSON package (DRV). The
device is characterized for operation over the free-air
temperature range of –40˚C to +105˚C.
Device Information(1)
PART NUMBER
PACKAGE
TPS22810
BODY SIZE (NOM)
SOT-23 (6)
2.90 mm × 2.80 mm
WSON (6)
2.00 mm × 2.00 mm
Thermal performance must be considered
2 Applications
•
•
•
•
The configurable rise time of the device greatly
reduces inrush current caused by large bulk load
capacitances, thereby reducing or eliminating power
supply droop. Undervoltage lock-out is used to turn
off the device if the VIN voltage drops below a
threshold value, ensuring that the downstream
circuitry is not damaged by being supplied by a
voltage lower than intended. The configurable QOD
pin controls the fall time of the device to allow design
flexibility for power down.
HD TV
Industrial Systems
Set Top Box
Surveillance systems
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VIN
Power
Supply
VOUT
CIN
CL
GND
QOD
ON
OFF
EN/
UVLO
RL
CT
TPS22810
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS22810
SLVSDH0C – DECEMBER 2016 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical DC Characteristics .......................................
Typical AC Characteristics........................................
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
13
13
17
10 Application and Implementation........................ 18
10.1
10.2
10.3
10.4
10.5
Application Information..........................................
ON and OFF Control.............................................
Input Capacitor (Optional).....................................
Output Capacitor (Optional) ..................................
Typical Application ...............................................
18
18
18
18
18
11 Power Supply Recommendations ..................... 23
12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Example .................................................... 24
12.3 Thermal Considerations ........................................ 24
13 Device and Documentation Support ................. 25
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
25
14 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
Changes from Revision B (May 2017) to Revision C
•
Page
Changed Rise time can be calculated by multiplying to Rise time can be calculated by dividing in the Feature
Description Section 9.3.4 Adjustable Rise Time (CT) .......................................................................................................... 17
Changes from Revision A (December2016) to Revision B
Page
•
Added WSON (DRV) current information in the Features , Description section and Recommended Operating
Conditions table ...................................................................................................................................................................... 1
•
Added WSON (DRV) package .............................................................................................................................................. 1
Changes from Original (December 2016) to Revision A
Page
•
Deleted IMAX and IPLS from the Absolute Maximum Ratings table .......................................................................................... 1
•
Deleted IMAX and IPLS from the Absolute Maximum Ratings table .......................................................................................... 4
•
Changed the Quiescent current MAX value From: 70 µA To: 80 µA in the Electrical Characteristics table ......................... 5
•
Changed the Quiescent current MAX value for VIN = 2.7 V From: 60 µA To: 70 µA in the Electrical Characteristics
table ....................................................................................................................................................................................... 5
•
Changed the Shutdown current MAX value From: 2.25 µA To: 2.3 µA in the Electrical Characteristics table...................... 5
2
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SLVSDH0C – DECEMBER 2016 – REVISED JANUARY 2018
5 Device Comparison Table
Package
QUICK OUTPUT
DISCHARGE
TA
MAXIMUM
OUTPUT
CURRENT
ENABLE
79 mΩ
DBV
Configurable
105°C
2A
Active High
79 mΩ
DRV
Configurable
105°C
3A
Active High
DEVICE
RON at 12 V
TPS22810
TPS22810
6 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
DRV Package
6-Pin WSON
Top View
VIN
1
6
VOUT
GND
2
5
QOD
EN/UVLO
3
4
CT
VOUT
1
6
VIN
QOD
2
5
EN/UVLO
CT
3
4
GND
Pin Functions
PIN
NAME
NO,
I/O
DESCRIPTION
SOT23
WSON
CT
4
3
O
Switch slew rate control. Can be left floating
EN/UVLO
3
5
I
Active high switch control input and UVLO adjustment. Do not leave
floating
GND
2
4
—
Device ground
Quick Output Discharge pin. This functionality can be enabled in one
of three ways.
•
Placing an external resistor between VOUT and QOD
•
Tying QOD directly to VOUT and using the internal resistor value
(RPD)
•
Disabling QOD by leaving pin floating
See the Quick Output Discharge (QOD) for more information
QOD
5
2
O
VIN
1
6
I
Switch input. Place ceramic bypass capacitor(s) between this pin and
GND
VOUT
6
1
O
Switch output
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SLVSDH0C – DECEMBER 2016 – REVISED JANUARY 2018
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
VIN
Input voltage
–0.3
20
V
VOUT
Output voltage
–0.3
min(VIN + 0.3, 20)
V
VEN/UVLO
EN/UVLO voltage
–0.3
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
–65
20
V
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Electrostatic
discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
2.7
18
V
0
18
V
VIN
V
VIN
Input voltage
VEN/UVLO
EN/UVLO voltage
VOUT
Output voltage
IMAX
Maximum continuous switch current, TA = 65°C (DBV)
2
Maximum continuous switch current, TA = 65°C (DRV)
3
TA
Operating free-air temperature
CIN
Input capacitor
(1)
(2)
(1)
–40
1 (2)
105
UNIT
A
°C
µF
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(MAX)], the
maximum power dissipation of the device in the application [PD(MAX)], and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(MAX) = TJ(MAX) – (θJA × PD(MAX)).
See the Detailed Description section.
7.4 Thermal Information
TPS22810
THERMAL METRIC
(1)
DBV (SOT23)
DRV (WSON)
6 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
182
74.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
127.2
80.3
°C/W
RθJB
Junction-to-board thermal resistance
16.9
44.3
°C/W
ψJT
Junction-to-top characterization parameter
26.4
3.2
°C/W
ψJB
Junction-to-board characterization parameter
36.3
44.6
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLVSDH0C – DECEMBER 2016 – REVISED JANUARY 2018
7.5 Electrical Characteristics
Unless otherwise noted, the specification in the following table applies over the following ambient operating temperature
–40°C ≤ TA ≤ +105°C. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
VIN = 18 V
VIN = 12 V
IQ, VIN
Quiescent
current
V = 18 V, I = 0 A
VIN = 5 V
VIN = 3.3 V
VIN = 2.7 V
VIN = 18 V
VIN = 12 V
ISD, VIN
Shutdown
current
VON = 0 V, VOUT = 0 V
VIN = 5 V
VIN = 3.3 V
VIN = 2.7 V
TA
MIN
–40°C to +85°C
TYP
MAX
62
80
–40°C to +105°C
UNIT
85
–40°C to +85°C
62
–40°C to +105°C
80
85
–40°C to +85°C
59
–40°C to +105°C
80
85
–40°C to +85°C
53
–40°C to +105°C
µA
80
85
–40°C to +85°C
49
70
0.5
2.3
–40°C to +105°C
85
–40°C to +85°C
–40°C to +105°C
3.8
–40°C to +85°C
0.5
–40°C to +105°C
2.3
3.8
–40°C to +85°C
0.5
–40°C to +105°C
2.3
3.8
–40°C to +85°C
0.5
–40°C to +105°C
µA
2.3
3.8
–40°C to +85°C
0.5
2.3
–40°C to +105°C
3.8
–40°C to +105°C
0.1
µA
2.62
V
IEN/UVLO
EN/UVLO pin
input leakage
current
VUVR
VIN UVLO
threshold, rising
–40°C to +105°C
VUVhyst
VIN UVLO
hysteresis
–40°C to +105°C
VENR
EN threshold
voltage, rising
–40°C to +105°C
1.13
1.23
1.3
V
VENF
EN threshold
voltage, falling
–40°C to +105°C
1.08
1.13
1.18
V
VSHUTF
EN threshold
voltage for low
IQ shutdown
–40°C to +105°C
0.5
0.75
0.9
V
VIN = 18 V, IOUT = 0 A
2
2.54
5%
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Electrical Characteristics (continued)
Unless otherwise noted, the specification in the following table applies over the following ambient operating temperature
–40°C ≤ TA ≤ +105°C. Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
TA
25°C
VIN = 18 V, IOUT = –200 mA
MIN
TYP
MAX
79
86
–40°C to +85°C
105
–40°C to +105°C
25°C
VIN = 12 V, IOUT = –200 mA
115
79
–40°C to +85°C
VIN = 9 V, IOUT = –200 mA
RON
115
79
–40°C to +85°C
25°C
VIN = 5 V, IOUT = –200 mA
115
79
–40°C to +85°C
VIN = 3.3 V, IOUT = –200 mA
–40°C to +85°C
Output pull
down resistance
RPD
92
115
–40°C to +105°C
VIN = 2.7 V, IOUT = –200 mA
mΩ
115
83
25°C
86
105
–40°C to +105°C
25°C
86
105
–40°C to +105°C
On-resistance
86
105
–40°C to +105°C
25°C
UNIT
125
86
95
–40°C to +85°C
120
–40°C to +105°C
130
VIN = VOUT = 18 V, VEN/UVLO = 0 V
–40°C to +105°C
290
350
VIN = VOUT = 12 V, VEN/UVLO = 0 V
–40°C to +105°C
265
350
VIN = VOUT = 5 V, VEN/UVLO = 0 V
–40°C to +105°C
250
400
Ω
TS
Thermal
shutdown
Threshold, VIN = 18 V
–40°C to +105°C
160
°C
TSHDN
Hyst
Thermal
shutdown
hysteresis
TSD hysteresis, VIN = 18 V
–40°C to +105°C
30
°C
6
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7.6 Switching Characteristics
Refer to the timing test circuit in Figure 16 (unless otherwise noted) for references to external components used for the test
condition in the switching characteristics table. Switching characteristics shown below are only valid for the power-up
sequence where VIN is already in steady state condition before the EN/UVLO pin is asserted high.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = 18 V, VEN/UVLO = 5 V, TA = 25 °C (unless otherwise noted)
tON
Turnon time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
tOFF
Turnoff time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
520
3.3
tR
VOUT rise time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
700
tF
VOUT fall time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
2
tD
Delay time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
180
µs
VIN = 12 V, VEN/UVLO = 5 V, TA = 25 °C (unless otherwise noted)
tON
Turnon time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
tOFF
Turnoff time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
380
3.3
tR
VOUT rise time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
460
tF
VOUT fall time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
2
tD
ON delay time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
150
µs
VIN = 3.3 V, VEN/UVLO = 5 V, TA = 25 °C (unless otherwise noted)
tON
Turnon time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
tOFF
Turnoff time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
185
3.3
tR
VOUT rise time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
120
tF
VOUT fall time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
2
tD
ON delay time
RL = 10 Ω, CIN = 1 µF, CL = 0.1 µF, CT = 2200 pF
130
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7
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SLVSDH0C – DECEMBER 2016 – REVISED JANUARY 2018
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90
1.8
80
1.6
70
1.4
Shutdown Current (PA)
Quiescent Current (PA)
7.7 Typical DC Characteristics
60
50
40
30
-40qC
25qC
85qC
105qC
20
10
0
2.7
4.7
-40qC
25qC
85qC
105qC
1.2
1
0.8
0.6
0.4
0.2
6.7
VEN/UVLO = 5 V
8.7
10.7
12.7
Input Voltage (V)
14.7
0
2.7
16.7 18
IOUT = 0 A
6.7
VEN/UVLO = 0 V
Figure 1. Quiescent Current vs Input Voltage
8.7
10.7
12.7
Input Voltage (V)
14.7
D002
IOUT = 0 A
Figure 2. Shutdown Current vs Input Voltage
VIN = 2.7 V
VIN = 3.3 V
VIN t 5 V
130
140
On-Resistance (m:)
120
110
100
90
80
70
120
100
80
60
40
-40qC
25qC
85qC
105qC
60
20
50
40
-40
-20
0
VEN/UVLO = 5 V
20
40
60
Temperature (qC)
80
0
2.7
100
IOUT = –200 mA
400
Output Pull-Down Resistance (:)
450
1.145
EN VIL (mV)
1.14
1.135
1.13
1.125
1.12
1.115
-40 qC
25qC
4.7
6.7
8.7
10.7
12.7
Input Voltage (V)
85qC
105qC
14.7
16.7 18
D004
IOUT = –200 mA
16.7 18
300
250
200
150
-40qC
25qC
85qC
105qC
100
50
2.7
4.7
6.7
VIN = VOUT
Figure 5. EN VIL vs Input Voltage
14.7
350
D006
IOUT = 0 A
8.7
10.7
12.7
Input Voltage (V)
Figure 4. On-Resistance vs Input Voltage
1.15
1.105
2.7
6.7
VEN/UVLO = 5 V
1.155
1.11
4.7
D003
Figure 3. On-Resistance vs Temperature
8
16.7 18
160
140
On-Resistance (m:)
4.7
D001
8.7
10.7
12.7
Input Voltage (V)
14.7
16.7 18
D007
VEN/UVLO = 0 V
Figure 6. Output Pull-Down Resistance vs Input Voltage
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7.8 Typical AC Characteristics
200
180
160
Delay Time (tD) (Ps)
VOUT Rise Time (tR) (Ps)
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
2.7
140
120
100
80
60
-40qC
25qC
85qC
105qC
4.7
6.7
CIN = 1 µF
CT = 2200 pF
8.7
10.7
12.7
Input Voltage (V)
14.7
-40qC
25qC
85qC
105qC
40
20
0
2.7
16.7 18
RL = 10 Ω
CL = 0.1 µF
6.7
CIN = 1 µF
CT = 2200 pF
Figure 7. VOUT Rise Time (tR) vs Input Voltage
8.7
10.7
12.7
Input Voltage (V)
14.7
16.7 18
D009
RL = 10 Ω
CL = 0.1 µF
Figure 8. Delay Time (tD) vs Input Voltage
1.8
5
1.6
4.5
4
1.4
Turnoff Time (tOFF) (Ps)
VOUT Fall Time (tF) (Ps)
4.7
D008
1.2
1
0.8
0.6
-40qC
25qC
85qC
105qC
0.4
0.2
0
2.7
4.7
6.7
CIN = 1 µF
8.7
10.7
12.7
Input Voltage (V)
14.7
3.5
3
2.5
2
1.5
-40qC
25qC
85qC
105qC
1
0.5
16.7 18
0
2.7
4.7
6.7
D010
RL = 10 Ω
CL = 0.1 µF
Figure 9. VOUT Fall Time (tF) vs Input Voltage
CIN = 1 µF
8.7
10.7
12.7
Input Voltage (V)
14.7
16.7 18
RL = 10 Ω
D011
CL = 0.1 µF
Figure 10. Turnoff Time (tOFF) vs Input Voltage
600
550
VIN
Turnon Time (tON) (Ps)
500
450
VON
400
350
300
VOUT
250
-40qC
25qC
85qC
105qC
200
150
100
2.7
4.7
CIN = 1 µF
CT = 2200 pF
6.7
8.7
10.7
12.7
Input Voltage (V)
14.7
RL = 10 Ω
IIN
16.7 18
D012
CL = 0.1 µF
Figure 11. Turnon Time (tON) vs Input Voltage
VIN = 5 V
RL = 10 Ω
CIN = 1 µF
CT = 2200 pF
CL = 0.1 µF
Figure 12. Rise Time tR at VIN = 5 V
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Typical AC Characteristics (continued)
VIN
VIN
VON
VON
VOUT
VOUT
IIN
VIN = 5 V
RL = 10 Ω
IIN
CIN = 1 µF
QOD = Open
CL = 0.1 µF
VIN = 12 V
RL = 10 Ω
Figure 13. Fall Time tF at VIN = 5 V
CIN = 1 µF
CT = 2200 pF
CL = 0.1 µF
Figure 14. Rise Time tR at VIN = 12 V
VIN
VON
VOUT
IIN
VIN = 12 V
RL = 10 Ω
CIN = 1 µF
QOD = Open
CL = 0.1 µF
Figure 15. Fall Time tF at VIN = 12 V
10
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8 Parameter Measurement Information
VIN
VOUT
CIN = 1 µF
+
CL
ON
(A)
-
RL
EN/UVLO
GND
OFF
TPS22810
GND
GND
A.
Rise and fall times of the control signal are 100 ns
Figure 16. Test Circuit
VON
50%
50%
tOFF
tOUT
VOUT
50%
50%
tF
tR
90%
VOUT
10%
10%
90%
100%
tD
Figure 17. Timing Waveforms
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9 Detailed Description
9.1 Overview
The TPS22810 is a 6-pin, 2.7-18-V load switch with thermal protection in two separate package options. To
reduce voltage drop for low voltage and high current rails, the device implements a low resistance N-channel
MOSFET which reduces the drop out voltage across the device.
The device starts its operation by monitoring the VIN bus. When VIN exceeds the undervoltage-lockout threshold
(VUVR), the device samples the EN/UVLO pin. A high level on this pin enables the internal MOSFET. As VIN
rises, the internal MOSFET of the device starts conducting and allow current to flow from VIN to VOUT. When
EN/UVLO is held low (below VENF), internal MOSFET is turned off.
A voltage V(EN/UVLO) < V(ENF) on this pin turns off the internal FET, thus disconnecting VIN from VOUT, while
voltage below V(SHUTF) takes the device into shutdown mode, with IQ less than 1 μA to ensure minimal power
loss.
The device has a configurable slew rate which helps reduce or eliminate power supply droop because of large
inrush currents. The device also features an internal RPD resistor, which discharges VOUT once the switch is
disabled.
During shutdown, the device has very low leakage currents, thereby reducing unnecessary leakages for
downstream modules during standby. Integrated control logic, driver, charge pump, and output discharge FET
eliminates the need for any external components which reduces solution size and bill of materials (BOM) count.
The device also features a QOD pin, which allows the configuration of the discharge rate of VOUT once the
switch is disabled.
The device has a thermal protection feature. Due to this device protects itself against thermal damage due to
over-temperature and over-current conditions. Safe Operating Area (SoA) requirements are thus inherently met
without any special design consideration by the board designer.
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9.2 Functional Block Diagram
VIN
Charge Pump
EN/UVLO
Control Logic
CT
VOUT
QOD
2.54 V
2.4 V
1.23 V
1.13 V
Thermal
Shutdown
GND
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9.3 Feature Description
9.3.1 On and Off Control
TThe EN/UVLO pin controls the state of the switch. EN/UVLO is active high and has a low threshold, making it
capable of interfacing with low-voltage signals. The EN/UVLO pin is compatible with standard GPIO logic
threshold. It can be used with any microcontroller with 1.2 V or higher GPIO voltage. This pin cannot be left
floating and must be driven either high or low for proper functionality.
9.3.2 Quick Output Discharge (QOD)
The TPS22810 includes a QOD feature. The QOD pin can be configured in one of three ways:
• QOD pin shorted to VOUT pin. Using this method, the discharge rate after the switch becomes disabled is
controlled with the value of the internal resistance RPD. The value of this resistance is listed in the Electrical
Characteristics table.
• QOD pin connected to VOUT pin using an external resistor REXT. After the switch becomes disabled, the
discharge rate is controlled by the value of the total resistance of the QOD. To adjust the total QOD
resistance, Equation 1 can be used.
RQOD = RPD + REXT
where
•
•
•
RQOD is the total output discharge resistance
RPD is the internal pulldown resistance
REXT is the external resistance placed between the VOUT and QOD pin.
(1)
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Feature Description (continued)
•
QOD pin is unused and left floating. Using this method, there is no quick output discharge functionality, and
the output remains floating after the switch is disabled.
Note that during thermal shutdown, the QOD functionality is not available. The device does not discharge the
load as RPD does not become engaged.
The fall times of the device depend on many factors including the total resistance of the QOD, VIN, and the
output capacitance. When QOD is connected to VOUT, the fall time changes over VIN as the internal RPD varies
over VIN. To calculate the approximate fall time of VOUT for a given RQOD, use Equation 2 and Table 1.
VCAP = VIN × e-t/τ
where
•
•
•
VCAP is the voltage across the capacitor (V)
t is the time since power supply removal (s)
τ is the time constant equal to RQOD × CL
(2)
The fall times' dependency on VIN becomes minimal as the QOD value increases with additional external
resistance. See Table 1 for QOD fall times.
Table 1. QOD Fall Times
FALL TIME (μs) 90% - 10%, CIN = 1 μF, IOUT = 0 A , VIN = 0 V, ON = 0 V (1)
VIN (V)
(1)
TA = 25°C
TA = 85°C
CL = 1 μF
CL = 10 μF
CL = 100 μF
CL = 1 μF
CL = 10 μF
CL = 100 μF
18
470
4700
47000
470
4700
47000
12
450
4500
45000
450
4500
45000
9
440
4400
44000
440
4400
44000
5
500
5000
50000
480
4800
48000
3.3
600
6000
60000
570
5700
57000
TYPICAL VALUES WITH QOD SHORTED TO VOUT
9.3.2.1 QOD when System Power is Removed
The adjustable QOD can be used to control the power down sequencing of a system even when the system
power supply is removed. When the power is removed, the input capacitor, CIN, discharges at VIN. Past the set
UVLO level, the pull-down resistance RPD becomes disabled and the output no longer becomes discharged. If
there is still remaining charge on the output capacitor, this results in longer fall times. Care must be taken such
that CIN is large enough to meet the device UVLO settings.
9.3.2.2 Internal QOD Considerations
Special considerations must be taken when using the internal RPD by shorting the QOD pin to the VOUT pin. The
internal RPD is a pulldown resistance designed to quickly discharge a load after the switch has been disabled.
Care must be used to ensure that excessive current does not flow through RPD during discharge so that the
maximum TJ of 125°C is not exceeded. When using only the internal RPD to discharge a load, the total capacitive
load must not exceed 200 uF. Otherwise, an external resistor, REXT, must be used to ensure the amount of
current flowing through RPD is properly limited and the maximum TJ is not exceeded. To ensure the device is not
damaged, the remaining charge from CL needs to decay naturally through the internal QOD resistance and must
not be driven.
9.3.3 EN/UVLO
As an input pin, EN/UVLO controls the ON and OFF state of the internal MOSFET. In its high state, the internal
MOSFET is enabled. A low on this pin turns off the internal MOSFET. High and Low levels are specified in the
parametric table of the datasheet
A voltage V(EN/UVLO < V(ENF) on this pin turns off the internal FET, thus disconnecting VIN from VOUT, while
voltage below V(SHUTF) takes the device into shutdown mode, with IQ less than 1 μA to ensure minimal power
loss.
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The EN/UVLO pin can be directly driven by a 1.8 V, 3.3 V or 5 V general purpose output pin.
The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (2.5 μs typical) for quick detection
of power failure. For applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is
particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO to GND.
The undervoltage lock out can be programmed by using an external resistor divider from supply VIN terminal to
EN/UVLO terminal to GND as shown in Figure 18. When an undervoltage or input power fail event is detected,
the internal FET is quickly turned off. If the Under-Voltage Lock-Out function is not needed, the EN/UVLO
terminal must be connected to the VIN terminal. EN/UVLO terminal must not be left floating.
The device also implements internal undervoltage-lockout (UVLO) circuitry on the VIN terminal. The device
disables when the VIN terminal voltage falls below internal UVLO Threshold V(UVF). The internal UVLO
threshold has a hysteresis of 125 mV (5% of V(UVR)). See Figure 19 and Figure 20.
VIN
VOUT
VIN
CL
CIN
2.54 V
2.4 V
GATE
CONTROL
R1
EN/
UVLO
1.23 V
1.13 V
Thermal
Shutdown
R2
GND
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Figure 18. Configuring UVLO with External Resistor Network
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VIN
VOUT
VIN
CL
CIN
2.54 V
2.4 V
GPIO
GATE
CONTROL
EN/
UVLO
1.23 V
1.13 V
Thermal
Shutdown
GND
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Figure 19. Using 1.8 V/3.3 V GPIO Signal Directly from Processor
VIN
VOUT
VIN
CL
CIN
2.54 V
2.4 V
GATE
CONTROL
EN/
UVLO
1.23 V
1.13 V
Thermal
Shutdown
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 20. Default UVLO Threshold V(UVR) Using No Additional External Components
9.3.4 Adjustable Rise Time (CT)
A capacitor to GND on the CT pin sets the slew rate. The voltage on the CT pin can be as high as 2.5 V. An
approximate formula for the relationship between CT and slew rate is shown in Equation 3. This equation
accounts for 10% to 90% measurement on VOUT and does NOT apply for CT < 1 nF.
Use Table 2 to determine rise times for when Ct ≥ 1 nF.
SR = 46.62 / Ct
where
•
16
SR is the slew rate (in V/µs)
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•
•
CT is the the capacitance value on the CT pin (in pF)
The units for the constant a are µs/V. The units for the constant b are µs/(V × pF).
(3)
Rise time can be calculated by dividing the input voltage by the slew rate. Table 2 contains rise time values
measured on a typical device. Rise times shown below are only valid for the power-up sequence where VIN is
already in steady state condition before the EN/UVLO pin is asserted high.
Table 2. Rise Time Table
RISE TIME (µs) 10% - 90%, CL = 0.1 µF, CIN = 1 µF, RL = 10 Ω
CT (pF)
VIN = 18 V
VIN = 12 V
VIN = 9 V
VIN = 5 V
VIN = 3.3 V
0
115
91
78
60
98
470
136
94
80
63
98
1000
310
209
158
91
102
2200
688
464
345
198
135
4700
1430
957
704
397
265
10000
3115
2085
1540
864
550
27000
8230
5460
4010
2245
1430
9.3.5 Thermal Shutdown
The switch disables when the junction temperature (TJ) rises above the thermal shutdown threshold, TSD. The
switch re-enables once the temperature drops below the TSD – TSD,HYS value.
9.4 Device Functional Modes
The features of the TPS22810 depend on the operating mode. Table 3 summarizes the Device Functional
Modes.
Table 3. Function Table
EN/UVLO
Device State
L
Disabled
H
Enabled
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
This section highlights some of the design considerations when implementing this device in various applications.
A PSPICE model for this device is also available in the product page of this device on www.ti.com (See the
Device Support section for more information).
10.2 ON and OFF Control
The EN/UVLO pin controls the state of the switch. Asserting EN/UVLO high enables the switch. EN/UVLO is
active high and has a low threshold, making it capable of interfacing with low-voltage signals. The EN/UVLO pin
is compatible with standard GPIO logic thresholds. It can be used with any microcontroller with 1.2 V or higher
GPIO voltage. This pin cannot be left floating and must be driven either high or low for proper functionality.
10.3 Input Capacitor (Optional)
To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a
discharged load capacitor, a capacitor needs to be placed between VIN and GND. A 1-μF ceramic capacitor, CIN,
placed close to the pins, is usually sufficient. Higher values of CIN can be used to further reduce the voltage drop
during high current applications. When switching heavy loads, it is recommended to have an input capacitor
about 10 times higher than the output capacitor to avoid excessive voltage drop.
10.4 Output Capacitor (Optional)
Due to the integrated body diode in the NMOS switch, a CIN greater than CL is highly recommended. A CL
greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This can result in current
flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN
dip caused by inrush currents during startup; however, a 10 to 1 ratio for capacitance is not required for proper
functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) can cause slightly more VIN dip upon
turnon due to inrush currents.
This can be mitigated by increasing the capacitance on the CT pin for a longer rise time.
10.5 Typical Application
This typical application demonstrates how the TPS22810 can be used to power downstream modules.
VIN
Power
Supply
VOUT
CIN
CL
GND
QOD
ON
OFF
EN/
UVLO
RL
CT
TPS22810
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Figure 21. Typical Application Schematic
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Typical Application (continued)
10.5.1 Design Requirements
For this design example, use the values listed in Table 4 as the design parameters:
Table 4. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
12 V
Load current
2A
CL
22 µF
Desired fall time
20 ms
Maximum acceptable inrush current
400 mA
10.5.2 Detailed Design Procedure
10.5.2.1 Shutdown Sequencing During Unexpected Power Loss
Using the adjustable Quick Output Discharge function of the TPS22810, adding a load switch to each power rail
can be used to manage the power down sequencing in the event of an unexpected power loss (that is battery
removal). To determine the QOD values for each load switch, first confirm the power down order of the device
you wish to power sequence. Be sure to check if there are voltage or timing margins that must be maintained
during power down. Next, consult Table 1 to determine appropriate CL and RQOD values for each power rail's
load switch so that the load switches' fall times correspond to the order in which they need to be powered down.
In the above example, we must have this power rail's fall time to be 4 ms. Using Equation 2, we can determine
the appropriate RQOD to achieve our desired fall time.
Since fall times are measured from 90% of VOUT to 10% of VOUT, using Equation 2, we get Equation 4 and
Equation 5.
1.2V
10.8V u e
(20ms)/(RQOD u(22PF))
(4)
(5)
RQOD = 413.7 Ω
Consulting Figure 6, RPD at VIN = 12 V is approximately 250 Ω. Using Equation 1, the required external QOD
resistance can be calculated as shown in Equation 6 and Equation 7.
413.7 Ω = 250 Ω + REXT
REXT = 163.7 Ω
(6)
(7)
Figure 22 through Figure 25 are scope shots demonstrating an example of the QOD functionality when power is
removed from the device (both ON and VIN are disconnected simultaneously). In the scope shots, the VIN = 12 V
and correspond to when RQOD = 1000 Ω, RQOD= 500 Ω, and QOD = VOUT with two values of CL = 10 µF and 22
µF.
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VIN
VIN
VON
VON
VOUT
VOUT
VIN = 12 V
CIN = 1 µF
CL = 10 µF
Figure 22. Fall Time tF at VIN = 12 V, RQOD = 1000 Ω
VIN = 12 V
VIN
VON
VON
VOUT
VOUT
CIN = 1 µF
CL = 10 µF
VIN = 12 V
Figure 24. tF at VIN = 12 V , QOD = VOUT
20
CL = 10 µF
Figure 23. Fall Time tF at VIN = 12 V, RQOD = 500 Ω
VIN
VIN = 12 V
CIN = 1 µF
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CIN = 1 µF
CL = 22 µF
Figure 25. tF at VIN = 12 V, RQOD = 1000 Ω
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VIN
VIN
VON
VON
VOUT
VIN = 12 V
VOUT
CIN = 1 µF
CL = 22 µF
VIN = 12 V
Figure 26. tF at VIN = 12 V, RQOD = 500 Ω
CIN = 1 µF
CL = 22 µF
Figure 27. tF at VIN = 12 V, QOD = VOUT
10.5.2.2 VIN to VOUT Voltage Drop
The VIN to VOUT voltage drop in the device is determined by the RON of the device and the load current. The
RON of the device depends upon the VIN conditions of the device. Refer to the RON specification of the device in
the Electrical Characteristics table of this datasheet. Once the RON of the device is determined based upon the
VIN conditions, use Equation 8 to calculate the VIN to VOUT voltage drop.
∆V = ILOAD × RON
where
•
•
•
ΔV is the voltage drop from VIN to VOUT
ILOAD is the load current
RON is the On-resistance of the device for a specific VIN
(8)
An appropriate ILOAD must be chosen such that the IMAX specification of the device is not violated.
10.5.2.3 Inrush Current
To determine how much inrush current is caused by the CL capacitor, use Equation 9.
dV
IINRUSH = CL ´ OUT
dt
where
•
•
•
•
IINRUSH is the amount of inrush caused by CL
CL is the capacitance on VOUT
dt is the Output Voltage rise time during the ramp up of VOUT when the device is enabled
dVOUT is the change in VOUT during the ramp up of VOUT when the device is enabled
(9)
The appropriate rise time can be calculated using the design requirements and the inrush current equation. As
we calculate the rise time (measured from 10% to 90% of VOUT), we account for this in our dVOUT parameter
(80% of VOUT = 9.6 V) as shown in Equation 10 and Equation 11.
400 mA = 22 µF × 9.6 V/dt
dt = 528 µs
(10)
(11)
To ensure an inrush current of less than 400 mA, choose a CT value that yields a rise time of more than 528 μs.
Consulting Table 2 at VIN = 12 V, CT = 4700 pF provides a typical rise time of 957 μs. Using this rise time and
voltage into Equation 9, yields Equation 12 and Equation 13.
IInrush = 22 µF × 9.6 V/ 957 µs
Inrush = 220 mA
(12)
(13)
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An appropriate CL value must be placed on VOUT such that the IMAX and IPLS specifications of the device are not
violated.
10.5.3 Application Curves
See the oscilloscope captures below for an example of how the CT capacitor can be used to reduce inrush
current for VIN = 12 V. See the Adjustable Rise Time (CT) section for rise times for corresponding CT values.
VIN
VIN
VON
VON
VOUT
VOUT
IIN
IIN
Figure 28. TPS22810 Inrush Current With
CL = 22 µF, CT = 0 pF
VIN
VIN
VON
VON
VOUT
VOUT
IIN
IIN
Figure 30. TPS22810 Inrush Current
With CL = 22 µF, CT = 27000 pF
22
Figure 29. TPS22810 Inrush Current
with CL = 22 µF, CT = 4700 pF
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Figure 31. TPS22810 Inrush Current
With CL = 100 µF, CT = 0 pF
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VIN
VIN
VON
VON
VOUT
VOUT
IIN
IIN
Figure 32. TPS22810 Inrush Current
With CL = 100 µF, CT = 4700 pF
Figure 33. TPS22810 Inrush Current
With CL = 100 µF, CT = 27000 pF
11 Power Supply Recommendations
The device is designed to operate from a VIN range of 2.7 V to 18 V. This supply must be well regulated and
placed as close to the device terminal as possible with the recommended 1-µF bypass capacitor. If the supply is
located more than a few inches from the device terminals, additional bulk capacitance may be required in
addition to the ceramic bypass capacitors. If additional bulk capacitance is required, an electrolytic, tantalum, or
ceramic capacitor of 1 µF may be sufficient.
The TPS22810 operates regardless of power sequencing order. The order in which voltages are applied to VIN
and ON does not damage the device as long as the voltages do not exceed the absolute maximum operating
conditions.
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12 Layout
12.1 Layout Guidelines
1. VIN and VOUT traces must be as short and wide as possible to accommodate for high current.
2. The VIN pin must be bypassed to ground with low ESR ceramic bypass capacitors. The typical
recommended bypass capacitance is 1-μF ceramic with X5R or X7R dielectric. This capacitor must be
placed as close to the device pins as possible.
12.2 Layout Example
1 VIN
VOUT 6
2 GND
QOD 5
3 EN/UVLO
CT 4
VIA to Power Ground Plane
Figure 34. Recommended Board Layout
12.3 Thermal Considerations
For best performance, all traces must be as short as possible. To be most effective, the input and output
capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have
on normal and short-circuit operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic
electrical effects along with minimizing the case to ambient thermal impedance.
The maximum IC junction temperature must be restricted to 150°C under normal operating conditions. To
calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use
Equation 14.
TJ(MAX) - TA
PD(MAX) =
qJA
where
•
•
•
•
24
PD(MAX) is the maximum allowable power dissipation
TJ(MAX) is the maximum allowable junction temperature (150°C for the TPS22810)
TA is the ambient temperature of the device
θJA is the junction to air thermal impedance. Refer to the Thermal Information table. This parameter is highly
dependent upon board layout.
(14)
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Developmental Support
For the TPS22810 PSpice Transient Model, see TPS22810 PSpice Transient Model
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• TPS22810 Load Switch Evaluation Module
• Selecting a Load Switch to Replace a Discrete Solution
• Timing of Load Switches
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com. In the upper right-hand corner, click the Alert me button. This registers you to receive a weekly
digest of product information that has changed (if any). For change details, check the revision history of any
revised document.
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2016–2018, Texas Instruments Incorporated
Product Folder Links: TPS22810
25
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS22810DBVR
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
19HF
TPS22810DBVT
ACTIVE
SOT-23
DBV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
19HF
TPS22810DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
1CRH
TPS22810DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
1CRH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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