TPS2350
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SLUS574D – JULY 2003 – REVISED OCTOBER 2013
Hot Swap Power Manager for Redundant –48-V Supplies
Check for Samples: TPS2350
FEATURES
1
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
Replaces OR-ing Diodes
Operating Supply Range of –12 V to –80 V
Withstands Transients to –100 V
Programmable Current Limit
Programmable Linear Inrush Slew Rate
Programmable UV/OV Thresholds
Programmable UV and OV Hysteresis
Fault Timer to Eliminate Nuisance Trips
Power Good and Fault Outputs
14-Pin SOIC and TSSOP Package
The TPS2350 is a hot swap power manager
optimized for replacing OR-ing diodes in redundant
power –48-V systems. The TPS2350 operates with
supply voltages from –12 V to –80 V, and withstands
spikes to –100 V.
The TPS2350 uses two power FETs as low voltage
drop diodes to efficiently select between two
redundant power supplies. This minimizes system
power dissipation and also minimizes voltage drop
through the power management chain.
The TPS2350 also uses a third power FET to provide
load current slew rate control and peak current
limiting that is programmed by one resistor and one
capacitor. The device also provides a power good
output to enable down-stream power converters and
a fault output to indicate load problems.
APPLICATIONS
•
•
•
•
–48-V Distributed Power Systems
Central Office Switching
ONET
Base Stations
TYPICAL APPLICATION DIAGRAM
RLOAD
D1
(A)
CLOAD
1
3
UV
Power Good
12
PG
Fault
2
4
RTN
Q1
GAT 11
TPS2350
RSENSE
0.01
SENSE 10
FLT
SOURCE
7
GATA
9
GATB
8
OV
FLTTIM
RAMP
–VINA
–VINB
5
6
14
13
CFLT
CRAMP
–VINB
–VINA
A.
D1 optional per application requirements.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated
TPS2350
SLUS574D – JULY 2003 – REVISED OCTOBER 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted) (1)
VALUE
Input voltage range, RTN
(2)
UNIT
–0.3 to 100
Input voltage range, –VINA to –VINB
–100 to 100
Input voltage range, FLTTIM, RAMP, SENSE, OV, UV (2)
–0.3 to 15
Output voltage range, FLT, PG (2) (3)
–0.3 to 100
Continuous output current, FLT, PG
10
mA
See the Thermal Information
table
Continuous total power dissipation
Electrostatic Discharge
Human body model (HBM)
2
Charged device model (CDM)
kV
1.5
Operating junction temperature range, TJ
–55 to 125
Storage temperature range, Tstg
–65 to 150
(1)
(2)
(3)
V
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to the more negative of –VINA and –VINB (unless otherwise noted).
With 10 kΩ minimum series resistance. Range limited to –0.3V to 80V from low impedance source.
SOIC/TSSOP-14 PACKAGE
(TOP VIEW)
RTN
FLT
UV
OV
FLTTIM
RAMP
SOURCE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
–VINA
–VINB
PG
GAT
SENSE
GATA
GATB
Device Information
TA
–40°C to 85°C
(1)
(2)
PACKAGE (1)
PART NUMBER
SOIC–14 (2)
TPS2350D
TSSOP–14 (2)
TPS2350PW
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
The D and PW packages are also available taped and reeled. Add an R suffix to the device type (i.e. TPS2350DR).
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
Input supply, –VINA, –VINB to RTN
–80
–48
–12
V
Operating junction temperature range
–40
85
°C
2
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UNIT
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THERMAL INFORMATION
TPS2350
THERMAL METRIC (1)
D (14 PINS)
PW (14 PINS)
θJA
Junction-to-ambient thermal resistance
95.9
120.8
θJB
Junction-to-board thermal resistance
51.5
62.8
θJCtop
Junction-to-case (top) thermal resistance
50.7
n/a
ψJT
Junction-to-top characterization parameter
8.3
1
ψJB
Junction-to-board characterization parameter
51.1
56.5
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
–VINA = –48 V, –VINB = 0 V, UV = 2.5 V, OV = 0.5 V, SENSE = 0 V, RAMP = 0 V, SOURCE = more negative of –VINA and
–VINB, all outputs unloaded, TA = –40°C to 85°C (unless otherwise noted) (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1000
1500
UNIT
Input Supply
ICC1A
Supply current
–VINA = –48 V, –VINB = 0 V
ICC2A
Supply current
–VINA = –80 V, –VINB = 0 V
ICC1B
Supply current
–VINB = –48 V, –VINA = 0 V
ICC2B
Supply current
–VINB = –80 V, –VINA = 0 V
VUVLO_I
Internal UVLO threshold voltage
To GAT pull up
VHYST
Internal UVLO hysteresis voltage
2000
1000
µA
1500
2000
–11.8
–10
–8.0
V
50
240
500
mV
To GAT pull up, 25°C
1.391
1.400
1.409
To GAT pull up, 0 to 70°C
1.387
1.400
1.413
To GAT pull up, –40 to 85°C
1.384
1.400
1.419
–11
–10
–9
Overvoltage and Undervoltage Inputs (OV and UV)
VTHUV
UV threshold voltage, UV rising, to
–VINA
V
IHYSUV
UV hysteresis
UV = –45.5 V
IILUV
UV low-level input current
UV = –47 V
VTHOV
OV threshold voltage, OV rising, to
–VINA
To GAT pull up
1.376
1.400
1.426
V
IHYSOV
OV hysteresis
OV = −45.5 V
–11.1
–10
–8.6
µA
IILOV
OV low-level input current
OV = –47 V
–1
1
µA
High level output, GAT–SOURCE
SENSE = SOURCE
11
14
17
V
ISINK_f
GAT sink current in fault
SENSE – SOURCE = 80 mV,
GAT = –43 V, FLTTIME = 5 V
30
75
ISINK_l
GAT sink current in linear mode
SENSE – SOURCE = 80 mV,
GAT = –43 V, FLTTIME = 2 V
IIN
SENSE input current
0.0 V < SENSE – SOURCE < 0.2 V
–1
VREF_K
Reference clamp voltage, SENSE –
SOURCE
RAMP – SOURCE = 6 V
34
VIO
Input offset voltage, SENSE –
SOURCE
RAMP – SOURCE = 0 V
–7
–1
µA
1
Linear Current Amplifier (LCA)
VOH
mA
5
10
1
42
µA
50
mV
9
Ramp Generator
ISRC1
RAMP source current, slow turn-on rate RAMP − SOURCE = 0.25 V
–800
–550
–300
nA
ISRC2
RAMP source current, normal rate
RAMP – SOURCE = 1 V and 3 V
–11.3
–10
–8.5
μA
VOL
Low-level output voltage
UV = SOURCE
5
mV
AV
Voltage gain, relative to SENSE
0 V < RAMP – SOURCE < 5 V
(1)
(2)
9.5
10
10.7
mV/V
All voltages are with respect to RTN unless otherwise stated.
Currents are positive into and negative out of the specified terminal.
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ELECTRICAL CHARACTERISTICS (continued)
–VINA = –48 V, –VINB = 0 V, UV = 2.5 V, OV = 0.5 V, SENSE = 0 V, RAMP = 0 V, SOURCE = more negative of –VINA and
–VINB, all outputs unloaded, TA = –40°C to 85°C (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
100
120
140
mV
2
4
7
µs
5
mV
µA
Overload Comparator
VTH_OL
SENSE current overload threshold
tRSP
Response time
SENSE – SOURCE = 200 mV
VOL
FLTTIM low-level output voltage, to
–VINA
UV = –48 V
ICHG
FLTTIM charging current, current limit
mode
FLTTIM – SOURCE = 2 V
VFLT
FLTTIM fault threshold voltage to
SOURCE
VRST
Fault reset threshold to SOURCE
IDSG
FLTTIM Discharge current, retry mode
FLTTIM – SOURCE = 2 V
D
Output duty cycle during retry cycles
SENSE – SOURCE = 80 mV,
FLTTIM − SOURCE = 2 V
IRST
FLTTIM discharge current, timer reset
mode
FLTTIM − SOURCE = 2 V,
SENSE = 2 V
Fault Timer
–54
–50
–41
3.75
4.00
4.25
V
0.5
0.38
0.75
1%
1.5%
1
µA
mA
Logic Outputs (FLT, PG)
IOHFLT
FLT high-level output leakage current
UV = –48 V, FLT – SOURCE = 80 V
–10
10
IOHPG
PG high-level output leakage current
UV = –45 V, PG – SOURCE = 80 V
–10
10
RDS(on)
FLT ON resistance
SENSE–SOURCE = 80 mV,
FLTTIM–SOURCE = 5 V,
I(FLT) = 1 mA
50
80
RDS(on)
PG ON resistance
UV = –48 V, IO(PG) = 1 mA
50
80
µA
Ω
Supply Selector
VTHA
Threshold voltage, –VINA falling
–VINB = –48 V, –VINA falling
–48.45
–48.40
–48.35
VTHB
Threshold voltage, –VINB falling
–VINA = –48 V, –VINB falling
–48.45
–48.40
–48.35
ISINK
GATA sink current
–VINA = 0 V, –VINB = –48 V,
GATA = –41 V
30
80
ISOURCE
GATA source current
–VINA = –48 V, –VINB = –0 V,
GATA = –41 V
ISINK
GATB sink current
–VINA = –48 V, –VINB = –0 V,
GATB = –41 V
ISOURCE
GATB source current
–VINA = 0 V, –VINB = –48 V,
GATB = –41 V
VOLA
GATA low voltage to –VINA
VINA = 0 V, –VINB = –48 V
VOLA
GATA high voltage to –VINA
–VINA = –48 V, –VINB = 0 V
VOLB
GATB low voltage to –VINB
–VINA = –48 V, –VINB = 0 V
VOLB
GATB high voltage to –VINB
–VINA = 0 V, –VINB = –48 V
4
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–50
30
mA
–20
80
–50
V
µA
mA
–20
µA
0.1
11
14
17
0.1
11
14
V
17
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PIN FUNCTIONS
PIN
NAME
NO.
I/O
DESCRIPTION
FLT
2
O
Open-drain, active-low indication that the part is in fault.
FLTTIM
5
I/O
Connection for user programming of the fault timeout period.
GAT
11
O
Gate drive for external N-channel FET that ramps load current and disconnects in the event
of a fault.
GATA
9
O
Gate drive for external N-channel FET that selects –VINA.
GATB
8
O
Gate drive for external N-channel FET that selects –VINB.
OV
4
I
Over voltage sense input.
PG
12
O
Open-drain, active-high indication that the power FET is fully enhanced.
RAMP
6
I/O
Programming input for setting the inrush current slew rate.
RTN
1
I
Supply return (ground).
SENSE
10
I
Positive current sense input.
SOURCE
7
I/O
Negative current sense input.
UV
3
I
Under voltage sense input.
–VINA
14
I
Negative supply input A.
–VINB
13
I
Negative supply input B.
PIN DESCRIPTIONS
FLT: Open-drain, active-low indication that TPS2350 has shut down due to a faulted load. This happens if the
load current stays limited by the linear current amplifier for more than the fault time (time to charge the FLTTIM
capacitor). FLT is cleared when both supplies drop below the UV-comparator threshold or one supply exceeds
the OV-comparator threshold. The FLT output is pulled to the lower of –VINA and –VINB. The FLT output is able
to sink 10 mA when in fault, withstand 80 V without leakage when not faulted, and withstand transients as high
as 100 V when limited by a series resistor of at least 10 kΩ.
FLTTIM: Connection for user programming of the fault timeout period. An external capacitor connected from
FLTTIM to SOURCE establishes the timeout period to declare a fault condition. This timeout protects against
indefinite current sourcing into a faulted load, and also provides a filter against nuisance trips from momentary
current spikes or surges. TPS2350 define a fault condition as voltage at the SENSE pin at or greater than the 42mV fault threshold. When a fault condition exists, the timer is active. The devices manage fault timing by
charging the external capacitor to the 4-V fault threshold, then subsequently discharging it at approximately 1%
the charge rate to establish the duty cycle for retrying the load. Whenever the fault latch is set (timer expired),
GAT and FLT are pulled low.
GAT: Gate drive for an external N-channel protection power MOSFET. When either input supply is above the UV
threshold and both are below the OV threshold, gate drive is enabled and the device begins charging the
external capacitor connected to RAMP. RAMP develops the reference voltage at the non-inverting input of the
internal LCA. The inverting input is connected to the current sense node, SENSE. The LCA acts to slew the pass
FET gate to force the SENSE voltage to track the reference. The reference is internally clamped to
42 mV, so the maximum current that can be sourced to the load is determined by the sense resistor value as
IMAX ≤ 42 mV/RSENSE. Once the load voltage has ramped up to the input dc potential and current demand drops
off, the LCA drives GAT 14 V above SOURCE to fully enhance the pass FET, completing the low-impedance
supply return path for the load.
GATA: Gate drive for an external N-channel power MOSFET to select –VINA. When –VINA is more negative
than –VINB, GATA is pulled 14 V above –VINA, turning on the –VINA power FET. When –VINB is more negative
than –VINA, GATA is pulled down to –VINB, turning off the –VINA power FET.
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GATB: Gate drive for an external N-channel power MOSFET to select –VINB. When –VINB is more negative
than –VINA, GATB is pulled 14 V above –VINB, turning on the –VINB power FET. When –VINA is more negative
than –VINB, GATB is pulled down to –VINA, turning off the –VINB power FET.
PG: Open-drain, active-high indication that load current is below the commanded current and the power FET is
fully enhanced. When commanded load current is more than the actual load current, the linear current amplifier
(LCA) will raise the power MOSFET gate voltage to fully enhance the power MOSFET. At this time, the PG
output will go high. This output can be used to enable a down-stream dc-to-dc converter. The PG output is pulled
to the lower of –VINA and –VINB. The PG output is able to sink 10 mA when in fault, withstand 80 V without
leakage when power is not good, and withstand transients as high as 100 V when limited by a series resistor of
at least 10 kΩ.
OV: Over voltage comparator input. This input is typically connected to a voltage divider between RTN and
SOURCE to sense the magnitude of the more negative input supply. If OV is less than 1.4 V above SOURCE,
UV is more than 1.4 V above SOURCE, and there is no fault, the linear current amp will be enabled. In the event
of a fault, pulling OV high or UV low will reset the fault latch and allow restarting. OV can also be used as an
active-low logic enable input. The over-voltage comparator hysteresis is programmed by the equivalent
resistance seen looking into the divider at the OV input.
RAMP: Programming input for setting inrush current and current slew rate. An external capacitor connected
between RAMP and SOURCE establishes turn-on current slew rate. During turn-on, TPS2350 charges this
capacitor to establish the reference input to the LCA at 1% of the voltage from RAMP to SOURCE. The closedloop control of the LCA and the pass FET maintains the current-sense voltage from SENSE to SOURCE at the
reference potential, so the load current slew rate is directly set by the voltage ramp rate at the RAMP pin. When
fully charged, RAMP can exceed SOURCE by 6 V, but the reference is internally clamped to 42 mV, limiting load
current to 42 mV/RSENSE. When the output is disabled via OV, UV, or due to a load fault, the RAMP capacitor is
discharged and held low to initialize for the next turn on.
RTN: Positive supply input. For negative voltage systems, this pin connects directly to the return node of the
input power bus.
SENSE: Current sense input. An external low-value resistor connected between SENSE and SOURCE is used
to monitor current magnitude. There are two internal device thresholds associated with the voltage at the SENSE
pin. During ramp-up of the load capacitance or during other periods of excessive demand, the linear current amp
(LCA) will regulate this voltage to 42 mV. Whenever the LCA is in current regulation mode, the capacitor at
FLTTIM is charging and the timer is running. If the LCA is saturated, GAT is pulled 14 V above SOURCE. At this
time, a fast fault such as a short circuit can cause the SENSE voltage to rapidly exceed 120 mV (the overload
threshold). In this case, the GAT pin is pulled low rapidly, bypassing the fault timer.
SOURCE: Connection to the sources of the input supply negative rail selector FETs and the negative terminal of
the current sense resistor. The supply select comparator will turn on the appropriate power FET to connect
SOURCE to the more negative of –VINA and –VINB.
UV: Under voltage comparator input. This input is typically connected to a voltage divider between RTN and
SOURCE to sense the magnitude of the more negative input supply. If UV is more than 1.4 V above SOURCE,
OV is less than 1.4 V above SOURCE, and there is no fault, the linear current amp will be enabled. In the event
of a fault, pulling UV low or OV high will reset the fault latch and allow restarting. UV can also be used as an
active high logic enable input. The under-voltage comparator hysteresis is programmed by the equivalent
resistance seen looking into the divider at the UV input.
–VINA: Negative supply input A. This pin connects directly to the first input supply negative rail.
–VINB: Negative supply input B. This pin connects directly to the second input supply negative rail.
6
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TYPICAL CHARACTERISTICS
SUPPLY SELECTOR THRESHOLD VOLTAGE
vs
AMBIENT TEMPERATURE, −VINA FALLING
SUPPLY SELECTOR THRESHOLD VOLTAGE
vs
AMBIENT TEMPERATURE, −VINB FALLING
–0.350
–0.350
V(RTN) = 0 V
Relative to –VINA
V(–VINB) = –48 V
–0.375
V(–VINB) = –20 V
–0.400
V(–VINB) = –80 V
–0.425
–0.450
–40
–15
10
35
60
85
VTHB – Threshold Voltage – V
VTHA – Threshold Voltage – V
V(RTN) = 0 V
Relative to –VINB
–0.375
V(–VINA) = –48 V
V(–VINA) = –20 V
–0.400
V(–VINA) = –80 V
–0.425
–0.450
–40
TA – Ambient Temperature – °C
Figure 1.
35
60
85
GATB HIGH-LEVEL OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE
16
16
V(–VINA) = –20 V
V(–VINA) = –48 V
VOHB – Output Voltage – V
VOHA – Output Voltage – V
10
TA – Ambient Temperature – °C
Figure 2.
GATA HIGH-LEVEL OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE
12
–15
8
V(–VINA) = –12 V
4
12
8
V(–VINB) = –12 V
4
V(RTN) = V (–VINB)= 0 V
Relative to –VINA
0
–40
V(–VINB) = –48 V
V(–VINB) = –20 V
V(RTN) = V (–VINA) = 0 V
Relative to –VINB
–15
10
35
60
TA – Ambient Temperature –°C
85
0
–40
Figure 3.
–15
10
35
60
TA – Ambient Temperature – °C
Figure 4.
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TYPICAL CHARACTERISTICS
GATx SINK CURRENT
vs
AMBIENT TEMPERATURE
SUPPLY CURRENT
vs
AMBIENT TEMPERATURE
1500
100
1200
ICC – Supply Current – µA
80
ISINK – Sink Current – mA
V (RTN) = V (–VINB) = 0 V
GATA Output
V(RTN) = V(–VINA) = 0 V
V(–VINB) = –48 V
VOUT(GATA) = –41 V
60
GATB Output
V(RTN) = V(–VINB) = 0 V
V(–VINA) = –48 V
VOUT(GATB) = –41 V
40
V(–VINA) = –80 V
900
600
V(–VINA) = –48 V
V(–VINA) = –20 V
V(–VINA) = –12 V
300
20
0
–40
0
–40
–15
10
35
60
–15
–9.0
IHYS_UV – Source Current – µA
VTH – Threshold Voltage – V
V(RTN) = V(–VINB) = 0 V
Relative to –VINA
OV Comparator
V(–VINA) = –80 V
1.40
UV Comparator
–48 V ≤ V(–VINA) ≤ –20 V
1.38
–15
10
35
60
85
–9.4
V(RTN) = V(–VINB) = 0 V
–48 V ≤ V(–VINA) ≤ –20 V
VIN(UV) – V IN(SOURCE) = 2.5 V
–9.8
–10.2
–10.6
–11.0
–40
TA – Ambient Temperature – °C
Figure 7.
8
85
UNDERVOLTAGE PULL-UP CURRENT
vs
AMBIENT TEMPERATURE
1.42
–40
60
Figure 6.
VOLTAGE COMPARATOR THRESHOLDS
vs
AMBIENT TEMPERATURE
1.39
35
TA – Ambient Temperature – °C
TA – Ambient Temperature – °C
Figure 5.
1.41
10
85
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–15
10
35
60
85
TA – Ambient Temperature – °C
Figure 8.
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TYPICAL CHARACTERISTICS
GAT HIGH-LEVEL OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE
RAMP OUTPUT CURRENT
vs
AMBIENT TEMPERATURE, REDUCED RATE MODE
–460
16
V(–VINA) = –48 V
VOH – Output Voltage – V
12
ISRC1 – RAMP Output Current – nA
V(RTN) = V(–VINB) = 0 V
VOUT(RAMP) – VIN(SOURCE) = 0.25V
V(–VINA) = –20 V
8
V(–VINA) = –12 V
4
V(RTN) = V(–VINB) = 0 V
VIN(SENSE) – VIN(SOURCE) = 0 V
IOUT(GAT) = 10 µA
0
–40
–15
10
35
60
–480
–500
V(–VINA) = –12 V
–520
–540
V(–VINA) = –48 V
V(–VINA) = –36 V
–560
–580
–40
85
–15
TA – Ambient Temperature – °C
35
60
85
TA – Ambient Temperature –°C
Figure 10.
Figure 9.
RAMP OUTPUT CURRENT
vs
AMBIENT TEMPERATURE, NORMAL RATE MODE
TIMER CHARGING CURRENT
vs
AMBIENT TEMPERATURE
–8.5
–46
Average for VOUT(RAMP) – VIN(SOURCE) = 1 V, 3 V
V(RTN) = V(–VINB) = 0 V
–80 V ≤ V(–VINA) ≤ –12 V
–9.1
ICHG – Charging Current – mA
ISRC2 – RAMP Output Current – mA
10
–9.7
–10.3
V(RTN) = V(–VINB) = 0 V
VOUT(FLTTIM) – V IN(SOURCE) = 2 V
–80 V ≤ V(–VINA) ≤ –20 V
–48
–52
–54
–10.9
–11.5
–40
–15
10
35
60
85
0
–40
TA – Ambient Temperature –°C
Figure 11.
–15
10
35
60
TA – Ambient Temperature – °C
Figure 12.
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9
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TYPICAL CHARACTERISTICS
TIMER DISCHARGE CURRENT
vs
AMBIENT TEMPERATURE
FAULT LATCH THRESHOLD VOLTAGE
vs
AMBIENT TEMPERATURE
0.50
V(RTN) = V(–VINB) = 0 V
V(–VINA) = –48 V
Relative to SOURCE
VFLT – Fault Latch Threshold – V
IDSG – Discharge Current – mA
0.45
4.25
V(RTN) = V(–VINB) = 0 V
–80 V ≤ V(–VINA) ≤ –20 V
VOUT(FLTTIM) – VIN(SOURCE) =2V
0.40
0.35
0.30
0.25
0.20
–40
–15
10
35
60
85
4.15
4.05
3.95
3.85
3.75
–40
TA – Ambient Temperature – °C
Figure 13.
10
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–15
10
35
60
85
TA – Ambient Temperature – °C
Figure 14.
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FUNCTIONAL BLOCK DIAGRAM
RTN
1
UV
Input UV
Comparator
+
3
1.4 V
Input OV
Comparator
OV
Disable
4
1.4 V
+
2
FLT
Fault Latch
120 mV
4 µs
Filter
+
Fault
Timer
Retry
Timer
S
Q
R
Q
Overload
Comparator
FLTTIM
5
SENSE
10
+
Linear Current
Amp
99R
RAMP
11 GAT
6
Disable
Power Good
Detection
42 mV
R
12
PG
+
7
SOURCE
Supply Select
Comparator
+
400 mV
Hysteresis
14
13
–VINA
–VINB
9 GATA
8
GATB
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APPLICATION INFORMATION
Supply Section
The supply selection comparator selects between –VINA and –VINB based on which supply has a larger
magnitude. To prevent chattering between two nearly identical supplies, the supply selection comparator has 400
mV of hysteresis. This prevents supply noise or ripple from tripping the comparator and should be adequate for
most systems. Hysteresis is set to 400 mV to give the highest noise margin without allowing conduction in the
body diodes of the supply selection FETs.
For systems with many cards, high current cards, or long cables between the power and the load, the voltage
loss in the cable can be significant. If the supplies are close to the same magnitude, then the voltage loss in the
cable could cause enough drop to exceed the supply selection comparator hysteresis. In this case, the supply
selection comparator hysteresis must be increased.
TPS2350 allows you to increase the hysteresis of the supply selection comparator with external resistors, limited
to the threshold of the external FETs. Figure 15 shows a system with higher hysteresis, set by R4, R5, R6 and
R7. The resistors act as a simple multiplier to increase the voltage differential required to switch the comparator.
For example, for R4 = R5 = 40 kΩ, and R6 = R7 = 20 kΩ, the hysteresis is approximately 1.2 V. Because of the
large hysteresis, the supply selection power FETs are replaced with dual power FETs, configured so that the
body diodes can never conduct. The GATA and GATB outputs are able to switch dual FETs, so no additional
drive or logic circuits are required.
RTN
CLOAD
R1
RLOAD
1
RTN
12 PG
POWER GOOD
2
FAULT
Q1
GA 11
T
SENSE 10
FLT
TPS2350
3
RSENSE
UV
SOURCE 7
R2
Q2
4
GATA 9
OV
Q3
GATB 8
FLTTIM RAMP
R3
5
6
CFLT
–VINA
–VINB
14
13
CRAMP
Q4
Q5
R6
R4
R7
R5
UDG03121
–VINB
–VINA
Figure 15. Typical Application to Develop Higher Supply Comparator Hysteresis
12
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APPLICATION INFORMATION
Setting the Sense Resistor Value
Due to the current-limiting action of the internal LCA, the maximum allowable load current for an implementation
is easily programmed by selecting the appropriate sense resistor value. The LCA acts to limit the sense voltage
VSENSE to its internal reference. Once the voltage at the RAMP pin exceeds approximately 4 V, this limit is the
clamp voltage, VREF_K. Therefore, a maximum sense resistor value can be determined from Equation 1.
34mV
RSENSE £
IMAX
(1)
where
• RSENSE is the resistor value
• IIMAX is the desired current limit
When setting the sense resistor value, it is important to consider two factors, the minimum current that may be
imposed by the TPS2350, and the maximum load under normal operation of the module. For the first factor, the
specification minimum clamp value is used, as seen in Equation 1. This method accounts for the tolerance in the
sourced current limit below the typical level expected (42 mV/RSENSE). (The clamp measurement includes LCA
input offset voltage; therefore, this offset does not have to be factored into the current limit again.) Second, if the
load current varies over a range of values under normal operating conditions, then the maximum load level must
be allowed for by the value of RSENSE. One example of this is when the load is a switching converter, or brick,
which draws higher input current, for a given power output, when the distribution bus is at the low end of its
voltage range, with decreasing draw at higher supply voltages. To avoid current limit operation under normal
loading, some margin should be designed in between this maximum anticipated load and the minimum current
limit level, or IIMAX > ILOAD(max), for Equation 1.
For example, using a 10-mΩ sense resistor for a nominal 2-A load application provides a minimum of 1.4 A of
overhead for load variance/margin. Typical bulk capacitor charging current during turn-on is 4.2 A (42 mV/
10 mΩ).
Setting the Inrush Slew Rate
The TPS2350 device enables user-programming of the maximum current slew rate during load start-up events. A
capacitor tied to the RAMP pin (CRAMP in the typical application diagram) controls the di/dt rate. Once the sense
resistor value has been established, a value for CRAMP, in microfarads, can be determined from Equation 2.
11.3
CRAMP =
æ di ö
100 ´ RSENSE ´ ç ÷
è dt ø (max)
(2)
where
• RSENSE is the sense resistor value in Ω
• (di/dt)(max) is the desired maximum slew rate in A/s
For example, if the desired slew rate for the typical application shown is 1500 mA/ms, the calculated value for
CRAMP is about 7500 pF. Selecting the next larger standard value of 8200 pF provides some margin for capacitor
and sense resistor tolerances.
The TPS2350 initiates ramp capacitor charging, and consequently load current slewing, at a reduced rate. This
reduced rate applies until the voltage on the RAMP pin is about 0.5 V. The maximum di/dt rate, as set by
Equation 2, is effective once the device switches to a 10-µA charging source.
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APPLICATION INFORMATION
Setting the Fault Timing Capacitor
The fault timeout period is established by the value of the capacitor connected to the FLTTIM pin, CFLT. The
timeout period permits riding out spurious current glitches and surges that may occur during operation of the
system, and prevents indefinite sourcing into faulted loads. However, to ensure smooth voltage ramping under all
conditions of load capacitance and input supply potential, the minimum timeout should be set to accommodate
these system variables. To do this, a rough estimate of the maximum voltage ramp time for a completely
discharged plug-in card provides a good basis for setting the minimum timer delay. This section presents a quick
procedure for calculating the timing capacitance requirement. However, for proper operation of the TPS2350,
there is an absolute minimum value of 0.01-µF for CFLT. This minimum requirement overrides any smaller results
of Equation 7 and Equation 8.
Due to the three-phase nature of the load current at turn-on, the load voltage ramp has potentially three distinct
phases. This profile depends on the relative values of load capacitance, input DC potential, maximum current
limit and other factors. The first two phases are characterized by the two different slopes of the current ramp; the
third phase, if required to complete load charging, is the constant-current charging at IMAX. Considering the two
current ramp phases to be one period at an average di/dt simplifies calculation of the required timing capacitor.
For the TPS2350, the typical duration of the soft-start period, tSS, is given by Equation 3.
tSS = 1260 ´ CRAMP
(3)
where
• tSS is the soft-start period in ms
• CRAMP is given in µF
During this current ramp period, the load voltage magnitude which is attained is estimated by Equation 4.
i AVG
2
VLSS =
´ (tSS )
2 ´ CLOAD ´ CRAMP ´ 100 ´ RSENSE
(4)
where
• VLSS is the load voltage reached during soft-start
• IAVG is 3.18 µA for the TPS2350
• CLOAD is the load capacitance in Farads
• tSS is the soft-start period in s
The quantity IAVG in Equation 4 is a weighted average of the two charge currents applied to CRAMP during turn-on,
considering the typical output values.
14
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APPLICATION INFORMATION
If the result of Equation 4 is larger than the maximum input supply value, then the load can be expected to
charge completely during the inrush slewing portion of the insertion event. However, if this voltage is less than
the maximum supply input, VIN(MAX), the HSPM transitions to the constant-current charging of the load. The
remaining amount of time required at IMAX is determined from Equation 5.
CLOAD ´ (VIN(MAX)-VLSS )
tCC =
VREF_K(MIN)
RSENSE
(5)
where
• tCC is the constant-current voltage ramp time, in seconds
• VREF_K(MIN) is the minimum clamp voltage, 34 mV
With this information, the minimum recommended value timing capacitor CFLT can be determined. The delay time
needed will be either a time tSS2 or the sum of tSS2 and tCC, according to the estimated time to charge the load.
The quantity tSS2 is the duration of the normal rate current ramp period, and is given by Equation 6.
tSS2 = 0.35 ´ CRAMP
(6)
where
• CRAMP is given in µF
Since fault timing is generated by the constant-current charging of CFLT, the capacitor value is determined from
either Equation 7 or Equation 8, as appropriate.
54 ´ tSS2
CFLT(MIN) =
3.75
(7)
CFLT(MIN) =
54 ´ (tSS2 + tCC )
3.75
(8)
where
• CFLT(MIN) is the recommended capacitor value, in µ-Farads
• tSS2 is the result of Equation 6, in seconds
• tCC is the result of Equation 5, in seconds
Continuing this calculation example, using a 220-µF input capacitor (CLOAD), Equation 3 and Equation 4 estimate
the load voltage ramping to approximately –45 V during the soft-start period. If the module should operate down
to –72-V input supply, approximately another 1.4 ms of constant-current charging may be required. Therefore,
Equation 6 and Equation 8 are used to determine CFLT(MIN), and the result is approximately 0.039-µF.
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APPLICATION INFORMATION
Setting the Undervoltage and Overvoltage Thresholds
The UV and OV pins can be used to set the undervoltage (VUV) and overvoltage (VOV) thresholds of the hot swap
circuit. When the input supply is below VUV or above VOV, the GAT pin is held low, disconnecting power from the
load, and the PG output is deasserted. When input voltage is within the UV/OV window, the GAT pin drive is
enabled, assuming all other input conditions are valid for turn-on.
Threshold hysteresis is provided via two internal sources which are switched to either pin whenever the
corresponding input level exceeds the internal 1.4-V reference. The additional bias shifts the pin voltage in
proportion to the external resistance connected to it. This small voltage shift at the device pin is gained up by the
external divider to input supply levels.
(a)
(b)
GND
GND
R1
200 kΩ
1%
1
R1
RTN
3 UV
R2
4.99 kΩ
1%
3 UV
TPS2350
(A)
TPS2350
4 OV
R3
3.92 kΩ
1%
(A)
4 OV
R2
SOURCE
SOURCE
R9
7
-48V
7
-48V
V UV_L
=
R1 + R2 + R3
R2 R3
´
V THUV
V OV_L
=
R1 + R2
R3
´
V THOV
A.
1
R8
RTN
+ R3
–
I HYSUV
´
R1
V UV_L
=
V OV_L
=
R1 + R2
R2
R8
+ R9
R9
´
V THUV
´
V THOV
UDG0312 1
Additional details omitted for clarity
Figure 16. Programming the Undervoltage and Overvoltage Thresholds
The UV and OV thresholds can be individually programmed with a three-resistor divider connected to the
TPS2350 as shown in the typical application diagram, and again in Figure 16a. When the desired trip voltages
and undervoltage hysteresis have been established for the protected board, the resistor values needed can be
determined from the following equations. Generally, the process is simplest by first selecting the top leg of the
divider (R1 in the diagram) needed to obtain the threshold hysteresis. This value is calculated from Equation 9.
V
R1= HYS_UV
10mA
(9)
where
• VHYS_UV is the undervoltage hysteresis value
16
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APPLICATION INFORMATION
For example, assume the typical application design targets have been set to undervoltage turn-on at 33 V (input
supply rising), turn-off at 31 V (input voltage falling), and overvoltage shutdown at 72 V. Then Equation 9 yields
R1 = 200 kΩ for the 2-V hysteresis. Once the value of R1 is selected, it is used to calculate resistors R2 and R3.
é
ù
1.4 ´ R1
VUV_L
R2 =
´ ê1–
ú
–5
(VUV_L -1.4) ë (VOV_L + 10 ´ R1)û
(10)
1.4 ´ R1 ´ VUV_L
R3 =
(V UV_L – 1.4) ´ (V OV_L + 10–5 ´ R1)
(11)
where
• VUV_L is the UVLO threshold when the input supply is low; i.e., less than VUV, and
• VOV_L is the OVLO threshold when the input supply is low; i.e., less than VOV
Again referring to the Figure 17a schematic, Equation 10 and Equation 11 produce R2 = 4.909 kΩ (4.99 kΩ
selected) and R3 = 3.951 kΩ (3.92 kΩ selected), as shown. For the selected values, the expected nominal
supply thresholds are VUV_L = 32.8 V, VUV_H = 30.8 V, and VOV_L = 72.6 V. The hysteresis of the overvoltage
threshold, as seen at the supply inputs, is given by the quantity (10 µA) × (R1 + R2). For the majority of
applications, this value is very nearly the same as the UV hysteresis, since typically R1 >> R2.
If more independent control is needed for the OVLO hysteresis, there are several options. One option is to use
separate dividers for both the UV and OV pins, as shown in Figure 16b. In this case, once R1 and R8 have been
selected for the required hysteresis per Equation 9, and values for the bottom resistors in the divider (R2 and R9
in Figure 16b) can be calculated using Equation 12.
VREF
RXVLO =
´ R(TOP)
(VXV_L – VREF)
(12)
where
• RXVLO is R2 or R9
• R(TOP) is R1 or R8 as appropriate for the threshold being set
• VXV_L is the under (VUV_L) or overvoltage (VOV_L) threshold at the supply input, and
• VREF is either VTHUV or VTHOV from the specification table, as required for the resistor being calculated.
Reverse Voltage Protection
In some applications, it may be necessary to protect the TPS2350 against reverse polarity supply connections or
input transients. If the potential at either the –VINA or –VINB pin rises above that of the RTN pin, device damage
may result. If the application environment is such that these conditions are anticipated, a small-signal diode
should be inserted between the supply return bus and the TPS2350 RTN pin, as shown in the Typical Application
diagram. A 75-V to 100-V rated device (VRRM), such as MMBD4148 or BAV19, is recommended.
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REVISION HISTORY
Changes from Revision B (December 2005) to Revision C
•
Replaced the Dissipations Rating table with the Thermal Information table ........................................................................ 3
Changes from Revision C (March 2011) to Revision D
•
18
Page
Page
Changed the FUNCTIONAL BLOCK DIAGRAM - Power Good Detection terminals were reversed ................................. 11
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS2350D
ACTIVE
SOIC
D
14
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2350
Samples
TPS2350DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2350
Samples
TPS2350PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2350
Samples
TPS2350PWG4
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2350
Samples
TPS2350PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS2350
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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