TPS2530DBVR

TPS2530 www.ti.com SLUSB67 – AUGUST 2012 Current-Limited, Power-Distribution Switches Check for Samples: TPS2530 FEATURES DESCRIPTION • • • • • • • • • • The TPS2530 power-distribution switch is intended for applications such as DisplayPort or USB Port where heavy capacitive loads and short-circuits are likely to be encountered. It offers 0.5 A fixed currentlimit thresholds. 1 2 Single Power Switch Pin for Pin with Existing TI Switch Portfolio™ Rated Currents of 0.5 A ±25% Accurate, Fixed, Constant Current Limit Fast Over-Current Response – 2 µs Operating Range: 2.7 V to 5.5 V Deglitched Fault Reporting Reverse Current Blocking Built-in Softstart Ambient Temperature Range: –40°C to 85°C The TPS2530 limits the output current to a safe level by operating in a constant-current mode when the output load exceeds the current-limit threshold. This provides a predictable fault current under all conditions. The fast overload response time eases the burden on the main supply to provide regulated power when the output is shorted. The power-switch rise and fall times are controlled to minimize current surges during turn-on and turn-off. APPLICATIONS • • • • DisplayPort USB Ports/Hubs, Laptops, Desktops Set Top Boxes Short-Circuit Protection TYPICAL APPLICATION TPS2530 VIN IN Fault Signal 0.1 μF RFLT 10 kΩ OUT VOUT 150 μF FLT Control Signal GND EN Figure 1. Typical Application DEVICE INFORMATION (1) MAXIMUM OPERATING CURRENT ENABLE BASE PART NUMBER PACKAGED DEVICE MARKING 0.5 High TPS2530 SOT23-5 (DBV) 2530 (1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see TI website at www.ti.com. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI Switch Portfolio is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS2530 SLUSB67 – AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Voltage range on IN, OUT, EN, FLT (2) MAX –0.3 6 V –6 6 V Voltage range from IN to OUT Maximum junction temperature, TJ Electrostatic Discharge Internally Limited HBM 2 CDM 500 IEC 6100-4-2, Contact / Air (3) (1) (2) (3) UNIT MIN kV V 8 15 kV Voltages are with respect to GND unless otherwise noted. See the Input and Output Capacitance section. VOUT was surged on a pcb with input and output bypassing per Figure 1 (except input capacitor was a 22 μF) with no device failures. THERMAL INFORMATION THERMAL METRIC (1) TPS2530 DBV (5 PINS) θJA Junction-to-ambient thermal resistance 224.9 θJCtop Junction-to-case (top) thermal resistance 95.2 θJB Junction-to-board thermal resistance 51.4 ψJT Junction-to-top characterization parameter 6.6 ψJB Junction-to-board characterization parameter 50.3 θJCbot Junction-to-case (bottom) thermal resistance N/A UNITS °C/W spacer (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VIN Input voltage, IN VEN NOM MAX UNIT 2.7 5.5 V Input voltage, EN 0 5.5 V VIH High-level input voltage, EN 2 VIL Low-level input voltage, EN 0.7 V IOUT Continuous output current, OUT (TPS2530) 0.5 A TJ Operating junction temperature IFLT Sink current into FLT 2 Submit Documentation Feedback V –40 125 °C 0 5 mA Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS2530 TPS2530 www.ti.com SLUSB67 – AUGUST 2012 ELECTRICAL CHARACTERISTICS: TJ = TA = 25°C (1) Unless otherwise noted: VIN = 5 V, VEN = VIN, IOUT = 0 A TEST CONDITIONS (2) PARAMETER MIN TYP MAX 25°C 103 120 –40°C ≤ (TJ, TA) ≤ 85°C 103 150 25°C 97 116 –40°C ≤ (TJ, TA) ≤ 85°C 97 143 1 1.25 0.01 1 UNIT POWER SWITCH VIN = 3.3 V RDS(on) Input – Output resistence VIN = 5 V mΩ CURRENT LIMIT IOS (3) Current-limit, See Figure 7 VIN = 3.3 V or 5 V 0.75 A SUPPLY CURRENT ISD Supply current, switch disabled ISE Supply current, switch enabled VIN = 3.3 V or 5 V, 25°C –40°C ≤ (TJ, TA ) ≤ 85°C, VIN = 5.5 V VIN = 3.3 V, 25°C 55 VIN = 5 V, 25°C 76 75 96 –40°C ≤ (TJ, TA ) ≤ 85°C, VIN = 5.5 V IREV (1) (2) (3) Reverse leakage current µA 2 µA 118 VOUT = 5.5 V, VIN = 0 V, measure IVOUT 0.2 1 µA Parametrics over a wider operational range are shown in the second ELECTRICAL CHARACTERISTICS table. Pulsed testing techniques maintain junction temperature close to ambient temperature. See CURRENT LIMIT section for explanation of this parameter. ELECTRICAL CHARACTERISTICS: –40°C ≤ TJ ≤ 125°C Unless otherwise noted: 2.7 V ≤ VIN ≤ 5.5 V, VEN = VIN, IOUT = 0 A, typical values are at 5 V and 25°C. TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT 97 200 mΩ POWER SWITCH RDS(on) Input – Output resistance ENABLE INPUT (EN) VIH High-level input Voltage VIL Low-level input Voltage Hysteresis tON 2 0.7 (2) 0.09 Leakage current VEN = 0 V or 5.5 V Turn on time VIN = 3.3 V, CL = 1 µF, RL = 100 Ω, EN ↑. See Figure 2, Figure 4 and Figure 5 Turn off time Rise time, output tF Fall time, output 0 1 1 1.75 2.5 0.8 1.35 1.9 0.25 0.45 0.65 0.2 0.3 0.4 0.7 1 1.3 VIN = 3.3 V, CL = 1 µF, RL = 100 Ω, EN ↑. See Figure 2, Figure 4 and Figure 5 µA ms 0.5 A tR –1 ms 0.5 A tOFF V VIN = 3.3 V, CL = 1 µF, RL = 100 Ω, See Figure 3 0.5 A VIN = 3.3 V, CL = 1 µF, RL = 100 Ω, See Figure 3 0.5 A ms ms CURRENT LIMIT IOS (3) Current-limit, See Figure 7 tIOS Short-circuit response time (2) (1) (2) (3) VIN = 5 V (see Figure 6), One-half full load → RSHORT = 50 mΩ, Measure from application to when current falls below 120% of final value 2 A µs Pulsed testing techniques maintain junction temperature close to ambient temperature. These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purpose of TI’s product warranty. See CURRENT LIMIT section for explanation of this parameter. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS2530 3 TPS2530 SLUSB67 – AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS: –40°C ≤ TJ ≤ 125°C (continued) Unless otherwise noted: 2.7 V ≤ VIN ≤ 5.5 V, VEN = VIN, IOUT = 0 A, typical values are at 5 V and 25°C. TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT SUPPLY CURRENT ISD Supply current, switch disabled 0.01 10 µA ISE Supply current, switch enabled 82 135 µA IREV Reverse leakage current (4) VOUT = 5.5 V, VIN = 0 V, Measure IVOUT 0.2 µA UNDERVOLTAGE LOCKOUT VUVLO Rising threshold VIN↑ Hysteresis (4) VIN↓ Output low voltage, FLT IFLT = 1 mA Off-state leakage VFLT = 5.5 V FLT deglitch FLT assertion and deassertion deglitch 3.5 In current limit 135 Not in current limit 155 2.2 2.46 2.6 65 V mV FLT tFLT 0.2 V 1 µA 12 ms 8 THERMAL SHUTDOWN TJ Rising threshold °C Hysteresis (4) (4) 20 °C These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purpose of TI’s product warranty. OUT tR RL tF 90% CL VOUT 10% Figure 2. Output Rise / Fall Test Load VEN 50% Figure 3. Power-On and Off Timing VEN 50% tON 50% 50% tON tOFF tOFF 90% 90% VOUT VOUT 10% 10% Figure 4. Enable Timing, Active High Enable Figure 5. Enable Timing, Active Low Enable Nonpreferred Preferred IOUT IOUT 120% ´ IOS 120% ´ IOS IOS IOS 0A tIOS tIOS Figure 6. Output Short Circuit Parameters 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS2530 TPS2530 www.ti.com SLUSB67 – AUGUST 2012 VIN Decreasing Load Resistance VOUT Slope = –RDS(on) 0V IOUT 0A IOS Figure 7. Output Characteristic Showing Current Limit FUNCTIONAL BLOCK DIAGRAM IN Current Sense Charge Pump CS OUT Current Limit Driver EN FLT UVLO OTSD Thermal Sense GND 8-ms Deglitch DEVICE INFORMATION DBV Package (Top View) OUT 1 GND 2 FLT 3 5 IN 4 EN PIN FUNCTIONS NAME PINS DESCRIPTION 5-PIN PACKAGE EN 4 Enable input, logic high turns on power switch. GND 2 Ground connection. IN 5 Input voltage and power-switch drain; connect a 0.1 µF or greater ceramic capacitor from IN to GND close to the IC. FLT 3 Active-low open-drain output, asserted during over-current, or over-temperature conditions. OUT 1 Power-switch output, connect to load. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS2530 5 TPS2530 SLUSB67 – AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS TPS2530 VIN IN (1) 680 μF IOUT VOUT OUT VIN2 0.1 μF CLOAD RLOAD 10 kΩ Enable Signal EN Fault Signal FLT GND (1) Helps with output shorting tests when external supply is used. Figure 8. Test Circuit for System Operation in Typical Characteristics Section 5 2 5 2 3 1.5 3 1.5 1 1 1 1 IOUT (A) 0 −3 EN −5 −2m−1m 0 VOUT 500m −1 0 −3 IOUT FLT −500m 1m 2m 3m 4m 5m 6m 7m 8m 9m 10m11m Time (s) −5 −2m−1m 0 G001 Figure 9. TPS2530 Output Rise/ Fall with 150-μF Load 1.5 1 1 −1 500m −3 8m 14m Time (s) 20m 5 2 3 1.5 1 1 −1 500m 0 IOUT 26m VOUT EN −5 −10m −500m 32m 0 G003 Figure 11. TPS2530 Enable and Disable Into Output Short 6 2.5 −3 0 2m EN, VOUT, FLT (V) 3 IOUT (A) EN, VOUT, FLT (V) 2 −5 −4m G002 VIN = 5 V, C L = 150 mF, RLoad = 50 mW, TPS2530 5 FLT FLT −500m 1m 2m 3m 4m 5m 6m 7m 8m 9m 10m11m Time (s) 7 2.5 VIN = 5 V, C L = 150 mF, R Load = 50 mW, TPS2530 VOUT IOUT Figure 10. TPS2530 Output Rise/ Fall with 1-μF Load 7 EN VOUT EN IOUT (A) EN, VOUT, FLT (V) 500m −1 2.5 VIN = 5 V, CL = 1 µF, RLoad = 10 Ω, TPS2530 IOUT (A) 7 VIN = 5 V, CL = 150 µF, RLoad = 10 Ω, TPS2530 EN, VOUT, FLT (V) 2.5 7 10m 20m 30m 40m Time (s) FLT 50m IOUT 60m −500m 70m G004 Figure 12. TPS2530 Pulsed Shorted Applied Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS2530 TPS2530 www.ti.com SLUSB67 – AUGUST 2012 TYPICAL CHARACTERISTICS (continued) 5 2 5 2 3 1.5 3 1.5 1 1 1 1 VIN = 5 V, CL = 150 µF, RLoad = 10 Ω, TPS2530 500m −3 0 VOUT 0 −3 −500m 1m 2m 3m 4m 5m 6m 7m 8m 9m 10m 11m Time (s) −5 −2m−1m 0 3 1.5 1 1 VOUT (V) 2 10 IOUT (A) EN, VOUT, FLT (V) 2.5 5 500m −1 0 −3 −5 −2m 0 VOUT FLT 2m 4m 6m Time (s) 8m FLT −500m 1m 2m 3m 4m 5m 6m 7m 8m 9m 10m11m Time (s) 24 VIN = 5 V, CL = 0 µF, RLoad = 50 mΩ, TPS2530 8 20 6 16 4 12 2 8 0 4 0 −2 IOUT VOUT −500m 12m 10m G006 Figure 14. TPS2530 Power Down – Enabled VIN = 5 V, CL = 150 µF, RLoad = 2Ω, TPS2530 EN IOUT G005 Figure 13. TPS2530 Power Up – Enabled 7 VOUT VIN IOUT FLT 500m −1 IOUT (A) VIN −5 −2m−1m 0 VIN, VOUT, FLT (V) IOUT (A) −1 IOUT (A) 7 VIN = 5 V, C L = 150 mF, RLoad = 10 W, TPS2530 VIN, VOUT , FLT (v) 2.5 2.5 7 −4 −4u −2u 0 2u IOUT 4u 6u −4 Time (s) G007 Figure 15. TPS2530 Enable with 2-Ω Load G008 Figure 16. TPS2530 Short Applied 100 1u 3.3 V 90 5.0 V 5.5 V 800n ISD (A) ISE (µA) 80 70 600n 400n 60 200n 50 3.3 V 40 −55 −15 5.0 V 25 65 Junction Temperature (°C) 5.5 V 105 145 0 −55 G009 Figure 17. Supply Current (Enabled) – ISE vs Temperature −15 25 65 Junction Temperature (°C) 105 Product Folder Links :TPS2530 G010 Figure 18. Supply Current (Disabled) – ISD vs Temperature Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated 145 7 TPS2530 SLUSB67 – AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 1.1 180 VIN = 5 V 160 IOS (A) RDS(on) (mW) 1 140 120 950m 100 900m 80 2.7 V 3.3 V 60 −55 −15 25 65 Junction Temperature (°C) 5.0 V 5.5 V 105 145 G011 Figure 19. Input – Output Resistance – RDS(on) vs Temperature 8 0.5 A Rated 850m −55 −15 25 65 Junction Temperature (°C) 105 145 G012 Figure 20. Current Limit – IOS vs Temperature Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS2530 TPS2530 www.ti.com SLUSB67 – AUGUST 2012 DETAILED DESCRIPTION TPS2530 is current-limited, power-distribution switch providing 0.5 A continuous load current in 3.3 V or 5 V circuits. The part use N-channel MOSFETs for low resistance, maintaining voltage to the load. It is designed for applications where short circuits or heavy capacitive loads are encountered. Device features include enable, reverse blocking when disabled, overcurrent protection, overtemperature protection, and deglitched fault reporting. UVLO The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turn on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large current surges. FLT is high impedance when the TPS2530 is in UVLO. ENABLE The logic enable input EN, controls the power switch, bias for the charge pump, driver, and other circuits. The supply current is reduced to less than 1 µA when the TPS2530 is disabled. Disabling the TPS2530 will immediately clear an active FLT indication. The enable input is compatible with both TTL and CMOS logic levels. The turn on and turn off times (tON, tOFF) are composed of a delay and a rise or fall time (tR, tF). The delay times are internally controlled. The rise time is controlled by both the TPS2530 and the external loading (especially capacitance). The fall time is controlled by the TPS2530 and the loading (R and C). An output load consisting of only a resistor will experience a fall time set by the TPS2530. An output load with parallel R and C elements will experience a fall time determined by the (R × C) time constant if it is longer than the TPS2530’s tF. The enable should not be left open, and may be tied to VIN or GND depending on the device. INTERNAL CHARGE PUMP The device incorporate an internal charge pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The driver incorporate circuitry that controls the rise and fall times of the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start functionally. The MOSFET power switch blocks current from OUT to IN when turned off by the UVLO or disabled. CURRENT LIMIT The TPS2530 responds to overloads by limiting output current to the static IOS levels shown in the Electrical Characteristics table. When an overload condition is present, the device maintains a constant output current, with the output voltage determined by (IOS x RLOAD). Two possible overload conditions can occur. The first overload condition occurs when either: 1) input voltage is first applied, enable is true, and a short circuit is present (load which draws IOUT > IOS), or 2) input voltage is present and the TPS2530 is enabled into a short circuit. The output voltage is held near zero potential with respect to ground and the TPS2530 ramps the output current to IOS. The TPS2530 limits the current to IOS until the overload condition is removed or the device begins to thermal cycle. The second condition is when an overload occurs while the device is enabled and fully turned on. The device responds to the overload condition within tIOS (Figure 6 and Figure 7) when the specified overload (per the Electrical Characteristics table) is applied. The response speed and shape will vary with the overload level, input circuit, and rate of application. The current-limit response varies between settling to IOS, or turnoff and controlled return to IOS. Similar to the previous case, the TPS2530 limits the current to IOS until the overload condition is removed or the device begins to thermal cycle. The TPS2530 thermal cycles if an overload condition is present long enough to activate thermal limiting in any of the above cases. This is due to the relatively large power dissipation [(VIN – VOUT) × IOS] driving the junction temperature up. The device turns off when the junction temperature exceeds 135°C (min) while in current limit. The device remains off until the junction temperature cools 20°C and then restarts. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS2530 9 TPS2530 SLUSB67 – AUGUST 2012 www.ti.com There are two kinds of current limit profiles typically available in TI switch products similar to the TPS2530. Many older designs have an output I vs V characteristic similar to the plot labeled “Current Limit with Peaking” in Figure 21. This type of limiting can be characterized by two parameters, the current limit corner (IOC), and the short circuit current (IOS). IOC is often specified as a maximum value. The TPS2530 does not present noticeable peaking in the current limit, corresponding to the characteristic labeled “Flat Current Limit” in Figure 21. This is why the IOC parameter is not present in the Electrical Characteristics tables. Current Limit with Peaking Flat Current Limit VIN VIN Decreasing Load Resistance VOUT 0V 0A Slope = –RDS(on) VOUT Slope = –RDS(on) Decreasing Load Resistance 0V IOUT 0A IOS IOC IOUT IOS Figure 21. Current Limit Profiles FLT The FLT open-drain output is asserted (active low) during an over-load or over-temperature condition. A 8 ms deglitch on both the rising and falling edged avoids false reporting at startup and during transients. A current limit condition shorter than the deglitch period clears the internal timer upon termination. The deglitch timer will not integrate with excessive ripple and large output capacitance may interface with operation of FLT around IOS as the ripple will drive the TPS2530 in and out of current limit. If the TPS2530 is in current limit and the over-temperature circuit goes active, FLT goes true immediately however exiting this condition is deglitched. FLT is tripped just as the knee of the constant-current limiting is entered. Disabling the TPS2530 clears and active FLT as soon as the switch turns off. FLT is high impedance when the TPS2530 is disabled or in undervoltage lockout (UVLO). APPLICATION INFORMATION INPUT AND OUTPUT CAPACITANCE Input and output capacitance improves the performance of the device. The actual capacitance should be optimized for the particular application. For all applications, a 0.1 µF or greater ceramic bypass capacitor between IN and GND is recommended as close to the device as possible for local noise de-coupling. All protection circuits such as TPS2530 will have the potential for input voltage overshoots and output voltage undershoots. Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high impedance (before turn on). Theoretically, the peak voltage is 2 times the applied. The second cause is due to the abrupt reduction of output short circuit current when the TPS2530 turns off and energy stored in the input inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as the TPS2530 output is shorted. Applications with large input inductance (e.g. connecting the evaluation board to the bench power-supply through long cables) may require large input capacitance reduce the voltage overshoot from exceeding the absolute maximum voltage of the device. The fast current-limit speed of the TPS2530 to hard output short circuits isolate the input bus form faults. However, ceramic input capacitance in the range of 1 µF to 22 µF adjacent to the TPS2530 input aids in both speeding response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are permitted. In order to keep front-end power circuit work normally, it is better to increase the output cap. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS2530 TPS2530 www.ti.com SLUSB67 – AUGUST 2012 Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred and the TPS2530 has abruptly reduced OUT current. Energy stored in the inductance will drive the OUT voltage down and potentially negative as it discharges. Application with large output inductance (such as from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. When implementing USB standard application, a 120 µF minimum output capacitance is required. Typically a 150 µF electrolytic capacitor is used, which is sufficient to control voltage undershoots. However, if the application does not require 120 µF of output capacitance, and there is potential to drive the output negative, a minimum of 10 µF ceramic capacitor on the output is recommended. The voltage undershoot should be controlled to less than 1.5 V for 10 µs. POWER DISSIPATION AND JUNCTION TEMPERATURE It is good design practice to estimate power dissipation and maximum expected junction temperature of the TPS2530. The system designer can control choices of package, proximity to other power dissipating devices, and printed circuit board (PCB) design based on these calculations. These have a direct influence on maximum junction temperature. Other factors such as airflow and maximum ambient temperature are often determined by system considerations. It is important to remember that these calculations do not include the effects of adjacent heat sources, and enhanced or restricted air flow. Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical. The following procedure requires iteration because power loss is due to the internal MOSFET I2 x RDS(on), and RDS(on) is a function of the junction temperature. As an initial estimate, use the RDS(on) at 125°C from the typical characteristics, and the preferred package thermal resistance for the preferred board construction from the thermal parameters section. TJ = TA + [(IOUT2 × RDS(on)) × θJA] Where: IOUT = rated OUT pin current (A) RDS(on) = Power switch on-resistance at an assumed TJ (Ω) TA = Maximum ambient temperature (°C) TJ = Maximum junction temperature (°C) θJA = Thermal resistance (°C/W) If the calculated TJ is substantially different from the original assumption, look up a new value of RDS(on) and recalculate. Under 85°C ambient temperature, the TPS2530 junction temperature TJ = 85 + 0.52 × 0.2 × 224.9 to approximately 96.5°C, so in a practical application, the RDS(on) is about 165 mΩ and never reach to maximum 200 mΩ as shown in the Electrical Characteristics table. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :TPS2530 11 PACKAGE OPTION ADDENDUM www.ti.com 26-Feb-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS2530DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2530 TPS2530DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 2530 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of