TPS2550
TPS2551
www.ti.com ........................................................................................................................................ SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008
ADJUSTABLE CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
FEATURES
1
•
•
•
•
•
•
•
•
•
•
2
•
•
DESCRIPTION
Adjustable Current-Limit, 100 mA–1100 mA
Fast Overcurrent Response - 2 µS Typical
85-mΩ High-Side MOSFET (DBV Package)
Reverse Input-Output Voltage Protection
Operating Range: 2.5 V to 6.5 V
Deglitched Fault Report
1-µA Maximum Standby Supply Current
Junction Temperature Range: –40°C to 125°C
Built-in Soft-Start
15 kV ESD Protection (with external
capacitance)
UL Listed – File No. E169910
Current-Limit Resistor Calculator – SLVC163
The TPS2550/51 power-distribution switch is
intended for applications where heavy capacitive
loads and short-circuits are likely to be encountered,
incorporating a 100-mΩ, N-channel MOSFET in a
single package. The current-limit threshold is user
adjustable between 100 mA and 1.1 A via an external
resistor. The power-switch rise and fall times are
controlled to minimize current surges during
switching.
The device limits the output current to a desired level
by switching into a constant-current mode when the
output load exceeds the current-limit threshold or a
short is present. An internal reverse-voltage detection
comparator disables the power-switch in the event
that the output voltage is driven higher than the input
to protect devices on the input side of the switch. The
FAULT logic output asserts low during both
overcurrent and reverse-voltage conditions.
APPLICATIONS
•
•
•
•
•
USB Ports/Hubs
Cell phones
Laptops
Heavy Capacitive Loads
Reverse-Voltage Protection
OUT
1
ILIM
2
3
FAULT
PAD
TPS2550/TPS2551
DRV PACKAGE
(TOP VIEW)
6
IN
5
4
GND
EN
0.1 mF
INPUT
1
6
2
3
5
4
OUT
ILIM
FAULT
USB
Port
OUT
IN
RFAULT
100 kW
TPS2550/TPS2551
DBV PACKAGE
(TOP VIEW)
IN
GND
EN
USB Data
TPS2550/51
5 V USB
120 mF *
FAULT Signal
FAULT
ILIM
Control Signal
EN
GND
RILIM
15 kW
PowerPAD
* USB Requirement that downstream-facing ports
are bypassed with at least 120 mF per hub
EN = Active Low for the TPS2550
EN = Active High for the TPS2551
Figure 1. Typical Application as USB Power
Switch
GENERAL SWITCH CATALOG
33 mW, Single
TPS201xA
TPS202x
TPS203x
0.2 A to 2 A
0.2 A to 2 A
0.2 A to 2 A
80 mW, Single
TPS2014
TPS2015
TPS2041B
TPS2051B
TPS2045A
TPS2049
TPS2055A
TPS2061
TPS2065
TPS2068
TPS2069
600 mA
1A
500 mA
500 mA
250 mA
100 mA
250 mA
1A
1A
1.5 A
1.5 A
80 mW, Dual
TPS2042B
TPS2052B
TPS2046B
TPS2056
TPS2062
TPS2066
TPS2060
TPS2064
500 mA
500 mA
250 mA
250 mA
1A
1A
1.5 A
1.5 A
80 mW, Dual
TPS2080
TPS2081
TPS2082
TPS2090
TPS2091
TPS2092
500 mA
500 mA
500 mA
250 mA
250 mA
250 mA
80 mW, Triple
TPS2043B
TPS2053B
TPS2047B
TPS2057A
TPS2063
TPS2067
500 mA
500 mA
250 mA
250 mA
1A
1A
80 mW, Quad
TPS2044B
TPS2054B
TPS2048A
TPS2058
500 mA
500 mA
250 mA
250 mA
80 mW, Quad
TPS2085
TPS2086
TPS2087
TPS2095
TPS2096
TPS2097
500 mA
500 mA
500 mA
250 mA
250 mA
250 mA
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TPS2550
TPS2551
SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008 ........................................................................................................................................ www.ti.com
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.
These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits. During storage or handling the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic
voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
AVAILABLE OPTIONS AND ORDERING INFORMATION
DEVICE
TPS2550
TPS2551
(1)
(2)
ENABLE
SON (2)
(DRV)
SOT23 (2)
(DBV)
RECOMMENDED MAXIMUM
CONTINUOUS LOAD CURRENT
Active low
TPS2550DRV
TPS2550DBV
1.1 A
Active high
TPS2551DRV
TPS2551DBV
1.1 A
AMBIENT
TEMPERATURE (1)
–40°C to 85°C
Maximum ambient temperature is a function of device junction temperature and system level considerations, such as power dissipation
and board layout. See dissipation rating table and recommended operating conditions for specific information related to these devices.
Add an R suffix to the device type for tape and reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
(2)
Voltage range on IN, OUT, EN or EN, ILIM, FAULT
VALUE
UNIT
–0.3 to 7
V
–7 to 7
V
Voltage range from IN to OUT
IOUT
Continuous output current
Internally limited
See "Dissipation Rating
Table"
Continuous total power dissipation
FAULT sink current
25
mA
ILIM source current
1
mA
HBM
2
kV
CDM
500
V
ESD
TJ
Maximum junction temperature
–40 to 150
°C
TSgt
Storage temperature
–65 to 150
°C
300
°C
Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltages are referenced to GND unless otherwise noted.
DISSIPATION RATING TABLE
BOARD
PACKAGE
THERMAL
RESISTANCE
θJA
THERMAL
RESISTANCE
θJC
TA ≤ 25°C
POWER
RATING
DERATING
FACTOR
ABOVE
TA = 25°C
TA = 70°C
POWER
RATING
TA = 85°C
POWER
RATING
TA = 110°C
POWER
RATING
Low-K (1)
DBV
350°C/W
55°C/W
285 mW
2.85 mW/°C
155 mW
114 mW
42 mW
High-K (2)
DBV
160°C/W
55°C/W
625 mW
6.25 mW/°C
340 mW
250 mW
93 mW
Low-K (1)
DRV
140°C/W
20°C/W
715 mW
7.1 mW/°C
395 mW
285 mW
107 mW
High-K (2)
DRV
75°C/W
20°C/W
1330 mW
13.3 mW/°C
730 mW
530 mW
200 mW
(1)
(2)
2
The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board.
The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
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Product Folder Link(s): TPS2550 TPS2551
TPS2550
TPS2551
www.ti.com ........................................................................................................................................ SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008
RECOMMENDED OPERATING CONDITIONS
VIN
Input voltage, IN
VEN
V/EN
Enable voltage
MIN
MAX
2.5
6.5
TPS2550
0
6.5
TPS2551
0
6.5
IOUT
Continuous output current, OUT
RILIM
Current-limit set resistor from ILIM to GND
I/FAULT
FAULT sink current
TJ
Operating virtual junction
temperature
DRV & DBV
UNIT
V
V
0
1.1
A
14.3
80.6
kΩ
0
10
mA
–40
125
°C
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, 2.5 V ≤ VIN ≤ 6.5 V, RILIM = 14.3 kΩ, V/EN = 0 V, or VEN = 5.0 V
(unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
POWER SWITCH
DBV package, TJ = 25 °C
85
DBV package, –40 °C ≤TJ ≤125 °C
rDS(on)
Static drain-source on-state resistance
DRV package, TJ = 25 °C
100
DRV package, –40 °C ≤TJ ≤105 °C
tf
VIN = 2.5 V
VIN = 6.5 V
Fall time, output
mΩ
150
VIN = 6.5 V
Rise time, output
115
145
DRV package, –40 °C ≤TJ ≤125 °C
tr
95
135
CL = 1 µF, RL = 100 Ω,
(see Figure 2)
VIN = 2.5 V
1.0
1.5
0.65
1.0
0.2
0.5
0.2
0.5
ms
ENABLE INPUT EN OR EN
VIH
High-level input voltage
VIL
Low-level input voltage
IEN
Input current
ton
Turnon time
toff
Turnoff time
1.1
0.66
VEN = 0 V or 6.5 V, V/EN = 0 V or 6.5 V
–0.5
CL = 1 µF, RL = 100 Ω, (see Figure 2)
V
0.5
µA
3
ms
3
ms
CURRENT LIMIT
IOS
Short-circuit current, OUT connected to GND
RILIM = 80.6 kΩ
110
215
RILIM = 38.3 kΩ
300
500
650
1050
1400
1650
290
315
340
RILIM = 15 kΩ
RILIM = 80.6 kΩ
IOC
Current-limit threshold (Maximum DC output current IOUT delivered to load)
RILIM = 38.3 kΩ
RILIM = 15 kΩ
tIOS
Response time to short circuit
300
620
665
705
1550
1650
1750
VIN = 5.0 V (see Figure 3)
mA
µs
2
REVERSE-VOLTAGE PROTECTION
Reverse-voltage comparator trip point
(VOUT – VIN)
Time from reverse-voltage condition to
MOSFET turn off
VIN = 5.0 V
95
135
190
mV
3
5
7
ms
0.1
1
µA
SUPPLY CURRENT
IIN_off
Supply current, low-level output
VIN = 6.5 V, No load on OUT, VEN = 6.5 V or VEN = 0 V, 14.3 kΩ
≤ RILIM ≤ 80.6 kΩ
IIN_on
Supply current, high-level output
VIN = 6.5 V, No load on OUT, VEN = 0 V or
VEN = 6.5 V
RILIM = 15 kΩ
150
µA
RILIM = 80.6 kΩ
130
µA
IREV
Reverse leakage current
VOUT = 6.5 V, VIN = 0 V
TJ = 25 °C
1
µA
(1)
0.01
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
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TPS2550
TPS2551
SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008 ........................................................................................................................................ www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating junction temperature range, 2.5 V ≤ VIN ≤ 6.5 V, RILIM = 14.3 kΩ, V/EN = 0 V, or VEN = 5.0 V
(unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
2.35
2.45
UNIT
UNDERVOLTAGE LOCKOUT
VUVLO
Low-level input voltage, IN
VIN rising
Hysteresis, IN
TJ = 25 °C
25
V
mV
FAULT FLAG
VOL
Output low voltage, FAULT
I/FAULT = 1 mA
Off-state leakage
V/FAULT = 6.5 V
FAULT deglitch
180
mV
1
µA
FAULT assertion or de-assertion due to overcurrent condition
5
7.5
10
ms
FAULT assertion or de-assertion due to reverse-voltage
condition
2
4
6
ms
THERMAL SHUTDOWN
Thermal shutdown threshold
155
Thermal shutdown threshold in current-limit
135
Hysteresis
4
°C
°C
15
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°C
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2550 TPS2551
TPS2550
TPS2551
www.ti.com ........................................................................................................................................ SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008
DEVICE INFORMATION
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
TPS2550DBV
TPS2551DBV
TPS2550DRV
TPS2551DRV
EN
3
–
4
–
I
Enable input, logic low turns on power switch
EN
–
3
–
4
I
Enable input, logic high turns on power switch
GND
2
2
5
5
IN
1
1
6
6
I
Input voltage; connect a 0.1 µF or greater
ceramic capacitor from IN to GND as close to the
IC as possible.
FAULT
4
4
3
3
O
Active-low open-drain output, asserted during
overcurrent, overtemperature, or reverse-voltage
conditions.
OUT
6
6
1
1
O
Power-switch output
ILIM
5
5
2
2
I
External resistor used to set current-limit
threshold; recommended 14.3 kΩ ≤ RILIM ≤ 80.6
kΩ.
PowerPAD
™
–
–
PAD
PAD
Ground connection; should be connected
externally to POWER PAD
Internally connected to GND; used to heat-sink
the part to the circuit board traces. Should be
connected to GND pin.
FUNCTIONAL BLOCK DIAGRAM
-
Reverse
Voltage
Comparator
+
IN
OUT
CS
4-ms
Deglitch
Current
Sense
Charge
Pump
Driver
EN
Current
Limit
FAULT
UVLO
GND
Thermal
Sense
8-ms Deglitch
ILIM
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TPS2550
TPS2551
SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008 ........................................................................................................................................ www.ti.com
PARAMETER MEASUREMENT INFORMATION
OUT
tf
tr
RL
CL
90%
VOUT
10%
90%
10%
TEST CIRCUIT
50%
VEN
VEN
50%
toff
ton
VOUT
50%
50%
toff
ton
90%
90%
VOUT
10%
10%
VOLTAGE WAVEFORMS
Figure 2. Test Circuit and Voltage Waveforms
IOS
IOUT
tIOS
Figure 3. Response Time to Short-Circuit Waveform
VOUT
DECREASING
LOAD
RESISTANCE
DECREASING
LOAD
RESISTANCE
IOS
IOC
IOUT
Figure 4. Output Voltage vs. Current-Limit Threshold
6
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TPS2550
TPS2551
www.ti.com ........................................................................................................................................ SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008
TYPICAL CHARACTERISTICS
Figure 5. Turnon Delay and Rise Time
Figure 6. Turnoff Delay and Fall Time
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TPS2550
TPS2551
SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008 ........................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 7. Device Enabled into Short-Circuit
Figure 8. Full-Load to Short-Circuit Transient Response
8
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TPS2551
www.ti.com ........................................................................................................................................ SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Figure 9. Short-Circuit to Full-Load Recovery Response
Figure 10. No-Load to Short-Circuit Transient Response
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TPS2550
TPS2551
SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008 ........................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 11. Short-Circuit to No-Load Recovery Response
Figure 12. No Load to 1Ω Transient Response
10
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TPS2551
www.ti.com ........................................................................................................................................ SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Figure 13. 1Ω to No Load Transient Response
Figure 14. Reverse-Voltage Protection Response
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TPS2550
TPS2551
SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008 ........................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (continued)
Figure 15. Reverse-Voltage Protection Recovery
2.40
UVLO - Undervoltage Lockout - V
2.39
2.38
2.37
UVLO Rising
2.36
2.35
2.34
UVLO Falling
2.33
2.32
2.31
2.30
-50
0
50
100
150
TJ - Junction Temperature - °C
Figure 16. UVLO – Undervoltage Lockout – V
12
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TPS2551
www.ti.com ........................................................................................................................................ SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008
TYPICAL CHARACTERISTICS (continued)
0.50
VIN = 6.5 V
IIN - Supply Current, Output Disabled - mA
0.45
0.40
VIN = 5 V
0.35
VIN = 3.3 V
0.30
0.25
VIN = 2.5 V
0.20
0.15
0.10
0.05
0
-50
0
50
TJ - Junction Temperature - °C
100
150
Figure 17. IIN – Supply Current, Output Disabled – µA
150
RILIM = 20 kW
VIN = 6.5 V
IIN - Supply Current, Output Enabled - mA
135
120
VIN = 5 V
105
VIN = 3.3 V
90
75
VIN = 2.5 V
60
45
30
15
0
-50
0
50
TJ - Junction Temperature - °C
100
150
Figure 18. IIN – Supply Current, Output Enabled – µA
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TPS2551
SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008 ........................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (continued)
20
VIN = 5 V,
TA = 25°C
18
Current Limit Response - ms
16
14
12
10
8
6
4
2
0
0
1.5
3
Peak Current - A
4.5
6
Figure 19. Current Limit Response – µs
rDS(on) - Static Drain-Source On-State Resistance - mW
150
125
DRV Package
100
DBV Package
75
50
25
0
-50
0
50
TJ - Junction Temperature - °C
100
150
Figure 20. MOSFET rDS(on) Vs. Junction Temperature
14
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TPS2551
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DETAILED DESCRIPTION
OVERVIEW
The TPS2550/51 are current-limited, power distribution switches using N-channel MOSFETs for applications
where short-circuits or heavy capacitive loads will be encountered. These devices allow the user to program the
current-limit threshold between 100 mA and 1.1 A via an external resistor. Additional device shutdown features
include overtemperature protection and reverse-voltage protection. The device incorporates an internal charge
pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to
the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The
charge pump operates from input voltages as low as 2.5 V and requires little supply current. The driver controls
the gate voltage of the power switch. The driver incorporates circuitry that controls the rise and fall times of the
output voltage to limit large current and voltage surges and provide built-in soft-start functionality.
OVERCURRENT
The TPS2550/51 responds to an overcurrent condition by limiting its output current to the IOC and IOS levels
shown in Figure 21. Three response profiles are possible depending on the loading conditions and are
summarized in Figure 4.
One response profile occurs if the TPS2550/51 is enabled into a short-circuit. The output voltage is held near
zero potential with respect to ground and the TPS2550/51 ramps the output current to IOS (see Figure 7).
A second response profile occurs if a short is applied to the output after the TPS2550/51 is enabled. The device
responds to the overcurrent condition within time tIOS (see Figure 3). The current-sense amplifier is over-driven
during this time and momentarily disables the internal current-limit MOSFET. The current-sense amplifier
gradually recovers and limits the output current to IOS.
A third response profile occurs if the load current gradually increases. The device first limits the load current to
IOC. If the load demands a current greater than IOC, the TPS2550/51 folds back the current to IOS and the output
voltage decreases to IOS x RLOAD for a resistive load, which is shown in Figure 4.
The TPS2550/51 thermal cycles if an overload condition is present long enough to activate thermal limiting in any
of the above cases. The device turns off when the junction temperature exceeds 135°C (typ). The device
remains off until the junction temperature cools 15°C (typ) and then restarts. The TPS2550/51 cycles on/off until
the overload is removed (see Figure 9 and Figure 11) .
REVERSE-VOLTAGE PROTECTION
The reverse-voltage protection feature turns off the N-channel MOSFET whenever the output voltage exceeds
the input voltage by 135 mV (typical) for 4-ms. This prevents damage to devices on the input side of the
TPS2550/51 by preventing significant current from sinking into the input capacitance. The N-channel MOSFET is
allowed to turn-on once the output voltage goes below the input voltage for the same 4-ms deglitch time. The
reverse-voltage comparator also asserts the FAULT output (active-low) after 4-ms.
FAULT RESPONSE
The FAULT open-drain output is asserted (active low) during an overcurrent, overtemperature or reverse-voltage
condition. The output remains asserted until the fault condition is removed. The TPS2550/51 is designed to
eliminate false FAULT reporting by using an internal delay "deglitch" circuit for overcurrent (7.5-ms) and
reverse-voltage (4-ms) conditions without the need for external circuitry. This ensures that FAULT is not
accidentally asserted due to normal operation such as starting into a heavy capacitive load. The deglitch circuitry
delays entering and leaving fault conditions. Overtemperature conditions are not deglitched and assert the
FAULT signal immediately.
UNDERVOLTAGE LOCKOUT (UVLO)
The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turn-on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large
current surges.
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SLVS736B – FEBRUARY 2008 – REVISED NOVEMBER 2008 ........................................................................................................................................ www.ti.com
ENABLE (EN OR EN)
The logic enable controls the power switch, bias for the charge pump, driver, and other circuits to reduce the
supply current. The supply current is reduced to less than 1-µA when a logic high is present on EN or when a
logic low is present on EN. A logic low input on EN or a logic high input on EN enables the driver, control circuits,
and power switch. The enable input is compatible with both TTL and CMOS logic levels.
THERMAL SENSE
The TPS2550/51 protects itself with two independent thermal sensing circuits that monitor the operating
temperature of the power-switch and disables operation if the temperature exceeds recommended operating
conditions. The device operates in constant-current mode during an overcurrent conditions, which increases the
voltage drop across power-switch. The power dissipation in the package is proportional to the voltage drop
across the power-switch, so the junction temperature rises during an overcurrent condition. The first thermal
sensor turns off the power-switch when the die temperature exceeds 135°C and the part is in current limit. The
second thermal sensor turns off the power-switch when the die temperature exceeds 155°C regardless of
whether the power-switch is in current limit. Hysteresis is built into both thermal sensors, and the switch turns on
after the device has cooled approximately 15°C. The switch continues to cycle off and on until the fault is
removed. The open-drain false reporting output FAULT is asserted (active low) immediately during an
overtemperature shutdown condition.
16
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APPLICATION INFORMATION
INPUT AND OUTPUT CAPACITANCE
Input and output capacitance improve the performance of the device; the actual capacitance should be optimized
for the particular application. For all applications, a 0.01 µF to 0.1µF ceramic bypass capacitor between IN and
GND is recommended as close to the device as possible for local noise de-coupling. This precaution reduces
ringing on the input due to power-supply transients. Additional input capacitance may be needed on the input to
reduce voltage overshoot from exceeding the absolute maximum voltage of the device during heavy transients.
This is especially important during bench testing when long, inductive cables are used to connect the evaluation
board to the bench power-supply.
Placing a high-value electrolytic capacitor on the output pin is recommended when the large transient currents
are expected on the output. Additionally, bypassing the output with a 0.01 µF to 0.1 µF ceramic capacitor
improves the immunity of the device to short-circuit transients.
PROGRAMMING THE CURRENT-LIMIT THRESHOLD
The overcurrent threshold is user programmable via an external resistor. Many applications require that the
minimum current-limit is above a certain current level or that the maximum current-limit is below a certain current
level, so it is important to consider the tolerance of the overcurrent threshold when selecting a value for RILIM.
The following equations and Figure 21 can be used to calculate the resulting overcurrent threshold for a given
external resistor value ILIM). Figure 21 includes current-limit tolerance due to variations caused by temperature
and process. The traces routing the RILIM resistor to the TPS2550/51should be as short as possible to reduce
parasitic effects on the current-limit accuracy.
There are two important current-limit thresholds for the device and are related by Figure 4. The first threshold is
the short-circuit current threshold IOS. IOS is the current delivered to the load if the part is enabled into a
short-circuit or a short-circuit is applied during normal operation. The second threshold is the overcurrent
threshold IOC. IOC is the peak DC current that can be delivered to the load before the device begins to limit
current. IOC is important if ramped loads or slow transients are common to the application. It is important to
consider both IOS and IOC when choosing RILIM. RILIM can be selected to provide a current-limit threshold that
occurs 1) above a minimum load current or 2) below a maximum load current.
To design above a minimum current-limit threshold, find the intersection of RILIM and the maximum desired load
current on the IOS(min) curve and choose a value of RILIM below this value. Programming the current-limit above a
minimum threshold is important to ensure start-up into full-load or heavy capacitive loads. The resulting
maximum DC load current is the intersection of the selected value of RILIM and the IOC(max) curve.
To design below a maximum DC current level, find the intersection of RILIM and the maximum desired load
current on the IOC(max) curve and choose a value of RILIM above this value. Programming the current-limit below a
maximum threshold is important to avoid current-limiting upstream power supplies causing the input voltage bus
to droop. The resulting minimum short-circuit current is the intersection of the selected value of RILIM and the
IOS(min) curve.
Overcurrent Threshold Equations (IOC):
• IOC(max) (mA) = (24500 V) / ILIM kΩ) 0.975
• IOC(typ) (mA) = (23800 V) / ILIM kΩ) 0.985
• IOC(min) (mA) = (23100 V) / ILIM kΩ) 0.996
Short-Circuit Current Equations (IOS):
• IOS(max) (mA) = (25500 V) / ILIM kΩ) 1.013
• IOS(typ) (mA) = (28700 V) / ILIM kΩ) 1.114
• IOS(min) (mA) = (39700 V) / ILIM kΩ) 1.342
where 14.3 kΩ ≤ RILIM ≤ 80.6 kΩ. IOS(typ) and IOS(max) are not plotted to improve graph clarity.
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1800
Current-Limit Threshold - mA
1700
1600
1500
1400
IOC(max)
1300
1200
1100
1000
IOC(typ)
IOC(min)
900
800
700
600
500
400
300
200
100
0
15
IOS(min)
20
25
30
35
40
45
50
RILIM - kW
55
60
65
70
75
80
Figure 21. Current-Limit Threshold Vs.RILIM
APPLICATION 1: DESIGNING ABOVE A MINIMUM CURRENT-LIMIT
Some applications require that current-limiting cannot occur below a certain threshold. For this example, assume
that 1 A must be delivered to the load so that the minimum desired current-limit threshold is 1000 mA. Use the
IOS equations and Figure 21 to select RILIM.
• IOS(min) (mA) = 1000 mA
• IOS(min) (mA) = (39700 V) / ILIM (kΩ)) 1.342
• RILIM (kΩ) = [(39700 V) / (IOS(min) (mA))] 1/1.342
• RILIM = 15.54 kΩ
Select the closest 1% resistor less than the calculated value: RILIM = 15.4 kΩ. This sets the minimum current-limit
threshold at 1 A . Use the IOC equations, Figure 21, and the previously calculated value for RILIM to calculate the
maximum resulting current-limit threshold.
• RILIM = 15.4 kΩ
• IOC(max) (mA) = (24500 V) / ILIM (kΩ)) 0.975
• IOC(max) (mA) = (24500 V) / (15 (kΩ)) 0.975
• IOC(max) = 1703 mA
The resulting maximum current-limit threshold is 1.7 A with a 15.4 kΩ resistor.
APPLICATION 2: DESIGNING BELOW A MAXIMUM CURRENT-LIMIT
Some applications require that current-limiting must occur below a certain threshold. For this example, assume
that the desired upper current-limit threshold must be below 1.25 A to protect an up-stream power supply. Use
the IOC equations and Figure 21 to select RILIM.
• IOC(max) (mA) = 1250 mA
• IOC(max) (mA) = (24500 V) / ILIM (kΩ)) 0.975
• RILIM (kΩ) = [(24500 V) / (IOC(max) (mA))] 1/0.975
• RILIM = 21.15 kΩ
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Select the closest 1% resistor greater than the calculated value: RILIM = 21.5 kΩ. This sets the maximum
current-limit threshold at 1.25 A . Use the IOS equations, Figure 21, and the previously calculated value for RILIM
to calculate the minimum resulting current-limit threshold.
• RILIM = 21.5 kΩ
• IOS(min) (mA) = (39700 V) / ILIM (kΩ)) 1.342
• IOS(min) (mA) = (39700 V) / (21.5 (kΩ)) 1.342
• IOS(min) = 647 mA
The resulting minimum current-limit threshold is 647 mA with a 21.5 kΩ resistor.
POWER DISSIPATION AND JUNCTION TEMPERATURE
The low on-resistance of the N-channel MOSFET allows small surface-mount packages to pass large currents. It
is good design practice to estimate power dissipation and junction temperature. The below analysis gives an
approximation for calculating junction temperature based on the power dissipation in the package. However, it is
important to note that thermal analysis is strongly dependent on additional system level factors. Such factors
include air flow, board layout, copper thickness and surface area, and proximity to other devices dissipating
power. Good thermal design practice must include all system level factors in addition to individual component
analysis.
Begin by determining the rDS(on) of the N-channel MOSFET relative to the input voltage and operating
temperature. As an initial estimate, use the highest operating ambient temperature of interest and read rDS(on)
from the typical characteristics graph. Using this value, the power dissipation can be calculated by:
PD = rDS(on) × IOUT2
Where:
PD = Total power dissipation (W)
rDS(on) = Power switch on-resistance (Ω)
IOUT = Maximum current-limit threshold (A)
This step calculates the total power dissipation of the N-channel MOSFET.
Finally, calculate the junction temperature:
TJ = PD × RΘJA + TA
Where:
TA = Ambient temperature (°C)
RΘJA = Thermal resistance (°C/W)
PD = Total power dissipation (W)
Compare the calculated junction temperature with the initial estimate. If they are not within a few degrees, repeat
the calculation using the "refined" rDS(on) from the previous calculation as the new estimate. Two or three
iterations are generally sufficient to achieve the desired result. The final junction temperature is highly dependent
on thermal resistance RθJA, and thermal resistance is highly dependent on the individual package and board
layout. The "Dissipating Rating Table" at the beginning of this document provides example thermal resistance for
specific packages and board layouts.
UNIVERSAL SERIAL BUS (USB) POWER-DISTRIBUTION REQUIREMENTS
One application for this device is for current-limiting in universal serial bus (USB) applications. The original USB
interface was a 12-Mb/s or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC
peripherals (e.g., keyboards, printers, scanners, and mice). As the demand for more bandwidth increased, the
USB 2.0 standard was introduced increasing the maximum data rate to 480-Mb/s. The four-wire USB interface is
conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data,
and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply. The USB specification classifies two different classes of
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devices depending on its maximum current draw. A device classified as low-power can draw up to 100 mA as
defined by the standard. A device classified as high-power can draw up to 500 mA. It is important that the
minimum current-limit threshold of the current-limiting power-switch exceed the maximum current-limit draw of
the intended application. The latest USB standard should always be referenced when considering the
current-limit threshold
The USB specification defines two types of devices as hubs and functions. A USB hub is a device that contains
multiple ports for different USB devices to connect and can be self-powered (SPH) or bus-powered (BPH). A
function is a USB device that is able to transmit or receive data or control information over the bus. A USB
function can be embedded in a USB hub. A USB function can be one of three types included in the list below.
• Low-power, bus-powered function
• High-power, bus-powered function
• Self-powered function
SPHs and BPHs distribute data and power to downstream functions. The TPS2550/51 has higher current
capability than required for a single USB port allowing it to power multiple downstream ports.
SELF-POWERED AND BUS-POWERED HUBS
A SPH has a local power supply that powers embedded functions and downstream ports. This power supply
must provide between 4.75 V to 5.25 V to downstream facing devices under full-load and no-load conditions.
SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller.
Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.
A BPH obtains all power from an upstream port and often contains an embedded function. It must power up with
less than 100 mA. The BPH usually has one embedded function, and power is always available to the controller
of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the
embedded function may need to be kept off until enumeration is completed. This is accomplished by removing
power or by shutting off the clock to the embedded function. Power switching the embedded function is not
necessary if the aggregate power draw for the function and controller is less than 100 mA. The total current
drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the
downstream ports, and it is limited to 500 mA from an upstream port.
LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS
Both low-power and high-power bus-powered functions obtain all power from upstream ports. Low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 µF at power up, the device must implement inrush current limiting.
USB POWER-DISTRIBUTION REQUIREMENTS
USB can be implemented in several ways regardless of the type of USB device being developed. Several
power-distribution features must be implemented.
• SPHs must:
– Current-limit downstream ports
– Report overcurrent conditions
• BPHs must:
– Enable/disable power to downstream ports
– Power up at
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