TPS272C45
SLVSF24B – DECEMBER 2020 – REVISED FEBRUARY 2022
TPS272C45 45-mΩ, Dual-Channel Smart High-Side Switch With Diagnostics
1 Features
3 Description
•
The TPS272C45 is a dual-channel smart high-side
switch designed to meet the requirements of industrial
control systems. The low on-resistance (RDS(on) of
45 mΩ) minimizes device power dissipation driving
a wide range (100 mA to 3 A) of output load
current. The device provides an additional low voltage
supply (3.3 V to 5 V) input pin to minimize no-load
power dissipation. The device integrates protection
features such as thermal shut down, output clamp,
and overcurrent limit. These features improve system
robustness during fault events such as short circuit.
•
•
•
•
•
•
•
•
Low RDS(on) (45-mΩ typical) high-side switch for
24-V industrial applications
Wide DC operating voltage range: 6 V to 36 V
Low quiescent current (Iq) of 0.5 mA per channel
(typical) from 24-V supply
Fixed (5.8 A) and adjustable (0.7 A to 4 A with
external resistor) current limiting
Drive inductive, capacitive, and resistive loads
– Integrated output clamp to support inductive
load discharge
– Capacitive load drive minimizing peak inrush
current through dual threshold current limiting
Robust output protection
– Thermal shutdown
– Protection against short to ground events
– Configurable fault handling
Enhanced diagnostic feature
– Output load current measurement
– Open load (off-state) detection
Package: 24-pin QFN (5 mm × 4 mm)
Functional Safety-Capable
– Documentation available to aid functional safety
system design
2 Applications
•
•
•
Industrial PLC systems
– Digital output modules
– IO-Link master ports
Motor drives
Building automation systems
The TPS272C45 device implements an adjustable
threshold current limiting circuit that improves the
reliability of the system by reducing inrush current
when driving large capacitive loads and minimizing
overload current. The device also implements a
configurable inrush current time period with a higher
level of allowed current to drive high inrush current
loads like lamps or for fast charging of capacitive
loads. The device also provides an accurate
load current sense that allows for improved load
diagnostics enabling better predictive maintenance.
The TPS272C45 device is available in a small 24-pin,
5 mm × 4 mm QFN leadless package with 0.5 mm pin
pitch minimizing the PCB footprint.
Device Information
PART NUMBER
TPS272C45
(1)
5-V/3.3-V Power
Supply (Optional)
PACKAGE(1)
QFN (24)
BODY SIZE (NOM)
5.00 mm × 4.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
24-V Power Supply
VDD
VS
EN1
EN2
FLT
DIA_EN
MCU
OUT1
SEL
SNS
To inductive,
capacitive and
resistive load
RSNS
ILIM1
ILIM2
ILIMD
RILIM1
RILIM2
RILIMD
OUT2
GND
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS272C45
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SLVSF24B – DECEMBER 2020 – REVISED FEBRUARY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
6.1 Recommended Connections for Unused Pins............ 6
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings........................................ 7
7.2 ESD Ratings............................................................... 7
7.3 Recommended Operating Conditions.........................7
7.4 Thermal Information....................................................8
7.5 Electrical Characteristics.............................................8
7.6 SNS Timing Characteristics...................................... 12
7.7 Switching Characteristics..........................................12
7.8 Typical Characteristics.............................................. 14
8 Parameter Measurement Information.......................... 16
9 Detailed Description......................................................18
9.1 Overview................................................................... 18
9.2 Functional Block Diagram......................................... 19
9.3 Feature Description...................................................19
9.4 Device Functional Modes..........................................39
10 Application and Implementation................................ 40
10.1 Application Information........................................... 40
10.2 Typical Application.................................................. 43
11 Power Supply Recommendations..............................48
12 Layout...........................................................................49
12.1 Layout Guidelines................................................... 49
12.2 Layout Example...................................................... 49
13 Device and Documentation Support..........................50
13.1 Documentation Support.......................................... 50
13.2 Receiving Notification of Documentation Updates..50
13.3 Support Resources................................................. 50
13.4 Trademarks............................................................. 50
13.5 Electrostatic Discharge Caution..............................50
13.6 Glossary..................................................................50
14 Mechanical, Packaging, and Orderable
Information.................................................................... 51
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2021) to Revision B (February 2022)
Page
• Removed duplicate functional block diagram from front page............................................................................1
• Deleted Preview only designation from all product variants in Section 5 .......................................................... 3
• Deleted Preview only designation from Figure 6-1 ............................................................................................ 4
• Deleted Preview only designation from Figure 6-2 ............................................................................................ 4
• Corrected typographic error in Pin 10 label for Figure 6-2 .................................................................................4
Changes from Revision * (December 2020) to Revision A (December 2021)
Page
• Changed status from "Advance Information" to "Production Data".....................................................................1
2
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SLVSF24B – DECEMBER 2020 – REVISED FEBRUARY 2022
5 Device Comparison Table
Device
Integrated
Low
Voltage
Regulator
Integrated
Clamp for
Inductive Loads
Fault Diagnosis
Current Limit
Advantage
TPS272C45A
No
Yes
Single FLT pin,
SNS pin provides
per -ch fault
Dual level, inrush
period
Lower device power dissipation with most of
the quiescent current drawn from the lower
voltage supply input – enables reduced total
heat dissipation and thus smaller module
sizes. Connect a 3.3V DC-DC regulator output
to VDD pin.
Single fault pin reduces IO count.
TPS272C45B
Yes
Yes
Single FLT pin,
SNS pin provides
per -ch fault
Dual level, inrush
period
Lower system costs with a single power
supply (cost of a low voltage regulator is
avoided).
Dual level, inrush
period
Enables usage of external TVS Clamp for high
inductive loading.
The device variant can be used with an
external supply on VDD pin or using the
internal 3.3-V regulation by GNDing the VDD
pin.
Single level
Dual FLT pins provides easier fault diagnosis.
The device variant can be used with an
external supply on VDD pin or using the
internal 3.3-V regulation by GNDing the VDD
pin.
TPS272C45C
TPS272C45D
Yes
Yes
No
Yes
Single FLT pin,
SNS pin provides
per -ch fault
Dual fault FLT1/
FLT2 pins
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SLVSF24B – DECEMBER 2020 – REVISED FEBRUARY 2022
NC
ILIM1
ILIM2
22
21
20
ILIM2
20
VS
ILIM1
21
23
NC
22
VS
VS
23
24
VS
24
6 Pin Configuration and Functions
OUT1
1
19
VDD
OUT1
1
19
GND
OUT1
2
18
ILIMD
OUT1
2
18
ILIMD
OUT1
3
17
GND
OUT1
3
17
GND
NC
4
16
EN1
NC
4
16
EN1
OUT2
5
15
EN2
OUT2
5
15
EN2
OUT2
6
14
LATCH
OUT2
6
14
LATCH
OUT2
7
13
SEL
OUT2
7
13
SEL
10
11
12
SNS
DIA_EN
DIA_EN
FLT
12
SNS
9
11
VS
10
FLT
8
9
VS
VS
VS
NC
ILIM1
ILIM2
23
22
21
20
Figure 6-2. RHF Package, 24-Pin QFN (Top View)
Version B
24
Figure 6-1. RHF Package, 24-Pin QFN (Top View)
Version A and C
PowerPadTM
VS
8
VS
PowerPadTM
OUT1
1
19
VDD
OUT1
2
18
FLT2
OUT1
3
17
GND
NC
4
16
EN1
OUT2
5
15
EN2
OUT2
6
14
LATCH
OUT2
7
13
SEL
8
9
10
11
12
VS
VS
FLT1
SNS
DIA_EN
PowerPadTM
Figure 6-3. RHF Package, 24-Pin QFN (Top View) Version D
Table 6-1. Pin Functions
PIN
4
I/O
DESCRIPTION
NAME
TPS272C45A,
TPS272C45C
TPS272C45B
TPS272C45D
DIA_EN
12
12
12
I
Enables diagnostic functionality
SEL
13
13
13
I
SEL = 0: SNS pin measures channel 1 load current or fault output SEL
= 1: SNS pin measures channel 2 load current or fault output.
LATCH
14
14
14
I
Sets retry behavior. LATCH = 0: auto-retry after faults or LATCH = 1:
latch off after faults.
EN2
15
15
15
I
Enables channel 2 output current
EN1
16
16
16
I
Enables channel 1 output current
GND
17
17, 19
17
GND
Device ground
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Table 6-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
TPS272C45A,
TPS272C45C
TPS272C45B
TPS272C45D
ILIMD
18
18
—
O
Connect RILIMD to GND to set higher inrush current limit time duration.
FLT2
—
—
18
O
Open drain output with pulldown to signal fault on Ch2 (active low
signal).
ILIM2
20
20
20
O
Connect RILIM2 to GND to set channel 2 current limit.
ILIM1
21
21
21
O
Connect RILIM1 to GND to set channel 1 current limit.
PowerPad
Pad
Pad
Pad
—
Heat dissipation pad – connect to device GND. Maximize PCB copper
area for the best heat dissipation.
VS
23, 24, 8, 9
23, 24, 8, 9
23, 24, 8, 9
I
Primary input supply, connect through vias down to a power plane to
connect the two set of VS power pins.
VOUT1
1, 2, 3
1, 2, 3
1, 2, 3
O
Channel 1 output
NC
4, 22
4, 22
4, 22
VOUT2
5, 6, 7
5, 6, 7
5, 6, 7
O
Channel 2 output
FLT
10
10
—
O
Open drain output with pulldown to signal fault on either channel (active
low signal).
FLT1
—
—
10
O
Open drain output with pulldown to signal fault on Ch1 (active low
signal).
SNS
11
11
11
O
Analog current output corresponding to load current – connect a
resistor to GND to convert to voltage.
No connect pin, leave unconnected
Version A: Connect low voltage supply input for lower
power dissipation
VDD
19
—
19
I
Version C, D: Optionally tie to gnd to use internal LDO or connect to
external low voltage supply.
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SLVSF24B – DECEMBER 2020 – REVISED FEBRUARY 2022
6.1 Recommended Connections for Unused Pins
The TPS272C45 is designed to provide an enhanced set of diagnostic and protection features. However, if the
system design only allows for a limited number of I/O connections, some pins can be considered as optional.
Table 6-2. Connections for Optional Pins
PIN NAME
SNS
CONNECTION IF NOT USED
IMPACT IF NOT USED
Ground through 1-kΩ resistor Analog current sense is not available.
LATCH
GND pin of IC
With LATCH unused (pin grounded), the device auto-retries after a fault.
If latched behavior is desired, but the system describes limited I/O, it is
possible to use one microcontroller output to control the latch function of
several high-side channels.
ILIMD
GND pin of IC
If ILIMD pin is connected to IC_GND, the current limit threshold is at a
constant value determined by the ILIM1/ILIM2 resistor values (delay time of
zero).
ILIM1/ILIM2
GND pin of IC
If either ILIMx pin is left floating or connected to IC_GND, the device is set
to the default internal current-limit threshold.
FLT / FLTx
GND pin of IC
If the FLT pin is unused, the system cannot read faults from the output.
SEL
GND pin of IC
With SEL unused, only channel one current sensing or Fault reporting is
available from the SNS pin.
DIA_EN
GND pin of IC
With DIA_EN unused, the analog current sense, open-load and short-tosupply diagnostics are not available.
VDD
GND pin of IC
Version A: Connect to a 3.3-V or 5-V supply
6
Version C, D: With VDD unused, all supply current is drawn from the
primary supply VS.
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SLVSF24B – DECEMBER 2020 – REVISED FEBRUARY 2022
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
Maximum continuous supply voltage, Versions A, B, D: VS
–0.7
48
V
Maximum transient (< 100 us) voltage at the supply pin, Versions A, B, D : VS
–0.7
60
V
Maximum continuous supply voltage Version C, VS
–0.7
60
V
Maximum voltage across the VS and OUT pins (VS - VOUT) Version C,
–0.7
71
V
Low voltage supply pin voltage, VDD
–1
5.5
V
Enable pin voltage, VEN1 and VEN2
–1
VS
V
LATCH pin voltage, VLATCH
–1
VS
V
Diagnostic Enable pin voltage, VDIA_EN
–1
VS
V
Sense pin voltage, VSNS
–1
VS
V
FLT pin voltage, Version A, B, C VFLT
–1
VS
V
FLTx pin voltage, Version D, VFLT1,VFLT2
–1
5.5
V
Select pin voltage, VSEL
–1
VS
V
Reverse ground current, IGND
VS < 0 V
Maximum junction temperature, TJ
Storage temperature, Tstg
(1)
–65
UNIT
–50
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
All pins except VS and OUTx
±2000
V
V(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
VS and OUTx with respect to
GND
±4000
V
V(ESD)
Electrostatic
discharge
Charged device model (CDM), ANSI/ESDA/JEDEC
JS-002(2)
All pins
±750
V
V(surge)
Electrostatic
discharge
Surge protection with 42 Ω, per IEC 61000-4-5;
1.2/50 μs (3)
OUTx pins
±1000
V
(1)
(2)
(3)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Tested with application circuit and supply voltage (VS) of 24-V, ENx pins High (Output Enabled) and and EN pins Low (Outputs
Disabled)
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VS_OPMAX
Nominal supply voltage
4.5
36
V
VDD
Low Voltage Supply Voltage
3.0
5.5
V
VEN1,
VEN2
Enable voltage
–1
36
V
VLATCH
LATCH voltage
–1
36
V
VDIA_EN
Diagnostic Enable voltage
–1
36
V
VFLT
FLT pin voltage (Versions A, B,C)
–1
36
V
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7.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VFLT1, FLT2
FLT1 , FLT2 pin voltage (Version D)
–1
5.5
V
VSEL
Select pin voltage
–1
36
V
VSNS
Sense pin voltage
–1
7
V
TA
Operating free-air temperature
–40
125
°C
(1)
UNIT
All operating voltage conditions are measured with respect to device GND
7.4 Thermal Information
TPS272C45
THERMAL
METRIC(1) (2)
RHF (QFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
32.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
22.5
°C/W
RθJB
Junction-to-board thermal resistance
10.2
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
10.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.7
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the SPRA953 application report.
The thermal parameters are based on a 4-layer PCB according to the JESD51-5 and JESD51-7 standards.
7.5 Electrical Characteristics
VS = 6 V to 36 V, VDD = 3.0 V to 3.6 V, TJ = -40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE AND CURRENT
8
VDS,Clamp
VDS clamp voltage
49
53
61
V
VS,OVPR
VS overvoltage protection Measured with respect to the GND pin of the device,
rising
ENx = HI
FET current = 10 mA, VS = 24 V
41.5
45.5
50
V
VS,OVPRF
VS overvoltage protection Measured with respect to the GND pin of the device,
recovery falling
ENx = HI
40
43.5
48
V
VS,OVPRD
VS overvoltage protection
Time from triggering the OVP fault to FET turn-off
deglitch time
30
72
85
µs
VS,UVLOR
VS undervoltage lockout
rising
Measured with respect to the GND pin of the device
3.5
4.0
4.5
V
VS,UVLOF
VS undervoltage lockout
falling
Measured with respect to the GND pin of the device
2.4
2.6
2.9
V
VDD,UVLOF
VDD undervoltage
lockout falling
Measured with respect to the GND pin of the device
2.63
2.8
2.9
V
VDD,UVLOR
VDD undervoltage lockout
Measured with respect to the GND pin of the device
rising
2.74
2.90
3.0
V
ILNOM
Continuous load current,
per channel
One channel enabled, TAMB = 85°C
4.0
A
Two channels enabled, TAMB = 85°C
3.0
A
IOUT(OFF)
Output leakage current
(per channel)
VS 1A
Multiply percentage
accuracy specification by
this factor
MIN
TYP
MAX
0.0416
–25
UNIT
mA
25
%
1.2
times
5.5
mA
2.35
V
10
µA
SNS CHARACTERISTICS
VDIA_EN = HI device in
VDIA_EN = HI, device in
FLT state of CH selected, FLT state of CH selected,
Vs>10 V
Vs>10 V
ISNSFH
ISNS fault high-level
ISNS_HR
VS - VSNS headroom
needed for current sense VS = 6V, ISNS = 3.4 mA
functionality
ISNSleak
ISNS leakage, with no
load
3.333
4.5
VDIA_EN = HI, VEN = HI, IL = 0 mA
CURRENT LIMIT CHARACTERISTICS
ICL
Current limitation Level
Heavy overload or short
circuit condition
RILIMx = GND, open, or
out of range (< 4.3 kΩ,
and > 80 kΩ)
4.3
5.8
6.95
A
ICL
Current limitation Level
Heavy overload or short
circuit condition
RILIMx = 5 kΩ, VVS-VOUT
>2V
3.15
4.1
4.7
A
ICL_LINPK
Overcurrent limit
threshold(1)
Overload condition(1)
RILIMx = 5 kΩ VVS-VVOUT
< 1V
4.78
A
ICL
Current limitation Level
Heavy overload or short
circuit condition
RILIMx = 10 kΩ, VVS-VOUT
>2V
2.3
A
ICL_LINPK
Overcurrent limit
threshold(1)
Overload condition
RILIMx = 10 kΩ VVS-VOUT
< 1V
2.42
A
ICL
ICL Current Limitation
Level
Heavy overload or short
circuit condition
RILIMx = 28.7 kΩ, VVSVVOUT > 2 V
0.82
A
ICL_LINPK
Overcurrent limit
threshold(1)
Overload condition(1)
RILIMx = 28.7 kΩ, VVSVOUT < 1 V
0.9
A
KCL
Current Limit Ratio
ICL_match12
ICL Current Limitation
Heavy overload or short
Level - Matching between
circuit condition
CH1 and CH2
ICL_ENPS
Peak current before
regulation while enabling
RILIMx = 5 kΩ to 20 kΩ, VS = 24V
switch into 100 mohm
load
ICL
Current limitation level
during inrush delay
period
Regulated current @
Short circuit when
Enabled
tDELAY
Nominal Higher Inrush
Current limit time delay
range
Set by resistor on ILIMD pin in discrete steps
tDELAY_VAR
Variation in ILIMD pin set
delay time
ICL,PRLL
Paralled Channels
Current Limitation Level
- Multiplier compared to
one channel
1.58
0.52
2.05
0.71
20.5
VEN1 tied to VEN2, VOUT1
tied to VOUT2
RILIMx = 10 kΩ, VVS-VOUT
= 24 V
RILIMx = 5 kΩ, RILIMD >
40 kΩ VVS-VOUT> 20 V
RILIMx = 5 kΩ to 20 kΩ
–10
A * kΩ
10
%
2.7 times
ICL
A
1.7
A
0
22
ms
–250
250
µs
1.3
1.5
1.1
FAULT CHARACTERISTICS
10
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7.5 Electrical Characteristics (continued)
VS = 6 V to 36 V, VDD = 3.0 V to 3.6 V, TJ = -40°C to 125°C (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
VENx = 0 V, VDIA_EN = 5 V
125
150
180
kΩ
Open-load (OL, wire
break) detection voltage
VS - VOUT
VENx = 0 V, VDIA_EN = 5 V
1.4
2.0
2.5
V
tOL1
Open Load (wire-break)
indication-time from ENx
falling
VENx HI to LO, VDIA_EN = 5 V, VSEL = X(2)
IOUT = 0 mA, Open load condition
170
300
440
µs
tOL2
Open load (wire-break)
indication-time from
DIA_EN rising
VENx = 0 V, VDIA_EN = LO to HI, VSEL = X(2)
IOUT = 0 mA, Open Load Condition
650
µs
tOL3
Open load (wire-break)
indication-time from VOUT VENx = 0 V, VDIA_EN = 5 V, VSEL = X(2)
rising beyond open load IOUT = 0 mA, VS – VOUTx = < 2 V
threshold
600
µs
TABS
Thermal shutdown
160
185
210
°C
TREL
Relative thermal
shutdown threshold
93
118
143
°C
THYS
Thermal shutdown
hysteresis
18
24
30
°C
Vol_FLT
Fault low-output voltage
(Versions A, B, C)
IFLT = 2 mA, sink current into the pin
0.4
V
Vol_FLTx
Fault low-output voltage
Version D
IFLT1 , IFLT2= 2 mA, sink current into the pin
0.4
V
tRETRY
Retry time
Time from fault shutdown until switch re-enable
(thermal shutdown or current limit).
Rpu_OL
Open-load (OL, wire
break) detection internal
pull-up resistor
VOL_off
TEST CONDITIONS
1
2
3
ms
EN1 AND EN2 PIN CHARACTERISTICS
VIL, ENx
Input voltage low-level
VIH, ENx
Input voltage high-level
VIHYS, ENx
Input voltage hysteresis
RENx
Internal pulldown resistor
IIH, EN
Input current high-level
0.8
2
V
350
0.8
VEN = 5 V
V
1.5
mV
2.5
5
MΩ
µA
DIA_EN PIN CHARACTERISTICS
VIL, DIA_EN
Input voltage low-level
VIH, DIA_EN
Input voltage high-level
2
VIHYS,
Input voltage hysteresis
200
350
530
mV
RDIA_EN
Internal pulldown resistor
0.8
1.5
2.5
MΩ
IIH, DIA_EN
Input current high-level
2.5
5.0
10.0
µA
0.8
V
DIA_EN
0.8
VDIA_EN = 5 V
V
V
SEL Characteristics
VIL, SEL
Input voltage low-level
VIH, SEL
Input voltage high-level
2
VIHYS, SEL
Input voltage hysteresis
200
350
530
mV
RSEL
Internal pulldown resistor
0.8
1.5
2.5
MΩ
IIH, SEL
Input current high-level
2.5
5.0
10.0
µA
0.8
V
VDIA_EN = 5 V
VDIA_EN = 5 V
V
LATCH PIN CHARACTERISTICS
VIL, LATCH
Input voltage low-level
VIH, LATCH
Input voltage high-level
2
V
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7.5 Electrical Characteristics (continued)
VS = 6 V to 36 V, VDD = 3.0 V to 3.6 V, TJ = -40°C to 125°C (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
Input voltage hysteresis
200
350
530
mV
RLATCH
Internal pulldown resistor
0.8
1.5
2.5
MΩ
IIH, LATCH
Input current high-level
2.5
5.0
10.0
µA
VIHYS,
LATCH
(1)
(2)
TEST CONDITIONS
VLATCH = 5 V
The maximum current output under overload condition before current limiting occurs.
SEL must be set to select the relevant channel. Diagnostics are performed on Channel 1 when SEL = 0 and diagnostics are performed
on channel 2 when SEL =1
7.6 SNS Timing Characteristics
VS = 6 V to 36 V, TJ = -40°C to +125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SNS TIMING - CURRENT SENSE
tSNSION1
Settling time from rising edge of DIA_EN
50% of VDIA_EN to 95% of settled ISNS
VENx = 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, IL = 2 A
30
µs
tSNSION1
Settling time from rising edge of DIA_EN
50% of VDIA_EN to 95% of settled ISNS
VENx = 5 V, VDIA_EN = 0 V to 5 V
RSNS = 1 kΩ, IL = 100 mA
60
µs
tSNSION2
Settling time from rising edge of EN and
DIA_EN
50% of VDIA_EN VEN to 95% of settled ISNS
VENx = VDIA_EN = 0 V to 5 V
VS = 24 V, RSNS = 1 kΩ, RL = 12 Ω
85
µs
tSNSION3
Settling time from rising edge of EN with
DIA_EN HI;
50% of VDIA_EN VEN to 95% of settled ISNS
VS=24V VENx = 0 V to 5 V, VDIA_EN =
5 V RSNS = 1 kΩ, IL = 2A
85
µs
tSNSIOFF1
Settling time from falling edge of DIA_EN
VENx = 5 V, VDIA_EN = 5 V to 0 V
RSNS = 1 kΩ, IL = 2 A
20
µs
tSETTLEH
Settling time from rising edge of load step
VEN1 = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 0.8 A to 2 A
20
µs
tSETTLEL
Settling time from falling edge of load step
VENx = 5 V, VDIA_EN = 5 V
RSNS = 1 kΩ, IOUT = 2 A to 0.8 A
20
µs
20
µs
SNS TIMING - MULTIPLEXER
tMUX
VENx = 5V, VDIA_EN = 5 V
Settling time from current sense on CHx to VSEL = 0 V to 5 V
CHy
RSNS = 1 kΩ, IOUT1 = 0.2 A, IOUT2 = 2
A
7.7 Switching Characteristics
VS = 6 V to 36 V, TJ = -40°C to +125°C (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
tDR
CH1 and CH2 Turnon delay time
VS = 24 V, RL = 48 Ω 50% of EN to
10% of VOUT
tDF
CH1 and CH2 Turnoff delay time
VS = 24 V, RL = 48 Ω 50% of EN to
90% of VOUT
25
35
50
µs
SR2R
VOUTx rising slew rate
VS = 24 V, 25% to 75% of VOUT,
RL = 48 Ω
0.45
0.65
1.05
V/µs
SR2F
VOUTx falling slew rate
VS = 24 V, 75% to 25% of VOUT,
RL = 48 Ω
0.5
0.9
1.4
V/µs
fmax
Maximum PWM frequency
1
kHz
tON
CH1 and CH2 Turnon time
VS = 24 V, RL = 48 Ω 50% of EN to
90% of VOUT
tOFF
CH1 and CH2 Turnoff time
VS = 24 V, RL = 48 Ω 50% of EN to
10% of VOUT
12
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10
15
25
µs
25
40
65
µs
40
50
80
µs
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7.7 Switching Characteristics (continued)
VS = 6 V to 36 V, TJ = -40°C to +125°C (unless otherwise noted)
Parameter
Test Conditions
Min
tON - tOFF
CH1 and CH2 Turnon and off
matching
1ms ON time switch enable
pulse VBB = 24 V, RL = 48 Ω
ΔPWM
CH1 and CH2 PWM accuracy average load current
200-µs enable pulse, VS = 24 V, RL =
48 Ω
–12.5
F = fmax
ΔPWM
CH1 and CH2 PWM accuracy average load current
–25
Typ
Max
Unit
0
25
µs
0
12.5
%
100-µs enable pulse, VS = 24 V, RL =
48 Ω
–20
F = fmax
10
%
tON - tOFF
100-µs enable pulse, VS = 24 V, RL =
CH1 Turnon and off timing matching 48 Ω
–40
F = fmax
10
µs
EON
Switching energy losses during
turnon
VS = 24 V, RL = 8 Ω, 1 ms pulse,
VOUT from 10% to 90% of VS
voltage
0.3
0.4
mJ
EOFF
Switching energy losses during
turnoff
VS = 24 V, RL = 8 Ω, 1 ms pulse,
VOUT from 10% to 90% of VS
voltage
0.25
0.35
mJ
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7.8 Typical Characteristics
Iq_VDD vs. Temperature
2.1
1.15
1.95
1.1
1.8
Iq (mA)
Iq (mA)
Iq_VS vs. Temperature
1.2
1.05
1
1.5
VS voltage
24 V
30 V
0.95
-50
-25
0
25
50
Temperature (oC)
VDD = 3.3 V
ROUT = open
75
100
VEN = 3.3 V
1.65
VDD voltage
5V
3.3 V
1.35
-50
125
VDIA_EN = 0 V
Figure 7-1. Quiescent Current (IQ_VS_DS) From VS
Input Supply vs Temperature
-25
0
25
50
Temperature (oC)
VS = 24 V
ROUT = open
75
100
VEN = 5 V
125
VDIA_EN = 0 V
Figure 7-2. Quiescent Current (IQ_VDD_DS) From
VDD Input Supply vs Temperature
RON vs. Temperature
80
RON (m)
70
60
50
40
VS voltage
24 V
30 V
30
-50
VDD = 0 V
ROUT = open
VEN = 5 V
VDIA_EN = 0 V
Figure 7-3. Quiescent Current (IQ_VS_SS) From VS
Input Supply vs Temperature
72
64
70
75
100
VEN = 5 V
125
VDIA_EN = 0 V
68
66
60
64
58
62
56
60
TOFF (s)
TON (s)
25
50
Temperature (oC)
Figure 7-4. On Resistance (RON) vs Temperature
62
54
52
50
58
56
54
52
50
48
48
46
46
44
VS Voltage
24 V
36 V
42
-20
0
VS = 24 V
ROUT = 48 Ω
20
40
60
Temperature (oC)
80
VEN = 0 V to 5 V
100
120
140
VDIA_EN = 0 V
Figure 7-5. Turn-on Time (tON) vs Temperature
14
0
IOUT = 200 mA
66
40
-40
-25
VS Voltage
24 V
36 V
44
42
40
-40
-20
0
VS = 24 V
ROUT = 48 Ω
20
40
60
Temperature (oC)
80
VEN = 0 V to 5 V
100
120
140
VDIA_EN = 0 V
Figure 7-6. Turn-off Time (tOFF) vs Temperature
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5
1.8
3
1.75
2
1.7
1.65
1
VIH
1.6
VIH, VIL (V)
0.7
0.5
ISNS (mA)
VIH
VIL
0.3
0.2
0.1
1.55
1.5
1.45
1.4
1.35
0.07
0.05
VIL
1.3
Temperature
−40C
25C
85C
125C
0.03
0.02
0.01
0.02 0.03
0.05 0.07 0.1
0.2
0.3 0.40.5 0.7
1
2
3
4 5
Load Current
VS = 24 V, 30 V
RSNS = 1 kΩ
VEN = 5 V
VDIA_EN = 5 V
1.25
1.2
1.15
-40
-20
0
VS = 24 V
20
40
60
Temperature (oC)
80
VDIA_EN = 0 V
100
120
140
ROUT = 1 kΩ
Figure 7-8. VIH, VIL vs Temperature
Figure 7-7. Current Sense Output Current (ISNSI) vs
Load Current (IOUT) Across Temperature
VEN = 0 V to 5 V
VS = 24 V
ROUT = 10 Ω
Figure 7-9. Turn-on Time (TON)
VEN = VDIAG_EN = 0
V to 5 V
VS = 24 V
ROUT = 10 Ω
Figure 7-11. ISNS Settling Time on DIA_EN
Transition
VEN = 5 V to 0 V
VS = 24 V
ROUT = 10 Ω
Figure 7-10. Turn-off Time (TOFF)
VEN = 5 V
VDIAG_EN = 5 V
IOUT1 = 0.5 A to 2 A
Figure 7-12. ISNS Settling Time on Rising Load Step
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8 Parameter Measurement Information
IDD
ILATCH
IEN1
VOUT1
VDD
VOUT2
LATCH
SEL
EN1
SNS
EN2
ILIM1
DIA_EN
ILIM2
FLT
ILIMD
IOUT2
IOUT2
ISEL
ISNS
IILIM1
IGND
VFL T
V ILIMD
GND
VOUT2
VSE L
V SNS
IILIMD
V ILIM1
IILIM2
V ILIM2
IFLT
V DIA_EN
VEN2
IDIA_EN
VEN1
VLATCH
VDD
VS
IEN2
VS
VOUT2
IS
Figure 8-1. Parameter Definitions
VEN(1)
50%
50%
90%
90%
tDR
tDF
VOUT
10%
10%
tON
A.
tOFF
Rise and fall time of VEN is 100 ns.
Figure 8-2. Switching Characteristics Definitions
16
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VEN1
VDIA_EN
IOUT1
ISNS
tSNSION1
tSNSION2
tSETTLEH
tSETTLEL
tSNSION3
tSNSIOFF1
VEN1
VDIA_EN
IOUT1
ISNS
Rise and fall times of control signals are 100 ns. Control signals include: EN, DIA_EN, SEL
SEL pin must be set to the appropriate value.
Figure 8-3. SNS Timing Characteristics Definitions
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9 Detailed Description
9.1 Overview
The TPS272C45 device is a dual channel 45-mΩ smart high-side switch that is intended to provide protection
for output ports in 24-V Industrial systems. The device is designed to drive a variety of resistive, inductive and
capacitive loads. The device integrates various protection features including overload protection through current
limiting, thermal protection, and short-circuit protection. For more details on the protection features, refer to the
Feature Description and Application Information sections of the document.
In addition, the device diagnostics features include the analog SNS output that is capable of providing a signal
proportional to the load current flowing through the switch or constant high current as a fault indication. The
high-accuracy load current sense allows for integration of load diagnostic features that can enable predictive
maintenance for the system by watching for leading indicators of load failures. The device also integrates open
load detection to enable protection against wire breaks. In addition, the device includes a single open drain FLT
pin output (version A, B, C) and dual FLT pin outputs (version D) that indicate device fault states such as short to
GND, short to supply, or overtemperature.
The TPS272C45 is one device in TI's industrial high side switch family. For each device, the part number
indicates elements of the device behavior. Figure 9-1 explains the device nomenclature.
TPS
27
2
C
45
40 V Industrial
High Side Switch
28
60 V Industrial
High Side Switch
RHFR
Package Designator
Prefix
27
X
Device Version
S
Single Channel
2
Dual Channel
4
Quad Channel
RON (mΩ)
Generation
Figure 9-1. Naming Convention
18
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9.2 Functional Block Diagram
VS
UV/OV
Detection
Internal Power
Supply
FET Vds Clamp
GND
GND
VDD
EN1
VOUT1
Gate Driver
EN2
Power FET
Power FET
Channel 1/2
Channel 1/2
LATCH
VOUT2
ILIM1
Current Limit
ILIM2
Thermal
Shutdown
ILIMD
FLT
DIA_EN
SEL
Open-load
detection
Fault Indication
SNS
SNS Mux
Current Sense
9.3 Feature Description
9.3.1 Programmable Current Limit
The TPS272C45 integrates a dual stage adjustable current limit. For the most efficient and reliable output
protection, the current limit can be set as close to the DC current level as possible. Sometimes, systems require
high inrush current handling as well (example incandescent lamp and capacitive loads). By integrating a dual
stage current limit, the TPS272C45 enables robust DC current limiting while still allowing flexible inrush handling.
With the adjustable current limit feature, a lower current limit setting can reduce the fault energy and the output
current during a load failure event such as a short-circuit or a partial load short (soft-short). By lowering fault
energy and current, the overall system improves through:
•
•
•
•
Reduced size and cost in current carrying components such as PCB traces and module connectors
Less disturbance at the power supply (VS pin) during a short circuit event
Less additional budget for the power supply to account for overload currents in one channel or more
Improved protection of the downstream load
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9.3.1.1 Inrush Current Handling
The TPS272C45 uses a resistor from the following pins to the IC GND to configure the current limit behavior:
ILIM1, ILIM2, and ILIMD. The ILIM1 and ILIM2 pin resistors set the current limit thresholds for CH1 and CH2
respectively while ILIMD pin resistor sets a delay time for the device to operate in a higher or lower current limit
during device start-up or output turn-on by retry after a fault (thermal) shutdown).
24-V Power Supply
5-V/3.3-V Power
Supply (Optional)
VS
VOUT1
VDD
ILIM1
VOUT2
ILIM2
RILIM1
RILIM2
ILIMD
GND
RILIMD
Load 1
Load 2
Figure 9-2. Current Limit Set Functionality
The ILIM1/ILIM2 thresholds and the ILIMD pin resistor controlled timing enable flexible inrush current control
behavior. The following table shows the various options available.
Table 9-1. Inrush Current Limit Options
Case
Number
ILIMD Resistor Inrush Delay Time Current Limit During
Settings
(ms)
Inrush Duration
1
Short to GND
2
Discrete resistor
values
(See table
below)
3
At the level set by
ILIM1/2 resistor
0
Programmable in
discrete steps
2- 18
40.2 kΩ +/–2%
Fixed 30
Notes
The device shows constant current limit threshold in each
channel at all times set by the ILIM1/2 resistors.
The current is set higher during the duration of the inrush
Current limit at 2
delay to support high inrush current loads like incandescent
times the level set by lamps. See figure (case 1) showing current limit behavior
ILIM1/2 resistor
enabling into a short circuit with ILIM1/2 threshold set at 2.2
A.
Current limit fixed at
1.5-A threshold for
Vds > 16 V, or at the
level set by ILIM1/2
resistor if Vds < 16 V
Additional feature to limit the current and power dissipation
during initial phase of charging large power supply capacitor
loads. The Vds dependence of current limit exists only
during the duration set by the ILIMD resistor.
If the ILIMD resistor is not connected (floating) or > 40.2 kΩ,
the inrush current limit behavior defaults to Case 3.
Table 9-2. Delay Resistor Values
20
ILIMD Resistor Value
Delay
3.48 kΩ
2 ms
7.15 kΩ
4 ms
12.1 kΩ
6 ms
17.8 kΩ
10 ms
24.9 kΩ
18 ms
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IOUT (A)
2 x ICL
ICL
Time (S)
EN (V)
VEN
Note: tDELAY set by ILIMD
Time (S)
tDELAY
Figure 9-3. Inrush Current Control (Case 2) With a Shorted Load
IOUT
1xILIM
(e.g. 2.2A)
1.5A
EN
Note : tDELAY = 30ms
tDELAY
Figure 9-4. Inrush Current Control (Case 3) With a Shorted Load
For the Case 2, when the ENx pin goes high to turn on one of the channels (or the channel is turned on
automatically to retry after a fault shutdwon), the device defaults to twice current limit threshold as determined
by RILIM1/RILIM2 or the maximum internal current limit level (whichever is lower). The internal current limit level
is defined in the Specifications section of this document. After a TDELAY period that is determined by RILIMD, the
current limit changes to the threshold determined by RILIM1/RILIM2. The delay can be set in the range from 0 (the
current limit threshold at all times set to that determined by RILIM1/RILIM2) to a maximum of 22 ms in dscrete
steps.
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Each channel operates independently with current limit thresholds controlled by RILIM1 and RILIM2(so both
channels can have separate current limit thresholds). If channel 2 is enabled after channel one, channel 2 has its
own separate timing.
The initial inrush current period when the current limit is higher enables two different system advantages when
driving loads
• Enables higher load current to be supported for a period of time of the order of milliseconds to drive high
inrush current loads like incandescent bulb loads.
• Enables fast capacitive load charging. In some situations, it is ideal to charge capacitive loads at a higher
current than the DC current to ensure quick supply bring up. This architecture allows a module to quickly
charge a capacitive load using the initial higher inrush current limit and then use a lower current limit to
reliably protect the module under overload or short circuit conditions.
While in current limiting mode, at any level, the device has a high power dissipation. If the FET temperature
exceeds the over-temperature shutdown threshold, the device turns off just the channel that is overloaded. After
cooling down, the device either latches off or re-tries, depending on the state of the LATCH pin. If the device is
turning off prematurely on start-up, TI recommends to improve the PCB thermal layout, lower the current limit to
lower power dissipation, or decrease the inrush current (capacitive loading).
9.3.1.2 Calculating RILIMx
To set the current limit thresholds, connect resistors from both ILIM1 and ILIM2 pins to GND. The current limit
threshold for each channel is determined by Equation 1 (RILIMx in kΩ):
ICL = KCL / RILIMx
(1)
The nominal KCL value to be used in the calculation is 20.5 A.kΩ. The allowed RILIMx range is between 5 kΩ
and 28.2 kΩ. If either pin is floating, grounded, or outside of the range specified, the current limit defaults to an
internal level that is defined in the Specifications section of this document.
9.3.1.3 Configuring ILIMx From an MCU
In many situations, modules like to allow the current limit to be set programmatically from an MCU. This action
enables a module to set current limits to fit the load after determining what load is plugged in. As described, the
TPS272C45 current limits are set by RILIMx. However, the RILIMx that is seen by the device can be configured
through small external FETs as shown in Figure 9-5.
24-V Power Supply
5-V/3.3-V Power
Supply (Optional)
VS
VDD
ILIM1
RILIM1_1
RILIM1_2
VOUT1
VOUT2
ILIM2
ILIMD
RILIMD
MCU_IO
GND
MCU_IO
Load 1
Load 2
Figure 9-5. Dynamic ILIMx Control
For example, RILIM1_1 can set the device to 500-mA ILIM while RILIM1_2 can set the device at 2-A ILIM. After
the MCU realizes how much current draw is required by the load, the MCU can drive one of the series FET's
22
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to set the ILIM to be ideal for the specific load. The current limit (ILIM1 and ILIM2) thresholds can be changed
dynamically, but the inrush current limit delay set with the ILIMD resistor cannot be changed after powerup.
The external FET switches used to dynamically adjust the current limit must be chosen with a minimum
capacitance (Coss) from the drain the ground. The total capacitance to PCB ground at the ILMx pins including
from traces must be limited to less than 100 pF.
9.3.2 Low Power Dissipation
There are two primary sources of power dissipation in the TPS272C45:
1. Resistive losses in the primary FET, which are calculated as (ILOAD)2 × RON
2. Controller losses due to quiescent operating current, which are calculated as IQ × VSUPPLY
If ILOAD is significantly more than 1 A, the resistive losses dominates the controller losses and they can be
ignored. However, if ILOAD is less than 1 A, the controller losses comprise a significant portion of the total device
power dissipation. To lower the controller losses, version A of the TPS272C45 introduces a secondary low
voltage supply on pin VDD that can power much of the device functionality. By lowering the controller supply
voltage from 24 V to 3.3 V, the total controller losses decrease significantly. Table 9-3 shows the impact this
second supply can make on the total device power dissipation calculated at a worst case supply voltage of 30
V, without diagnostics enabled. There is an additional contribution to power dissipation from the current sense
circuitry as well as the sensed current out of the SNS pin when diagnostics are enabled. Savings of over 80 mW
per channel in the IC is achieved by powering the device with a separate 3.3-V supply.
Table 9-3. Power Dissipation Calculations
ILOAD
500 mA (both channels)
2 A (both channels)
Version
Resistive Losses
(Maximum, 125°C)
Controller Losses
(Maximum, 125°C)
Total PDISS (Maximum,
125°C)
B
39 mW
211 mW
250 mW
A
39 mW
50 mW
89 mW
B
624 mW
211 mW
735 mW
A
624 mW
50 mW
674 mW
By using version TPS272C45A and providing a 3.3-V supply to the VDD pin, for a 500-mA output module the
worst case device total heating is cut from 250 mW to 89 mW, about a 30% decrease in per channel power
dissipation. This lower power dissipation, in addition to the small size of the TPS272C45, enables modules
that have many low current outputs to shrink the size of their casings without limiting output power distribution
capability. To minimize power dissipation, the VDD supply must be powered by a small DC/DC providing the less
than 5 mA per device. Multiple devices can use one DC/DC converter to limit system costs, as shown in Figure
9-6.
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24-V Power Supply
5-V/3.3-V
DC/DC
VS
VOUT1
VDD
GND
VOUT2
VS
VOUT1
VDD
GND
VOUT2
To Addional
TPS272C45
Figure 9-6. Secondary Low Voltage Supply Schematic
For higher current modules, the resistive losses dominate the total power dissipation and the impact of the
secondary supply is less valuable. For example, Table 9-3 shows that for a 2-A output, providing the secondary
supply lowers the total device dissipation by only 12%. In this case, to lower total system costs, versions with
an internal regulator that need only single supply input can be used. If using versions C or D and the secondary
supply is not useful or available, the VDD pin can be grounded and all current is drawn from the primary supply
with no loss of functionality, but higher power dissipation.
9.3.3 Protection Mechanisms
The TPS272C45 protects the system against load fault events like short circuits, inductive load kickback,
overload events, overvoltage and over-temperature events. This section describes the details for protecting
against each of these fault cases.
There are a number of protection features which, if triggered, causes the switch to automatically disable:
•
•
•
Current limit
Thermal shutdown
DC overvoltage on VS supply above the overvoltage protection threshold, VOVPR
When one of these protections are triggered for either channel, the device enters the FAULT state. In the FAULT
state, the fault indication is available on the FLT pin for an MCU to monitor and react to.
The fault indication is reset and the switch turns back on when all of the below conditions are met:
•
•
24
LATCH pin is low
tRETRY has expired
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All faults are cleared (thermal shutdown, current limit, overvoltage)
9.3.3.1 Short-Circuit Protection
TPS272C45 provides output short-circuit protection to ensure that the device prevents current flow in the event
of a low impedance path to GND, removing the risk of damage or significant supply droop. The device is
specified to protect against short-circuit events regardless of the state of the ILIM pins and or supply voltages up
to 36V and across the entire opeprating temperature range -40 °C 125°C.
Figure 9-7 shows the behavior of the TPS272C45 when the device is enabled into an overload condition and
then recovers to a normal load.
Voltage (V)
VS
VS - VDS
Time (s)
Current (A)
ICL_ENPS
ICL
INOM
dt
Time (s)
Figure 9-7. Enable into Short-Circuit Behavior
Due to the low impedance path, the output current rapidly increases until it hits the current limit threshold. Due to
the response time of the current limiting circuit, the measured maximum current can temporarily exceed the ICL
value defined as ICL_ENPS, before it settles to the current limit regulation value (ICL).
In this state high power is dissipated in the FET, so eventually the internal thermal protection temperature for the
FET is reached and the device safely shuts down. Then if LATCH pin is low the part waits tRETRY amount of time
and turns back on.
Figure 9-8 shows the behavior of the TPS272C45 when a short-circuit occurs when the device is in the on-state
and already outputting current. When the internal pass FET is fully enabled, the current clamping settling time
is slower so to ensure overshoot is limit, the device implements a fast trip turn-off at a high current threshold
(approximately 40% higher than ICL). When this fast trip threshold is hit, the device shuts off after a delay for a
short period of time before quickly re-enabling and clamping the current to the regulation current limit level (ICL)
after a brief transient overshoot to the higher peak current level. The device then keeps the current clamped at
the regulation current limit until the thermal shutdown temperature is hit and the device safely shuts off.
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Current (A)
ICL_ENPS
ICL
Thermal Shutdown
INOM
tRETRY
Time (s)
Figure 9-8. On-State Short-Circuit Behavior
Overload Behavior shows the behavior of the TPS272C45 when there is a small change in impedance that
sends the load current above the ICL threshold. The current rises to ICL_LIN above the regulation level. Then the
current limit regulation loop kicks in and the current drops to the ICL value.
Current (A)
ICL_ENPS
ICL_LINPK
ICL
INOM
Thermal Shutdown
tRETRY
Time (s)
Figure 9-9. Overload Behavior
In all of these cases, the internal thermal shutdown is safe to hit repetitively. There is no device risk or lifetime
reliability concerns from repeatedly hitting this thermal shutdown level.
9.3.3.1.1 VS During Short-to-Ground
When VOUT is shorted to ground, the module power supply (VS) can see a transient decrease. This decrease is
caused by the sudden increase in current flowing through the cable inductance. For ideal system behavior, TI
recommends that the module maintain VS > 3 V (above the maximum VUVLOF) during VOUT short-to-ground. This
event is typically accomplished by placing bulk capacitance on the power supply node. If VS goes below VUVLOF,
the device can sustain unexpected latch and timing behavior.
9.3.3.2 Inductive Load Demagnetization
When switching off an inductive load, the inductor can impose a negative voltage on the output of the switch.
The TPS272C45 includes voltage clamps between VS and VOUT to limit the voltage across the FETs and
demagnetize load inductance if there is any. The negative voltage applied at the OUT pin drives the discharge of
inductor current. Figure 9-10 shows the device discharging a 40-mH load.
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Figure 9-10. TPS272C45 Inductive Discharge (40 mH)
Single pulse Inductive Discharge Energy (mJ)
The maximum acceptable load inductance is a function of the energy dissipated in the device and therefore the
load current and the inductive load. The maximum energy and the load inductance the device can withstand for
one pulse inductive dissipation at 125°C is shown in Figure 9-11.The device can withstand 50% of this energy
for one million inductive repetitive pulses with a >4-Hz repetitive pulse. If the application parameters exceed this
device limit, use a protection device like a freewheeling diode to dissipate the energy stored in the inductor.
700
650
600
550
500
450
400
350
300
250
200
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Current (A)
Figure 9-11. TPS272C45 Inductive Load Discharge Energy Capability at 125°C
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For more information on driving inductive loads, refer to TI's How to Drive Inductive, Capacitive, and Lighting
Loads With Smart High-Side Switches application report.
9.3.3.3 Thermal Shutdown
The TPS272C45 includes a temperature sensor on the power FET and also within the controller portion of the
device. The device registers a thermal shutdown fault:
•
TJ,FET > TABS
•
TJ,FET - TJ,control > TREL
After the fault is detected, the switch turns off. If TJ,FET passes TABS, the fault is cleared when the switch
temperature decreases by the hysteresis value, THYS. If instead the TREL threshold is exceeded, the fault is
cleared after TRETRY passes.
Each channel shuts down independently in case of a thermal event, as each has its own temperature sensor and
fault reporting.
9.3.3.4 Undervoltage Lockout on VS (UVLO)
The device monitors the supply voltage at the VS pin to prevent unpredicted behaviors in the event that the
supply voltage is too low. When the supply voltage falls down to VUVLOF, the device enters the shut down state
automatically. When the supply rises up to VUVLOR, the device turns back on.
Fault is not indicated on the FLT pin during an UVLO event. During an initial ramp of VVS from 0 V at a ramp
rate slower than 1 V/ms, VENx pins must be held low until VS is above the UVLO threshold. For best operation,
ensure that VS has risen above UVLO before setting the VENx pins to high.
9.3.3.5 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
The device monitors the input supply voltage VVDD (in versions A/C/D with external supply input) to prevent
unpredictable behavior in the event that the supply voltage is too low. When the supply voltage falls down to
VVDD_UVLOF, the device switches operation to the VS (24 V) power supply, but results in increased current draw
from the VS supply input.
9.3.3.6 Power-Up and Power-Down Behavior
All versions of the device power up from the OFF state only when the VS supply input exceeds the VVSUVLOR
threshold (independent of the VDD supply input level). When VS supply is above the threshold, the internal
regulators are enabled, the device version is recognized. The device then enters the standby state. With
versions A, C, and D and using using an external supply on VDD pin - the device will use the internal regulators
until the VDD voltage exceeds VVDD_UVLOR.
In case the VDD power supply is enabled first and the VDD voltage exceeds VVDD_UVLOR before the VS supply is
up and the VS voltage exceeds VSUVLOR, the device remains in the off-state.
The behavior of all versions of the device in case of brown-out or power loss in VS supply is as described in
Undervoltage Lockout on VS (UVLO). For versions A, C, and D if the VDD power supply is lost (VDD supply
voltage falls below VVDD_UVLOR threshold), the device switches over to the internal power supply, the switch
outputs are disabled.
9.3.3.7 Overvoltage Protection (OVPR)
The device monitors the supply voltage VVS to prevent higher voltages from appearing at the output than can
be supported by the load, when the supply voltage is too high. When the supply voltage goes above VVS_OVPR,
the FET is shut down automatically after a deglitch time to prevent short transients or noise from triggering the
protection. When the supply falls below VVS_OVPF, the FET is allowed to turn back on.
9.3.4 Diagnostic Mechanisms
As systems demand more intelligence, it is becoming increasingly important to have robust diagnostics
measuring the conditions of output power. The TPS272C45 integrates many diagnostic features that enable
modules to provide predictive maintenance and intelligence power monitoring to the system.
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9.3.4.1 Current Sense
The SNS output can be used to sense the load current through either channel. The SNS pin outputs a current
that is proportional to the load current through either channel, depending on the state of the SEL pin. This
current is sourced into an external resistor to create a voltage that is proportional to the load current. This
voltage can be measured by an ADC or comparator and used to implement intelligent current monitoring for a
system. To ensure accurate sensing measurement, RSNS must be connected to the same ground potential as the
μC ADC.
The SNS pin output is controlled by the SEL pin. If SEL pin is low, SNS outputs load current proportional to
channel 1, whereas if SEL is high SNS outputs load current proportional to channel 2.
Equation 3 shows the transfer function for calculating the load current from the SNS pin current.
ISNSI = IOUT / KSNS
(2)
KSNS is defined in the Specifications section.
9.3.4.1.1 RSNS Value
The following factors must be considered when selecting the RSNS value:
•
•
•
•
Current sense ratio (KSNS)
Largest and smallest diagnosable load current required for application operation
Full-scale voltage of the ADC
Resolution of the ADC
For an example of selecting RSNS value, reference RISNS Calculation in the applications section of this data
sheet.
9.3.4.1.1.1 Current Sense Output Filter
To achieve the most accurate current sense value, TI recommends to filter the SNS output. There are two
methods of filtering:
•
•
Low-Pass RC filter between the SNS pin and the ADC input. This filter is illustrated in Figure 10-1 with
typical values for the resistor and capacitor. The designer must select a CSNS capacitor value based on
system requirements. A larger value provides improved filtering but a smaller value allows for faster transient
response.
The ADC and microcontroller can also be used for filtering. TI recommends that the ADC collects several
measurements of the SNS output. The median value of this data set must be considered as the most
accurate result. By performing this median calculation, the microcontroller can filter out any noise or outlier
data.
9.3.4.2 Fault Indication
The following faults are registered on the FLTx pin:
•
•
•
•
FET thermal shutdown
Active current regulation
Thermal Shutdown caused by current limitation
Open-load (FET OFF state only)
Open-load or short-to-supply are not indicated while the switch is enabled, although in on-state these conditions
can still be detected through the sensed current (ISNS current). Hence, if there is a fault indication while the
channel is enabled, then it must be either due to an overcurrent or overtemperature event. On the other hand, a
fault indication while the output (FET) is disabled must be either due to an open load or output short-to-supply.
In versions A, B, C of the device, the open drain FLT pin output is a global fault output. FLT pin indicates a fault
when one occurs in either channel. The FLT signal can be deactivated by toggling the EN input of the faulted
channel and sequential toggling of ENx inputs can be used to determine the faulted channel. In versions A, B, C
of the device the SNS pin also indicates the fault status of the channel, provided the faulted channel is selected
with the SEL pin.
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In version D of the device, there are two (FLT1 and FLT2) pin outputs corresponding the presence of a fault in
each channel. The independent FLTx signals can be used to easily determine the faulted channel. The FLTx
signal is deactivated by toggling the EN input of the faulted channel. In version D of the device the SNS pin does
not indicate the fault status of the channel, just the load current sense.
Table 9-4 shows the states for both the SNS pin and the FLT pins based on the fault states and ENx/SEL pin
state (applies to versions A, B, C). By looking at these pins, it is possible to detect where the fault has occurred.
The method to identify the channel that caused the FLT signal is as follows when an MCU is monitoring the SNS
pin output. If the SNS is signaling a fault (with ISNSFH current output) while SEL=LO, then the fault is in channel
1, whereas with SEL=HI, the fault is in channel 2. If SNS pin signals fault with SEL at either LO or HI, then
both channels are faulted. As discussed earlier, the type of faults (whether it is overcurrent, overtemperature or
open-load) can be determined by the state of EN input in each channel. If the SNS pin output is not monitored, it
is still possible to identify the channel that is faulted. To do this, the EN pin in each channel must be toggled (LO
to HI or HI to LO as the case can be). If the fault indication on the FLT pin is removed by toggling the EN input
in a channel, then the fault is in that channel. If the fault indication does not go away with toggling EN input of
both channels, then the fault is in both. The time duration for toggling the EN input must be kept below 10 us to
ensure that there is no impact on the actual output of the channels.
Table 9-4. Device Fault Mux (Versions A, B, C)
INPUTS
CH1 FAULT
CH2 FAULT
SNS
FLT
0
0
0
CH1 load current
High
0
0
1
CH1 load current
Low
0
1
0
Corresponds to fault
case(1)
Low
0
1
1
Corresponds to fault
case(1)
Low
1
0
0
CH2 load current
High
Corresponds to fault
case(1)
Low
1
0
1
1
1
0
CH2 load current
Low
1
Corresponds to fault
case(1)
Low
1
(1)
OUTPUTS
SEL
1
Table 9-5 describes this behavior
While typically the SNS pin output corresponds to ILOAD, in a fault case the switch turns off and ILOAD goes to
zero so the SNS behavior is modified in a fault case. In the event of a fault cases where SEL is monitoring the
proper channel, the SNS pin outputs a voltage level corresponding to the fault type to enable improved diagnosis
as shown in Table 9-5.
By looking at the combination of the ENx condition, FLT , and SNS pins, it is possible to distinguish between fault
states. Each channel has independent fault states, so the table below applies to CH1 when SEL = LO and CH2
when SEL = HI.
Table 9-5. Distinguishing Different Fault Cases (Versions A, B, C)
Channel State
Enabled
Disabled
30
Fault Case
SNS
FLT
Regulating current past the initial inrush delay
set by ILIMD resistor
ISNSFH
Low
Short-to-supply/open-load
0
High
TJ overtemperature
ISNSFH
Low
Short-to-supply/open-load
ISNSFH
Low
TJ overtemperature
0
High
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In version D of the device the fault table is shown in Table 9-6. By looking at these pins, it is possible to
detect which channel the fault has occurred. As discussed earlier, the type of faults (whether it is overcurrent,
overtemperature or open_load) can be determined by the state of EN input in each channel.
Table 9-6. Device Fault Mux (Version D)
INPUTS
OUTPUTS
CH1 FAULT
CH2 FAULT
FLT1
FLT2
0
0
High
High
0
1
High
Low
1
0
Low
High
1
1
Low
Low
9.3.4.2.1 Fault Event Diagrams
Note
All timing diagrams assume that the SEL pin is low to measure channel one behavior on the SNS pin.
DIA_EN and SEL pins have no effect on the FLT (versions A, B, C) or FLT1, FLT2 (version D) pin
output.
The LATCH, SEL, DIA_EN, and ENx pins are controlled by the user. The timing diagrams represent
possible use-cases.
Figure 9-12 shows the device fault reporting behavior in the event of a fault in channel 2 (only) with LATCH and
SEL pin set to LO. As shown, the fault signaling is deactivated when EN is toggled (in this case from HI to LO to
HI). The faulted channel can be determined by toggling the EN pin with a short pulse (less than 10-us wide) that
does not affect the output of the channel.
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CH2_FAULT
FAULT
t
EN2
t
FLT
t
Figure 9-12. FLT Pin Behavior (Versions A, B, C)
Figure 9-13 shows the device fault reporting behavior in the event of an overcurrent fault when EN goes high. As
shown, the fault signaling is active only after the initial inrush current limit phase is complete.
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IOUTx
2xICL
1xICL
FLT
T_delay
t
t
ENx
t
Figure 9-13. FLT Pin Behavior With an Overcurrent Event On Channel Enable (Versions A, B,C)
Figure 9-14 shows the device fault and retry behavior when there is a slow creep into an overcurrent event. As
shown, the switch clamps the current until it hits thermal shutdown, and then the device remains latched off until
the LATCH pin is low.
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FLT
µC
resets
the latch
LATCH
DIA_EN
SNS
High-z
Current
SNS
SNS signals
over-current
FLT
High-z
High-z
Current
SNS
High-z
VOUTx
EN high throughout
ENx
TABS
THYS
TJ
tRETRY
ICL
IOUTx
t
Load reaches limit. Current is
limited. Temp reaches limit.
Switch is disabled. Temp
decreases by THYS, but
waits for LATCH
Switch follows ENx.
Normal operation.
Figure 9-14. Current Limit – Latched Behavior
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Figure 9-15 shows the behavior with LATCH tied to GND; hence, the switch retries after the fault is cleared and
tRETRY has expired.
Signaling
FLT
FLT
DIA_EN
SNS
High-z
Current
Sense
High-z
SNS signals
over-current
High-z
Current
Sense
High-z
VOUTx
EN stays high throughout
ENx
TABS
THYS
TJ
tRETRY
ICL
IOUTx
t
Load reaches limit.
Current is limited. Temp
reaches limit.
Switch is disabled. TJ
decreases by THYS
Switch follows ENx.
Normal operation.
Figure 9-15. Current Limit – LATCH = 0
When the switch retries after a shutdown event, the fault indication remains until VOUTx has risen to VVS – 1.8 V.
After VOUTx has risen, the FLT output is reset and current sensing is available. If there is a short-to-ground and
VOUT is not able to rise, the SNS fault indication remains indefinitely. Figure 9-16 illustrates auto-retry behavior
and provides a zoomed-in view of the fault indication during retry.
Note
Figure 9-16 assumes that tRETRY has expired by the time that TJ reaches the hysteresis threshold.
LATCH = LO and DIA_EN = HI
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FLT
SNS signals
over-current
SNS signals
over-current
SNS signals
over-current
SNS signals
over-current
SNS
VOUT
EN
TABS
THYS
TJ
t
FLT
SNS signals over-current
Current Sense
SNS
VS – 1.8 V
VOUT
EN
TABS
THYS
TJ
t
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Figure 9-16. Fault Indication During Retry
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9.3.4.3 Short-to-Supply or Open-Load Detection
The TPS272C45 is capable of detecting short-to-supply and open-load events regardless of whether the switch
is turned on or off, however the two conditions use different methods to signify fault. This feature enables
systems to recognize mis-wiring or wire-break events.
9.3.4.3.1 Detection With Switch Enabled
When the switch is enabled, the short-to-supply and open-load conditions are detected through the current
sense feature. In both cases, the load current drops from the nominal value and instead be measured as close to
zero. By measuring load current through the SNS pin, this state can be recognized.
9.3.4.3.2 Detection With Switch Disabled
While the switch is disabled and DIA_EN high, an internal comparator watches the condition of VOUT. The
TPS272C45 includes a nominally 150-kΩ pull-up resistor from OUT pin to VS pin in series with a switch
controlled by the DIA_EN signal. So, if the load is disconnected (open load condition) or there is a short to
supply the VOUT voltage is pulled towards VVS. In either of these events, the internal comparator measures VOUT
as higher than the open load threshold (VOL,off) and a fault is indicated on the FLT pin (Version A) or FLTx pins
(Version D) and on the SNS pin (only for versions A, B, C). No external component is required in most cases,
however if there is a pull-down resistor to GND on VOUT, an additional external pull-up resistor can be necessary
to bias VOUT appropriately.
Open load fault signaling on the SNS and the internal pull-up on OUT is enabled only if DIA_EN is set HI. To
detect open-load threshold at higher pull-down load current, an external pull-up resistor (and potentially a switch)
can be needed.
While the switch is disabled, the fault indication mechanisms continuously represent the present status.
For example, if VOUT decreases from greater than VOL_off to less than VOL_off, the fault indication is reset.
Additionally, the fault indication is reset upon the falling edge of DIA_EN (for SNS pin) or the rising edge of EN.
VS
An_ol_fault
V(OL,off)
OUT
TPS272C45
RL
FLT
Rpu_ext
Rpu
Digital
GND
Figure 9-17. Open-Load Detection Circuit
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FLT
DIA_EN
SNS goes to ISNSFH
to indicate OpenLoad FLT
High-z
SNS
High-z
tOL2
Enabled
VOL
VOUT
EN
t
Open-Load occurs
Switch is disabled
and the condition is
determined by the
internal comparator.
The open-load fault is
indicated.
SNS output is
disabled
Copyright © 2019, Texas Instruments Incorporated
Figure 9-18. Open-Load Detection Timing
9.3.4.4 Current Sense Resistor Sharing
Multiple high-side devices can use the same RSNS as shown in Figure 9-19. This action reduces the total number
of passive components in the system and the number of ADC terminals that are required of the microcontroller.
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Microcontroller
GPIO
DIA_EN
Switch 1
SNS
GPIO
DIA_EN
Switch 2
SNS
GPIO
DIA_EN
Switch 3
SNS
GPIO
DIA_EN
Switch 4
SNS
ADC
RPROT
CSNS
RSNS
Figure 9-19. Sharing RSNS Among Multiple Devices
9.4 Device Functional Modes
During typical operation, the TPS272C45 can operate in a number of states that are described below.
9.4.1 Off
OFF state occurs when the device is not powered.
9.4.2 Diagnostic
DIAGNOSTIC state occurs with DIA_EN is high but ENx are both low. The switch can be used to perform
diagnostics like off-state open-load detection in this state.
9.4.3 Active
In ACTIVE state, the switch is enabled with ENx high. The diagnostic functions like current sense can be either
on or off during ACTIVE state.
9.4.4 Fault
The FAULT state is entered if a fault shutdown occurs (thermal shutdown or current limit). After all faults are
cleared, the LATCH pin is low, and the retry timer has expired, the device transitions out of FAULT state. If the
EN pin is high, the switch re-enables. If the EN pin is low, the switch remains off.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
Figure 10-1 shows the schematic of a typical application of the TPS272C45. The schematic includes all standard
external components. This section of the data sheet discusses the considerations in implementing commonly
required application functionality.
If reverse polarity can be applied to the VS supply voltage input, the ground network protection circuit must be
added. The diode prevents the reverse current flow from the GND pin to supply. An additional resistor of 10
ohms or less is added to reduce the current flow if the VS to GND voltage rating is exceeded during any surge
conditions. TI recommends the 1-K resistor in parallel to keep the GND potential close to the board GND under
conditions where the ground network diode can be reverse biased.
VDD
CVDD
VS
CVIN1
CVIN2
VS
VDD
DIA_EN
GND
SEL
RFLT
Optional
Reverse
Polarity
Protection
FLT
EN1
EN2
I/O Source
RILIMD
ILIMD
Load
VOUT1
RILIM1
ILIM1
RILIM2
COUT
ILIM2
Load
VOUT2
COUT
SNS
ADC
RPROT
RSNS
CSNS
Copyright © 2019, Texas Instruments Incorporated
Figure 10-1. System Diagram
40
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Table 10-1. Recommended External Components
COMPONENT
TYPICAL VALUE
RSNS
1 kΩ
Translate the sense current into sense voltage.
PURPOSE
RPROT
10 kΩ
Low-pass RC filter resitance and protection for the ADC input.
Low-pass filter capacitance for the ADC input.
CSNS
100 pF
RILIMx
5 kΩ to 40 kΩ
CVin1
4.7 nF to Device GND
Filtering of voltage transients (for example, ESD, IEC 61000-4-5) and improved
emissions.
CVin2
100 nF to Module GND
Stabilize the input supply and filter out low frequency noise.
CVDD
2.2 uF to Module GND
Stabilize the input supply and limit supply excursions.
Set current limit threshold, connect from pin to IC GND.
COUT
22 nF
ZTVS
36-V TVS
Filtering of voltage transients (for example, ESD, RF transients)
DGND, ZGND
Diode + < 10 ohm from
Device GND to Module
GND
Clamp surge voltages at the supply input.
Optional for reverse polarity protection if needed.
10.1.1 IEC 61000-4-5 Surge
The TPS272C45 is designed to survive against IEC 61000-4-5 surge using external TVS clamps. The device
is rated to 48 V ensuring that external TVS diodes can clamp below the rated maximum voltage of the
TPS272C45. Above 48 V, the device includes VDS clamps to help shunt current and ensure that the device
survives the transient pulses. Depending on the class of the output, TI recommends that the system has a
SMBJ36A or SMCJ36A between VS and module GND.
10.1.2 Inverse Current
Inverse current occurs when 0 V < VVS < VOUT. In this case, current can flow from VOUT to VS. Inverse current
cannot be caused by a purely resistive load. However, a capacitive or inductive load can cause inverse current.
For example, if there is a significant amount of load capacitance and the VS node has a transient droop, VOUT
can be greater than VS.
The TPS272C45 does not detect inverse current. When the switch is enabled, inverse current passes through
the switch. When the switch is disabled, inverse current can pass through the MOSFET body diode. The device
continues operating in the normal manner during an inverse current event.
10.1.3 Loss of GND
The ground connection can be lost either on the device level or on the module level. If the ground connection is
lost, both the channel outputs are disabled irrespective of the EN input level. If the switch was already disabled
when the ground connection was lost, the outputs remain disabled even when the channels are enabled. The
steady state current from the output to the load that remains connected to the system ground is below the
level specified in the Specifications section of this document. When the ground is reconnected, normal operation
resumes.
10.1.4 Paralleling Channels
If an application requires lower power dissipation than is possible with a 45-mΩ switch, the TPS272C45 can
have both channel outputs and ENx pins tied together to function as a single 22.5-mΩ high side switch. In this
case, there is some decrease in ISNS and ILIM accuracy, however the device functions properly.
10.1.5 Thermal Information
When outputting current, the TPS272C45 heats up due to the power dissipation. The transient thermal
impedance curve can be used to determine the device temperature during a pulse current of a given duration
(time). This ZθJA value here corresponds to a JEDEC standard 2s2p thermal test PCB with no thermal vias.
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60
50
Zth_ja (oC/W)
40
30
20
10
0
1E-5
0.0001
0.001
0.01
0.1
0.5
2 3 5 10 20
100
1000
time (s)
Figure 10-2. TPS272C45 Transient Thermal Impedance
42
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10.2 Typical Application
This application example demonstrates how the TPS272C45 device can be used as output switches in a digital
output module. In this example, consider an 8-channel module with a maximum output current capability of 2 A
per channel.
Backplane
Power
24-V Field
Power
V+
TPS272C45
VS
VDD
Charge
Pump
Output
Clamp
Gate
drive
VOUT
MON
VOUT 1
VOUT 2
Fault and Protection
EN
FLT
SEL
DIA_EN
A0
A1
Current
Sense/
FAULT
SNS
VSNS
GND
VS
VOUT
4
TPS272C45
A6
2
GND
A7
To Additional
Channels
Figure 10-3. Block Diagram for PLC Digital Output Module
10.2.1 Design Requirements
For this design example, use the input parameters shown in Table 10-2.
Table 10-2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VS
24 V +/–20%
Load
2-A maximum DC
Load type
Resistive, Inductive, Capacitive
Load current sense
Maximum of 2.4 A
Regulation current limit (ILIM)
2.6-A typical
Ambient temperature
70°C
Device version
A
10.2.2 Detailed Design Procedure
10.2.2.1 RILIM Calculation
In this application, the TPS272C45 must allow for the maximum DC current with margin but minimize the energy
in the switch and the load on the input supply during a fault condition by minimizing the current limit.
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The nominal current limit must be set such that the worst case (lowest) current limit is higher than the maximum
load current (2 A). Because the lower limit is 23% below the typical value, for this application, the best ILIM set
point is approximately 2.6 A for both channels. The below equation allows you to calculate the RILIM value that is
placed from the ILIMx pins to GND pin of the device. RILIM is calculated in kΩ.
RILIM = KCL / ICL
(3)
The KCL value in the Specifications section is 20.5 A × kΩ. So the calculated value of RILIM closest 2% resistor is
7.87 kΩ.
10.2.2.2 Diagnostics
If the load is disconnected due a break in the connecting wire, an alert is desired. Open-load detection can be
performed in the switch-enabled state with the current sense feature of the TPS272C45 device. Similarly in the
off-state, a check for wire break can be performed. Under open load condition, with the DIA_EN set high, the
current in the SNS pin is the fault current and the can be detected from the sense voltage measurement.
10.2.2.2.1 Selecting the RISNS Value
Table 10-3 shows the requirements for the load current sense in this application. The KSNS value is specified for
the device and can be found in the Specifications section.
Table 10-3. RSNS Calculation Parameters
PARAMETER
EXAMPLE VALUE
Current sense ratio (KSNS)
1200
Largest diagnosable load current
2.4 A
Smallest diagnosable load current
50 mA
Full-scale ADC voltage
5V
ADC resolution
10 bit
The load current measurement up to 2.4 A ensures that even in the event of a overcurrent but below the
set current limit, the MCU can register and react by turning off the FET while the low level of 50 mA allows
for accurate measurement of low load currents and enable the distinction open load faults from nominal load
currents.
The RSNS resistor value can be selected such that the largest diagnosable load current puts the SNS pin
voltage (VSNS) less than the ADC full-scale. With this design, any ADC value that shows full scale (FS) can be
considered a fault. Additionally, the RSNS resistor value must ensure that the smallest diagnosable load current
does not cause VSNS to fall below at a least a few LSB of the ADC. With the given example values, a 2.4-kΩ
sense resistor satisfies both requirements shown in Table 10-4.
Table 10-4. VSNS Calculation
44
LOAD (A)
SENSE RATIO
ISNS (mA)
RSNS (Ω)
VSNS (V)
% of 5-V ADC
2.4
1200
2.0
2400
4.8
96%
0.024
1200
0.02
2400
0.048
0.96% (9 LSB)
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10.2.3 Application Curves
Upon enabling our device into a capacitive load, TPS272C45 defaults its current limit to 2x ICL for a period of
time programmed set by ILIMD. In the figure below, you can see TPS272C45 charging a 1-mF capacitor using
the inrush current handling feature. During the first 4 mS after enabling the device, IOUT1 is 2 times the icl
programmed (4 A). After, the 4-mS period, the current folds back to the programmed icl (2 A).
Figure 10-4. TPS272C45 Capacitor Charging
If the device has a no-load case due to an open load or wire-break, the device registers the fault even in an
off-state if the DIA_EN pin is high. Figure 10-5 shows the device behavior when an open load event is registered
with EN low and DIAG_EN is raised. Systems can PWM DIA_EN to lower system power losses while still
watching for open load events and the same timing applies.
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Figure 10-5. Open-Load (tOL) Detection Time
If the output of the TPS272C45 is short-circuited, the device protects the system from failure. Depending on
RILIM, the current limit set-point varies. The waveforms below show examples of the current limit behavior when
the device is enabled into a short circuit.
In the Figure 10-6, the output is permanently shorted. Upon enabling the device, the current reaches the 2 times
current limit is enabled for 6 mS set by ILIMD resistor. After the inrush current period, the current is reduced to
the programmed current limit set by RILIM. In this case, because the power dissipation is low enough, the device
is able to constantly act as a current source.
Figure 10-6. Enabling into Short (RILIM = 10 k , VS = 6 V, Delay = 6 mS)
46
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In Figure 10-7, the output is also permanently shorted. Upon enabling the device, the current reaches the 2
times current limit, however because the power dissipation is greater due to the higher input voltage at Vs the
device reaches its thermal shutdown threshold and disables itself before reaching the programmed delay time.
Figure 10-7. Enabling into Short (RILIM = 10 k , VS = 24 V, Delay = 6 mS)
The Figure 10-8 shows that after the device has been enabled into a short and due to the high power dissipation,
the device reaches its thermal shutdown threshold. The device then shuts down the FET for a period of tRETRY
and re-enables the FET into the short. The capture shows the continuous retry cycle and protection because the
short is permanently applied.
Figure 10-8. Permanent Short Behavior (RILIM = 10 k , VS = 24 V, Delay = 6 mS)
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In the event a short is applied to the output while a load is being driven, the device activates its fast trip
comparator and shutdown the output to limit the inrush current. The device then immediately re-enables into
the short and limit the current to the programmed current limit value. The figure below describes the described
behavior.
Figure 10-9. On-State Short circuit (RILIM = 10 k , VS = 24 V )
11 Power Supply Recommendations
The TPS272C45 device is designed to operate in a 24-V industrial system. The allowed supply voltage range
(VS pin) is 6 V to 36 V as measured at the VSpin with respect to the GND pin of the device. In this range
the device meets full parametric specifications as listed in the Electrical Characteristics table. The maximum
continuous operating voltage is 36 V. The device is also designed to withstand voltage transients beyond this
range. The device version A requires an external power supply input in the range 3.0 V to 5.5 V. The C and
D versions of the device have an secondary internal regulator (nominally 3.3 V) but an external supply can be
optionally provided at the VDD pin to lower the power dissipation in the IC. Version B always use an internal
3.3V regulator, so a single 24V supply (VS pin) is sufficient.
Table 11-1. Operating Voltage Range
48
Supply voltage pin
Input Supply Voltage Range
Note
VS
6 V to 36 V
Nominal supply voltage, all parametric
specifications apply. The device is completely
short-circuit protected up to 125°C.
VDD
3.0 to 5.5 V
Required for version A, and optional for
versions C and D. A DC/DC converter supply
reduces the overall power dissipation.
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12 Layout
12.1 Layout Guidelines
To achieve optimal thermal performance, connect the exposed pad to a large copper pour. On the top PCB layer,
the pour can extend beyond the package dimensions as shown in the example below. In addition to this, TI
recommends to also have a GND plane either on one of the internal PCB layers or on the bottom layer.
Vias must connect this plane to the top GND pour.
Ensure that all external components are placed close to the pins. Device current limiting performance can be
harmed if the RILIM is far from the pins and extra parasitics are introduced.
FLT
VS
VS
10
9
8
12
SNS
DIA_EN
SEL
11
12.2 Layout Example
13
LATCH
14
EN2
15
PowerPadTM
7
OUT2
6
OUT2
5
OUT2
EN1
16
4
NC
GND
17
3
OUT1
ILIMD
18
2
OUT1
1
OUT1
21
22
23
24
19
20
VDD
ILIM2
ILIM1
NC
VS
VS
Figure 12-1. Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
•
•
Texas Instruments, Adjustable Current Limit of Smart Power Switches application report
Texas Instruments, How to Drive Inductive, Capacitive, and Lighting Loads With Smart High-Side Switches
application report
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
50
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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16-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS272C45ARHFR
ACTIVE
VQFN
RHF
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
272C45A
Samples
TPS272C45BRHFR
ACTIVE
VQFN
RHF
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
272C45B
Samples
TPS272C45CRHFR
ACTIVE
VQFN
RHF
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
272C45C
Samples
TPS272C45DRHFR
ACTIVE
VQFN
RHF
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
272C45D
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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