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TPS342
SBVS211B – AUGUST 2012 – REVISED APRIL 2015
TPS342x Low-Power, Push-Button Controllers With Configurable Delay
1 Features
3 Description
•
•
•
The TPS3420, TPS3421, and TPS3422 (TPS342x)
are low-current, ultrasmall, push-button reset timers.
These devices use a long timing setup delay to
provide the intended system reset, and avoid resets
from short push-button closures or key presses. This
reset configuration also allows for differentiation
between software interrupts and hard system resets.
1
•
•
•
•
Very Small Package: 1.45-mm × 1.00-mm SON
Operating Range: 1.6 V to 6.5 V
Single (TPS3422) or Dual (TPS3420 and
TPS3421) Push-Button Inputs
Low Supply Current: 250 nA (Typical)
Two-State Logic, User-Selectable Input Delay:
– For Example: 7.5 s and 0 s
– Multiple Timing Options Available
Fixed Time-out Pulse at RST (TPS3421 and
TPS3422): 400 ms (Typical)
– Other Timing Options Available on Request
Active Low, Open-Drain Output
2 Applications
•
•
•
•
•
•
•
Smart Phones
Tablets, Ultrabooks™
Gaming Consoles
Portable Consumers
Navigation Devices
Consumer Medical
Toys
The TPS3420 and TPS3421 monitor two inputs (PB1
and PB2) and output an active-low reset pulse signal
(RST) when both inputs are low for the selected time
delay. For the TPS3421, RST remains low for a
factory-programmed fixed time. For the TPS3420,
RST remains low until one of the PBx inputs is
released. The need for a dedicated reset button is
eliminated because two inputs are used to ensure
reset. The TPS3422 monitors one input (PB1) and
outputs an active-low reset pulse signal (RST) when
PB1 is low for the selected time delay.
The TPS342x have an open-drain output that can be
wire-ORed with other open-drain devices. The
TPS342x operate from 1.6 V to 6.5 V over the –40°C
to +125°C temperature range, and provide a precise,
space-conscious micropower solution for system
resetting needs.
Device Information(1)
PART NUMBER
TPS342x
PACKAGE
USON (6)
BODY SIZE (NOM)
1.45 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TPS3421 Typical Application Diagram
Standby Supply Current vs Supply Voltage
VIN = 1.6 V to 6.5 V
1.4
VCC
PB1
RST
PushButton
Switch
Reset
Microprocessor,
PMU
TPS3421
PB2
TS
PushButton
Switch
GND
Standby Supply Current (µA)
VDD
1.2
±40C
+0C
+25C
+85C
+105C
+125C
1
0.8
0.6
0.4
0.2
GND
0
0
1
2
3
4
VCC (V)
5
6
7
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS342
SBVS211B – AUGUST 2012 – REVISED APRIL 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagrams ..................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Applications ................................................ 13
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2012) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Added Typical to Low supply current bullet in Features list .................................................................................................. 1
•
Added Typical to Fixed time-out pulse bullet in Features list ................................................................................................ 1
•
Changed Pin Configuration and Functions section; updated table format ............................................................................ 3
•
Changed Absolute Maximum Ratings table; added storage temperature range (Tstg) specification ..................................... 4
•
Changed Start-up time to start-up delay, added parametric symbol...................................................................................... 5
Changes from Original (August 2012) to Revision A
•
2
Page
Changed data sheet from product preview to production data .............................................................................................. 1
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5 Pin Configuration and Functions
TPS3420, TPS3421: DRY Package
6-Pin USON
Top View
RST
1
6
PB2
GND
2
5
TS
PB1
3
4
VCC
TPS3422: DRY Package
6-Pin USON
Top View
RST
1
6
TST
GND
2
5
TS
PB1
3
4
VCC
Pin Functions
PIN
NAME
I/O
DESCRIPTION
TPS3420/21
TPS3422
GND
2
2
—
PB1
3
3
I
Push-button input. PB1 and PB2 must be held low for greater than tTIMER time to
assert the reset output.
PB2
6
—
I
Second push-button input. PB1 and PB2 must be held low for greater than tTIMER time
to assert the reset output.
RST
1
1
O
Active low, open-drain output. Reset is asserted (goes low) when both PB1 and PB2
are held low for longer than tTIMER time (only PB1 for TPS3422).
For TPS3420: Reset is deasserted when either PBx input goes high.
For TPS3421,TPS3422: Reset is deasserted after fixed time of tRST.
TS
5
5
I
Time delay selection input. Connect to VCC or GND for different tTIMER selections. In
normal operation, the TS pin state should not be changed because it is intended to be
permanently connected to either GND or VCC. If switching the TS pin is required, it
should be done during power off, or when either PBx input is high.
TST
—
6
—
VCC
4
4
I
Ground.
Connect this pin to GND or VCC during normal device operation.
Supply voltage input. Connect a 1.6-V to 6.5-V supply to VCC to power the device. It is
good analog design practice to place a 0.1-µF ceramic capacitor close to this pin.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
Voltage
Current
Temperature (2)
(1)
(2)
(1)
MIN
MAX
VCC
–0.3
7
UNIT
RST
–0.3
7
PB1, PB2
–0.3
7
TS
–0.3
VCC + 0.3
RST pin
–20
20
Operating junction, TJ
–40
125
Storage, Tstg
–65
150
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
As a result of the low dissipated power in this device, it is assumed that TJ = TA.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC
Input supply voltage
1.6
6.5
V
VTS
TS pin voltage
0
VCC
V
VPB1, VPB2
PB1 and PB2 pin voltage
0
6.5
V
VRST
RST pin voltage
0
6.5
IRST
RST pin current
0.00035
8
V
mA
6.4 Thermal Information
TPS342x
THERMAL METRIC (1)
DRY (USON)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
1185.2
RθJB
Junction-to-board thermal resistance
184.7
ψJT
Junction-to-top characterization parameter
34.9
ψJB
Junction-to-board characterization parameter
182.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance
69.6
(1)
4
322
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
All specifications are over the operating temperature range of –40°C < TJ < 125°C and 1.6 V ≤ VCC ≤ 6.5 V, unless otherwise
noted. Typical values are at TJ = 25°C and VCC = 3.3 V.
PARAMETER
VCC
TEST CONDITIONS
Input supply
MIN
VCC = 3.3 V
TPS3421,
TPS3422
VCC = 3.3 V
TPS3420
Supply current
(active timer) (1)
High-level input
voltage
VIH
Low-level input
voltage
VIL
µA
3.3
µA
nA
350
nA
VCC = 6.5 V, –40°C < TJ < 85°C
1.2
µA
VCC = 6.5 V
3.4
µA
12
TPS3422
PB1, PB2 = 0 V, VCC = 6.5 V
106
136
TPS3421,
TPS3422
PB1, PB2
0.7 VCC
TPS3420
PB1, PB2
0.85
TPS3421,
TPS3422
PB1, PB2
0
0.3 VCC
TPS3420
PB1, PB2
0
0.3
Input current
(PB1, PB2)
(1)
1
6
IPB
65
–50
50
TPS3422
PB1, PB2 = VCC
–50
50
VCC ≥ 4.5 V, ISINK = 8 mA
0.4
VCC ≥ 3.3 V, ISINK = 5 mA
0.3
VCC ≥ 1.6 V, ISINK = 3 mA
0.3
High impedance, V RST = 6.5 V
–0.35
V
kΩ
PB1, PB2 = 0 V or VCC
Open-drain output leakage current
µA
V
TPS3420
TPS3421
Low-level output voltage
Ilkg(OD)
V
PB1, PB2 = 0 V, VCC = 6.5 V
PB1 internal pullup resistance
(TPS3422)
UNIT
6.5
TPS3420,
TPS3421
RPB1
VOL
MAX
250
VCC = 6.5 V, –40°C < TJ < 85°C
VCC = 6.5 V
Supply current
(standby)
ICC
TYP
1.6
0.35
nA
V
µA
Includes current through pullup resistor between input pin (PB1) and supply pin (VCC) for TPS3422.
6.6 Timing Requirements
All specifications are over the operating temperature range of –40°C < TJ < 125°C and 1.6 V ≤ VCC ≤ 6.5 V, unless otherwise
noted. Typical values are at TJ = 25°C and VCC = 3.3 V.
MIN
TYP
–20%
tTIMER
Push-button timer
(1)
6
7.5
9
TPS3420D: TS = VCC
10
12.5
15
6
7.5
9
TPS3421Ey, TPS3422Ey: TS = VCC
s
0
–20%
Reset pulse duration
UNIT
20%
TPS3420D: TS = GND
TPS3421Ey, TPS3422Ey: TS = GND
tRST
MAX
20%
TPS3421xC
64
80
96
TPS3421xG
320
400
480
TPS3422xG
320
400
480
ms
tDD
Detection delay (from input to
RST) (2)
For 0-s tTIMER condition
150
µs
tSD
Start-up delay (2)
VCC rising
300
µs
(1)
(2)
For devices with a 0-second delay while TS = VCC, this option is only for factory testing and is not intended for normal operation. In
normal operation, the TS pin should be tied to GND.
For devices with a 0-second delay when TS = VCC, reset asserts in tDD time when both PB inputs go low in this configuration. During
start-up, if the PB inputs are low, reset asserts after a start-up time delay. This value is specified by design.
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PB1
ttimer = 7.5 s
PB2
ttimer = 7.5 s
trst(1)
RST
(1)
For the TPS3420, tRST is not a fixed time, but instead depends on one of the PB pins going high.
Figure 1. TPS3420 Timing Diagram
PB1
ttimer = 7.5 s
PB2
ttimer = 7.5 s
RST
trst = 400 ms
Figure 2. TPS3421 Timing Diagram
Timer End
PB1
ttimer = 7.5 s
RST
trst = 400 ms
Figure 3. TPS3422 Timing Diagram
6
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6.7 Typical Characteristics
At TJ = 25°C and VCC = 3.3 V, unless otherwise noted.
8
Standby Supply Current (µA)
1.2
±40C
+0C
+25C
+85C
+105C
+125C
7
Active Supply Current (µA)
1.4
1
0.8
0.6
0.4
0.2
6
5
4
±40C
+0C
3
+25C
2
+85C
1
+105C
+125C
0
0
0
1
2
3
4
VCC (V)
5
6
0
7
1
2
3
4
5
6
7
VCC (V)
C001
C002
PB1 = PB2 = GND
Figure 4. TPS3421: Standby Supply Current vs Supply
Voltage
Figure 5. TPS3421: Active Supply Current vs Supply Voltage
412
7.8
Vcc = 1.6 V
Vcc = 1.6 V
Reset Pulse Duration (ms)
Push-Button Timer (s)
Vcc = 6.5 V
7.7
7.6
7.5
7.4
-50
-25
0
25
50
75
100
Temperature (C)
Vcc = 6.5 V
408
404
400
125
C003
TS = GND
396
-50
-25
0
25
50
75
100
Temperature (C)
Figure 6. Push-Button Timer vs Temperature
C004
Figure 7. Reset Pulse Duration vs Temperature
0.5
0.8
±40C
0.7
±40C
+0C
0.6
+25C
0.5
+85C
0.4
+125C
+0C
0.4
+25C
VOL (V)
VOL (V)
125
0.3
0.2
+85C
0.3
+125C
0.2
0.1
0.1
0
0
0
2
4
6
Output Sink Current (mA)
8
10
0
2
4
6
8
Output Sink Current (mA)
C005
VCC = 1.6 V
10
C006
VCC = 3.3 V
Figure 8. Output Voltage Low vs Output Sink Current
Figure 9. Output Voltage Low vs Output Sink Current
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Typical Characteristics (continued)
At TJ = 25°C and VCC = 3.3 V, unless otherwise noted.
0.5
±40C
+0C
0.4
VOL (V)
+25C
+85C
0.3
+125C
0.2
0.1
0
0
2
4
6
Output Sink Current (mA)
8
10
C007
VCC = 6.5 V
Figure 10. Output Voltage Low vs Output Sink Current
8
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7 Detailed Description
7.1 Overview
The TPS342x are a family of push-button reset devices with an extended setup period that prevents resets from
occurring as a result of short-duration switch closures. See Table 1 for details.
The TPS3420 is a dual-channel device with an output that asserts when both inputs (PB1 and PB2) are held low
for the push-button timer duration, and deasserts when either input PBx is released.
The TPS3421 is a dual-channel device with an output that asserts when both inputs (PB1 and PB2) are held low
for the push-button timer duration, and deasserts after the reset time-out duration.
The TPS3422 is a single-channel device with an output that asserts when the PB1 input is held low for the pushbutton timer duration, and deasserts after the reset time-out duration.
The TPS342x family also has a TS pin that selects between two different push-button timing options by
connecting the pin to either GND or VCC.
Table 1. Device Family Options
DEVICE
CHANNELS
INPUT
RESET BEHAVIOR
(DEASSERTION)
TPS3420
2
NMOS-based threshold
Input (PBx) dependent
TPS3421
2
External pullup to VCC
Fixed pulse
TPS3422
1
Internal pullup
Fixed pulse
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7.2 Functional Block Diagrams
VCC
RST
PB1
Digital Logic
and
Delay Generator
Input
Logic
PB2
TS
Timing Selector
(Two-State Logic)
GND
Oscillator
Figure 11. TPS3420 Block Diagram
VCC
RST
PB1
Digital Logic
and
Delay Generator
Input
Logic
PB2
TS
Reset Pulse
Generator
Timing Selector
(Two-State Logic)
GND
Oscillator
Figure 12. TPS3421 Block Diagram
VCC
RST
Digital Logic
and
Delay Generator
PB1
TS
Reset Pulse
Generator
TST
Timing Selector
(Two-State Logic)
GND
Oscillator
Figure 13. TPS3422 Block Diagram
10
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7.3 Feature Description
7.3.1 Push-Button Timer Selection (TS)
The TPS342x offer two different push-button timer options (tTIMER) for system flexibility with the use of the TS pin.
Connect the TS pin to either GND or VCC for two different timing options, as shown in Table 2.
Table 2. Push-Button Timer Option Examples
PUSH-BUTTON TIMER
PRODUCT
TS = VCC
TS = GND
RESET PULSE
TPS3420DDRYR/T
12.5 s
7.5 s
N/A
TPS3421EGDRYR/T
0s
7.5 s
400 ms
TPS3422EGDRYR/T
0s
7.5 s
400 ms
During normal operation, the TS pin state should not be changed because TS is intended to be permanently
connected to either ground or VCC. The state of the TS pin is checked during power up and when either PBx
input is high. Therefore, if a different timing option is desired, the state must be changed during power off, or
when either PBx input is high, to avoid false operation.
7.3.2 Inputs
This section discusses the inputs of the TPS342x devices.
7.3.2.1 TPS3420 Inputs (PB1, PB2)
The TPS3420 has two NMOS-based threshold inputs (PB1, PB2) with a VIH ≥ 0.85 V, and a VIL ≤ 0.3 V. When
input conditions are met (that is, when both inputs are simultaneously held low for the push-button timer period,
tTIMER), the device asserts a reset low, as shown in Figure 1. Reset deassertion occurs when either input goes
high. The reset pulse occurs only one time after each valid input condition. At least one input pin must be
released (goes high) and then driven low for the tTIMER period before RST asserts again.
7.3.2.2 TPS3421 Inputs (PB1, PB2)
The TPS3421 has two inputs: PB1 and PB2. External pullup resistors to VCC are required to pull the input pins
high. When input conditions are met (that is, when both inputs are held low simultaneously for the push-button
timer period, tTIMER), the device asserts a single reset pulse of a fixed time (tRST); see Figure 2. Reset
deassertion is independent of the inputs because tRST is a fixed time pulse. A reset pulse occurs only one time
after each valid input condition. At least one input pin must be released (go high) and then driven low for the
tTIMER duration before RST asserts again.
7.3.2.3 TPS3422 Inputs (PB1)
The TPS3422 has only one input: PB1. This input has an internal pullup resistor to VCC. When input conditions
are met (that is, when the input is held low for the push-button timer period, tTIMER), the device asserts a single
reset pulse of a fixed time (tRST); see Figure 3. Reset deassertion is independent of the input because tRST is a
fixed time pulse. A reset pulse occurs only one time after each valid input condition. The input pin must be
released (go high) and then driven low for the tTIMER period before RST asserts again.
7.3.3 Output (RST)
The TPS342x have an open-drain output. A pullup resistor must be used to hold the line high when the output is
in a high-impedance state (not asserted). By connecting a pullup resistor to the proper voltage rail, the output
can be connected to other devices at correct interface voltage levels. The TPS342x output can be pulled up to
6.5 V, independent of the device supply voltage. To ensure proper voltage levels, make sure to choose the
correct pullup resistor values. The pullup resistor value is determined by VOL, sink current capability, and output
leakage current (Ilkg(OD)). These values are specified in Electrical Charactersitcs.
The Inputs (PB1, PB2) describes how the output is asserted or deasserted. See Figure 1 (TPS3420), Figure 2
(TPS3421), or Figure 3 (TPS3422) for a timing diagram that describes the relationship between the PB1 and PB2
inputs and the output. Figure 14 shows the TPS3421 reset timing.
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PB1
PB2
ttimer
ttimer
ttimer
RST
trst
No
Second
Pulse
trst
Figure 14. TPS3421 Reset Timing Diagram
Any change in input condition is detected after reset is deasserted. If input PB1 or PB2 has a pulse (low-to-highto-low) during the tRST period, the change is not recognized by the device. If input PB1 or PB2 go high during the
tRST period, the change is detected after reset is deasserted.
7.4 Device Functional Modes
7.4.1 Normal Operation (VDD > 1.6 V)
When the voltage on VDD is greater than 1.6 V (VDD(min)) for approximately 300 μs (tSD), the RST signal
corresponds to the state of the PB1 and PB2 pins; see Table 1.
7.4.2 Below VDD(min) (1.6 V > VDD > 1.3 V)
When the voltage on VDD is less than 1.6 V but greater than 1.3 V (typical), the RST signal corresponds to the
state of the PB1 and PB2 pins; however, the electrical specifications in the Electrical Characteristics and Timing
Requirements tables do not apply when VDD < VDD(min).
7.4.3 Power-On Reset (VDD < 1.3 V)
When the voltage on VDD is lower than 1.3 V (typical), the RST output should be high-impedance. However, it is
not ensured to be in a high impedance state under all conditions.
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS342x family of devices are small, low-current, push-button reset timers. These devices use a long timing
setup delay to provide the system reset signals, and avoid resets from short push-button closures. This reset
configuration allows for differentiation between user inputs and hard system resets. TPS342x uses an open drain
output, has an input voltage range of 1.6 V to 6.5 V, and is specified from –40°C to +125°C.
The TPS3420 and TPS3421 are used to monitor two inputs while TPS3422 is used to monitor a single input.
8.2 Typical Applications
8.2.1 Single Input With Fixed Reset Pulse Duration
If only one input must be monitored to set the state of a logic pin, such as the enable pin of a load switch, use
the TPS3422. After a reset event has occurred, RST is held low for a fixed amount of time (tRST) regardless of
the state of the PB1 pin.
An application diagram is shown in Figure 15.
VIN = 1.6 V to 6.5 V
+
VCC
IN
RST
PB1
Load
Switch
ON
OUT
System
Power
GND
Push-Button
Switch
TPS3422
TS
TST
GND
A.
Connect TS to VCC or ground for different PB time delays.
Figure 15. TPS3422 Application Diagram
8.2.1.1 Design Requirements
Table 3 lists the design requirements for Figure 15.
Table 3. Design Requirements and Results
DESIGN REQUIREMENTS
Single input
DESIGN RESULT
PB1
Does not react to input signal less than 5 s
6 s (minimum)
Reset pulse greater than 240 ms
320 ms (minimum)
ICC < 5 µA
3.3 μA (maximum)
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8.2.1.2 Detailed Design Procedure
When the output switches to the high-Z state, the rise time of the RST node depends on the pullup resistance
and the capacitance on that node. Choose pullup resistors that satisfy both the downstream timing requirements
and the sink current required to have a VOL low enough for the application; 1-kΩ to 1-MΩ resistors are a good
choice for low-capacitive loads.
8.2.1.3 Application Curve
412
Reset Pulse Duration (ms)
Vcc = 1.6 V
Vcc = 6.5 V
408
404
400
396
-50
-25
0
25
50
75
Temperature (C)
100
125
C004
Figure 16. Reset Pulse Duration vs Temperature
8.2.2 Dual Input Applications
If two inputs must be monitored to set the state of a microprocessor reset pin, either the TPS3420 or the
TPS3421 can be used. The system functionality determines which device to use. Use the TPS3420 if RST must
be held low until the signal on one of the PBx pins transitions to a logic high state. Use the TPS3421 if RST
should only be held low for a fixed amount of time (tRST) regardless of the state of the PBx pins.
An application diagram that is suitable for either the TPS3420 and the TPS3421 is shown in Figure 17.
VIN = 1.6 V to 6.5 V
+
VDD
VCC
Microprocessor
TS
PB1
Device
RST
PB2
Reset
GND
GPIO
GPIO
Push-Button
Switch 1
A.
Push-Button
Switch 2
Connect TS to VCC or ground for different PB time delays. Connect one PB input to ground for use as a single
channel.
Figure 17. TPS3420 or TPS3421 Application Diagram
14
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8.2.2.1 Design Requirements
Table 4 lists the design requirements for Figure 17.
Table 4. Design Requirements and Results
DESIGN RESULT
DESIGN REQUIREMENTS
TPS3420
TPS3421
Dual input
PB1 and PB2
PB1 and PB2
Does not react to input signal less
than 5 s
6 s (minimum)
6 s (minimum)
Reset pulse greater than 140 ms
Depends on PBx timing
320 ms (minimum)
True
Does not depend on PBx timing
Reset pulse ends after at least
one input goes high
8.2.2.2 Detailed Design Procedure
Determine which version of the TPS342x family best suits the functional performance required.
When the output switches to the high-Z state, the rise time of the RST node depends on the pullup resistance
and the capacitance on that node. Choose pullup resistors that satisfy both the downstream timing requirements
and the sink current required to have a VOL low enough for the application; 1-kΩ to 1-MΩ resistors are a good
choice for low-capacitive loads.
8.2.2.3 Application Curve
412
Reset Pulse Duration (ms)
Vcc = 1.6 V
Vcc = 6.5 V
408
404
400
396
-50
-25
0
25
50
75
Temperature (C)
100
125
C004
Figure 18. Reset Pulse Duration vs Temperature
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8.2.3 Latched Reset Signal
Some applications require the reset signal (RST) to be latched and only change state after a second low input
signal is received. To achieve a latched version of the RST signal, a D-flip-flop can be used. The output of the Dflip-flop, Q, is then connected to the device to be reset.
See Figure 19 for an example of a latched reset signal configuration.
VCC
VCC
VCC
100 k
PB1
D
Q
CLK
Q
RST
TPS3422
TST
PB1
VCC
1 k
Latched Reset
Signal
TS
SN74LVC1G74
VCC
GND
PRE
RDELAY
CLR
GND
CDELAY
VCC
CLR
Q
Q
PB1
RST
Figure 19. Latched Reset Schematic and Timing Diagram
8.2.3.1 Design Requirements
Table 5 summarizes the design requirements for Figure 19.
Table 5. Design Requirements and Results
DESIGN REQUIREMENTS
Single input
PB1
Latched output
Q
Does not react to input signal less than 5 s
16
DESIGN RESULT
6 s (minimum)
Reset pulse greater than 200 ms
320 ms (minimum)
ICC < 20 µA
13.3 μA (maximum)
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8.2.3.2 Detailed Design Procedure
Once a positive-edge triggered D-flip-flop is chosen, make sure the slew rate of the RST signal is fast enough to
trigger the flip-flop. For the SN74LVC1G74 shown in Figure 19, TI recommends a 1-kΩ pullup resistor. The RC
time constant of the delay cap (CDELAY) and delay resistor (RDELAY)should be 10 times the rise time of the input
voltage to VCC so that a clear signal is sent to the D-flip-flop, to initialize it into a known state.
8.2.3.3 Application Curve
Figure 20. Latched Reset Waveforms Using SN74LVC1G74
9 Power Supply Recommendations
The input power supply should range from 1.6 V to 6.5 V and should be well regulated. Though not required, it is
good analog design practice to place a 0.1-µF ceramic capacitor close to the VCC pin.
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10 Layout
10.1 Layout Guidelines
Follow these guidelines for laying out the printed circuit board (PCB) that is used for the TPS342x.
• Place the VCC decoupling capacitor close to the device.
• Avoid using long traces for the VCC supply node. The VDD capacitor (CVDD), along with parasitic inductance
from the supply to the capacitor, can form an LC tank and create ringing with peak voltages above the
maximum VCC voltage.
10.2 Layout Example
Pullup
Voltage
RP
RST
Flag
PB1
Signal
1
6
2
5
3
4
PB2
Signal
Input
Supply
Figure 21. Layout Example (DRY Package)
18
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS3421EG. The TPS3421EGEVM-156 Evaluation Module (and related user's guide) can be requested at the TI
website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS3421EG is available through the product folder under
Tools & Software.
11.1.2 Device Nomenclature
Table 6. Device Nomenclature
PRODUCT
DESCRIPTION
TPS3420xzzza
TPS3421xyzzza
TPS3422xyzzza
x is the push-button timer option.
y is the different reset timeout pulse option.
zzz is the package designator.
a is the tape or reel quantity.
11.2 Documentation Support
11.2.1 Related Documentation
•
TPS3421EGEVM-156 User's Guide, SLVU781
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS3420
Click here
Click here
Click here
Click here
Click here
TPS3421
Click here
Click here
Click here
Click here
Click here
TPS3422
Click here
Click here
Click here
Click here
Click here
11.4 Trademarks
Ultrabooks is a trademark of Intel Corporation.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
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16-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS3420DDRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AD
TPS3420DDRYT
ACTIVE
SON
DRY
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AD
TPS3421ECDRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AB
TPS3421ECDRYT
ACTIVE
SON
DRY
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AB
TPS3421EGDRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AC
TPS3421EGDRYT
ACTIVE
SON
DRY
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AC
TPS3422EGDRYR
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AE
TPS3422EGDRYT
ACTIVE
SON
DRY
6
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AE
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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