TPS3701DDCT

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPS3701 ZHCSD07 – NOVEMBER 2014 TPS3701 用于过压和欠压检测且具有内部基准电压的 36V 窗口比较器 1 特性 3 说明 宽电源电压范围：1.8V 至 36V 可调节阀值：低至 400mV 针对过压和欠压检测的开漏输出 低静态电流：7µA（典型值） 高阈值精度： – 0.75%（整个温度范围内） – 0.25%（典型值） 内部滞后：5.5mV（典型值） 温度范围：-40°C 至 125°C 封装： – 小外形尺寸晶体管 (SOT)-6 封装 • • • • • 1 • • • TPS3701 宽电源电压窗口比较器工作电压范围为 1.8V 至 36V。 此器件具有两个内部基准电压为 400mV 的 精密比较器和两个额定电压为 25V 的开漏输 出（OUTA 和 OUTB），分别用于过压和欠压检测。 TPS3701 可用作窗口比较器或两个独立的电压监视 器；用外部电阻器设置监视电压。 2 应用 工业控制系统 嵌入式计算模块 数字信号处理器 (DSP)、微控制器和微处理器 笔记本和台式计算机 便携式和电池供电类产品 现场可编程门阵列 (FPGA) 和专用集成电路 (ASIC) 系统 • • • • • • 当 INA 引脚的电压降至负向阈值以下时，OUTA 被驱 动为低电平；当 INA 引脚的电压升至正向阈值以上 时，OUTA 被驱动为高电平。 当 INB 引脚的电压升至 正向阈值以上时，OUTB 被驱动为低电平；而 INB 引 脚的电压降至负向阈值以下时，OUTB 被驱动为高电 平。 TPS3701 的两个比较器均内置有滞后特性，可抑 制噪声，避免触发错误，从而确保运行输出稳定。 TPS3701 采用 SOT-6 封装，额定工作结温范围为 –40°C 至 125°C。 器件信息(1) 部件号 TPS3701 SOT (6) 2.90mm x 1.60mm 典型误差与结温之间的关系 VPULLUP 0 V to 25 V 1.8 V to 36 V 封装尺寸（标称值） (1) 要了解所有可用封装，请见数据表末尾的封装选项附录。 典型应用 VMON 封装 0.04 0.1 mF VDD R1 RP1 OUTA INA RP2 R2 To a reset or enable input of the system. Device Typical Threshold Error (%) 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.1 -0.12 INA Negative Threshold INB Positive Threshold -0.14 OUTB INB R3 GND -0.16 -40 -20 0 20 40 60 80 100 120 TJ 140 D012 1 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. English Data Sheet: SBVS240 TPS3701 ZHCSD07 – NOVEMBER 2014 www.ti.com.cn 目录 1 2 3 4 5 6 7 特性 .......................................................................... 应用 .......................................................................... 说明 .......................................................................... 修订历史记录 ........................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 7 Absolute Maximum Ratings ..................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 11 8 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Application ................................................. 16 9 Power Supply Recommendations...................... 18 10 Layout................................................................... 19 10.1 Layout Guidelines ................................................. 19 10.2 Layout Example .................................................... 19 11 器件和文档支持 ..................................................... 20 11.1 11.2 11.3 11.4 Detailed Description ............................................ 10 文档支持 ............................................................... 商标 ....................................................................... 静电放电警告......................................................... 术语表 ................................................................... 20 20 20 20 12 机械封装和可订购信息 .......................................... 20 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 4 修订历史记录 2 日期 修订版本 注释 2014 年 11 月 * 最初发布版本 Copyright © 2014, Texas Instruments Incorporated TPS3701 www.ti.com.cn ZHCSD07 – NOVEMBER 2014 5 Pin Configuration and Functions DDC Package SOT-6 (Top View) OUTA 1 6 OUTB GND 2 5 VDD INA 3 4 INB Pin Functions PIN NAME NO. I/O GND 2 — INA 3 I Comparator A input. This pin is connected to the voltage to be monitored with the use of an external resistor divider. When the voltage at this terminal drops below the threshold voltage VIT–(INA), OUTA is driven low. INB 4 I Comparator B input. This pin is connected to the voltage to be monitored with the use of an external resistor divider. When the voltage at this terminal exceeds the threshold voltage VIT+(INB), OUTB is driven low. OUTA 1 O INA comparator open-drain output. OUTA is driven low when the voltage at this comparator is less than VIT–(INA). The output goes high when the sense voltage rises above VIT+(INA). OUTB 6 O INB comparator open-drain output. OUTB is driven low when the voltage at this comparator exceeds VIT+(INB). The output goes high when the sense voltage falls below VIT–(INB). VDD 5 I Supply voltage input. Connect a 1.8-V to 36-V supply to VDD to power the device. It is good analog design practice to place a 0.1-µF ceramic capacitor close to this pin. Copyright © 2014, Texas Instruments Incorporated DESCRIPTION Ground 3 TPS3701 ZHCSD07 – NOVEMBER 2014 www.ti.com.cn 6 Specifications 6.1 Absolute Maximum Ratings (1) Over operating junction temperature range, unless otherwise noted. VALUE MIN Voltage (2) –0.3 +40 V VOUTA, VOUTB –0.3 +28 V VINA, VINB –0.3 +7 V 40 mA –40 +125 °C Output pin current Temperature Operating junction, TJ (2) UNIT VDD Current (1) MAX Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to network ground terminal. 6.2 Handling Ratings MIN MAX UNIT –65 +150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) –2000 +2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) –500 +500 Tstg Storage temperature range V(ESD) Electrostatic discharge (1) (2) V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply pin voltage 1.8 36 V VINA, VINB Input pin voltage 0 1.7 V VOUTA, VOUTB Output pin voltage 0 25 V IOUTA, IOUTB Output pin current 10 mA TJ Junction temperature +125 °C 0 –40 +25 6.4 Thermal Information TPS3701 THERMAL METRIC (1) DDC (SOT) UNITS 6 PINS RθJA Junction-to-ambient thermal resistance 201.6 RθJC(top) Junction-to-case (top) thermal resistance 47.8 RθJB Junction-to-board thermal resistance 51.2 ψJT Junction-to-top characterization parameter 0.7 ψJB Junction-to-board characterization parameter 50.8 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A (1) 4 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 版权 © 2014, Texas Instruments Incorporated TPS3701 www.ti.com.cn ZHCSD07 – NOVEMBER 2014 6.5 Electrical Characteristics Over the operating temperature range of TJ = –40°C to +125°C, 1.8 V ≤ VDD < 36 V, and pullup resistors RP1,2 = 100 kΩ, unless otherwise noted. Typical values are at TJ = 25°C and VDD = 12 V. PARAMETER VDD TEST CONDITIONS Supply voltage range MIN TYP 1.8 (1) MAX 36 VOL ≤ 0.2 V UNIT V V(POR) Power-on reset voltage 0.8 V VIT–(INA) INA pin negative input threshold voltage VDD = 1.8 V to 36 V 397 400 403 mV VIT+(INA) INA pin positive input threshold voltage 400 405.5 413 mV VHYS(INA) INA pin hysteresis voltage (HYS = VIT+(INA) – VIT–(INA)) 2 5.5 12 mV VIT–(INB) INB pin negative input threshold voltage VDD = 1.8 V to 36 V 387 394.5 400 mV VIT+(INB) INB pin positive input threshold voltage 397 400 403 mV VHYS(INB) INB pin hysteresis voltage (HYS = VIT+(INB) – VIT–(INB)) 2 5.2 12 mV VOL Low-level output voltage VDD = 1.8 V, IOUT = 3 mA 130 250 mV VDD = 5 V, IOUT = 5 mA 150 250 mV IIN Input current (at INA, INB pins) ID(leak) Open-drain output leakage current VDD = 1.8 V and 36 V, VOUT = 25 V IDD Supply current VDD = 1.8 V – 36 V UVLO Undervoltage lockout (2) VDD falling (1) (2) VDD = 1.8 V to 36 V VDD = 1.8 V to 36 V VDD = 1.8 V and 36 V, VINA, VINB = 6.5 V –25 +1 +25 nA VDD = 1.8 V and 36 V, VINA, VINB = 0.1 V –15 +1 +15 nA 10 300 nA 8 11 µA 1.5 1.7 V 1.3 The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. If less than V(POR), the output is undetermined. When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined if less than V(POR). 版权 © 2014, Texas Instruments Incorporated 5 TPS3701 ZHCSD07 – NOVEMBER 2014 www.ti.com.cn 6.6 Timing Requirements PARAMETER TEST CONDITION MIN TYP MAX UNIT .tpd(HL) High-to-low propagation delay (1) VDD = 24 V, ±10-mV input overdrive, RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV 9.9 µs tpd(LH) Low-to-high propagation delay (1) VDD = 24 V, ±10-mV input overdrive, RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV 28.1 µs Startup delay VDD = 5 V 155 µs tr Output rise time VDD = 12 V, 10-mV input overdrive, RL = 100 kΩ, CL = 10 pF, VO = (0.1 to 0.9) × VDD 2.7 µs tf Output fall time VDD = 12 V, 10-mV input overdrive, RL = 100 kΩ, CL = 10 pF, VO = (0.9 to 0.1) × VDD 0.12 µs td(start) (1) (2) (2) High-to-low and low-to-high refers to the transition at the input pins (INA and INB). During power on, VDD must exceed 1.8 V for at least 150 µs (typ) before the output state reflects the input condition. VDD V(POR) VIT+(INA) INA V HYS VIT±(INA) OUTA t pd(LH) t pd(HL) t pd(LH) VIT+(INB) INB V HYS VIT±(INB) OUTB t pd(LH) t pd(HL) t d(start) 图 1. Timing Diagram 6 版权 © 2014, Texas Instruments Incorporated TPS3701 www.ti.com.cn ZHCSD07 – NOVEMBER 2014 6.7 Typical Characteristics At TJ = 25°C and VDD = 12 V, unless otherwise noted. 10 22 INA INB 20 Minimum Pulse Width (Ps) Supply Current (PA) 8 6 4 TJ = -40qC TJ = 0qC TJ = 25qC TJ = 85qC TJ = 125qC 2 18 16 14 12 10 8 6 4 2 0 0 0 6 12 18 24 Supply Voltage (V) 30 36 0 5 10 15 20 25 30 Overdrive (%) D001 35 40 45 50 D011 VDD = 24 V 图 2. Supply Current vs Supply Voltage 图 3. Minimum Pulse Duration vs Threshold Overdrive Voltage (1) 400.2 408.5 408 400.05 407 VIT-(INA) (mV) VIT-(INB) (mV) 407.5 VDD = 1.8 V VDD = 12 V VDD = 36 V 406.5 406 405.5 399.9 399.75 399.6 405 VDD = 1.8 V VDD = 12 V VDD = 36 V 399.45 404.5 404 -40 -20 0 20 40 60 TJ (qC) 80 100 120 399.3 -40 140 图 4. INA Positive Input Threshold Voltage (VIT+(INA)) vs Temperature 80 100 120 140 D002 395.1 394.8 VIT-(INB) (mV) VIT+(INB) (mV) 40 60 TJ (qC) 395.4 399.9 399.75 394.5 394.2 393.9 393.6 393.3 399.6 393 -20 0 20 40 60 TJ (qC) 80 100 120 140 D004 图 6. INB Positive Input Threshold Voltage (VIT+(INB)) vs Temperature (1) 20 395.7 VDD = 1.8 V VDD = 12 V VDD = 36 V 400.05 399.45 -40 0 图 5. INA Negative Input Threshold Voltage (VIT–(INA)) vs Temperature 400.35 400.2 -20 D005 392.7 -40 VDD = 1.8 V VDD = 12 V VDD = 36 V -20 0 20 40 60 TJ (qC) 80 100 120 140 D003 图 7. INB Negative Input Threshold Voltage (VIT–(INB)) vs Temperature Minimum pulse duration required to trigger output high-to-low transition. INA = negative spike below VIT– and INB = positive spike above VIT+. 版权 © 2014, Texas Instruments Incorporated 7 TPS3701 ZHCSD07 – NOVEMBER 2014 www.ti.com.cn Typical Characteristics (接 接下页) At TJ = 25°C and VDD = 12 V, unless otherwise noted. 4500 3500 4000 3000 3500 3000 2000 Count Count 2500 1500 2500 2000 1500 1000 1000 500 500 402 401 400 398 408 407 406 405 404 399 0 0 D020 D022 VIT-(INA) Threshold Voltage (mV) VIT+(INA) Threshold Voltage (mV) VDD = 1.8 V VDD = 1.8 V 图 8. INA Positive Input Threshold Voltage (VIT+(INA)) Distribution 图 9. INA Negative Input Threshold Voltage (VIT–(INA)) Distribution 3000 3500 2500 3000 2500 Count 1500 1000 2000 1500 397 396 393 402 401 0 400 0 399 500 398 500 395 1000 394 Count 2000 D021 D023 VIT+(INB) Threshold Voltage (mV) VIT-(INB) Threshold Voltage (mV) VDD = 1.8 V VDD = 1.8 V 图 10. INB Positive Input Threshold Voltage (VIT+(INB)) Distribution 图 11. INB Negative Input Threshold Voltage (VIT–(INB)) Distribution 3.3 VDD = 1.8 V, INA to OUTA VDD = 36 V, INA to OUTA VDD = 1.8 V, INB to OUTB VDD = 36 V, INB to OUTB 11 10 9 8 7 6 5 -40 -20 0 20 40 60 TJ (qC) 80 100 120 Input step ±200 mV 图 12. Propagation Delay vs Temperature (High-to-Low Transition at the Inputs) 8 Low-to-High Propagation Delay (Ps) High-to-Low Propagation Delay (Ps) 12 140 D007 VDD = 1.8 V, INA to OUTA VDD = 36 V, INA to OUTA VDD = 1.8 V, INB to OUTB VDD = 36 V, INB to OUTB 3 2.7 2.4 2.1 1.8 1.5 1.2 -40 -20 0 20 40 60 TJ (qC) 80 100 120 140 D008 Input step ±200 mV 图 13. Propagation Delay vs Temperature (Low-to-High Transition at the Inputs) 版权 © 2014, Texas Instruments Incorporated TPS3701 www.ti.com.cn ZHCSD07 – NOVEMBER 2014 Typical Characteristics (接 接下页) At TJ = 25°C and VDD = 12 V, unless otherwise noted. 0.5 0.6 TJ = -40qC TJ = 0qC TJ = 25qC TJ = 85qC TJ = 125qC 0.5 0.4 VOL (V) VOL (V) 0.4 TJ = -40qC TJ = 0qC TJ = 25qC TJ = 85qC TJ = 125qC 0.3 0.3 0.2 0.2 0.1 0.1 0 0 0 1 2 3 4 5 6 IOUT (mA) 7 8 9 10 0 1 2 3 4 D009 VDD = 1.8 V 5 6 IOUT (mA) 7 8 9 10 D010 VDD = 12 V 图 14. Output Voltage Low vs Output Sink Current 图 15. Output Voltage Low vs Output Sink Current 210 Startup Delay (Ps) 195 VDD (2 V/div) 180 Startup Delay Period OUTA (2 V/div) 165 150 OUTB (2 V/div) 135 120 -40 -20 0 20 40 60 TJ (qC) 80 100 120 140 D025 VDD = 5 V Time (50 µs/div) VDD = 5 V, VINA = 390 mV, VINB = 410 mV, VPULLUP = 3.3 V 图 17. Startup Delay 图 16. Startup Delay vs Temperature VDD (2 V/div) Startup Delay Period OUTA (2 V/div) OUTB (2 V/div) Time (50 µs/div) VDD = 5 V, VINA = 410 mV, VINB = 390 mV, VPULLUP = 3.3 V 图 18. Startup Delay 版权 © 2014, Texas Instruments Incorporated 9 TPS3701 ZHCSD07 – NOVEMBER 2014 www.ti.com.cn 7 Detailed Description 7.1 Overview The TPS3701 combines two comparators (referred to as A and B) and a precision reference for over- and undervoltage detection. The TPS3701 features a wide supply voltage range (1.8 V to 36 V) and high-accuracy window threshold voltages of 400 mV (0.75% over temperature) with built-in hysteresis. The outputs are rated to 25 V and can sink up to 10 mA. Set each input pin (INA, INB) to monitor any voltage above 0.4 V by using an external resistor divider network. Each input pin has very low input leakage current, allowing the use of large resistor dividers without sacrificing system accuracy. To form a window comparator, use the two input pins and three resistors (see the Window Comparator Considerations section). In this configuration, the TPS3701 is designed to assert the output signals when the monitored voltage is within the window band. Each input can also be used independently. The relationship between the inputs and the outputs is shown in 表 1. Broad voltage thresholds are supported that enable the device to be used in a wide array of applications. 表 1. Truth Table CONDITION OUTPUT INA > VIT+(INA) OUTA high Output A high impedance STATUS INA < VIT–(INA) OUTA low Output A asserted INB > VIT+(INB) OUTB low Output B asserted INB < VIT–(INB) OUTB high Output B high impedance 7.2 Functional Block Diagram VDD INA OUTA A OUTB B INB Reference GND 10 版权 © 2014, Texas Instruments Incorporated TPS3701 www.ti.com.cn ZHCSD07 – NOVEMBER 2014 7.3 Feature Description 7.3.1 Inputs (INA, INB) The TPS3701 combines two comparators with a precision reference voltage. Each comparator has one external input; the other input is connected to the internal reference. The rising threshold on INB and the falling threshold on INA are designed and trimmed to be equal to the reference voltage (400 mV). This configuration optimizes the device accuracy when used as a window comparator. Both comparators also have built-in hysteresis that proves immunity to noise and ensures stable operation. The comparator inputs swings from ground to 1.7 V (7.0 V absolute maximum), regardless of the device supply voltage used. Although not required in most cases, it is good analog design practice to place a 1-nF to 10-nF bypass capacitor at the comparator input for noisy applications in order to reduce sensitivity to transient voltage changes on the monitored signal. For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA voltage drops below VIT–(INA). When the voltage exceeds VIT+(INA), OUTA goes to a high-impedance state; see 图 1. For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB exceeds VIT+(INB). When the voltage drops below VIT–(INB) OUTB goes to a high-impedance state; see 图 1. Together, these two comparators form a window-detection function as described in the Window Comparator Considerations section. 7.3.2 Outputs (OUTA, OUTB) In a typical TPS3701 application, the outputs are connected to a reset or enable input of the processor [such as a digital signal processor (DSP), application-specific integrated circuit (ASIC), or other processor type] or the outputs are connected to the enable input of a voltage regulator [such as a dc-dc converter or low-dropout regulator (LDO)]. The TPS3701 provides two open-drain outputs (OUTA and OUTB); use pullup resistors to hold these lines high when the output goes to a high-impedance state. Connect pullup resistors to the proper voltage rails to enable the outputs to be connected to other devices at correct interface voltage levels. The TPS3701 outputs can be pulled up to 25 V, independent of the device supply voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor values. The pullup resistor value is determined by VOL, output capacitive loading, and output leakage current (ID(leak)). These values are specified in the Electrical Characteristics table. Use wired-OR logic to merge OUTA and OUTB into one logic signal. 表 1 and the Inputs (INA, INB) section describe how the outputs are asserted or high impedance. See 图 1 for a timing diagram that describes the relationship between threshold voltages and the respective output. 7.4 Device Functional Modes 7.4.1 Normal Operation (VDD > UVLO) When the voltage on VDD is greater than 1.8 V for at least 155 µs, the OUTA and OUTB signals correspond to the voltage on INA and INB as listed in 表 1. 7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO) When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage, V(POR), the OUTA and OUTB signals are asserted and high impedance, respectively, regardless of the voltage on INA and INB. 7.4.3 Power On Reset (VDD < V(POR)) When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (V(POR)), both outputs are in a high-impedance state. 版权 © 2014, Texas Instruments Incorporated 11 TPS3701 ZHCSD07 – NOVEMBER 2014 www.ti.com.cn 8 Application and Implementation 注 Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS3701 is used as a precision dual-voltage supervisor in several different configurations. The monitored voltage (VMON), VDD voltage, and output pullup voltage can be independent voltages or connected in any configuration. The following sections show the connection configurations and the voltage limitations for each configuration. 8.1.1 Window Comparator Considerations The inverting and noninverting configuration of the comparators forms a window-comparator detection circuit using a resistor divider network, as shown in 图 19 and 图 20. The input pins can monitor any system voltage above 400 mV with the use of a resistor divider network. INA and INB monitor for undervoltage and overvoltage conditions, respectively. VMON 1.8 V to 25 V R1 (2.21 MW) RP1 (50 kW) VDD R2 (13.7 kW) OUT OUTA INA Device UV OUTB INB R3 (69.8 kW) VMON OV OUT GND 图 19. Window Comparator Block Diagram Overvoltage Limit VMON(OV) VMON(OV_HYS) VMON Undervoltage Limit VMON(UV_HYS) VMON(UV) OUTB OUTA 图 20. Window Comparator Timing Diagram 12 版权 © 2014, Texas Instruments Incorporated TPS3701 www.ti.com.cn ZHCSD07 – NOVEMBER 2014 Application Information (接 接下页) The TPS3701 flags the overvoltage or undervoltage condition with the greatest accuracy. The highest accuracy threshold voltages are VIT–(INA) and VIT+(INB), and correspond with the falling undervoltage flag, and the rising overvoltage flag, respectively. These thresholds represent the accuracy when the monitored voltage is within the valid window (both OUTA and OUTB are in a high-impedance state), and correspond to the VMON(UV) and VMON(OV) trigger voltages, respectively. If the monitored voltage is outside of the valid window (VMON is less than the undervoltage limit, VMON(UV), or greater than overvoltage limit, VMON(OV)), then the input threshold voltages to re-enter the valid window are VIT+(INA) or VIT–(INB), and correspond with the VMON(UV_HYS) and VMON(OV_HYS) monitored voltages, respectively. The resistor divider values and target threshold voltage can be calculated by using 公式 1 through 公式 4: RTOTAL = R1 + R2 + R3 (1) Choose an RTOTAL value so that the current through the divider is approximately 100 times higher than the input current at the INA and INB pins. Resistors with high values minimize current consumption; however, the input bias current degrades accuracy if the current through the resistors is too low. See application report SLVA450, Optimizing Resistor Dividers at a Comparator Input, for details on sizing input resistors. R3 is determined by 公式 2: RTOTAL R3 = VIT+(INB) VMON(OV) where • VMON(OV) is the target voltage at which an overvoltage condition is detected. (2) R2 is determined by either 公式 3 or 公式 4: R2 = RTOTAL VIT+(INA) - R3 VMON(UV_HYS) where • R2 = VMON(UV_HYS) is the target voltage at which an undervoltage condition is removed as VMON rises. (3) RTOTAL VIT-(INA) - R3 VMON(UV) where • VMON(UV) is the target voltage at which an undervoltage condition is detected. (4) 8.1.2 Input and Output Configurations 图 21 to 图 24 show examples of the various input and output configurations. 版权 © 2014, Texas Instruments Incorporated 13 TPS3701 ZHCSD07 – NOVEMBER 2014 www.ti.com.cn Application Information (接 接下页) VPULLUP (up to 25 V) 1.8 V to 36 V VDD OUTA INA To a reset or enable input of the system. Device OUTB INB GND 图 21. Interfacing to Voltages Other than VDD 1.8 V to 25 V VDD OUTA INA To a reset or enable input of the system. Device OUTB INB GND 图 22. Monitoring the Same Voltage as VDD 14 版权 © 2014, Texas Instruments Incorporated TPS3701 www.ti.com.cn ZHCSD07 – NOVEMBER 2014 Application Information (接 接下页) VMON 1.8 V to 25 V VDD R1 OUTA INA R2 Device OUTB INB R3 To a reset or enable input of the system. GND NOTE: The inputs can monitor a voltage higher than VDD (max) with the use of an external resistor divider network. 图 23. Monitoring a Voltage Other than VDD 1.8 V to 18 V 5V OUTA VDD INA 12 V To a reset or enable input of the system. VIT±(INA) VIT+(INA) VIT±(INB) VIT+(INB) OUTB Device INB GND NOTE: In this case, OUTA is driven low when an undervoltage condition is detected at the 5-V rail and OUTB is driven low when an overvoltage condition is detected at the 12-V rail. 图 24. Monitoring Overvoltage for One Rail and Undervoltage for a Different Rail 8.1.3 Immunity to Input Pin Voltage Transients The TPS3701 is immune to short voltage transient spikes on the input pins. Sensitivity to transients depends on both transient duration and amplitude; see 图 3, Minimum Pulse Duration vs Threshold Overdrive Voltage. 版权 © 2014, Texas Instruments Incorporated 15 TPS3701 ZHCSD07 – NOVEMBER 2014 www.ti.com.cn 8.2 Typical Application VMON 24 V 0.01 F + VPULLUP 3.3 V ± 2.0 MŸ VDD 100 kŸ INA OUTA Device 6.81 kŸ INB 100 kŸ OUTB GND 30.9 kŸ 图 25. 24-V, 10% Window Comparator 8.2.1 Design Requirements 表 2. Design Parameters PARAMETER DESIGN REQUIREMENT DESIGN RESULT Monitored voltage 24-V nominal, rising (VMON(OV)) and falling (VMON(UV)) threshold ±10% nominal (26.4 V and 21.6 V, respectively) VMON(OV) = 26.4 V ±2.7%, VMON(UV) = 21.6 V ±2.7% Output logic voltage 3.3-V CMOS 3.3-V CMOS Maximum current consumption 30 µA 24 µA 8.2.2 Detailed Design Procedure 1. Determine the minimum total resistance of the resistor network necessary to achieve the current consumption specification by using 公式 1. For this example, the current flow through the resistor network was chosen to be 13 µA; a lower current can be selected, however, care should be taken to avoid leakage currents that are artifacts of the manufacturing process. Leakage currents significantly impact the accuracy if they are greater than 1% of the resistor network current. VMON(OV ) 26.4 V RTOTAL 2.03 M I 13 PA where • • VMON(OV) is the target voltage at which an overvoltage condition is detected as VMON rises. I is the current flowing through the resistor network. (5) 2. After RTOTAL is determined, R3 can be calculated using 公式 6. Select the nearest 1% resistor value for R3. In this case, 30.9 kΩ is the closest value. RTOTAL 2.03 MW R3 = VIT+(INB) = 0.4 V = 30.7 kW 26.4 V VMON(OV) (6) 3. Use 公式 7 to calculate R2. Select the nearest 1% resistor value for R2. In this case, 6.81 kΩ is the closest value. RTOTAL 2.03 M: R2 x VIT (INA  )  R3 x 0.4 V  30.9 k N VMON(UV ) 21.6 V (7) 4. Use 公式 8 to calculate R1. Select the nearest 1% resistor value for R1. In this case, 2 MΩ is the closest value. R1 RTOTAL  R2  R3 2.03 M  N  N 0 (8) 16 版权 © 2014, Texas Instruments Incorporated TPS3701 www.ti.com.cn ZHCSD07 – NOVEMBER 2014 5. The worst-case tolerance can be calculated by referring to Equation 13 in application report SLVA450, Optimizing Resistor Dividers at a Comparator Input. An example of the rising threshold error, VMON(OV), is given in 公式 9: § VIT(INB) $&& 72/9IT(INB) ‡ ¨ ¨ VMON(OV ) © · 0.4 · § ¸ ‡72/R ‡ ¨ ¸ ‡  ¸ © 26.4 ¹ ¹ where • • • % TOL(VIT+(INB)) is the tolerance of the INB positive threshold. % ACC is the total tolerance of the VMON(OV) voltage. % TOLR is the tolerance of the resistors selected. (9) 6. When the outputs switch to the high-Z state, the rise time of the OUTA or OUTB node depends on the pullup resistance and the capacitance on the node. Choose pullup resistors that satisfy the downstream timing requirements; 100-kΩ resistors are a good choice for low-capacitive loads. 8.2.3 Application Curves VDD (10 V/div) OUTA (2 V/div) OUTB (2 V/div) Time (5 ms/div) 图 26. 24-V Window Monitor Output Response 版权 © 2014, Texas Instruments Incorporated 17 TPS3701 ZHCSD07 – NOVEMBER 2014 www.ti.com.cn 9 Power Supply Recommendations The TPS3701 has a 40-V absolute maximum rating on the VDD pin, with a recommended operating condition of 36 V. If the voltage supply that is providing power to VDD is susceptible to any large voltage transient that may exceed 40 V, or if the supply exhibits high voltage slew rates greater than 1 V/µs, take additional precautions. Place an RC filter between the supply and VDD to filter any high-frequency transient surges on the VDD pin. A 100-Ω resistor and 0.01-µF capacitor is required in these cases, as shown in 图 27. 100 Ÿ 0.01 F + ± VPULLUP R1 VDD INA OUTA INB OUTB R2 R3 GND 图 27. Using an RC Filter to Remove High-Frequency Disturbances on VDD 18 版权 © 2014, Texas Instruments Incorporated TPS3701 www.ti.com.cn ZHCSD07 – NOVEMBER 2014 10 Layout 10.1 Layout Guidelines • • • Place R1, R2, and R3 close to the device to minimize noise coupling into the INA and INB nodes. Place the VDD decoupling capacitor close to the device. Avoid using long traces for the VDD supply node. The VDD capacitor (CVDD), along with parasitic inductance from the supply to the capacitor, may form an LC tank and create ringing with peak voltages above the maximum VDD voltage. If this is unavoidable, see 图 27 for an example of filtering VDD. 10.2 Layout Example Pullup Voltage RP1 RP2 Overvoltage Flag Undervoltage Flag Monitored Voltage R1 1 6 2 5 3 4 R2 CVDD Input Supply R3 图 28. Recommended Layout 版权 © 2014, Texas Instruments Incorporated 19 TPS3701 ZHCSD07 – NOVEMBER 2014 www.ti.com.cn 11 器件和文档支持 11.1 文档支持 11.1.1 相关文档　 相关文档，请参见以下应用报告和用户指南（可从 TI 网站获取）： • 应用报告 SLVA600 —《使用 TPS3700 作为负轨过压和欠压检测器》。 • 应用报告 SLVA450 —《优化比较器输入端的电阻分压器》。 • 用户指南 SLVU683 —《TPS3700EVM-114 评估模块》。 11.2 商标 All trademarks are the property of their respective owners. 11.3 静电放电警告 ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可 能会损坏集成电路。 ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可 能会导致器件与其发布的规格不相符。 11.4 术语表 SLYZ022 — TI 术语表。 这份术语表列出并解释术语、首字母缩略词和定义。 12 机械封装和可订购信息 以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对 本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。 20 版权 © 2014, Texas Instruments Incorporated 重要声明 德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据 JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售 都遵循在订单确认时所提供的TI 销售条款与条件。 TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使 用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。 TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险， 客户应提供充分的设计与操作安全措施。 TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权 限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用 此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它 知识产权方面的许可。 对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行 复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。 在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明 示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。 客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法 律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障 及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而 对 TI 及其代理造成的任何损失。 在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用 的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。 TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。 只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面 向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有 法律和法规要求。 TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要 求，TI不承担任何责任。 产品 应用 数字音频 www.ti.com.cn/audio 通信与电信 www.ti.com.cn/telecom 放大器和线性器件 www.ti.com.cn/amplifiers 计算机及周边 www.ti.com.cn/computer 数据转换器 www.ti.com.cn/dataconverters 消费电子 www.ti.com/consumer-apps DLP® 产品 www.dlp.com 能源 www.ti.com/energy DSP - 数字信号处理器 www.ti.com.cn/dsp 工业应用 www.ti.com.cn/industrial 时钟和计时器 www.ti.com.cn/clockandtimers 医疗电子 www.ti.com.cn/medical 接口 www.ti.com.cn/interface 安防应用 www.ti.com.cn/security 逻辑 www.ti.com.cn/logic 汽车电子 www.ti.com.cn/automotive 电源管理 www.ti.com.cn/power 视频和影像 www.ti.com.cn/video 微控制器 (MCU) www.ti.com.cn/microcontrollers RFID 系统 www.ti.com.cn/rfidsys OMAP应用处理器 www.ti.com/omap 无线连通性 www.ti.com.cn/wirelessconnectivity 德州仪器在线技术支持社区 www.deyisupport.com IMPORTANT NOTICE 邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122 Copyright © 2014, 德州仪器半导体技术（上海）有限公司 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) TPS3701DDCR ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ZABO TPS3701DDCT ACTIVE SOT-23-THIN DDC 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ZABO (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2017 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 IMPORTANT NOTICE 重要声明 德州仪器 (TI) 公司有权按照最新发布的 JESD46 对其半导体产品和服务进行纠正、增强、改进和其他修改，并不再按最新发布的 JESD48 提 供任何产品和服务。买方在下订单前应获取最新的相关信息，并验证这些信息是否完整且是最新的。 TI 公布的半导体产品销售条款 (http://www.ti.com/sc/docs/stdterms.htm) 适用于 TI 已认证和批准上市的已封装集成电路产品的销售。另有其 他条款可能适用于其他类型 TI 产品及服务的使用或销售。 复制 TI 数据表上 TI 信息的重要部分时，不得变更该等信息，且必须随附所有相关保证、条件、限制和通知，否则不得复制。TI 对该等复制文 件不承担任何责任。第三方信息可能受到其它限制条件的制约。在转售 TI 产品或服务时，如果存在对产品或服务参数的虚假陈述，则会失去 相关 TI 产品或服务的明示或暗示保证，且构成不公平的、欺诈性商业行为。TI 对此类虚假陈述不承担任何责任。 买方和在系统中整合 TI 产品的其他开发人员（总称“设计人员”）理解并同意，设计人员在设计应用时应自行实施独立的分析、评价和判断，且 应全权 负责并确保 应用的安全性， 及设计人员的 应用 （包括应用中使用的所有 TI 产品）应符合所有适用的法律法规及其他相关要求。设计 人员就自己设计的 应用声明，其具备制订和实施下列保障措施所需的一切必要专业知识，能够 (1) 预见故障的危险后果，(2) 监视故障及其后 果，以及 (3) 降低可能导致危险的故障几率并采取适当措施。设计人员同意，在使用或分发包含 TI 产品的任何 应用前， 将彻底测试该等 应用 和 该等应用中所用 TI 产品的 功能。 TI 提供技术、应用或其他设计建议、质量特点、可靠性数据或其他服务或信息，包括但不限于与评估模块有关的参考设计和材料（总称“TI 资 源”），旨在帮助设计人员开发整合了 TI 产品的 应用， 如果设计人员（个人，或如果是代表公司，则为设计人员的公司）以任何方式下载、 访问或使用任何特定的 TI 资源，即表示其同意仅为该等目标，按照本通知的条款使用任何特定 TI 资源。 TI 所提供的 TI 资源，并未扩大或以其他方式修改 TI 对 TI 产品的公开适用的质保及质保免责声明；也未导致 TI 承担任何额外的义务或责任。 TI 有权对其 TI 资源进行纠正、增强、改进和其他修改。除特定 TI 资源的公开文档中明确列出的测试外，TI 未进行任何其他测试。 设计人员只有在开发包含该等 TI 资源所列 TI 产品的 应用时， 才被授权使用、复制和修改任何相关单项 TI 资源。但并未依据禁止反言原则或 其他法理授予您任何TI知识产权的任何其他明示或默示的许可，也未授予您 TI 或第三方的任何技术或知识产权的许可，该等产权包括但不限 于任何专利权、版权、屏蔽作品权或与使用TI产品或服务的任何整合、机器制作、流程相关的其他知识产权。涉及或参考了第三方产品或服务 的信息不构成使用此类产品或服务的许可或与其相关的保证或认可。使用 TI 资源可能需要您向第三方获得对该等第三方专利或其他知识产权 的许可。 TI 资源系“按原样”提供。TI 兹免除对资源及其使用作出所有其他明确或默认的保证或陈述，包括但不限于对准确性或完整性、产权保证、无屡 发故障保证，以及适销性、适合特定用途和不侵犯任何第三方知识产权的任何默认保证。TI 不负责任何申索，包括但不限于因组合产品所致或 与之有关的申索，也不为或对设计人员进行辩护或赔偿，即使该等产品组合已列于 TI 资源或其他地方。对因 TI 资源或其使用引起或与之有关 的任何实际的、直接的、特殊的、附带的、间接的、惩罚性的、偶发的、从属或惩戒性损害赔偿，不管 TI 是否获悉可能会产生上述损害赔 偿，TI 概不负责。 除 TI 已明确指出特定产品已达到特定行业标准（例如 ISO/TS 16949 和 ISO 26262）的要求外，TI 不对未达到任何该等行业标准要求而承担 任何责任。 如果 TI 明确宣称产品有助于功能安全或符合行业功能安全标准，则该等产品旨在帮助客户设计和创作自己的 符合 相关功能安全标准和要求的 应用。在应用内使用产品的行为本身不会 配有 任何安全特性。设计人员必须确保遵守适用于其应用的相关安全要求和 标准。设计人员不可将 任何 TI 产品用于关乎性命的医疗设备，除非已由各方获得授权的管理人员签署专门的合同对此类应用专门作出规定。关乎性命的医疗设备是 指出现故障会导致严重身体伤害或死亡的医疗设备（例如生命保障设备、心脏起搏器、心脏除颤器、人工心脏泵、神经刺激器以及植入设 备）。此类设备包括但不限于，美国食品药品监督管理局认定为 III 类设备的设备，以及在美国以外的其他国家或地区认定为同等类别设备的 所有医疗设备。 TI 可能明确指定某些产品具备某些特定资格（例如 Q100、军用级或增强型产品）。设计人员同意，其具备一切必要专业知识，可以为自己的 应用选择适合的 产品， 并且正确选择产品的风险由设计人员承担。设计人员单方面负责遵守与该等选择有关的所有法律或监管要求。 设计人员同意向 TI 及其代表全额赔偿因其不遵守本通知条款和条件而引起的任何损害、费用、损失和/或责任。 邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122 Copyright © 2017 德州仪器半导体技术（上海）有限公司