Table of Contents
www.ti.com
User’s Guide
TPS3840EVM Voltage Supervisor User Guide
ABSTRACT
This user’s guide describes the TPS3840EVM evaluation module (EVM). This guide contains the EVM
schematic, bill of materials (BOM), assembly drawing, and top and bottom board layouts.
Table of Contents
1 Trademarks..............................................................................................................................................................................1
2 Introduction.............................................................................................................................................................................2
2.1 Related Documentation......................................................................................................................................................3
2.2 TPS3840 Applications........................................................................................................................................................3
3 Schematic, Bill of Materials, and Layout.............................................................................................................................. 4
3.1 TPS3840EVM Schematic...................................................................................................................................................5
3.2 TPS3840EVM Bill of Materials........................................................................................................................................... 6
3.3 Layout and Component Placement....................................................................................................................................7
4 EVM Connectors..................................................................................................................................................................... 9
4.1 EVM Test Points.................................................................................................................................................................9
4.2 EVM Jumpers.....................................................................................................................................................................9
5 EVM Setup and Operation....................................................................................................................................................10
5.1 Input Power (VDD)............................................................................................................................................................ 10
5.2 Monitoring Voltage on VDD..............................................................................................................................................10
5.3 Reset Output ( RESET )................................................................................................................................................... 11
5.4 Reset Time Delay Programming (program tD via CT)...................................................................................................... 11
6 Revision History................................................................................................................................................................... 12
List of Figures
Figure 2-1. TPS3840EVM Board Top.......................................................................................................................................... 2
Figure 2-2. TPS3840EVM Board Bottom.....................................................................................................................................3
Figure 3-1. TPS3840EVM Schematic..........................................................................................................................................5
Figure 3-2. Component Placement—Top Assembly....................................................................................................................7
Figure 3-3. Component Placement—Bottom Assembly.............................................................................................................. 7
Figure 3-4. Layout—Top.............................................................................................................................................................. 7
Figure 3-5. Layout—Bottom.........................................................................................................................................................7
Figure 3-6. Top Layer...................................................................................................................................................................8
Figure 3-7. Bottom Layer............................................................................................................................................................. 8
Figure 3-8. Top Solder Mask........................................................................................................................................................8
Figure 5-1. TPS3840EVM RESET Asserted Due to MR Pulled Low.........................................................................................10
Figure 5-2. TPS3840EVM RESET Deasserted Due to MR Pulled High, With Delay tD, CT Floating........................................ 10
Figure 5-3. TPS3840EVM Startup Delay Time (tSTRT) with VDD = 1.6 V and CT Floating........................................................ 11
Figure 5-4. TPS3840EVM Glitch Immunity................................................................................................................................ 11
Figure 5-5. TPS3840EVM RESET Delay Time (tD) with CT Tied to GND Through 1-µF Capacitor.......................................... 12
Figure 5-6. TPS3840EVM RESET Delay Time (tD) with CT Tied to GND Through 0.01-µF Capacitor..................................... 12
Figure 5-7. TPS3840EVM RESET Delay Time (tD) with CT Floating.........................................................................................12
List of Tables
Table 3-1. BOM............................................................................................................................................................................6
Table 4-1. Test Points.................................................................................................................................................................. 9
Table 4-2. List of Onboard Jumpers.............................................................................................................................................9
Table 5-1. Nominal Supply and Typical Threshold Voltages......................................................................................................10
1 Trademarks
All trademarks are the property of their respective owners.
SNVU611A – DECEMBER 2018 – REVISED MAY 2021
Submit Document Feedback
TPS3840EVM Voltage Supervisor User Guide
Copyright © 2021 Texas Instruments Incorporated
1
Introduction
www.ti.com
2 Introduction
The TPS3840EVM is an evaluation module (EVM) for the TPS3840 voltage supervisor. The TPS3840EVM can
be used with any TPS3840 device variant but please note that if using the push-pull variants (TPS3840PLXX
or TPS3840PHXX), the shunt on J2 must be removed as push-pull devices do not use a pull-up resistor so R1
must be disconnected. Please also note if using TPS3840EVM with the active-high variant (TPS3840PHXX),
the active-low RESET label on the EVM board and throughout this User Guide becomes active-high RESET.
The TPS3840 has a supply voltage range of 1.5 V to 10 V, and offers input connections for all device input
and output pins. Test points are provided to give the user access to an extra ground connection if needed for
oscilloscope or multimeter measurements.
Figure 2-1. TPS3840EVM Board Top
2
TPS3840EVM Voltage Supervisor User Guide
SNVU611A – DECEMBER 2018 – REVISED MAY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
www.ti.com
Introduction
Figure 2-2. TPS3840EVM Board Bottom
2.1 Related Documentation
TPS3840 Nano Power, High Input Voltage Supervisor with MR and programmable delay data sheet, SBVS085
2.2 TPS3840 Applications
•
•
•
•
•
Grid Infrastructure (Circuit Breakers, Smart Meters, monitor and protection equipment)
Factory Automation (Field Transmitters, PLC)
Fire Safety Systems
Electronic Point of Sale
Portable, Battery-Powered Systems
SNVU611A – DECEMBER 2018 – REVISED MAY 2021
Submit Document Feedback
TPS3840EVM Voltage Supervisor User Guide
Copyright © 2021 Texas Instruments Incorporated
3
Schematic, Bill of Materials, and Layout
www.ti.com
3 Schematic, Bill of Materials, and Layout
This section provides a detailed description of the TPS3840EVM schematic, bill of materials (BOM), and layout.
4
TPS3840EVM Voltage Supervisor User Guide
SNVU611A – DECEMBER 2018 – REVISED MAY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
www.ti.com
Schematic, Bill of Materials, and Layout
3.1 TPS3840EVM Schematic
VCC
J1
2
1
R1
10.5k
J2
S H-J 1
1
2
J3
TP 1
1
2
J4
TP 2
TP 3
U?
/RES ET_DL 1
VDD_DL
2
C1
1uF
3
TP 5
GND_DL
CT_DL
RES ET
CT
S H-J 2
5
TP 4
VDD
GND
MR
4
/MR_DL
C2
1uF
TP S 3840DL29DBVR
J5
1
2
1
2
3
C3
0.01uF
J6
1
2
GND
GND
GND
GND
Figure 3-1. TPS3840EVM Schematic
SNVU611A – DECEMBER 2018 – REVISED MAY 2021
Submit Document Feedback
TPS3840EVM Voltage Supervisor User Guide
Copyright © 2021 Texas Instruments Incorporated
5
Schematic, Bill of Materials, and Layout
www.ti.com
3.2 TPS3840EVM Bill of Materials
Table 3-1. BOM
DESIGNATOR
6
QUANTITY
VALUE
PACKAGE
REFERENCE
DESCRIPTION
Printed Circuit Board
PART NUMBER
LP015
MANUFACTURER
!PCB
1
C1
1
1 µF
CAP, CERM, 1 µF, 16 V, ± 10%, X5R, 0603
0603
GRM185R61C105KE44 MuRata
D
C2
1
1 µF
CAP, CERM, 1 uF, 16 V, +/- 10%, X7R, 0603
0603
GRM188R71C105KA12 MuRata
D
C3
1
0.01 µF
CAP, CERM, 0.01 µF, 10 V, ± 10%, X7R, 0603
0603
GRM188R71C103KA01 MuRata
D
SJ-5303 (CLEAR)
H1, H2, H3, H4
4
Bumpon, Hemisphere, 0.44 X 0.20, Clear
Transparent Bumpon
J1, J2, J3, J5, J6
5
Header, 100mil, 2x1, TH
Header, 2x1, 100mil, TH 800-10-002-10-001000
J4
1
R1
1
SH-J1, SH-J2
Any
3M
Mill-Max
Header, 100mil, 3x1, TH
Header, 3x1, 100mil, TH 800-10-003-10-001000
Mill-Max
RES, 10.5 k, 1%, 0.1 W, 0603
0603
RC0603FR-0710K5L
Yageo
2
Shunt, 100mil, Tin plated, Black
Shunt Connector Black
Open Top, 2x1
SNT-100-BK-T-H
Samtec
TP1, TP2, TP3, TP4,
TP5
5
Test Point, Miniature, SMT
Test Point, Miniature,
SMT
5019
Keystone
U1
1
Nano Power, Wide VIN Voltage Detector with
Programmable Delay, DBV0005A (SOT-23-5)
DBV0005A
TPS3840DL29DBVR
Texas Instruments
FID1, FID2, FID3
0
Fiducial mark. There is nothing to buy or mount.
Fiducial
N/A
N/A
10.5k
TPS3840EVM Voltage Supervisor User Guide
SNVU611A – DECEMBER 2018 – REVISED MAY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
www.ti.com
Schematic, Bill of Materials, and Layout
3.3 Layout and Component Placement
Figure 3-2 and Figure 3-3 show the top and bottom assemblies of the printed circuit board (PCB) to show the
component placement on the EVM.
Figure 3-4 and Figure 3-5 show the top and bottom layouts, Figure 3-6 and Figure 3-7 show the top and bottom
layers, and Figure 3-8 shows the top solder mask of the EVM.
Figure 3-2. Component Placement—Top Assembly
Figure 3-3. Component Placement—Bottom
Assembly
Figure 3-4. Layout—Top
Figure 3-5. Layout—Bottom
SNVU611A – DECEMBER 2018 – REVISED MAY 2021
Submit Document Feedback
TPS3840EVM Voltage Supervisor User Guide
Copyright © 2021 Texas Instruments Incorporated
7
Schematic, Bill of Materials, and Layout
www.ti.com
Figure 3-6. Top Layer
Figure 3-7. Bottom Layer
Figure 3-8. Top Solder Mask
8
TPS3840EVM Voltage Supervisor User Guide
SNVU611A – DECEMBER 2018 – REVISED MAY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
www.ti.com
EVM Connectors
4 EVM Connectors
This section describes the connectors, jumpers, and test points on the EVM as well as how to connect, set up,
and properly use the EVM. Each device has an independent supply connection, but all grounds are connected
on the board.
4.1 EVM Test Points
Table 4-1 lists the test points and functional descriptions. All pins of the device are broken out to test points on
the EVM.
Table 4-1. Test Points
Test Point
Number
Test Point
Silkscreen Label
TP1
CT
TP2
VDD
TP3
RESET
TP4
MR
TP5
GND
Function
Description
Connection to CT pin
Allows user to monitor the CT pin. This pin charges up
according to the CT pin configuration. The CT capacitor
sets the reset delay.
Connection to VDD pin
Allows user to monitor the VDD pin. The VDD pin connects
to the input power supply.
Connection to RESET pin
Allows user to monitor the RESET output pin.
Connection to MR pin
Allows user to monitor the logic level of the manual reset
pin. Logic low on MR forces a reset.
Connection to GND pin.
Allows user to connect to the ground plane.
4.2 EVM Jumpers
Table 4-2 lists the jumpers on the TPS3840EVM. As ordered, the EVM will have five jumpers installed.
Table 4-2. List of Onboard Jumpers
Jumper
Default Connection
J1
Shorted
Both pins on J1 are connected together. Connect either pin on jumper J1 to the input power
supply.
J2
Closed
Connect a shunt jumper to jumper J2 to use R1 as the pull-up resistor on the RESET output
pin.
J3
Shorted
Both pins on J3 are connected together. Use either pin on jumper J3 to monitor the RESET
output pin.
J4
J5
J6
Description
Jumper J4 configures the CT pin to set the reset delay. Connect a shunt jumper to pin 2 and
pin 3 of jumper J4 to use C2 as the delay capacitor for the CT pin. Connect shunt jumper to
Closed (pin 2, pin 3)
pin 1 and pin 2 of jumper J4 to use C3 as the delay capacitor. Remove shunt jumper from
jumper J4 to set the default fixed delay of 50 µs (maximum).
Shorted
Open
Both pins on J5 are connected together. Use either pin on jumper J5 as the ground
connection.
Jumper J6 configures the manual reset pin. Remove shunt jumper from J6 and leave floating
for normal operation. Connect shunt jumper to J6 to force a reset. Pin 1 of jumper J6 can
also be connected to a control signal to set the logic level on MR pin. If pin 1 on jumper J6 is
logic low, the device remains in reset.
SNVU611A – DECEMBER 2018 – REVISED MAY 2021
Submit Document Feedback
TPS3840EVM Voltage Supervisor User Guide
Copyright © 2021 Texas Instruments Incorporated
9
www.ti.com
EVM Setup and Operation
5 EVM Setup and Operation
This section describes the functionality and operation of the TPS3840EVM. The user should read the TPS3840
datasheet for electrical characteristics of the device.
5.1 Input Power (VDD)
The VDD supply is connected through the J1 header on board. Both pins of jumper J1 are connected together so
power can be applied to either pin. Supply voltage is dependent on what the user wants to monitor, but the range
is 1.6 V to 10 V. Table 5-1 details the nominal supply and typical threshold voltage.
Table 5-1. Nominal Supply and Typical Threshold Voltages
Device
Nominal Supply Voltage (V)
Typical Threshold Voltage (V)
TPS3840DL29
2.9
2.9 ± 1%
5.1.1 Manual Reset ( MR)
The TPS3840 devices offers a manual reset pin that is utilized via jumper J6. If a shunt jumper is placed on
jumper J6, the RESET pin is asserted and forced into a low state. After the shunt jumper is removed and
VDD is above its reset threshold, MR returns to a logic high due to the internal pull-up resistor, and RESET is
deasserted to logic high after the user-defined delay expires. If jumper J6 is left floating, the device operates
normally as the MR pin defaults to logic high. Pin 1 of jumper J6 can also be connected to a control signal to
set the logic level on MR pin. If pin 1 on jumper J6 is logic low, the device asserts a reset. There is also a test
point TP4 connected directly to the MR pin in case the user wants to monitor the MR pin. See Figure 5-1 through
Figure 5-5.
MR
MR
MR Deassertion Delay (tMR_tD) = 7.44 µs
MR Assertion Delay (tMR_RES) = 384 ns
RESET
RESET
Figure 5-1. TPS3840EVM RESET Asserted Due to
MR Pulled Low
Figure 5-2. TPS3840EVM RESET Deasserted Due
to MR Pulled High, With Delay tD, CT Floating
5.2 Monitoring Voltage on VDD
The TPS3840 device monitors voltage via the VDD pin. The EVM provides jumper J1 and test point TP2 for
connecting the power supply input to the VDD pin. If the voltage on this pin drops below VIT, RESET is asserted
low. The VDD pin is connected internally to a comparator through an internal resistor divider at the positive input
and the negative input is connected to an internal reference. The internal resistor divider is set to provide the
input voltage threshold to cause a reset, VIT-, that corresponds to the chosen device variant. Please see the
Device Comparison Table in the TPS3840 Datasheet for more information on the different device variants.
Upon startup, the TPS3840 requires VDD to be above VDD (MIN) = 1.6 V for a maximum of 500 µs before the
RESET output is in the correct logic state. Figure 5-3 shows the actual startup delay may be much shorter than
the maximum of 500 µs especially in the case when VDD is above VDD (MIN) = 1.6 V but below VIT- + VHYS
because this case does not require the additional RESET time delay (tD) for RESET to transition to logic high like
in the case when VDD is above VIT- + VHYS. The startup delay when VDD is above VIT- + VHYS must account for
the RESET time delay (tD). The TPS3840 has built-in glitch immunity so voltage transients on VDD are ignored
if the pulse duration is 10 µs or less as shown in Figure 5-4. The glitch immunity specification depends on the
amplitude of the voltage transient and the operating conditions. Please see the Glitch Immunity specification in
the Timing Requirements section of the TPS3840 Datasheet for more detailed information.
10
TPS3840EVM Voltage Supervisor User Guide
SNVU611A – DECEMBER 2018 – REVISED MAY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
EVM Setup and Operation
www.ti.com
VDD
Glitch Immunity VIT- (tGI_VIT-) = 10 µs
VDD
Startup Delay (tSTRT) = 62 µs
RESET
RESET
Figure 5-3. TPS3840EVM Startup Delay Time (tSTRT)
with VDD = 1.6 V and CT Floating
Figure 5-4. TPS3840EVM Glitch Immunity
5.3 Reset Output ( RESET )
The TPS3840EVM comes populated with TPS3840DL29 device variant which has open-drain, active-low output
topology for the RESET pin. The other device variants provide different output topolgies and can be used on
this EVM. Note: if using a TPS3840 device variant with push-pull output topology, the pull-up resistor must be
disconnected by leaving jumper J2 open. The EVM provides a jumper J3 and a test point TP3 connected directly
to the RESET pin for monitoring and/or interfacing to other devices. The reset signal will be asserted low when
MR is pulled low or when the voltage on the VDD pin falls below VIT-. When the voltage on VDD rises higher
than the hysteresis voltage above the threshold voltage, and the MR pin is pulled high or floating, the reset pins
will deassert and remain deasserted until a reset condition occurs again.
5.4 Reset Time Delay Programming (program tD via CT)
The TPS3840 device has two options for setting the RESET time delay: connect CT pin to a capacitor to GND,
or leave CT pin floating. The reset time delay can be set to a minimum value of 50 µs by leaving the CT pin
floating, or a maximum value of approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time
delay (tD) can be programmed to any value within the range by connecting a capacitor no larger than 10 µF
between CT pin and GND. The relationship between external capacitor (CCT_EXT) at CT pin and the RESET time
delay is given by Equation 1.
tD = -ln (0.29) x RCT x CCT_EXT + tD (no cap)
(1)
Equation 1 is simplified to Equation 2 by plugging RCT and TD(no cap) given in the Electrical Characteristics Table
in TPS3840 Datasheet
tD = 618937 x CCT_EXT + 50 µs
(2)
Equation 3 solves for external capacitor value (CCT_EXT)
CCT_EXT = (tD- 50 µs) ÷ 618937
(3)
The recommended maximum delay capacitor for the TPS3840 is limited to 10 µF as this ensures there is
enough time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs,
the previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition
before the delay capacitor discharges completely, the delay capacitor will begin charging from a voltage above
zero and the reset delay will be shorter than expected. Larger delay capacitors can be used so long as the
capacitor has enough time to fully discharge during the duration of the voltage fault.
The EVM provides the jumper J4 to configure the CT pin and test point TP1 to monitor the CT pin. Place a
shunt jumper on pin 2 (middle pin) and pin 3 (left pin) of jumper J4 to connect CT to delay capacitor C2. This
connects the CT pin to a 1-µF capacitor to set the RESET delay (tD) to ~619 ms as shown in Figure 5-5. Or
place a shunt jumper on pin 1 (right pin) and pin 2 (middle pin) of jumper J4 to connect CT to delay capacitor
C3. This connects the CT pin to a 0.01-µF capacitor to set the RESET delay (tD) to ~6.2 ms as shown in Figure
5-6. By removing the shunt jumper from jumper J4, the RESET time delay defaults to the minimum value of 50
µs. Figure 5-7 shows the actual delay with no capacitor may be shorter than the typical value of 50 µs. If using a
different delay capacitor, the capacitor must be ≥ 100 pF to be recognized.
SNVU611A – DECEMBER 2018 – REVISED MAY 2021
Submit Document Feedback
TPS3840EVM Voltage Supervisor User Guide
Copyright © 2021 Texas Instruments Incorporated
11
Revision History
www.ti.com
VDD
VDD
Reset Delay (tD) = 5.8 ms
Reset Delay (tD)= 654 ms
RESET
RESET
Figure 5-5. TPS3840EVM RESET Delay Time (tD)
with CT Tied to GND Through 1-µF Capacitor
Figure 5-6. TPS3840EVM RESET Delay Time (tD)
with CT Tied to GND Through 0.01-µF Capacitor
VDD
Reset Delay (tD) = 22 µs
RESET
Figure 5-7. TPS3840EVM RESET Delay Time (tD) with CT Floating
6 Revision History
Changes from Revision * (December 2018) to Revision A (March 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................2
• Time delay consistent with the datasheet 80 µs to 50 µs................................................................................. 11
12
TPS3840EVM Voltage Supervisor User Guide
SNVU611A – DECEMBER 2018 – REVISED MAY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.
www.ti.com
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
2
www.ti.com
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
3
www.ti.com
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
4
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
www.ti.com
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
5
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
工商网监
湘ICP备2023018690号
