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TPS386000RGPR

TPS386000RGPR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    VQFN-20_4X4MM-EP

  • 描述:

    IC SUPERVISOR 4 CHANNEL 20QFN

  • 数据手册
  • 价格&库存
TPS386000RGPR 数据手册
Order Now Product Folder Support & Community Tools & Software Technical Documents Reference Design TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 TPS386000 and TPS386040 Quad Supply Voltage Supervisors With Adjustable Delay and Watchdog Timer 1 Features 3 Description • • The TPS3860x0 family of supply voltage supervisors (SVSs) can monitor four power rails that are greater than 0.4 V and one power rail less than 0.4 V (including negative voltage) with a 0.25% (typical) threshold accuracy. Each of the four supervisory circuits (SVS-n) assert a RESETn or RESETn output signal when the SENSEm input voltage drops below the programmed threshold. With external resistors, the threshold of each SVS-n can be programmed (where n = 1, 2, 3, 4 and m = 1, 2, 3, 4L, 4H). 1 • • • • • • • • • • Four Independent Voltage Supervisors Channel 1: – Adjustable Threshold Down to 0.4 V – Manual Reset (MR) Input Channels 2, 3: – Adjustable Threshold Down to 0.4 V Channel 4: – Adjustable Threshold at Any Positive or Negative Voltage – Window Comparator Adjustable Delay Time: 1.4 ms to 10 s Threshold Accuracy: 0.25% Typical Very Low Quiescent Current: 11 μA Typical Watchdog Timer With Dedicated Output Well-Controlled Output During Power Up TPS386000: Open-Drain RESETn and WDO TPS386040: Push-Pull RESETn and WDO Package: 4-mm × 4-mm, 20-Pin VQFN Each SVS-n has a programmable delay before releasing RESETn or RESETn. The delay time can be set independently for each SVS from 1.4 ms to 10 s through the CTn pin connection. Only SVS-1 has an active-low manual reset (MR) input; a logic-low input to MR asserts RESET1 or RESET1. SVS-4 monitors the threshold window using two comparators. The extra comparator can be configured as a fifth SVS to monitor negative voltage with voltage reference output VREF. The TPS3860x0 has a very low quiescent current of 11 μA (typical) and is available in a small, 4-mm x 4mm, VQFN-20 package. 2 Applications • • • • • Device Information(1) All DSP and Microcontroller Applications All FPGA and ASIC Applications Telecom and Wireless Infrastructure Industrial Equipment Analog Sequencing PART NUMBER TPS3860x0 PACKAGE VQFN (20) BODY SIZE (NOM) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. VMON(2) VMON(3) VMON(4) VDD3 VDD4 VDD1 VDD RS1H MR VMON(1) VDD2 TPS386000 Typical Application Circuit: Monitoring Supplies for an FPGA TPS386000 RS2H VMON(2) SENSE1 RESET1 SENSE2 RESET2 SENSE3 RESET3 SENSE4L RESET4 SENSE4H WDO RST RS3H VMON(3) Microprocessor DSP FPGA RS4H WDI GPIO CT4 RS4L VREF CT3 RS3L CT2 RS2L GND RS1L CT1 VMON(4) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 7 8 1 1 1 2 4 6 Absolute Maximum Ratings ..................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Timing Requirements ................................................ 8 Switching Characteristics .......................................... 8 Typical Characteristics ............................................ 14 Parameter Measurement Information ................ 18 Detailed Description ............................................ 19 8.1 Overview ................................................................. 19 8.2 Functional Block Diagrams ..................................... 20 8.3 Feature Description................................................. 22 8.4 Device Functional Modes........................................ 23 9 Application and Implementation ........................ 25 9.1 Application Information............................................ 25 9.2 Typical Application .................................................. 28 10 Power Supply Recommendations ..................... 29 11 Layout................................................................... 30 11.1 Layout Guidelines ................................................. 30 11.2 Layout Example .................................................... 30 12 Device and Documentation Support ................. 31 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Device Support .................................................... Documentation Support ....................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 31 31 31 32 32 32 32 13 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (October 2015) to Revision F • Page Changed the text in the Power Supply Recommendations section from: This power supply should be less than 1.8 V in normal operation to: This power supply should not be less than 1.8 V in normal operation............................................ 29 Changes from Revision D (September 2013) to Revision E Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 • Changed Features bullets about Channel 1, 2, 3, and 4 ...................................................................................................... 1 • Changed all references of VCC (and ICC) to VDD ( and IDD) throughout the document ............................................................ 4 • Changed the description of SENSE4L pin function ............................................................................................................... 4 • Changed the description of SENSE4H pin function .............................................................................................................. 4 • Changed the description of MR pin function ......................................................................................................................... 4 • Changed the description of WDI pin function ........................................................................................................................ 4 • Moved ESD ratings from the Absolute Maximum Ratings table to the ESD Ratings table.................................................... 6 • Deleted the Dissipation Ratings table and added the Thermal Information table ................................................................. 6 • Moved timing and switching parameters (tW, tD, tWDT) from the Electrical Characteristics table to the respective Timing Requirements and Switching Characteristics tables .................................................................................................. 8 • Changed the x-axis title notation from CT to CTn in the TPS386040 RESETn Time-out Period vs CTn graph ................. 14 • Changed the Watchdog Timer (WDT) Truth Table; deleted RESET condition column heading ........................................ 24 • Changed title of SENSE INPUT section to Undervoltage Detection ................................................................................... 25 • Changed Equation 1, Equation 2, and Equation 3 VCC notations to VMON.......................................................................... 25 • Changed title of Window Comparator section to Undervoltage and Overvoltage Detection ............................................... 25 • Changed VCC4 reference in first paragraph of Undervoltage and Overvoltage Detection section to VMON(4) .................... 25 • Changed Equation 4 and Equation 5 VCC4 references to VMON(4)....................................................................................... 25 2 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 • Changed the SVS-4: Window Comparator image ............................................................................................................... 25 • Added VCC to VMON(4) in the Window Comparator Operation image ................................................................................... 26 • Changed title of Sensing Voltage Less Than 0.4 V to Sensing a Negative Voltage............................................................ 26 • Changed Equation 6 and Equation 7 references to VCC4 to VMON(4)................................................................................... 26 • Changed the SVS4: Negative Voltage Sensing image ........................................................................................................ 26 Changes from Revision C (August 2011) to Revision D • Page Deleted TPS386020 and TPS386060 devices from data sheet............................................................................................. 1 Changes from Revision B (March 2011) to Revision C • Page Changed Figure 31............................................................................................................................................................... 21 Changes from Revision A (January 2010) to Revision B Page • Changed data sheet title......................................................................................................................................................... 1 • Changed Features bullets ...................................................................................................................................................... 1 • Changed Applications bullets ................................................................................................................................................. 1 • Changed first sentence of second paragraph in Description text........................................................................................... 1 • Changed low quiescent current value in last paragraph of Description text from 12µA to 11µA........................................... 1 • Changed front-page typical application circuit figure.............................................................................................................. 1 • Added sentence to pin 6 description in Pin Assignments table.............................................................................................. 4 • Changed last sentence of pin 13 description in Pin Assignments table................................................................................. 4 • Added text to first sentence of first paragraph of General Description section. ................................................................... 22 • Changed link in Window Comparator section to new Figure 32 .......................................................................................... 25 • Deleted typo in Equation 4 and moved Equation 4 to Window Comparator section............................................................ 25 • Deleted typo in Equation 5 and moved Equation 5 to Window Comparator section............................................................ 25 • Added Figure 32 ................................................................................................................................................................... 25 • Changed link in Sensing Voltage Less Than 0.4V section to new Figure 34....................................................................... 26 • Added Figure 34 ................................................................................................................................................................... 26 • Changed caption for Figure 35 ............................................................................................................................................. 28 Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 3 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com 5 Pin Configuration and Functions WDI WDO RESET4 RESET3 RESET2 20 19 18 17 16 RGP Package 20-Pin VQFN Top View MR 1 15 RESET1 CT4 2 14 VDD CT3 3 13 VREF CT2 4 12 GND CT1 5 11 NC 7 8 9 10 SENSE4L SENSE3 SENSE2 SENSE1 SENSE4H 6 Thermal Pad Pin Functions PIN NAME NO. I/O DESCRIPTION VDD 14 I GND 12 — Supply voltage. TI recommends connecting a 0.1-μF ceramic capacitor close to this pin. SENSE1 10 I Monitor voltage input to SVS-1 When the voltage at this terminal drops below the threshold voltage (VITN), RESET1 is asserted. SENSE2 9 I Monitor voltage input to SVS-2 When the voltage at this terminal drops below the threshold voltage (VITN), RESET2 is asserted. SENSE3 8 I Monitor voltage input to SVS-3 When the voltage at this terminal drops below the threshold voltage (VITN), RESET3 is asserted. SENSE4L 7 I Falling monitor voltage input to SVS-4. When the voltage at this terminal drops below the threshold voltage (VITN), RESET4 is asserted. SENSE4H 6 I Rising monitor voltage input to SVS-4. When the voltage at this terminal exceeds the threshold voltage (VITP), RESET4 is asserted. This pin can also be used to monitor the negative voltage rail in combination with VREF pin. Connect to GND if not being used. CT1 5 — Reset delay programming pin for SVS-1 CT2 4 — Reset delay programming pin for SVS-2 CT3 3 — Reset delay programming pin for SVS-3 CT4 2 — Reset delay programming pin for SVS-4 Ground Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor, or leaving it open, selects a fixed delay time (see the Electrical Characteristics). Connecting a capacitor > 220 pF between this pin and GND selects the programmable delay time (see the Reset Delay Time section). VREF 13 O Reference voltage output. By connecting a resistor network between this pin and the negative power rail, SENSE4H can monitor the negative power rail. This pin is intended to only source current into resistor(s). Do not connect resistor(s) to a voltage higher than 1.2 V. Do not connect only a capacitor. MR 1 I Manual reset input for SVS-1. Logic low level of this pin asserts RESET1. WDI 20 I Watchdog timer (WDT) trigger input. Inputting either a positive or negative logic edge every 610 ms (typical) prevents WDT time out at the WDO or WDO pin. Timer starts from releasing event of RESET1. NC 11 — Not internal connection. TI recommends connecting this pin to the GND pin (pin 12), which is next to this pin. PAD — This pad is the IC substrate. This pad must be connected only to GND or to the floating thermal pattern on the printed-circuit board (PCB). Thermal Pad 4 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 Pin Functions (continued) PIN NAME NO. I/O DESCRIPTION TPS386000 RESET1 15 O Active low reset output of SVS-1 RESET2 16 O Active low reset output of SVS-2 RESETn is an open-drain output pin. When RESETn is asserted, this pin remains in a lowimpedance state. When RESETn is released, this pin goes to a high-impedance state after the delay time programmed by CTn. A pullup resistor to VDD or another voltage source is required. RESET3 17 O Active low reset output of SVS-3 RESET4 18 O Active low reset output of SVS-4 WDO 19 O Watchdog timer output. This is an open-drain output pin. When WDT times out, this pin goes to a low-impedance state to GND. If there is no WDT time-out, this pin stays in a high-impedance state. RESET1 15 O Active low reset output of SVS-1 RESET2 16 O Active low reset output of SVS-2 RESET3 17 O Active low reset output of SVS-3 RESET4 18 O Active low reset output of SVS-4 WDO 19 O Watchdog timer output. This is a push-pull output pin. When WDT times out, this pin goes to logic low. If there is no WDT time-out, this pin stays in logic high. TPS386040 RESETn is a push-pull logic buffer output pin. When RESETn is asserted, this pin remains logic low. When RESETn is released, this pin goes to logic high after the delay time programmed by CTn. Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 5 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings Over operating junction temperature range, unless otherwise noted. (1) Voltage MIN MAX Input, VDD –0.3 7 CT pin, VCT1, VCT2, VCT3, VCT4 –0.3 VDD + 0.3 VRESET1, VRESET2, VRESET3, VRESET4, VMR, VSENSE1, VSENSE2, VSENSE3, VSENSE4L, VSENSE4H, VWDI, VWDO –0.3 7 Current RESETn , RESETn, WDO, WDO, VREF pin Power dissipation Continuous total Temperature (1) (2) UNIT V 5 mA See Thermal Information table Operating virtual junction, TJ (2) –40 150 Operating ambient, TA –40 125 Storage, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. As a result of the low dissipated power in this device, it is assumed that TJ = TA. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Over operating junction temperature range (unless otherwise noted). MIN VDD VSENSE (1) NOM MAX UNIT 1.8 6.5 V 0 VDD V WDI(HI) 0.7VDD VDD V WDI(LO) 0 0.3VDD V VMR 0 VDD V CTn 0.22 1000 nF RPULL-UP 6.5 100 10000 kΩ TJ –40 25 125 °C (1) All sense inputs. 6.4 Thermal Information TPS3860x0 THERMAL METRIC (1) RGP (VQFN) UNIT 20 PINS RθJA Junction-to-ambient thermal resistance 46 °C/W RθJC(top) Junction-to-case (top) thermal resistance 52.8 °C/W RθJB Junction-to-board thermal resistance 22.4 °C/W ψJT Junction-to-top characterization parameter 1.3 °C/W ψJB Junction-to-board characterization parameter 22.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 4.3 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 6.5 Electrical Characteristics Over the operating temperature range of TJ = –40°C to 125°C, 1.8 V < VDD < 6.5 V, RRESETn (n = 1, 2, 3, 4) = 100 kΩ to VDD (TPS386000 only), CRESETn (n = 1, 2, 3, 4L, 4H) = 50 pF to GND, RWDO = 100 kΩ to VDD, CWDO = 50 pF to GND, VMR = 100 kΩ to VDD, WDI = GND, and CTn (n = 1, 2, 3, 4) = open, unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER VDD TEST CONDITIONS Input supply range IDD MIN TYP 1.8 Supply current (current into VDD pin) Power-up reset voltage (2) (3) MAX 6.5 VDD = 3.3 V, RESETn or RESETn not asserted, WDI toggling (1), no output load, and VREF open 11 VDD = 6.5 V, RESETn or RESETn not asserted, WDI toggling (1), no output load, and VREF open 13 22 UNIT V 19 μA 0.9 V VITN Negative-going input threshold voltage SENSE1, SENSE2, SENSE3, SENSE4L 396 400 404 mV VITP Positive-going input threshold voltage SENSE4H 396 400 404 mV VHYSN Hysteresis (positive-going) on VITN SENSE1, SENSE2, SENSE3, SENSE4L 3.5 10 mV VHYSP Hysteresis (negative-going) on VITP SENSE4H 3.5 10 mV ISENSE Input current at SENSEm pin VSENSEm = 0.42 V –25 ±1 +25 nA CT1 CCT1 > 220 pF, VCT1 = 0.5 V (4) 245 300 355 CT2, CT3, CT4 CCTn > 220 pF, VCTn = 0.5 V (4) 235 300 365 CCTn > 220 pF 1.18 1.238 1.299 V 0.3VDD V ICT CTn pin charging current VTH(CTn) CTn pin threshold VIL MR and WDI logic low input VIH MR and WDI logic high input VOL (max) = 0.2 V, IRESETn = 15 μA 0 0.7VDD V IOL = 1 mA 0.4 SENSEn = 0 V, 1.3 V < VDD < 1.8 V, IOL = 0.4 mA (2) 0.3 Low-level WDO output voltage IOL = 1 mA 0.4 High-level RESETn or RESETn output voltage TPS386040 only IOL = –1 mA VDD – 0.4 High-level WDO output voltage TPS386040 only IOL = –1 mA VDD – 0.4 SENSEn = 0 V, 1.3 V < VDD < 1.8 V, IOL = –0.4 mA (2) VDD – 0.3 ILKG RESETn, RESETn, WDO, and WDO leakage current TPS386000 only VREF CIN Low-level RESETn or RESETn output voltage VOL VOH (1) (2) (3) (4) VRESETn = 6.5 V, RESETn, RESETn, WDO, and WDO are logic high –300 Reference voltage output 1 μA < IVREF < 0.2 mA (source only, no sink) 1.18 Input pin capacitance CTn: 0 V to VDD, other pins: 0 V to 6.5 V nA V V V V 1.2 300 nA 1.22 V 5 pF Toggling WDI for a period less than tWDT negatively affects IDD. These specifications are beyond the recommended VDD range, and only define RESETn or RESETn output performance during VDD ramp up. The lowest supply voltage (VDD) at which RESETn or RESETn becomes active; tRISE(VDD) ≥ 15 μs/V. CTn (where n = 1, 2, 3, or 4) are constant current charging sources working from a range of 0 V to VTH(CTn), and the device is tested at VCTn = 0.5 V. For ICT performance between 0 V and VTH(CTn), see Figure 28. Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 7 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com 6.6 Timing Requirements Over the operating temperature range of TJ = –40°C to 125°C, 1.8 V < VDD < 6.5 V, RRESETn (n = 1, 2, 3, 4) = 100 kΩ to VDD (TPS386000 only), CRESETn (n = 1, 2, 3, 4L, 4H) = 50 pF to GND, RWDO = 100 kΩ to VDD, CWDO = 50 pF to GND, VMR = 100 kΩ to VDD, WDI = GND, and CTn (n = 1, 2, 3, 4) = open, unless otherwise noted. Nominal values are at TJ = 25°C. MIN Input pulse width to SENSEm and MR pins tW TYP MAX UNIT SENSEm: 1.05 VITN → 0.95 VITN or 0.95 VITP → 1.05 VITP 4 μs MR: 0.7 VDD → 0.3 VDD 1 ns 6.7 Switching Characteristics Over the operating temperature range of TJ = –40°C to 125°C, 1.8 V < VDD < 6.5 V, RRESETn (n = 1, 2, 3, 4) = 100 kΩ to VDD (TPS386000 only), CRESETn (n = 1, 2, 3, 4L, 4H) = 50 pF to GND, RWDO = 100 kΩ to VDD, CWDO = 50 pF to GND, VMR = 100 kΩ to VDD, WDI = GND, and CTn (n = 1, 2, 3, 4) = open, unless otherwise noted. Typical values are at TJ = 25°C. PARAMETER TEST CONDITIONS tD tWDT Watchdog timer time-out period (1) (1) MIN TYP MAX 14 20 24 225 300 375 450 600 750 CTn = Open RESETn or RESETn delay time CTn = VDD UNIT ms ms Start from RESET1 or RESET1 release or last WDI transition. VDD 0.9 V t SENSE1 Vhys– VIT– t MR t RESET1 td td t Figure 1. SVS-1 Timing Diagram 8 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 VCC 0.9 V t SENSE2 Vhys– VIT– t RESET2 td t Figure 2. SVS-2 Timing Diagram VDD 0.9 V t SENSE3 Vhys– VIT– t RESET3 td td t Figure 3. SVS-3 Timing Diagram Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 9 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com VDD 0.9 V t SENSE4L VHYS– VIT– t SENSE4H VIT+ VHYS+ t RESET4 tD t Figure 4. SVS-4 Timing Diagram 10 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 MR t RESET1 t WDI t (Internal timer) tWDT Timeout Zero t WDO t Figure 5. WDT Timing Diagram Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 11 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com Event 1 WDI Event 2 Event 3 t RESET1 t MR = WDO tWDT t (Internal timer) t Figure 6. Legacy WDT Configuration Timing Diagram 12 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 WDI Event 1 RESET1 MR = WDO tD (Internal timer) Figure 7. Enlarged View of Event 1 from Figure 6 Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 13 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com 6.8 Typical Characteristics At TA = 25°C, and VDD = 3.3 V, with both options (TPS386000 and TPS386040) having the same characteristics, unless otherwise noted. 20 10000 +125°C +85°C 16 +105°C RESETn Delay (ms) 18 IDD (mA) 14 12 10 0°C 8 +25°C -40°C 6 4 2 +85°C 100 +25°C 0°C +125°C 10 -40°C NOTE: UVLO released at approximately 1.5V. 0 0 1 2 3 4 VDD (V) 5 6 1 0.0001 7 Figure 8. TPS386040 Supply Current vs Supply Voltage 0.001 0.01 CTn (mF) 0.1 1 Figure 9. TPS386040 RESETn Time-out Period vs CTn 25 360 CT1 CT3 340 CT2 15 RESETn Delay (ms) 20 RESETn Delay (ms) 1000 CT4 10 5 320 CT1 CT3 300 CT2 280 CT4 260 0 240 -50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 Temperature (°C) 10 30 50 70 90 110 130 Temperature (°C) Figure 10. TPS386040 (CTn = Open) RESETn Time-out Period vs Temperature Figure 11. TPS386040 (CTn = VDD) RESETn Time-out Period vs Temperature 700 550 680 660 450 CT3 WDO Delay (ms) RESETn Delay (ms) 500 CT4 400 CT1 CT2 350 640 600 580 VDD = 6.5 V 560 540 300 NOTE: These curves contain variance of capacitor values. 520 500 250 -50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 Figure 12. TPS386040 (CTn = 0.1 µF) RESETn Time-out Period vs Temperature Submit Documentation Feedback 10 30 50 70 90 110 130 Temperature (°C) Temperature (°C) 14 VDD = 1.8 V VDD = 3.3 V 620 Figure 13. TPS386040 WDO Time-out Period vs Temperature Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 Typical Characteristics (continued) At TA = 25°C, and VDD = 3.3 V, with both options (TPS386000 and TPS386040) having the same characteristics, unless otherwise noted. 408 SENSE4H 10 SENSE4L SENSE2 SENSE1 SENSE3 1 VITN, (VITN + VHYSN) (mV) SENSEn Pulse Width (ms) 100 406 VITN + VHYSN, VDD = 6.5 V 404 VITN + VHYSN, VDD = 1.8 V 402 VITN + VHYSN, VDD = 3.3 V VITN, VDD = 6.5 V 400 VITN, VDD = 1.8 V VITN, VDD = 3.3 V 398 396 0.1 0.1 1 10 -50 100 -30 -10 10 Overdrive (%) 30 50 70 90 110 130 Temperature (°C) See Figure 29 for measurement technique Figure 14. TPS386040 SENSEn Minimum Pulse Width vs SENSEn Threshold Overdrive Voltage Figure 15. TPS386040 SENSE1 Threshold Voltage vs Temperature 408 406 VITN, (VITN + VHYSN) (mV) VITN, (VITN + VHYSN) (mV) 408 VITN + VHYSN, VDD = 6.5 V 404 VITN + VHYSN, VDD = 1.8 V 402 VITN + VHYSN, VDD = 3.3 V 400 VITN, VDD = 1.8 V VITN, VDD = 3.3 V 398 406 VITN + VHYSN, VDD = 3.3 V 404 VITN + VHYSN, VDD = 1.8 V 402 VITN, VDD = 3.3 V 400 VITN, VDD = 6.5 V 398 VITN, VDD = 1.8 V VITN, VDD = 6.5 V 396 396 -50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130 Temperature (°C) Temperature (°C) Figure 16. TPS386040 SENSE2 Threshold Voltage vs Temperature Figure 17. TPS386040 SENSE3 Threshold Voltage vs Temperature 408 404 406 VITN + VHYSN, VDD = 3.3 V VITP, (VITP + VHYSP) (mV) VITN, (VITN + VHYSN) (mV) VITN + VHYSN, VDD = 6.5 V VITN + VHYSN, VDD = 6.5 V 404 VITN + VHYSN, VDD = 1.8 V 402 VITN, VDD = 1.8 V 400 VITN, VDD = 6.5 V VITN, VDD = 3.3 V 398 402 VITP + VHYSP, VDD = 3.3 V VITP + VHYSP, VDD = 6.5 V 400 VITP, VDD = 1.8 V 398 VITP + VHYSP, VDD = 1.8 V 396 VITP, VDD = 6.5 V 394 VITP, VDD = 3.3 V 396 392 -50 -30 -10 10 30 50 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130 Temperature (°C) Temperature (°C) Figure 18. TPS386040 SENSE4L Threshold Voltage vs Temperature Figure 19. TPS386040 SENSE4H Threshold Voltage vs Temperature Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 15 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com Typical Characteristics (continued) 0.200 0.200 0.180 0.180 Low-Level Output Voltage (V) Low-Level Output Voltage (V) At TA = 25°C, and VDD = 3.3 V, with both options (TPS386000 and TPS386040) having the same characteristics, unless otherwise noted. 0.160 0.140 VDD = 1.8 V, 25°C 0.120 0.100 VDD = 3.3 V, 25°C 0.080 0.060 0.040 0.020 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VDD = 1.8 V 0.140 VDD = 3.3 V 0.120 0.100 0.080 0.060 VDD = 6.5 V 0.040 0.020 VDD = 6.5 V, 25°C 0 0.160 0 0.9 -50 1.0 -30 -10 10 30 50 70 90 110 130 Temperature (°C) Output Sink Current (mA) Figure 20. Output Voltage Low vs Output Current Figure 21. Output Voltage Low at 1 mA vs Temperature 0 0 VDD = 6.5 V, 25°C VDD = 6.5 V -0.05 VDD = 1.8 V, 25°C -0.100 VDD - VOH (V) VDD - VOH (V) -0.050 VDD = 3.3 V, 25°C -0.150 -0.200 -0.10 VDD = 3.3 V -0.15 VDD = 1.8 V -0.20 -0.250 -0.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -50 -30 -10 10 30 50 70 90 110 130 Temperature (°C) Output Source Current (mA) Figure 22. Output Voltage High vs Output Current 1.200 Figure 23. Output Voltage High at 1 mA vs Temperature 1.200 0°C 1.198 1.198 1.196 1.196 25°C -40°C 85°C VREF (V) VREF (V) 0°C 105°C 1.194 125°C 25°C 105°C 1.194 125°C 1.192 1.192 1.190 1.190 1.188 1.188 0 50 100 150 200 250 300 350 400 0 50 Figure 24. TPS386040 VREF Output Load Regulation (VDD = 1.8 V) Submit Documentation Feedback 100 150 200 250 300 350 400 Load (μA) Load (μA) 16 85°C 40°C Figure 25. TPS386040 VREF Output Load Regulation (VDD = 3.3 V) Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 Typical Characteristics (continued) At TA = 25°C, and VDD = 3.3 V, with both options (TPS386000 and TPS386040) having the same characteristics, unless otherwise noted. 1.207 1.207 1.205 1.205 Reference Voltage (V) 0°C VREF (V) 1.203 1.201 1.199 -40°C 25°C 85°C 105°C 1.197 1.195 50 100 150 200 250 300 1.201 VDD = 3.3 V 1.199 VDD = 1.8 V 1.197 125°C 0 VDD = 6.5 V 1.203 350 400 Load (μA) 1.195 -50 -30 -10 10 30 50 70 90 110 130 Temperature (°C) Figure 26. TPS386040 VREF Output Load Regulation (VDD = 6.5 V) Figure 27. TPS386040 VREF at 0 µA vs Temperature 0.33 0.32 Current (μA) 0.1 V 0.31 0V 0.3 V 0.5 V 0.30 1.1 V 0.29 0.9 V 0.7 V 0.28 0.27 -50 -30 -10 10 30 50 70 Temperature (°C) 90 110 130 Figure 28. TPS386040 CT1 to CT4 Pin Charging Current vs Temperature Over CT Pin Voltage Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 17 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com 7 Parameter Measurement Information SENSEn Voltage (V) VITN = 0.42V VITN = 0.4V Y1 Z1 Y2 Z2 X1 = Z1 ´ 100 (%) 0.4 X2 = Z2 ´ 100 (%) 0.4 X1 and X2 are overdrive (%) values calculated from actual SENSEn voltage amplitudes measured as Z1 and Z2. YN is the minimum pulse width that gives RESETn or RESETn transition. Greater ZN produces shorter YN. For SENSE4H, this graph should be inverted 180 degrees on the voltage axis. Time Figure 29. Overdrive Measurement Method 18 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 8 Detailed Description 8.1 Overview The TPS3860x0 multi-channel supervisory family of devices combines four complete SVS function sets into one IC, along with a watchdog timer, a window comparator, and negative voltage sensing. The design of each SVS channel is based on the single-channel supervisory device series, TPS3808. The TPS3860x0 is designed to assert RESETn or RESETn signals, as shown in Table 1, Table 2, Table 3, and Table 4. The RESETn or RESETn outputs remain asserted during a user-configurable delay time after the event of reset release (see the Reset Delay Time section). The TPS3860x0 has a very low quiescent current of 11 μA (typical) and is available in a small, 4-mm × 4-mm, 20-Pin VQFN package. Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 19 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com 8.2 Functional Block Diagrams VDD WDO WDI WDT VREF VREF RESET1 SENSE1 Delay 0.4V MR CT1 RESET2 SENSE2 Delay 0.4V CT2 RESET3 SENSE3 Delay 0.4V CT3 RESET4 SENSE4L Delay 0.4V SENSE4H CT4 GND Figure 30. TPS386000 Block Diagram 20 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 Functional Block Diagrams (continued) VDD WDO WDI WDT VREF VREF SENSE1 Delay RESET1 0.4V MR CT1 SENSE2 Delay RESET2 0.4V CT2 SENSE3 Delay RESET3 0.4V CT3 SENSE4L Delay RESET4 0.4V SENSE4H CT4 GND Figure 31. TPS386040 Block Diagram Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 21 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com 8.3 Feature Description 8.3.1 Voltage Monitoring Each SENSEm (m = 1, 2, 3, 4L) pin can be set to monitor any voltage threshold above 0.4 V using an external resistor divider. The SENSE4H pin can be used for any overvoltage detection greater than 0.4 V, or for negative voltage detection using an external resistor divider (see the Sensing a Negative Voltage section). A broad range of voltage threshold and reset delay time adjustments can be supported, allowing these devices to be used in a wide array of applications. The TPS3860x0 is relatively immune to short negative transients on the SENSEn pin. Sensitivity to transients depends on threshold overdrive, as shown in (Figure 14). 8.3.2 Manual Reset The manual reset (MR) input allows external logic signal from other processors, logic circuits, and/or discrete sensors to initiate a device reset. Because MR is connected to SVS-1, the RESET1 or RESET1 pin is intended to be connected to processor(s) as a primary reset source. A logic low at MR causes RESET1 or RESET1 to assert. After MR returns to a logic high and SENSE1 is above its reset threshold, RESET1 or RESET1 is released after the user-configured reset delay time. Unlike the TPS3808 series, the TPS3860x0 does not integrate an internal pullup resistor between MR and VDD. To control the MR function from more than one logic signal, the logic signals can be combined by wired-OR into the MR pin using multiple NMOS transistors and one pullup resistor. 8.3.3 Watchdog Timer The TPS3860x0 provides a watchdog timer with a dedicated watchdog error output, WDO or WDO. The WDO or WDO output enables application board designers to easily detect and resolve the hang-up status of a processor. As with MR, the watchdog timer function of the device is also tied to SVS-1. Figure 5 shows the timing diagram of the WDT function. Once RESET1 or RESET1 is released, the internal watchdog timer starts its countdown. Inputting a logic level transition at WDI resets the internal timer count and the timer restarts the countdown. If the TPS3860x0 fails to receive any WDI rising or falling edge within the WDT period, the WDT times out and asserts WDO or WDO. After WDO or WDO is asserted, the device holds the status with the internal latch circuit. To clear this time-out status, a reset assertion of RESET1 or RESET is required. That is, a negative pulse to MR, a SENSE1 voltage less than VITN, or a VDD power down is required. To reset the processor by WDT time-out, WDO can be combined with RESET1 by using the wired-OR with the TPS386000 option. For legacy applications where the watchdog timer time-out causes RESET1 to assert, connect WDO to MR; see Figure 35 for the connections and see Figure 6 and Figure 7 for the timing diagrams. 22 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 Feature Description (continued) 8.3.4 Reset Output In a typical TPS3860x0 application, RESETn or RESETn outputs are connected to the reset input of a processor (DSP, CPU, FPGA, ASIC, and so forth), or connected to the enable input of a voltage regulator (DC-DC, LDO, and so forth). The TPS386000 provides open-drain reset outputs. Pullup resistors must be used to hold these lines high when RESETn is not asserted, or when RESETn is asserted. By connecting pullup resistors to the proper voltage rails (up to 6.5 V), RESETn or RESETn output nodes can be connected to the other devices at the correct interface voltage levels. The pullup resistor should be no smaller than 10 kΩ to ensure the safe operation of the output transistors. By using wired-OR logic, any combination of RESETn can be merged into one logic signal. The TPS386040 provides pushpull reset outputs. The logic high level of the outputs is determined by the VDD voltage. With this configuration, pullup resistors are not required and some board area can be saved. However, all the interface logic levels should be examined. All RESETn or RESETn connections must be compatible with the VDD logic level. The RESETn or RESETn outputs are defined for VDD voltage higher than 0.9 V. To ensure that the target processor(s) are properly reset, the VDD supply input should be fed by the available power rail as early as possible in application circuits. Table 1, Table 2, Table 3, and Table 4 are truth tables that describe how the outputs are asserted or released. Figure 1, Figure 2, Figure 3, and Figure 4 show the SVS-n timing diagrams. When the conditions are met, the device changes the state of SVS-n from asserted to released after a userconfigurable delay time. However, the transitions from released-state to asserted-state are performed almost immediately with minimal propagation delay. Figure 3 describes the relationship between threshold voltages (VITN and VHYSN) and SENSEm voltage; and all SVS-1, SVS-2, SVS-3, and SVS-4 have the same behavior of Figure 3. 8.4 Device Functional Modes The following tables show the state of the output and the status of the part under various conditions. Table 1. SVS-1 Truth Table OUTPUT STATUS MR = Low CONDITION SENSE1 < VITN RESET1 = Low Reset asserted MR = Low SENSE1 > VITN RESET1 = Low Reset asserted MR = High SENSE1 < VITN RESET1 = Low Reset asserted RESET1 = High Reset released after delay MR = High SENSE1 > VITN Table 2. SVS-2 Truth Table CONDITION OUTPUT STATUS SENSE2 < VITN RESET2 = Low Reset asserted SENSE2 > VITN RESET2 = High Reset released after delay Table 3. SVS-3 Truth Table CONDITION OUTPUT STATUS SENSE3 < VITN RESET3 = Low Reset asserted SENSE3 > VITN RESET3 = High Reset released after delay Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 23 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com Table 4. SVS-4 Truth Table OUTPUT STATUS SENSE4L < VITN CONDITION SENSE4H > VITP RESET4 = Low Reset asserted SENSE4L < VITN SENSE4H < VITP RESET4 = Low Reset asserted SENSE4L > VITN SENSE4H > VITP RESET4 = Low Reset asserted RESET4 = High Reset released after delay SENSE4L > VITN SENSE4H < VITP Table 5. Watchdog Timer (WDT) Truth Table CONDITION 24 WDO WDO RESET1 WDI PULSE INPUT OUTPUT STATUS Low High Asserted Toggling WDO = low Remains in WDT time-out Low High Asserted 610 ms after last WDI↑ or WDI↓ WDO = low Remains in WDT time-out Low High Released Toggling WDO = low Remains in WDT time-out Low High Released 610 ms after last WDI↑ or WDI↓ WDO = low Remains in WDT time-out High Low Asserted Toggling WDO = high Normal operation High Low Asserted 610 ms after last WDI↑ or WDI↓ WDO = high Normal operation High Low Released Toggling WDO = high Normal operation High Low Released 610 ms after last WDI↑ or WDI↓ WDO = low Enters WDT timeout Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Undervoltage Detection The SENSEm inputs are pins that allow any system voltages to be monitored. If the voltage at the SENSE1, SENSE2, SENSE3, or SENSE4L pins drops below VITN, then the corresponding reset outputs are asserted. If the voltage at the SENSE4H pin exceeds VITP, then RESET4 or RESET4 is asserted. The comparators have a builtin hysteresis to ensure smooth reset output assertions and deassertions. In noisy applications, it is good analog design practice to place a 1-nF to 10-nF bypass capacitor at the SENSEm input to reduce sensitivity to transients, layout parasitics, and interference between power rails monitored by this device. A typical connection of resistor dividers are shown in Figure 35. All the SENSEm pins can be used to monitor voltage rails down to 0.4 V. Threshold voltages can be calculated using Equation 1 to Equation 3. VMON(1) = (1 + RS1H/RS1L) × 0.4 (V) VMON(2) = (1 + RS2H/RS2L) × 0.4 (V) VMON(3) = (1 + RS3H/RS3L) × 0.4 (V) (1) (2) (3) 9.1.2 Undervoltage and Overvoltage Detection The comparator at the SENSE4H pin has the opposite comparison polarity to the other SENSEm pins. In the configuration shown in Figure 32, this comparator monitors overvoltage of the VMON(4) node; combined with the comparator at SENSE4L, SVS-4 forms a window comparator. VMON(4, VMON(4, = {1+ RS4H/(RS4M + RS4L)} × 0.4 (V) OV) = {1+ (RS4H + RS4M)/RS4L} × 0.4 (V) (4) UV) where • • VMON(4, VMON(4, is the undervoltage threshold. OV) is the overvoltage threshold. UV) (5) VDD (1.8V to 6.5V) VMON(4) (3.0V to 3.6V) RS41H 316kΩ RP4 VDD RESET4 SENSE4L RS41M 8.06kΩ CT4 SENSE4H RS41L 40.2kΩ GND Figure 32. SVS-4: Window Comparator Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 25 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com Application Information (continued) VMON(4)_target2 Overvoltage Limit VMON(4)_target2(HYSP) VDD4 VMON(4)_target1(HYSN) Undervoltage Limit VMON(4)_target1 RESET4 Figure 33. Window Comparator Operation 9.1.3 Sensing a Negative Voltage By using voltage reference output VREF, the SVS-4 comparator can monitor negative voltage or positive voltage lower than 0.4V. Figure 34 shows this usage in an application circuit. SVS-4 monitors the positive and negative voltage power rail (for example, 15-V and –15-V supply to an op amp) and the RESET4 or RESET4 output status continues to be as described in Table 4. RS42H is located at higher voltage position than RS42L. The threshold voltage calculations are shown in Equation 6 and Equation 7. VMON(4, VMON(4, NEG) POS) = (1+RS41H/RS41L) × 0.4 (V) = (1+RS42L/RS42H) × 0.4 – RS42L/RS42H × VREF = 0.4 – [RS42L/RS42H × 0.8 (V)] VDD (1.8V to 6.5V) VMON(4, NEG) VMON(4, POS) (–15V) (+15V) RESET4 SENSE4L RS41L 200kΩ CT4 SENSE4H RS42H 200kΩ RP4 VDD RS41H 7.32MΩ RS42L 3.83MΩ (6) (7) VREF GND Figure 34. SVS4: Negative Voltage Sensing 26 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 Application Information (continued) 9.1.4 Reset Delay Time Each of the SVS-n channels can be configured independently in one of three modes. Table 6 describes the delay time settings. Table 6. Delay Timing Selection CTn CONNECTION DELAY TIME Pullup to VDD 300 ms (typical) Open 20 ms (typical) Capacitor to GND Programmable To select the 300-ms fixed delay time, the CTn pin should be pulled up to VDD using a resistor from 40 kΩ to 200 kΩ. There is a pulldown transistor from CTn to GND that turns on every time the device powers on to determine and confirm CTn pin status; therefore, a direct connection of CTn to VDD causes a large current flow. To select the 20-ms fixed delay time, the CTn pin should be left open. To program a user-defined adjustable delay time, an external capacitor must be connected between CTn and GND. The adjustable delay time can be calculated by the following equation: CCT (nF) = [tDELAY (ms) – 0.5 (ms)] × 0.242 (8) Using this equation, a delay time can be set to between 1.4 ms to 10 s. The external capacitor should be greater than 220 pF (nominal) so that the TPS3860x0 can distinguish it from an open CT pin. The reset delay time is determined by the time it takes an on-chip, precision 300-nA current source to charge the external capacitor to 1.24 V. When the RESETn or RESETn outputs are asserted, the corresponding capacitors are discharged. When the condition to release RESETn or RESETn occurs, the internal current sources are enabled and begin to charge the external capacitors. When the CTn voltage on a capacitor reaches 1.24 V, the corresponding RESETn or RESETn pins are released. A low leakage type capacitor (such as ceramic) should be used, and that stray capacitance around this pin may cause errors in the reset delay time. Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 27 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com 9.2 Typical Application Figure 35 shows a typical application circuit. Sequence: VIN VMON(4) VMON(3) VMON(2) VMON(1) DC-DC LDO VMON(4) EN4 DC-DC LDO VMON(1) EN3 DC-DC LDO VIN VMON(3) VMON(2) RS4H EN2 RP5 RP4 RP3 RP2 RP1 VDD RS3H RS2H RS1H DC-DC LDO MR VREF WDI WDO SENSE1 RESET1 SENSE2 TPS386000 RESET2 SENSE3 RESET3 SENSE4L RESET4 VDD1 VDD2 RESET VDD3 VDD4 DSP CPU FPGA CLK SENSE4H CT1 RS4M CT1 RS4L RS3L RS2L CT2 CT2 CT3 CT3 CT4 GND CT4 RS1L Figure 35. Typical Application Circuit 9.2.1 Design Requirements This design is intended to monitor the voltage rails for an FPGA. Table 7 summarizes the design requirements. Table 7. Design Requirements PARAMETER 28 DESIGN REQUIREMENT VDD 5V VMON(1) 1.8 V –5% VMON(2) 1.5 V –5% VMON(3) 1.2 V –5% VMON(4) 1 V ±5% Approximate start-up time 100 ms Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 9.2.2 Detailed Design Procedure Select the pullup resistors to be 100 kΩ to ensure that VOL ≤ 0.4 V. Use Equation 8 to set CT = 22 nF for all channels to obtain an approximate start-up delay of 100 ms. Select RSnL = 10 kΩ for all channels to ensure DC accuracy. Use Equation 1 through Equation 5 to determine the values of RSnH and RS4M. Using standard 1% resistors, Table 8 shows the results. Table 8. Design Results RESISTOR VALUE (kΩ) RS1H 32.4 RS2H 25.5 RS3H 18.7 RS4H 14.3 RS4M 1 The FPGA does not have a separate watchdog failure input, so a legacy connection is used by connecting WDO to MR. 9.2.3 Application Curves 100 25 CT1 CT3 CT2 15 SENSEn Pulse Width (ms) RESETn Delay (ms) 20 CT4 10 5 0 -50 -30 -10 10 30 50 70 90 110 130 Temperature (°C) SENSE4H 10 SENSE4L SENSE2 SENSE1 SENSE3 1 0.1 0.1 1 10 100 Overdrive (%) See Figure 29 for measurement technique Figure 36. TPS386040 (CTn = Open) RESETn Time-Out Period vs Temperature Figure 37. TPS386040 SENSEn Minimum Pulse Width vs SENSEn Threshold Overdrive Voltage 10 Power Supply Recommendations The TPS386000 can operate from a 1.8-V to a 6.5-V input supply. TI recommends placing a 0.1-µF capacitor placed next to the VDD pin to the GND node. This power supply should not be less than 1.8 V in normal operation to ensure that the internal UVLO circuit does not assert reset. Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 29 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com 11 Layout 11.1 Layout Guidelines Follow these guidelines to lay out the printed-circuit board (PCB) that is used for the TPS3860x family of devices. • Keep the traces to the timer capacitors as short as possible to optimize accuracy. • Avoid long traces from the SENSE pin to the resistor divider. Instead, run the long traces from the RSnH to VMON(n). • Place the VDD decoupling capacitor (CVDD) close to the device. • Avoid using long traces for the VDD supply node. The VDD capacitor (CVDD), along with parasitic inductance from the supply to the capacitor, can form an LC tank and create ringing with peak voltages above the maximum VDD voltage. WDI WDO RESET4 RESET3 RESET2 11.2 Layout Example 20 19 18 17 16 MR 1 15 RESET1 CT4 2 14 VDD CT3 3 13 VREF Thermal Pad 5 11 NC 6 7 8 9 10 SENSE1 CT1 SENSE2 GND SENSE3 12 SENSE4L 4 SENSE4H CT2 Denotes vias for application purposes Figure 38. Example Layout (RGP Package) 30 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 TPS386000, TPS386040 www.ti.com SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support 12.1.1.1 Evaluation Modules Two evaluation modules (EVMs) are available to assist in the initial circuit performance evaluation using the TPS3860x0. The TPS386000EVM-736 evaluation module and TPS386040EVM evaluation module can each be requested at the Texas Instruments website through the device product folders or purchased directly from the TI eStore. 12.1.1.2 Spice Models Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS3860x0 is available through the device product folders under Simulation Models. 12.1.2 Device Nomenclature Table 9. Device Nomenclature (1) PRODUCT TPS3860x0yyyz (1) DESCRIPTION x is device configuration option xxx = 0: Open-drain, active low xxx = 4: Push-pull, active low yyy is package designator z is package quantity For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation see the following: • TPS3860xxEVM-736 User's Guide, SLVU450 • User's Guide for the TPS386000 and TPS386040 EVM, SLVU341 12.3 Related Links Table 10 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 10. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS386000 Click here Click here Click here Click here Click here TPS386040 Click here Click here Click here Click here Click here Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 Submit Documentation Feedback 31 TPS386000, TPS386040 SBVS105F – SEPTEMBER 2009 – REVISED OCTOBER 2018 www.ti.com 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 32 Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated Product Folder Links: TPS386000 TPS386040 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS386000RGPR ACTIVE QFN RGP 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 386000 TPS386000RGPT ACTIVE QFN RGP 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 386000 TPS386040RGPR ACTIVE QFN RGP 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 386040 TPS386040RGPT ACTIVE QFN RGP 20 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 386040 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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