TPS40021-EP
www.ti.com
SLUSB58 – SEPTEMBER 2012
ENHANCED, LOW-INPUT VOLTAGE-MODE SYNCHRONOUS BUCK CONTROLLER
Check for Samples: TPS40021-EP
FEATURES
1
•
•
•
•
2
•
•
•
•
•
Operating Input Voltage 2.25 V to 5.5 V
Output Voltage as Low as 0.7 V
1% Internal 0.7-V Reference
Predictive Gate Drive™ N-Channel MOSFET
Drivers for Higher Efficiency
Externally Adjustable Soft-Start and Short
Circuit Current Limit
Programmable Fixed-Frequency 100-kHz to
1-MHz Voltage-Mode Control
Source or Sink Current
Quick Response Output Transient
Comparators With Power Good Indication
Provide Output Status
16-Pin PowerPAD™ Package
APPLICATIONS
•
•
•
•
•
Networking Equipment
Telecom Equipment
Base Stations
Servers
DSP Power
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
(1)
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Available in Military (–55°C to 125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Custom temperature ranges available
DESCRIPTION
The TPS40021 is a dc-to-dc controller designed for non-isolated synchronous buck regulators, providing
enhanced operation and design flexability through user programmability.
The device utilizes a proprietary Predictive Gate Drive technology to minimize the diode conduction losses
associated with the high-side and synchronous rectifier N-channel MOSFET transistions. The integrated charge
pump with boost circuit provides a regulated 5-V gate drive for both the high side and synchronous rectifier
N-channel MOSFETs. The use of the Predictive Gate Drive technology and charge pump/boost circuits combine
to provide a highly efficient, smaller and less expensive converter.
Design flexibility is provided through user programmability of such functions as: operating frequency, short circuit
current detection thresholds, soft-start ramp time, and external synchronization frequency. The operating
frequency is programmable using a single resistor over a frequency range of 100 kHz to 1 MHz. Higher operating
frequencies yield smaller component values for a given converter power level as well as faster loop closure.
The short circuit current detection is programmable through a single resistor, allowing the short circuit current
limit detection threshold to be easily tailored to accommodate different size (RDS(on)) MOSFETs. The short circuit
current function provides pulse-by-pulse current limiting during soft-start and short term transient conditions as
well as a fault counter to handle longer duration short circuit current conditions. If a fault is detected the controller
shuts down for a period of time determined by six consecutive soft-start cycles. The controller automatically
retries the output every seventh soft-start cycle.
In addition to determining the off time during a fault condition, the soft-start ramp provides a closed loop
controlled ramp of the converter output during startup. Programmability allows the ramp rate to be adjusted for a
wide variety of output L-C component values.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Predictive Gate Drive, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS40021-EP
SLUSB58 – SEPTEMBER 2012
www.ti.com
The output voltage transient comparators provide a quick response , first strike, approach to output voltage
transients. The output voltage is sensed through a resistor divider at the OSNS pin. If an overvoltage condition is
detected the HDRV gate drive is shut-off and the LDRV gate drive is turned on until the output is returned to
regulation. Similarly, if an output undervoltage condition is sensed the HDRV gate drive goes to 95% duty cycle
to pump the output back up quickly. In either case, the PowerGood open drain output pulls low to indicate an
output voltage out of regulation condition. The PowerGood output can be daisy-chained to the SS/SD pin or
enable pin of other controllers or converters for output voltage sequencing. The transient comparators can be
disabled by simply tying the OSNS pin to VDD.
The TPS40021 can be externally synchronized through the ILIM/SYNC pin up to 1.5× the free-running frequency.
This allows multiple contollers to be synchronized to eliminate EMI concerns due to input beat frequencies
between controllers.
VDD
VDD 2.25 V − 5.5 V
VOUT
1
ILIM/
SYNC
2
VDD
3
OSNS
4
FB
5
BOOT1 16
HDRV
15
SW
14
BOOT2
13
COMP
PVDD
12
6
SS/SD
LDRV
11
7
RT
PGND
10
SGND
2
VOUT
TPS40021
PWRGD 9
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
ORDERABLE
PART NUMBER
TJ
PACKAGE
–55°C to 125°C
Plastic HTSSOP PowerPAD
(PWP) (2)
(1)
(2)
TPS40021MPWPREP
Tape and Reel, 2000
TPS40021MPWPEP
Tube, 90
TOP-SIDE
MARKING
VID NUMBER
V62/12601-01XE
40021M
V62/12601-01XE-T
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
With Cu NIPDAU lead/ball finish
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range unless otherwise noted
SS/SD, VDD, PVDD, OSNS
MIN
MAX
–0.3
6
BOOT2, BOOT1
VIN
Input voltage range
VSW + 6
SW
–0.3
SWT (SW transient < 50 ns)
10.5
V
–5
FB, ILIM
–0.3
6
VOUT
Output voltage range
COMP, PWRGD, RT
–0.3
6
IS
Sink current
PWRGD
TJ
Maxium juction temperature
Tstg
Storage temperature
10
–65
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
UNIT
V
mA
150
°C
150
°C
260
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
THERMAL INFORMATION
TPS40021-EP
THERMAL METRIC (1)
PWP
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance (2)
θJCtop
Junction-to-case (top) thermal resistance (3)
28
θJB
Junction-to-board thermal resistance (4)
9
38.3
(5)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (6)
8.9
θJCbot
Junction-to-case (bottom) thermal resistance (7)
2.9
(1)
(2)
(3)
(4)
(5)
(6)
(7)
0.4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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RECOMMENDED OPERATING CONDITIONS
MIN
MAX
Supply voltage, VIN
2.25
5.50
UNIT
V
Operating temperature range, TJ
–55
125
°C
MAX
UNIT
5.50
V
V
ELECTRICAL CHARACTERISTICS
TJ = −55°C to 125°C, TJ = TA, VDD = 5.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
INPUT SUPPLY
VDD
Input voltage range
VPVDD
PVDD pin voltage
VDD = 3.3 V
4.9
5.2
Switching current
500 kHz, No load on HDRV, LDRV
3.5
5
Quiescent current
FB = 0.8 V
2
3
Shutdown current
SS/SD = 0 V, Outputs OFF
IDD
VUVLO
2.25
mA
0.38
1
1.95
2.05
2.15
72
130
200
2.25 V ≤ VDD ≤ 5.00 V, RT = 69.8 kΩ
405
500
575
2.25 V ≤ VDD ≤ 5.00 V, RT = 34.8 kΩ
740
950
1100
VPEAK − VVAL
0.80
0.93
1.07
V
0.24
0.31
0.41
V
VOSNS = VDD, RT = 34.8 kΩ, VDD = 3.3 V, FB = 0 V
85
94
VOSNS = VDD, RT = 70 kΩ, VDD = 5 V, FB = 0 V
90
95
Minimum on-voltage
Hysteresis
mV
OSCILLATOR
fOSC
Accuracy
VRAMP
Ramp voltage
VVAL
Ramp valley voltage
kHz
PWM
dMAX
Maximum duty cycle
dMIN
Minimum duty cycle
tMIN
Minimum HDRV on-time (1)
%
0
250
%
ns
ERROR AMPLIFIER
2.25 V ≤ VDD ≤ 5 V
VFB
Feedback input voltage
IBIAS
Input bias current
VOH
High-level output voltage
IOH = 0.5 mA, VFB = GND
VOL
Low-level output voltage
IOL = 0.5 mA, VFB = VDD
IOH
High-level output source
current
VFB = GND
IOL
Low-level output sink current
VFB = VDD
GBW
Gain bandwidth (2)
AOL
Open loop gain
0.683
2
0.690
0.701
V
30
130
nA
2.5
0.08
2.7
3
V
0.15
7
V
mA
8
mA
10
MHz
53
85
dB
165
190
215
µA
-20
0
20
mV
200
300
CURRENT LIMIT
ISINK
Current limit sink current
VOS
Current limit offset voltage
Minimum HDRV on−time in
overcurrent
tON
2.25 V ≤ VDD ≤ 5.00 V, RT = 69.8 kΩ
VDD = 3.3 V
ns
Switch leading-edge blanking
pulse time (2)
tSS
Soft-start cycles
VILIM
Current limit input voltage
range
140
6
2
cycles
VDD
V
5.4
µA
SOFT START
ISS
(1)
(2)
4
Soft-start source current
Outputs = OFF
2
3.3
Operation below the minimum on-time could result in overlap of the HDRV and LDRV outputs.
Specified by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
TJ = −55°C to 125°C, TJ = TA, VDD = 5.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.2
0.26
0.29
V
0.25
0.28
0.32
V
1
2.5
5
Ω
0.7
1.5
3
Ω
1
2.5
5
Ω
0.41
0.80
1.50
Ω
SHUTDOWN
VSD
Shutdown threshold voltage
VEN
Device enable threshold
voltage
OUTPUT DRIVER
RHDHI
High-side driver pull-up
resistance
V(BOOT1) − V(SW) = 3.3 V, ISOURCE = 100 mA
RHDLO
High-side driver pull-down
resistance
V(BOOT1) − V(SW) = 3.3 V, ISINK = 100 mA
RLDHI
Low-side driver pull-up
resistance
PVDD = 3.3 V, ISOURCE = 100 mA
RLDLO
Low-side driver pull-down
resistance
PVDD = 3.3 V, ISINK = 100 mA
tLRISE
Low-side driver rise time
15
35
ns
tLFALL
Low-side driver fall time
10
25
ns
tHRISE
High-side driver rise time
15
35
ns
tHFALL
High-side driver fall time
10
25
ns
CLOAD = 1 nF
THERMAL SHUTDOWN
Shutdown temperature (3)
TSD
165
Hysteresis (3)
°C
15
CHARGE PUMP
RVB2
RDS(on) VDD to BOOT2
VDD = 5 V, ISOURCE = 10 mA
2.8
6.6
10.4
Ω
RB2P
RDS(on) BOOT2 to PVDD
VDD = 5 V, ISOURCE = 10 mA
2.8
5.6
8.4
Ω
RPB1
RDS(on) PVDD to BOOT1
VDD = 5 V, ISOURCE = 10 mA
2.9
5.9
8.9
Ω
POWER GOOD
VPGD
Pull-down voltage
VOSNS = 0.8 V, IPWRGD = 0.5 mA, VDD = 3.3 V
50
90
140
mV
tONHPL
Output sense high to power
good low delay time
0.7 V ≤ VOSNS ≤ 0.8 V, IPWRGD = 0.5 mA,
VDD = 3.3 V
6
10
14
µs
tONLPL
Output sense low to power
good low delay time
0.6 V ≤ VOSNS ≤ 0.7 V, IPWRGD = 0.5 mA,
VDD = 3.3 V
6
10
14
µs
tSDHPH
Shutdown high to power good
high delay time
VOSNS = 0.7 V, IPWRGD = 0.5 mA, VDD = 3.3 V,
0 V ≤ VSS/SD ≤ 0.4 V
2
4
6
µs
tSDLPL
Shutdown low to power good
low delay time
VOSNS = 0.7 V, IPWRGD = 0.5 mA, VDD = 3.3 V,
0 V ≤ VSS/SD ≤ 0.4 V
0.5
1.5
3
µs
tONHPH
Output sense high to nominal
to power good high delay time
0.7 V ≤ VOSNS ≤ 0.8 V, IPWRGD = 0.5 mA,
VDD = 3.3 V
140
500
1000
ns
tONLPH
Output sense low to nominal
to power good high delay time
0.6 V ≤ VOSNS ≤ 0.7 V, IPWRGD = 0.5 mA,
VDD = 3.3 V
140
500
1000
ns
23
29
35
8
15
22
-37
-31
-25
8
15
22
TRANSIENT COMPARATORS
Overvoltage output threshold
voltage
VOV
Referenced to VFB
Hysteresis
Undervoltage output threshold
voltage
VUV
Referenced to VFB
Hysteresis
VDIS
(3)
OSNS minimum disable
voltage
Referenced to VDD
0.5
mV
mV
V
Specified by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
TJ = −55°C to 125°C, TJ = TA, VDD = 5.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYNCHRONIZATION
VENSY
Synchronization enable low
threshold voltage
VBLNK
Synchronization current limit
enable threshold voltage
tMIN
Minimum synchronization
input pulse width
0.7
Referenced to VDD
-0.7
V
V
35
50
ns
PREDICTIVE DELAY
VSWP
tLDHD
tHDLD
Sense voltage to modulate
delay
-200
mV
Maximum delay modulation
LDRV OFF-to-HDRV ON
40
65
90
Counter delay/bit time
LDRV OFF-to-HDRV ON
2.5
4.5
6.2
Maximum delay modulation
HDRV OFF-to-LDRV ON
80
Counter delay/bit time
HDRV OFF-to-LDRV ON
5
ns
ns
RECTIFIER ZERO CURRENT COMPARATOR
tZBLNK
(4)
6
Zero current blanking time (4)
150
ns
Specified by design. Not production tested.
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DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
NO.
NAME
I/O
DESCRIPTION
PWP
BOOT1
16
I
This pin provides a bootstrapped supply for the high side FET driver, enabling the gate of the high
side FET to be driven above the input supply rail. Connect a capacitor from this pin to the SW pin.
BOOT2
13
I
This pin provides a secondary bootstrapping necessary for generation of PVDD. Connect a
capacitor from this pin to SW.
COMP
5
O
Output of the error amplifier. Refer to Electrical Characteristics table for loading constraints.
FB
4
I
Inverting input of the error amplifier. In normal operation, VFB is equal to the internal reference level
of 690 mV.
HDRV
15
O
The gate drive output for the high side N-channel MOSFET switch is bootstrapped to near PVDD for
good enhancement of the high-side switch. The HDRV switches from BOOT1 to SW.
ILIM/SYNC
1
I
The current limit pin is used to set the current limit threshold. A current sink from this pin to GND
sets the threshold voltage for output short circuit current across a resistor connected to VDD.
Synchronization is accomplished by pulling IMAX to less than 1 V for a period greater than the
minimum pulse width and then releasing. An open collector or drain device should be used. These
pulses must be of higher frequency than the free running frequency of the local oscillator.
LDRV
11
O
Gate drive output for the low-side synchronous rectifier N-channel MOSFET. LDRV switches from
PVDD to PGND.
OSNS
3
O
The output sense pin is connected to a resistor divider from VOUT to GND (identical to the main
feedback loop) and is used to sense power good condition and provides reference for the transient
comparators.
PGND
10
O
Power (high-current) ground used by LDRV.
PWRGD
9
-
Power good. This is an open-drain output which connects to the supply via an external resistor.
PVDD
12
O
This pin is the regulated output of the charge-pump and provides the supply voltage for the LDRV
driver stage. PVDD also drives the bootstrap circuit which generates the voltage on BOOT1.
RT
7
I
External pin for programming the oscillator frequency. Connnected a resistor between this pin and
GND.
SGND
8
-
Signal ground
SS/SD
6
I
The soft-start/shutdown pin provides user programmable soft-start timing and shutdown capability
for the controller.
SW
14
I
This pin, used for overcurrent, zero-current, and in the anti-cross conduction sensing is connected
to the switched node on the converter. Output short circuit is detected by sensing the voltage at this
pin with respect to VDD while the high-side switch is on. Zero current is detected by sensing the pin
voltage with respect to ground when the low-side rectifier MOSFET is on.
VDD
2
I
Power input for the device. Maximum voltage is 5.5 V. De-coupling of this pin is required.
PWP PACKAGE
(TOP VIEW)
ILIM/SYNC
VDD
OSNS
FB
COMP
SS/SD
RT
SGND
1
2
3
4
5
6
7
8
THERMAL
PAD
16
15
14
13
12
11
10
9
BOOT1
HDRV
SW
BOOT2
PVDD
LDRV
PGND
PWRGD
A.
For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002.
B.
PowerPAD heat slug must be connected to SGND (Pin 8), or electrically isolated from all other pins.
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FUNCTIONAL BLOCK DIAGRAM
VDD
2
OSNS
3
VDD
0.719 V
PWRGD
VDD
SS
ACTIVE
9
CHARGE
PUMP
13
BOOT2
12
PVDD
16
BOOT1
15
HDRV
14
SW
11
LDRV
10
PGND
1
ILIM/SYNC
0.659 V
FB
4
0.69 V
COMP
+
+
5
UVLO
RT
OSC
DRV
PREDICTIVE
GATE
DRIVE(tm)
PWM
LOGIC
PWM
CLK
PVDD
UVLO
7
IRT
DRV
FAULT
CLK
ISS
SS/SD
SOFT
START
VDD
SS
ACTIVE
FAULT
COUNTER
IRT
CURRENT LIMIT
COMPARATOR
−
OC
6
DCHG
+
UVLO
SD
SYNC
0.28 V
8
VDD
1V
UVLO
UVLO
DISABLE
+
+
SGND
VDD
1.4 V
8
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APPLICATION INFORMATION
The TPS40021 is a low-input voltage, synchronous, voltage mode-buck controller. A typical application circuit is
shown in Figure 1. These controllers are designed to allow construction of high-performance dc-to-dc converters
with input voltages from 2.25 V to 5.5 V, and output voltages as low as 690 mV. Using a top side N-channel
MOSFET for the primary buck switch results in lower switch resistance for a given gate charge.
The device controls the delays from main switch off to rectifier turn on and from rectifier turn off to main switch
turn on in a way that minimizes diode losses (both conduction and recovery) in the synchronous rectifier. The
reduction in these losses is significant and can mean that for a given converter power level, smaller FETs can be
used, or that heat sinking can be reduced or even eliminated.
The TPS40021 is the controller of choice for most general purpose synchronous buck designs, operating in two
quadrant mode (i.e. source or sink current) full time. This device provides the best performance for output voltage
load transient response over the widest load current range.
The controller provides for a coarse short circuit current-limit function that provides pulse-by-pulse current
limiting, as well as integrates short circuit current pulses to determine the existence of a persistant fault state at
the converter output. If a fault is detected, the converter shuts down for a period of time (determined by six softstart cycles) and then restarts. The current-limit threshold is adjustable with a single resistor connected from VDD
to the ILIM/SYNC pin. This overcurrent function is designed to protect against catastrophic faults only, and
cannot be guaranteed to protect against all overcurrent conditions.
The controller implements a closed-loop soft start function. Startup ramp time is set by a single external capacitor
connected to the SS/SD pin. The SS/SD pin also doubles as a shutdown function.
Voltage Reference
The bandgap cell is designed with a trimmed, curvature corrected (< 1%) 0.69-V output, allowing output voltages
as low as 690 mV to be obtained.
Oscillator
The ramp waveform is a saw-tooth form at the PWM frequency with a peak voltage of 1.25 V, and a valley of
0.3 V. The PWM duty cycle is limited to a maximum of 97%, allowing the bootstrap and charge pump capacitors
to charge during every cycle.
Bootstrap/Charge Pump
The TPS40021 includes a charge pump to boost the drive voltage to the power MOSFET’s to higher levels when
the input supply is low. A capacitor connected from PVDD to PGND is the storage cap for the pump. A capacitor
connected from SW to BOOT2 gets charged every switching cycle while LDRV is high and its charge is dumped
on the PVDD capacitor when HDRV goes high. An internal switch disables the charge pump when the voltage on
PVDD reaches approximately 4.8 V and enables pumping when PVDD falls to approximately 4.6 V. The highside driver uses the capacitor from SW to BOOT1 as its power supply. When SW is low, this capacitor charges
from the PVDD capacitor. When the SW pin goes high, this capacitor provides above-rail drive for the high-side
N-channel FET.
PVDD, BOOT1 and BOOT2 are pre-charged to the VDD voltage during a shutdown condition. For low-input
voltage converters, utilizing higher gate threshold voltage MOSFETs, it may be necessary to add an Schottky
diode from VDD (anode) to BOOT1 to guarantee sufficient voltage for initial start up. Once switching starts the
charge pump reverses bias on the Schottky diode.
Drivers
The HDRV and LDRV MOSFET drivers are capable of driving gate-to-source voltages up to 5.0 V. Using
appropriate MOSFETs, a 25-A converter can be achieved. The LDRV driver switches between VDD and ground,
while the HDRV driver is referenced to SW and switches between BOOT1 and SW. The maximum voltage
between BOOT1 and SW is 5.0 V when PVDD is in regulation.
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9
10
C9
330 µF
C8
330 µF
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R2
10 kΩ
R4
118 kΩ
C14
2200 pF
C13
0.022 µF
R7
30.1 kΩ
C12
22 µF
C15 47 pF
C11
22 µF
R6
10 kΩ
C10
330 µF
C16
R8
1800 pF 2.87 kΩ
R5
8.66 kΩ
+
+
R1
8.66 kΩ
VDD +
3.3 V
FB
4
DNG
8S
7
6
RT
SS/SD
PGND
LDRV
PVDD
BOOT2
SW
HDRV
BOOT1
PWRGD
PWP
OSNS
3
COMP
VDD
2
5
ILIM/SYNC
TPS4002XPWP
1
R3
1.5 kΩ
9
10
11
12
13
14
15
16
C3
10 µF
R9
10 kΩ
Q2
Si7880DP
C11
1µF
C2 1 µF
C17
15 nF
R10
2.2 Ω
L1
0.75 µF
Q1
Si7858DP
+
C4
470 µF
+
C5
470 µF
+
C6
470 F
1.25 V
20 A
C7
10 µF
TPS40021-EP
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Figure 1. Typical Application
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Synchronous Rectification and Predictive Gate Delay
In a normal buck converter, when the high−side switch turns off, current is flowing in the inductor. Since this
current cannot be stopped immediately a rectifier or catch device is used to give this current a path to flow and
maintain voltage levels at a safe level. This device can be a simple diode or it can be an actively−controlled
transistor if a control signal is available to drive it. The TPS40021 provides a signal to drive an N−channel
MOSFET as a synchronous rectifier. This control signal is carefully coordinated with the drive signal for the main
switch so that there is absolute minimum dead−time between the turn off of one FET and the turn on of the
other. This TI−patented function, predictive gate delay, uses information from the current switching cycle to
adjust the delays for the next cycle virtually eliminating diode conduction while preventing cross−conduction or
shoot through. Figure 2 shows the switch−node voltage waveform for a synchronously rectified buck converter
during the synchronous rectification period. Illustrated are the relative effects of a fixed delay drive scheme
(constant, pre−set delays for the turn−off to turn−on intervals), an adaptive delay drive scheme (variable delays
based on voltages sensed on the current switching cycle) and TI’s predictive delay drive scheme. Since the
diode voltage drop is greater than the conduction drop of the FET, the longer time spent in diode conduction, the
more power dissipated in the rectifier and the lower the efficiency. Also, not shown in the figure, is the fact that
the predictive delay circuit can actually prevent the body diode from becoming forward biased at all, avoiding
reverse recovery and its associated losses. This results in a significant power savings when the main FET turns
on.
The predictive gate drive architecture on the TPS40021 requires a minimum pulse width of greater than 150 ns
for proper operation. At pulse widths below 150 ns, the low−side FET turn−on could overlap the high−side FET
turn−off leading to cross conduction in the power stage.
GND
Channel Conduction
Body Diode Conduction
Fixed Delay
Adaptive Delay
Predictive Delay
Figure 2. Switch Node Waveforms for Synchronous Buck Converter
Output Short Circuit Protection
Output short circuit protection in the TPS40021 is sensed by looking at the voltage across the main FET while it
is on. If the voltage exceeds a pre-set threshold, the current pulse is terminated, and a counter inside the device
is incremented. If this counter fills up, a fault condition is declared and the chip disables switching for a period of
time and then attempts to restart the converter with a full soft-start cycle. The more detailed explanation follows.
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In each switching cycle, a comparator looks at the voltage across the top side FET while it is on. If the voltage
across that FET exceeds a programmable threshold voltage, then the current switching pulse is terminated and a
3-bit counter (eight counts) is incremented by one count. If during the switching cycle the top side FET voltage
does not exceed a preset threshold, then this counter is decremented by one count. (The counter does not wrap
around from seven to zero or from zero to seven). If the counter reaches a full count of seven, the device
declares that a fault condition exists at the output of the converter. In this state, switching stops and the soft-start
capacitor is discharged. The counter is decremented by one by the soft start cap discharge. When the soft-start
capacitor is fully discharged, the discharge circuit is turned off and the cap is allowed to charge up at the nominal
charging rate, When the soft-start capacitor reaches approximately 1.3 V, it is discharged again and the
overcurrent counter is decremented by one count. The capacitor is charged and discharged, and the counter
decremented until the count reaches zero (a total of six times). When this happens, the outputs are again
enabled as the soft-start capacitor generates a reference ramp for the converter to follow while attempting to
restart. During this soft-start interval (whether or not the controller is attempting to do a fault recovery or starting
for the first time), pulse-by-pulse current limiting is in effect, but overcurrent pulses are not counted to declare a
fault until the soft-start cycle has been completed. It is possible to have a supply try to bring up a short circuit for
the duration of the soft-start period plus seven switching cycles. Power stage designs should take this into
account if it makes a difference thermally. Figure 3 shows the details of the overcurrent operation.
(+)
VTS
(−)
Overcurrent
Threshold
Voltgage
Internal PWM
VTS
0V
External
Main Drive
Normal Cycle
Overcurrent
Cycle
Figure 3. Switch Node Waveforms for Synchronous Buck Converter
Figure 4 shows the behavior of key signals during initial startup, during a fault and a successfully fault recovery.
At time t0, power is applied to the converter. The voltage on the soft-start capacitor (VCSS) begins to ramp up At
t1, the soft-start period is over and the converter is regulating its output at the desired voltage level. From t0 to
t1, pulse-by-pulse current limiting was in effect, and from t1 onward, overcurrent pulses are counted for purposes
of determining if a fault exists. At t2, a heavy overload is applied to the converter. This overload is in excess of
the overcurrent threshold, the converter starts limiting current and the output voltage falls to some level
depending on the overload applied. During the period from t2 to t3, the counter is counting overcurrent pulses
and at time t3 reaches a full count of 7. The soft-start capacitor is then discharged, the outputs are disabled, the
counter decremented, and a fault condition is declared.
12
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VDD
1.3 V
0.6 V
0.6 V
VCSS
FAULT
ILOAD
VOUT
t0
Counter
t1
t4
t2 t3
0
t5
6
1
2
3
4
5
5
6
7
t6
4
t7
3
t8
2
t9
1
t
t10
0
cycles
Figure 4. Overcurrent/Fault Waveforms
When the soft-start capacitor is fully discharged, it begins charging again at the same rate that it does on startup,
with a nominal 3-μA current source. As the capacitor voltage reaches full charge, it is discharged again and the
counter is decremented by one count. These transitions occur at t3 through t9. At t9, the counter has been
decremented to zero. Now the fault logic is cleared, the outputs are enabled and the converter attempts to restart
with a full soft-start cycle. The converter comes into regulation at t10.
The internal SS signal is a diode drop below VCSS. When VCSS reaches one diode drop above ground, (≅ 0.6 V)
the output (VOUT) begins it’s soft-start ramp.
Setting the Short Circuit Current Limit Threshold
Connecting a resistor from VDD to ILIM sets the current limit. A current sink in the chip causes a voltage drop
across the resistor connected to ILIM. This voltage drop is the short circuit current threshold for the part. The
current that the ILIM pin sinks is dependent on the value of the resistor connected to RT and is given by:
0.69 V
ILIM = 19 · ¾
RT
(1)
The tolerance of the current sink is too loose to do an accurate current limit. The main purpose is for hard fault
protection of the power switches. Given the tolerance of the ILIM sink current, and the RDS(on) range for a
MOSFET, it is generally possible to apply a load that thermally damages the converter. This device is intended
for embedded converters where load characteristics are defined and can be controlled. A small capacitor can be
added between ILIM and VDD for filtering. However, capacitors should not be used if the synchronization
function is to be used.
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Soft-Start and Shutdown
The soft−start and shutdown functions are common to the SS/SD pin. The voltage at this pin over−rides the
reference voltage on the error amplifier during startup. This controls the output voltage slew rate and the surge
current required to charge the output capacitor at startup, allowing for a smooth startup with no overshoot of the
output voltage. Initial HDRV pulse widths during Soft−Start are typically very narrow, likely less than 150ns. As a
result, HDRV and LDRV can be on simultaneously, resulting in cross−conduction the MOSFETs of the power
stage. To minimize cross−conduction during soft−start, the soft−start time when the pulse widths are less than
150ns should be kept to a minimum. A shutdown feature can be implemented by pulling SS/SD to GND via a
transistor as shown in Figure 5.
3.3 µA
6
CSS
SS/SD
SHUTDOWN
TPS40021
Figure 5. Shutdown Implementation
ISS
· tSS (F)
CSS = V¾
(2)
FB
where tSS is the start up time in seconds.
Switching Frequency
The switching frequency is programmed by a resistor from RT to SGND. Nominal switching frequency can be
calculated by:
3
· 10
¾
- 5.09 (kW)
RT (kW) = 37.736
fOSC (kHz)
(3)
Synchronization
The TPS40021 can be synchronized to an external reference frequency higher than the free running oscillator
frequency. The recommended method is to use a diode and a push pull drive signal as shown in Figure 6.
PREFERRED
ALTERNATE
VDD
VDD
TPS40021PWP
50 ns to 100 ns
Minumize
Output/Stray
Capacitance
on ILIM Node
TPS40021PWP
1
ILIM/SYNC
1
ILIM/SYNC
2
VDD
2
VDD
50 ns to 100 ns
Figure 6. Synchronization Methods
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This design allows synchronization up to the maximum operating frequency of 1 MHz. For best results the
nominal operating frequency of a converter that is to be synchronized should be kept as close as practicable to
the synchronization frequency to avoid excessive noise induced pulse width jitter. A good target is to shoot for
the free run frequency to be 80% of the synchronized frequency. This ensures that the synchronization source is
the frequency determining element in the system and not to adversely affect noise immunity.
Other methods of implementing the synchronization function include using an open collector or open drain output
device directly, or discreet devices to pull the ILIM/SYNC pin down. These do work but performance can suffer at
high frequency because the ILIM/SYNC pin must rise to (VDD − 1.0 V) before the next switching cycle begins.
Any time that this requires is directly subtracted from the maximum pulse width available and should be
considered when choosing devices to drive ILIM/SYNC. Consequently, the lowest output capacitance devices
work best.
During a synchronization cycle, the current sink on the ILIM/SYNC pin becomes disabled when ILIM/SYNC is
pulled below 1.0 V. The ILIM/SYNC current sink remains disabled until ILIM/SYNC reaches (VDD −1.0 V) This
removes the load on the ILIM/SYNC pin to allow the voltage to slew rapidly depending on the ILIM resistor and
any stray capacitance on the pin. To maximize this slew rate, minimize stray capacitance on this pin.
The duration of the synchronization pulse pulling ILIM/SYNC low shoud be between 50 ns and 100 ns. Longer
durations may limit the maximum obtainable duty cycle.
Transient Comparators and Power Good
The TPS40021 makes use of a separate pin, OSNS, to monitor output voltage for these two functions. In normal
operation, OSNS is connected to the output via a resistor divider. It is important to make this divider the same
ratio as the divider for the feedback network so that in normal operation the voltage at OSNS is the same as the
voltage at FB, 0.69 V nominal.
The PWRGD pin is an open drain output that is pulled low when the voltage at OSNS falls outside 0.69 V ±4.6%
(approximately). A delay has been purposely built into the PWRGD pin pulling low in response to an out of band
voltage on OSNS, to minimize the need for filtering the signal in the event of a noise glitch causing a brief out of
band OSNS voltage. The PWRGD signal returns to high when the OSNS signal returns to approximately ±1% of
nominal (0.69 V ±1%).
The transient comparators override the conventional voltage control loop when the output voltage exceeds a
±4.6% window. If the output transition is high (i.e. load steps down from 90% load to 10 % load) then the HDRV
gate drive is terminated, 0% duty cycle, the LDRV gate drive is turned on to sink output current until VOUT returns
to within 1% of nominal. Conversely when VOUT drops outside the window (i.e. step load increases from 10%
load to 90% load) HDRV increases to maximum duty cycle until VOUT returns to within 1% of nominal (see
Figure 7).
During start-up, the transient comparators control the state of PWRGD as previously described. However, the
operation of the gate drive outputs is not affected (see Figure 8).
The transient comparators provide an improvement in load transient recovery time if used properly. In some
situations, recovery time may be one half of the time required without transient comparators. Keep in mind that
the transient comparator concept is a double-edged sword. While they provide improved transient recovery time,
they can also lead to instability if incorrectly applied. For proper functionality, design a feedback loop for the
converter that places the closed loop unity gain frequency at least five times higher than the 0-dB frequency of
the output L-C filter. If not, the feedback loop cannot respond to the ring of the L-C on a transient event. The ring
is likely to be large enough to disturb the transient comparators and the result is a power oscillator. Another
helpful action is to ground the feedback loop divider and the OSNS divider at the SGND pin. Make sure both
dividers measure the same physical location on the output bus. These help avoid problems with resistive drops
at higher loads causing problems.
Connecting OSNS to VDD disables the transient comparators. This also disables the PWRGD function.
Alternatively, OSNS and FB can be tied together. This connection allows a proper PWRGD at startup, though
transient performance diminishes.
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< 10 µs
4.6%
1%
FB
−1%
− 4.6%
− 4.6%
10 µs
PWRGD
10 µ s
500 n s
500 n s
SW
98 % Duty Cycle
0 % Duty Cycle
98 % Duty Cycle
0 % Duty Cycle
Figure 7. Duty Cycle Waveforms
VDD
1.3 V
0.6 V
0.3 V
SS/SD
VOUT − 1%
500 ns
VOUT
1.5 µs
Transient Comparators Enabled
4µs
PWRGD
Transient Comparators Disabled
Figure 8. Transient Comparator Waveforms
16
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Layout Considerations
Successful operation of the TPS40021 is dependent upon the proper converter layout and grounding techniques.
High current returns for the SR MOSFET’s source, input capacitance, output capacitance, PVDD capacitance,
and input bypass capacitors (if applicable), should be kept on a single ground plane or wide trace connected to
the PGND (pin10) through a short wide trace. Control components connected to signal ground, as well as the
PowerPad thermal pad, should be connected to a single ground plane connected to SGND (pin 8) through a
short trace. SGND and PGND should be connected at a single point using a narrow trace.
Proper operation of Predictive Gate Drive technology and IZERO functions are dependent upon detecting lowvoltage thresholds on the SW node. To ensure that the signal at the SW pin accurately represents the voltage at
the main switching node, the connection from SW (pin 14) to the main switching node of the converter should be
kept as short and wide as possible and should ideally be kept on the top level with the power components. If the
SW trace must traverse multiple board layers between the TPS40021 and the main switching node, multiple vias
should be used to minimize the trace impedance.
Gate drive outputs, LDRV and HDRV (pins 11 and 15, respectively) should be kept as short as possible to
minimize inductances in the traces. If the gate drive outputs need to traverse multiple board layers multiple vias
should be used.
Charge pump components, BOOT1, BOOT2, PVDD, and any input bypass capacitors (if required), should be
kept as close as possible to their respective pins. Ceramic bypass capacitors should be used if the input
capacitors are located more than a couple of inches away from the TPS40021. If a bypass capacitor is not
needed the trace from the input capacitors to VDD (pin2) should be kept as short and wide as possible to
minimize trace impedance. If multiple board layers are traversed multiple vias should be used.
Manufacturer’s instructions should be followed for proper layout of the external MOSFETs. Thermal impedances
given in the manufacturer’s datasheets are for a given mounting technique with a specified surface area under
the drain of the MOSFET. PowerPad package information can be found in the APPLICATION INFORMATION
section of this datasheet.
Refer to TPS40021 EVM−001 High Efficiency Synchronous Buck Converter with PWM Controller Evaluation
Module (HPA009) User’s Guide, (Literature No. SLUU144A) for a typical board layout.
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit
board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depends
on the size of the PowerPAD package. For a 16-pin TSSOP (PWP) package the area is 5 mm x 3.4 mm [3].
Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently
small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is
needed to prevent wicking the solder away from the interface between the package body and the solder-tinned
area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is
plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not
plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a
diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked
through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally
Enhanced Package[3] for more information on the PowerPAD package.
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REFERENCE DESIGN
This design used the TPS40020 PWM controller to facilitate a step-down application from 3.3-V to 1.5 V (see
Figure 11). Design specifications include:
• Input voltage: 2.5 V ≤ VIN ≤ 5.0 V
• Nominal output voltage: 3.3 V
• Output voltage VOUT: 1.5 V
• Output current IOUT: 20 A
• Switching frequency: 300 kHz
Setting the Frequency
Choosing the optimum switching frequency is complicated. The higher the frequency, the smaller the inductance
and capacitance needed, so the smaller the size, but then the the switching losses are higher, the efficiency is
poorer. For this evaluation module, 300 kHz is chosen for reasonable efficiency and size.
A resistor R4, which is connected from pin 7 to ground, programs the oscillator frequency. The approximate
operating frequency is calculated in Equation 3.
Using Equation 2, RT is calculated to be 120 kΩ and a 118-kΩ resistor is chosen for 300 kHz operation.
Inductance Value
The inductance value can be calculated by Equation 4.
VOUT
VOUT
·3 - ¾
L(min) = ¾
VIN(max)
f · IRIPPLE
(4)
where IRIPPLE is the ripple current flowing through the inductor, which affects the output voltage ripple and core
losses.
Based on 24% ripple current and 300 kHz, the inductance value is calculated to 0.71 μH and a 0.75-μH inductor
(part number is CDEP149−0R7) is chosen. The DCR of this inductor is 1.1 mΩ and the loss is 440 mW, which is
approximately 1.5% of output power.
IRIPPLE
COUT(min) = 8¾
·f·V
(5)
VRIPPLE
ESROUT = ¾
IRIPPLE
(6)
RIPPLE
With 1.2% output voltage ripple, the needed capacitance is at least 109 μF and its ESR should be less than
3.75 mΩ. Three 2-V, 470-μF, POSCAP capacitors from Sanyo are used. The ESR is 10 mΩ each.
The required input capacitance is calculated in Equation 7. The calculated value is approximately 390 μF for a
100-mV input ripple. Three 6.0-V, 330-μF POSCAP capacitors with 10 mΩ ESR are used to handle 10 A of RMS
input current. Additionally, two ceramic capacitors are used to reduce the switching ripple current.
1
CIN(min) = IOUT(max) · D(max) · ¾
fOSC · VIN(ripple)
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3.3 V
+
R6 10 kΩ
C9
330 µF
+
R2
10 kΩ
C16
R8
2.87 kΩ 1800 pF
C8
330 µF
+
R1
8.66 kΩ
C10
330 µF
C12
22 µF
C13
0.022 µF
R17
30.1 kΩ
R4
118 kΩ
C14
220 pF
SW
14
SGND PWP
8
PWRGD 9
PGND 10
LDRV 11
PVDD 12
BOOT2 13
RT
SS/SD
COMP
FB
OSNS
7
6
5
4
3
HDRV 15
VDD
2
TPS40021PWP
ILIM/SYNC BOOT1 16
1
R3
1.43 kΩ
C15 47 pF
R5 8.66 kΩ
C11
22 µF
C3
10 µF
R9 10 kΩ
Q2
S7880DP
C2 1 µF
C1
1µ F
C17
15 nF
R10
2.2 Ω
L1
0.75 µF
Q1
Si7858DP
+
C4
470 µF
+
C5
470 µF
+
C6
470 F
C7
10 µF
1.5 V
20 A
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Figure 9. Reference Design Schematic
Input and Output Capacitors
The output capacitance and its ESR needed are calculated in Equation 5 and Equation 6.
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Compensation Design
Voltage-mode control is used in this evaluation module, using R2, R7, R8, C14, C15, and C16 to form a Type-III
compensator network. The L-C frequency of the power stage is approximately 4.9-kHz and the ESR-zero is
around 34 kHz. The overall crossover frequency, f0db, is chosen at 43-kHz for reasonable transient response and
stability. Two zeros fZ1 and fZ2 from the compensator are set at 2.4 kHz and 4 kHz. The two poles, fP1 and fP2 are
set at 34 kHz and 115 kHz. The frequency of poles and zeros are defined by the following equations:
1
fZ1 = 2¾
p · R7 · C14
1
(assuming R2 > R8)
fZ2 = 2¾
p · R2 · C16
1
fP1 = 2¾
p · R8 · C16
1
(assuming C14 > C15)
fP2 = 2¾
p · R7 · C15
(8)
(9)
(10)
(11)
The transfer function for the compensator is calculated in Equation 12.
A(s) =
(1 + s · C14 · R7) · [1 + s · C16 · (R2 + R3)]
¾
C15
¾ ) + s · R7 · C15] · (1 + s · R8 · C16)
s · R2 · C14 · [(1 + C14
(12)
Figure 10 shows the close loop gain and phase. The overall crossover frequency is approximately 30 kHz. The
phase margin is 57°.
OVERALL GAIN AND PHASE
vs
OSCILLATOR FREQUENCY
50
200
Gain
40
150
30
Gain (dB)
10
50
Phase
0
0
–10
–20
Phase (°)
100
20
–50
–30
–100
–40
–50
–150
100
1k
10k
100k
Oscillator Frequency (kHz)
G001
Figure 10.
MOSFETs and Diodes
For a 1.5-V output voltage, the lower the RDS(on) of the MOSFET, the higher the efficiency. Due to the high
current and high conduction loss, the MOSFET should have very low conduction resistance (RDS(on)) and thermal
resistance. Si7858DP is chosen for its low RDS(on) (between 3 mΩ and 4 mΩ) and Power-Pak package.
Current Limiting
Resistor R3 sets the short current limit threshold. The RDS(on) of the upper MOSFET is used as a current sensor.
The current limit, IOUT(CL) is initialized at 30% above the maximum output current, IOUT(max), which is 28 A. Then
R3 can be calculated in Equation 14 and yields a value of 1.4 kΩ. An R3 of 1.43 kΩ is selected.
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VFB
0.69
V
¾
ILIM = (19 · ¾
R4 ) = (19 · 118 kW ) = 111.1 (µA)
K · RDS(on) · IOUT(CL) 1.5 · 0.004 · 28A
= ¾
R3 = ¾
= 1.4 (k W)
ILIM
ILIM
(13)
(14)
where
RDS(on) is the on-resistor of Q1 (4 mΩ)
Temperature coefficient, K=1.5
VFB = 0.69 V
R4 = 118 kΩ
Voltage Sense Regulator
R1 and R2 operate as the output voltage divider. The error amplifier reference voltage (VFB) is 0.69 V. The
relationship between the output voltage and divider is described in Equation 15. Using a 10-kΩ resistor for R2
and 1.5-V output regulation, R1 is calculated as 8.52 kΩ, 8.66 kΩ is selected for R1.
VFB
VOUT
0.69V = ¾
1.5V
¾= ¾
® R1 = 8.52kW
R1 R1 + R2 ® ¾
R1 + 10kW
R1
(15)
Transient Comparator
The output voltage transient comparators provide a quick response, first strike, approach to output voltage
transients. The output voltage is sensed through a resistor divider at the OSNS pin, using R5 and R6 shown in
Figure 9. If an overvoltage condition is detected, the HDRV gate drive is shut off and the LDRV gate drive is
turned on until the output is returned to regulation. Similarly, if an output undervoltage condition is sensed, the
HDRV gate drive goes to 95% duty cycle to pump the output back up quickly. The voltage divider should be
exactly the same as resistors R1 and R2 discussed previously. Resistor R5 = 8.66 kΩ and R6 = 10 kΩ in this
evaluation module.
Efficiency Curves
The tested efficiency at different loads and input voltages are shown in Figure 11. The maximum efficiency is as
high as 93% at 1.5-V output. The efficiency is around 88% when the load current (ILOAD) is 20 A.
EFFICIENCY
vs
OUTPUT LOAD CURRENT
0.95
VIN = 2.5 V
Efficiency (%)
0.90
VIN = 4.0 V
0.85
VIN = 5.0 V
0.80
VIN = 3.3 V
0.75
0.70
0
5
10
15
20
Load Current (A)
G002
Figure 11.
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Typical Operating Waveforms
VIN = 3.3 V
ILOAD = 20 A
VIN = 3.3 V
ILOAD = 20 A
VSW (2 V/div)
VOUTac (10 mV/div)
Time (1 μs/div)
Time (1 μs/div)
G003
Figure 12.
G004
Figure 13.
Transient Response and Output Ripple Voltage
The output ripple is about 15 mVP−P at 20-A output. When the load changes from 4 A to 20 A, the overshooting
voltage is about 35 mV.
Figure 14 shows the transient waveform with and without the transient comparator. Using the transient
comparator yields a settling time of 10-μs faster than without.
The output ripple is about 15 mVP−P at 20-A output. When the load changes from 0 A to 13 A, the overshoot
voltage is approximately 80 mV, and the undershoot is is approximately 60 mV as shown in Figure 15. When the
transient comparator is triggered, the powergood (PWRGD) signal goes low.
22
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VOUTac (50 mV/div)
IOUT (10 A/div)
Time (200 μs/div)
VIN = 3.3 V
VIN = 3.3 V
Without Transient
Comparator
With Transient
Comparator
With Transient
Comparator
Without Transient
Comparator
IOUT (10 A/div)
IOUT (10 A/div)
Time (10 μs/div)
Time (10 μs/div)
G005
Figure 14. Transient Response Undershoot/Overshoot
VPWRGD
(2.5 V/div)
VOUTac (100 mV/div)
IOUT (10 A/div)
Time (200 μs/div)
G006
Figure 15. Transient Response
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TYPICAL CHARACTERISTICS
SPACER
MAXIMUM DUTY CYCLE
vs
JUNCTION TEMPERATURE
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
1000
99
950
900
Oscillator Frequency (kHz)
Maximum Duty Cycle (%)
98
97
96
VDD = 3.3 V, RT = 69.8 kΩ
95
RT = 35 kΩ
850
800
750
700
650
600
RT = 69.8 kΩ
550
94
VDD = 5 V, RT = 35 kΩ
500
450
93
–50
–25
0
25
50
75
100
–50
125
–25
0
25
75
50
100
G008
G007
Figure 16.
Figure 17.
SHUTDOWN SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
REFERENCE VOLTAGE
vs
JUNCTION TEMPERATURE
0.700
697
695
0.650
693
Reference Voltage (mV)
Shutdown Supply Current (mA)
0.675
0.625
0.600
0.575
691
689
687
0.550
685
0.525
0.500
683
–50
–25
0
25
50
75
100
125
–50
Junction Temperature (°C)
–25
0
25
50
75
100
125
Junction Temperature (°C)
G009
Figure 18.
24
125
Junction Temperature (°C)
Junction Temperature (°C)
G010
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
SPACER
SWITCHING FREQUENCY
vs
TIMING RESISTANCE
SOFT-START SOURCING CURRENT
vs
JUNCTION TEMPERATURE
3.50
1000
VIN = 3.9 V
3.45
900
3.40
Soft-Start Sourcing Current (μA)
Switching Frequency (kHz)
800
700
600
500
400
3.35
3.30
3.25
3.20
3.15
300
3.10
200
3.05
3.00
100
20
40
60
80
100
120
140
–50
160
–25
0
25
50
75
100
125
Junction Temperature (°C)
Timing Resistance (kΩ)
G012
G011
Figure 20.
Figure 21.
ILIM OFFSET VOLTAGE
vs
JUNCTION TEMPERATURE
SHUTDOWN THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
0.30
20
0.29
15
VDD = 2.0
0.28
Shutdown Threshold Voltage (V)
ILIM Offset Voltage (mV)
10
5
0
VDD = 3.2
–5
–10
Enable
0.27
0.26
0.25
Disable
0.24
0.23
0.22
–15
0.21
VDD = 4.9
0.20
–20
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
G014
G013
Figure 22.
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
SPACER
ILIM SINK CURRENT
vs
JUNCTION TEMPERATURE
200
198
VDD = 3.3 V
VOUT = 1.5 V
fSW = 300 kHz
VOUT
ILIM Sink Current (μA)
196
194
192
190
LDRV
188
186
SW
184
182
VDD = 3 V
RT = 69.8 kΩ
180
Time (1 μs/div)
G016
–50
–25
0
25
50
75
100
125
Junction Temperature (°C)
G015
Figure 24.
Figure 25. TPS40021 Discontinuous Mode (DCM)
VDD = 3.3 V
VOUT = 1.5 V
fSW = 300 kHz
VOUT
VDD = 3.3 V
VOUT = 1.5 V
fSW = 300 kHz
SS/SD
VOUT
LDRV
SW
SW
Time (1 μs/div)
Time (20 ms/div)
G017
Figure 26. TPS40021 IZERO Detection – DCM
26
G018
Figure 27. Output Current Fault Operation
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SLUSB58 – SEPTEMBER 2012
TYPICAL CHARACTERISTICS (continued)
SPACER
VDD = 3.3 V
VOUT = 1.5 V
fSW = 300 kHz
ILOAD = 5 A
SS/SD
PVDD
VDD = 3.3 V
VOUT = 1.5 V
fSW = 300 kHz
ILOAD = 5 A
SW
VOUT
PWRGD
VOUT
Time (1 ms/div)
Time (25 μs/div)
G019
G020
Figure 28. Start-Up Operation Without Transient
Comparators
Figure 29. PVDD Hysteresis
VDD = 3.3 V
VOUT = 1.5 V
fSW = 300 kHz
ILOAD = 5 A
VDD = 3.3 V
VOUT = 1.5 V
fSW = 300 kHz
ILOAD = 5 A
SD
SS/SD
COMP
SW
VOUT
PWRGD
Time (200 μs/div)
Time (1 ms/div)
G022
G021
Figure 30. Start-Up Operation With Transient Comparators
Figure 31. COMP Shutdown Operation
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TYPICAL CHARACTERISTICS (continued)
SPACER
VDD = 3.3 V
VOUT = 1.5 V
fSW = 300 kHz
VDD = 3.3 V
VOUT = 1.5 V
fSYNC = 330 kHz
ILIM
SW
SS/SD
PWRGD
LDRV
Time (500 ns/div)
Time (1 μs/div)
G024
G023
Figure 32. PWRGD Shutdown Operation
28
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Figure 33. External Synchronization
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Product Folder Links: TPS40021-EP
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS40021MPWPEP
ACTIVE
HTSSOP
PWP
16
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
40021M
TPS40021MPWPREP
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
40021M
V62/12601-01XE
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
40021M
V62/12601-01XE-T
ACTIVE
HTSSOP
PWP
16
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
40021M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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