PW
TPS40090
TPS40091
RHD
SLUS578B – OCTOBER 2003 – REVISED MAY 2006
www.ti.com
HIGH-FREQUENCY, MULTIPHASE CONTROLLER
Check for Samples: TPS40090, TPS40091
FEATURES
1
DROOP
REF
COMP
5
6
7
CSCN
ILIM
3
4
CS3
CS4
1
11
NC
EN/SYNC
24
12
GNDS
VIN
23
13
PGOOD
BP5
22
14
NC
15
25
SS
VOUT
NC
17
10
16
26
RT
DIFFO
NC
GND
FB
9
19
8
27
18
Internet Servers
Network Equipment
Telecommunications Equipment
DC Power Distributed Systems
28
CS1
PWM3
•
•
•
•
CS2
PWM4
APPLICATIONS
EN/SYNC
VIN
BP5
PWM1
PWM2
PWM3
PWM4
GND
RT
SS
PGOOD
GNDS
RHD PACKAGE
(BOTTOM VIEW)
2
•
•
•
•
1% Internal 0.7-V Reference
Resistive Divider Set Output Voltage
True Remote Sensing Differential Amplifier
Resistive or DCR Current Sensing
Current Sense Fault Protection
Programmable Load Line
Compatible with UCC37222 Predictive Gate
Drive™ Technology Drivers
24-Pin Space-Saving TSSOP Package
28-Pin QFN Package
TPS40090: Binary Outputs
TPS40091: 3-State Outputs
24
23
22
21
20
19
18
17
16
15
14
13
21
•
•
•
•
•
•
•
Patent pending.
1
2
3
4
5
6
7
8
9
10
11
12
CS1
CS2
CS3
CS4
CSCN
ILIM
DROOP
REF
COMP
FB
DIFFO
VOUT
20
(1)
PW PACKAGE
(TOP VIEW)
PWM1
•
Two-, Three-, or Four-Phase Operation
5-V to 15-V Operating Range
Programmable Switching Frequency Up to
1-MHz/Phase
Current Mode Control With Forced Current
Sharing(1)
PWM2
•
•
•
2
DESCRIPTION
The TPS4009x is a two-, three-, or four-phase programmable synchronous buck controller that is optimized for
low-voltage, high-current applications powered by a 5-V to 15-V distributed supply. A multi-phase converter offers
several advantages over a single power stage including lower current ripple on the input and output capacitors,
faster transient response to load steps, improved power handling capabilities, and higher system efficiency.
Each phase can be operated at a switching frequency up to 1-MHz, resulting in an effective ripple frequency of
up to 4-MHz at the input and the output in a four-phase application. A two-phase design operates 180 degrees
out-of-phase, a three-phase design operates 120 degrees out-of-phase, and a four-phase design operates 90
degrees out-of-phase as shown in Figure 1.
The number of phases is programmed by connecting the de-activated phase PWM output to the output of the
internal 5-V LDO. In two-phase operation the even phase outputs should be de-activated.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Predictive Gate Drive is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated
TPS40090
TPS40091
SLUS578B – OCTOBER 2003 – REVISED MAY 2006
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
The TPS4009x uses fixed frequency, peak current mode control with forced phase current balancing. When
compared to voltage mode control, current mode results in a simplified feedback network and reduced input line
sensitivity. Phase current is sensed by using either current sense resistors installed in series with output
inductors or, for improved efficiency, by using the DCR (direct current resistance) of the filter inductors. The latter
method involves generation of a current proportional signal with an R-C circuit (shown in Figure 10).
The R-C values are selected by matching the time constants of the R-C circuit and the inductor; R-C = L/DCR.
With either current sense method, the current signal is amplified and superimposed on the amplified voltage error
signal to provide current mode PWM control.
An output voltage droop can be programmed to improve the transient window and reduce size of the output filter.
Other features include a single voltage operation, a true differential sense amplifier, a programmable current
limit, soft-start and a power good indicator.
SIMPLIFIED TWO-PHASE APPLICATION DIAGRAM
TPS40090PW
CBP5
2
CS2
4
CS4
CS3
RCS3
3
CCS3
14
PGOOD
22
BP5
6
ILIM
17
GND
CSCN
5
CCS1
R CS1
CSS
15
CS1
1
VIN
23
VIN (4.5 V to 15 V)
CIN
SS
R ILIM2
L1
RRT
16
RT
7
DROOP
8
REF
R DROOP
R ILIM1
R FB2
2
21
BP5
CREF
R FB3
PWM1
24
EN/SYNC
9
COMP
10
FB
CFB1
PWM2
20
PWM4
18
L2
R FB1
PWM3
11
DIFFO
13
GNDS
12
VOUT
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TI
Synchronous
Buck
Driver
19
TI
Synchronous
Buck
Driver
VOUT
(0.7 V to 3.5 V)
COUT
Copyright © 2003–2006, Texas Instruments Incorporated
Product Folder Link(s): TPS40090 TPS40091
TPS40090
TPS40091
SLUS578B – OCTOBER 2003 – REVISED MAY 2006
www.ti.com
ORDERING INFORMATION
PACKAGE (1)
TA
Plastic TSSOP (PW) (2)
40°C to 85°C
OUTPUT
PART NUMBER
Binary
TPS40090PW
3-State
TPS40091PW
TPS40090RHDR
QFN (RHD) (3)
(1)
(2)
(3)
TPS40091RHDR
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
The PWP package is available taped and reeled. Add a R suffix to the device type (i.e., TPS40090PWR).
The RHD package is available taped and reeled. Add a R suffix to the device type (i.e., TPS40090RHDR) to order quantities of 3000
parts per reel. Add a T suffix to the device type (i.e., TPS40090RHDT) to order quantities of 250 parts per reel.
ABSOLUTE MAXIMUM RATING
over operating free-air temperature range unless otherwise noted (1)
TPS40090
TPS40091
EN/SYNC, VIN,
16.5 V
VIN
Input voltage range
VOUT
Output voltage range
TJ
Operating junction temperature range
-40°C to 125°C
Tstg
Storage temperature
-5°C to 150°C
(1)
CS1, CS2, CS3, CS4, CSCN, DROOP, FB, GNDS, ILIM, VOUT
-0.3 V to 6 V
REF, COMP, DIFFO, PGOOD, SS, RT, PWM1, PWM2, PWM3, PWM4, BP5
-0.3 V to 6 V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VIN
Input voltage
4.5
15
V
TA
Operating free-air temperature
-40
85
°C
Copyright © 2003–2006, Texas Instruments Incorporated
Product Folder Link(s): TPS40090 TPS40091
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TPS40090
TPS40091
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ELECTRICAL CHARACTERISTICS
TA = -40°C to 85°C, VIN = 12 V, R(RT) = 64.9 kΩ, TJ = TA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Operating voltage range, VIN
4.5
15
VIN
UVLO
Rising VIN
4.25
4.45
VIN
UVLO (1)
Falling VIN
4.1
4.35
IIN
Shutdown current, VIN
IIN
Quiescent current switching
Four channels, 400 kHz each, no load
V
2
10
μA
4
6
mA
OSCILLATOR/SYNCHRONIZATION
Phase frequency accuracy
Four channels, RRT = 64.9 kΩ
370
Phase frequency set range (1)
Four channels
100
415
1200
455
Synchronization frequency range (1)
Four channels
800
9600
Synchronization input threshold (1)
Four channels
VBP5/2
4-phase operation
87.5%
2- and 3-phase operation
83.3%
kHz
V
PWM
Maximum duty cycle per channel
Minimum duty cycle per channel
(1)
0
Minimum controllable on-time (1)
50
100
ns
0.700
0.707
V
25
150
nA
ERROR AMPLIFIER
Feedback input voltage
0.693
Feedback input bias current
VFB = 0.7 V
VOH
High-level output voltage
ICOMP = -1 mA
VOL
low-level output voltage
ICOMP = 1 mA
GBW
Gain bandwidth (1)
5
MHz
AVOL
Open loop gain (1)
90
dB
2.5
2.9
0.5
0.8
V
SOFT START
ISS
Soft-start source current
3.5
5
6
μA
VSS
Soft-start clamp voltage
0.95
1.00
1.05
V
Enable threshold voltage
0.8
2
ENABLE
Enable voltage capability (1)
2.5
VIN(max)
V
PWM OUTPUT
Ilkg
PWM pull-up resistance
IOH = 5 mA
27
45
PWM pull-down resistance
IOL = 10 mA
27
45
PWM output leakage (1)
3-State
(2)
1
Ω
μA
5V REGULATOR
VOUT
Output voltage
External ILOAD = 2 mA on BP5
Pass device voltage drop
VIN = 4.5 V, No external load on BP5
4.8
Short circuit current
(1)
(2)
4
10
5
5.2
V
200
mV
30
mA
Specified by design. Not production tested.
TPS40091 only.
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Copyright © 2003–2006, Texas Instruments Incorporated
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TPS40091
SLUS578B – OCTOBER 2003 – REVISED MAY 2006
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
TA = -40°C to 85°C, VIN = 12 V, R(RT) = 64.9 kΩ, TJ = TA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
4.9
5.4
MAX
UNIT
CURRENT SENSE AMPLIFIER
Gain transfer
100 mV ≤ V(CS) ≤ 100 mV, VCSRTN = 1.5 V
Gain variance between phases
VCS = 100 mV
-4%
Input offset variance at zero current
VCS = 0 V
-3.5
Input common mode
(3)
0
0
Bandwidth (3)
5.9
V/V
4%
3.5
4
18
mV
V
MHz
DIFFERENTIAL AMPLIFIER
Gain
CMRR
1
Gain tolerance
VOUT 4 V vs 0.7 V, VGNDS = 0 V
Common mode rejection ratio (3)
0.7 V ≤ VOUT ≤ 4 V
Bandwidth
(3)
-0.5%
V/V
0.5%
60
dB
5
MHz
RAMP
Ramp amplitude (3)
0.4
0.5
0.6
V
POWER GOOD
PGOOD high threshold
wrt VREF
10%
14%
PGOOD low threshold
wrt VREF
-14%
-10%
VOL
Low-level output voltage
IPGOOD = 4 mA
Ilkg
PGOOD output leakage
VPGOOD = 5 V
0.35
0.60
V
50
80
μA
OUTPUT OVERVOLTAGE/UNDERVOLTAGE FAULT
VOV
Overvoltage threshold voltage
VFBK relative to VREF
15%
19%
VUV
Undervoltage threshold voltage
VFBK relative to VREF
-18%
-14%
LOAD LINE PROGRAMMING
IDROOP
(3)
Pull-down current on DROOP
4-phase, VCS = 100 mV
40
μA
Specified by design. Not production tested.
Copyright © 2003–2006, Texas Instruments Incorporated
Product Folder Link(s): TPS40090 TPS40091
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TPS40090
TPS40091
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
22
O
Output of an internal 5V regulator. A 4.7-μF capacitor should be connected from this pin to ground. For 5V applications,
this pin should be connected to VDD.
7
9
O
Output of the error amplifier. The voltage at this pin determines the duty cycle for the PWM.
27
1
I
28
2
I
1
3
I
CS4
2
4
I
CSCN
3
5
I
Common point of current sense resistors or filter inductors
DIFFO
9
11
O
Output of the differential amplifier. The voltage at this pin represents the true output voltage without drops that result
from high current in the PCB traces
DROOP
5
7
I
Used to program droop function. A resistor between this pin and the REF pin sets the desired droop value.
EN/SYNC
24
24
I
A logic high signal on this input enables the controller operation. A pulsing signal to this pin synchronizes the main
oscillator to the rising edge of an external clock source. These pulses must be of higher frequency than the free
running frequency of the main oscillator set by the resistor from the RT pin.
FB
8
10
I
Inverting input of the error amplifier. In closed loop operation, the voltage at this pin is the internal reference level of
700 mV. This pin is also used for the PGOOD and OVP comparators.
GND
17
17
GNDS
12
13
I
Inverting input of the differential amplifier. This pin should be connected to ground at the point of load.
ILIM
4
6
I
Used to set the cycle-by-cycle current limit threshold. If ILIM threshold is reached, the PWM cycle is terminated and the
converter delivers limited current to the output. Under these conditions the undervoltage threshold is reached
eventually and the controller enters the hiccup mode. The controller stays in hiccup mode for seven consecutive cycles.
At the eighth cycle the controller attempts a full start-up sequence.
PGOOD
13
14
O
Power good indicator of the output voltage. This open-drain output connects to the supply via an external resistor.
PWM1
21
21
O
PWM2
20
20
O
PWM3
19
19
O
PWM4
18
18
O
REF
6
8
O
Output of an internal 0.7-V reference voltage.
RT
16
16
I
Connecting a resistor from this pin to ground sets the oscillator frequency.
VIN
23
23
I
Power input for the chip. De-coupling of this pin is required.
VOUT
10
12
I
Noninverting input of the differential amplifier. This pin should be connected to VOUT at the point of load.
SS
15
15
I
Provides user programmable soft-start by means of a capacitor connected to the pin.
NC
11, 14,
25, 26
-
-
No connect pins
NAME
RHD
PW
22
COMP
CS1
CS2
CS3
BP5
6
Used to sense the inductor current in the phases. Inductor current can be sensed with an external current sense
resistor or by using an external circuit and the inductor's DC resistance. They are also used for overcurrent protection
and forced current sharing between the phases.
Ground connection to the device.
Phase shifted PWM outputs which control the external drivers. The high output signal commands a PWM cycle. The
low output signal commands controlled conduction of the synchronous rectifiers. These pins are also used to program
various operating modes as follows: for three-phase mode, PWM4 is connected to 5 V; for two-phase mode, PWM2
and PWM4 are connected to 5 V.
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TPS40091
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www.ti.com
FUNCTIONAL BLOCK DIAGRAM
RT
16
TPS40090PW
COMP
9
CLOCK
FB 10
+
5 mA
DROOP 7
REF
8
01
A = -(K +Y)
B = +1
A
SS 15
+
21 PWM1
IDROOP
B
1/N
+ 700 mV
02
+
20 PWM2
PH2
PH4
A
DIFFO 11
GNDS 13
VOUT 12
CSCN
1
CS2
2
CS3
CS4
3
4
+
19 PWM3
A
+
04
B
5
CS1
03
B
+
18 PWM4
A
gM
PHDET
IPH1
+
gM
+
IPH3
gM
+
PH2
IPH2
B
Σ IPH x K
PH2
gM
+
IPH1
IPH4
IPH2
POWER
GOOD
IPH3
CURRENT
LIMIT
5V
REG
IPH4
14
16
24
PGOOD
ILIM
EN/SYNC
Product Folder Link(s): TPS40090 TPS40091
23 VIN
22 BP5
17 GND
PH4
Copyright © 2003–2006, Texas Instruments Incorporated
PH4
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7
TPS40090
TPS40091
SLUS578B – OCTOBER 2003 – REVISED MAY 2006
www.ti.com
APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
The TPS4009x is a multiphase, synchronous, peak current mode, buck controller. The controller uses external
gate drivers to operate N-channel power MOSFETs. The controller can be configured to operate in a two-, three-,
or four-phase power supply.
The controller accepts current feedback signals from either current sense resistors placed in series with the filter
inductors or current proportional signals derived from the inductors' DCR.
Other features include an LDO regulator with UVLO to provide single voltage operation, a differential input
amplifier for precise output regulation, user programmable operation frequency for design flexibility, external
synchronization capability, programmable pulse-by-pulse overcurrent protection, output overvoltage protection,
and output undervoltage shutdown.
DIFFERENTIAL AMPLIFIER
The unity gain differential amplifier with high bandwidth allows improved regulation at a user-defined point and
eases layout constraints. The output voltage is sensed between the VOUT and GNDS pins. The output voltage
programming divider is connected to the output of the amplifier (DIFFO). The differential amplifier can be used
only for output voltages lower then 3.3 V.
If there is no need for a differential amplifier, or if the output voltage required is higher than 3.3-V, the differential
amplifier can be disabled by connecting the GNDS pin to the BP5 pin. The voltage programming divider in this
case should be connected directly to the output of the converter.
CURRENT SENSING AND BALANCING
The controller employs a peak current-mode control scheme, which naturally provides a certain degree of current
balancing. With current mode, the level of current feedback should comply with certain guidelines depending on
duty factor, known as slope compensation to avoid sub-harmonic instability. This requirement can prohibit
achieving a higher degree of phase current balance. To avoid the controversy, a separate current loop that
forces phase currents to match is added to the proprietary control scheme. This effectively provides high degree
of current sharing independently of properties of controller's small signal response.
High-bandwidth current amplifiers can accept as an input voltage either voltage drop across dedicated precise
current-sense resistors, or inductor's DCR voltage derived by an R-C network, or thermally compensated voltage
derived from the inductor's DCR. The wide range of current-sense settings eases the cost and complexity
constraints and provides performance superior to those found in controllers using low-side MOSFET current
sensing.
8
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SETTING CONTROLLER CONFIGURATION
By default, the controller operates at four-phase configuration. The alternate number of active phases is
programmed by connecting unused PWM outputs to BP5. (See Figure 1) For example, for three-phase
operation, the unused fourth phase output, PWM4, should be connected to BP5. For two-phase operation, the
second, PWM2, and the fourth, PWM4, outputs should be connected to BP5.
POWER UP
Capacitors connected to the BP5 pin and the soft-start pin set the power-up time. When EN is high, the capacitor
connected to the BP5 pin gets charged by the internal LDO as shown in Figure 2.
4.5 C BP5
t BPS +
8 10 *3
(1)
EN
1
4-Phase
Operation
BP5
2
3
SS
4
1.0
0.7
1
3-Phase
Operation
2
VOUT
3
4
BP5
PGOOD
1
t - Time
2-Phase
Operation
2
BP5
3
4
BP5
Figure 1. Programming Controller Configuration
Figure 2. Power-Up Waveforms
Copyright © 2003–2006, Texas Instruments Incorporated
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TPS40091
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When the BP5 pin voltage crosses its lower undervoltage threshold and the power-on reset function is cleared,
the calibrated current source starts charging the soft start capacitor. The PGOOD pin is held low during the start
up. The rising voltage across the capacitor serves as a reference for the error amplifier assuring start-up in a
closed loop manner. When the soft start pin voltage reaches the level of the reference voltage VREF = 0.7 V, the
converter's output reaches the regulation point and further rise of the soft start voltage has no effect on the
output.
0.7 C SS
t SS +
5 10 *6
(2)
When the soft-start voltage reaches level of 1 V, the power good (PGOOD) function is cleared and reported on
the PGOOD pin. Normally, the PGOOD pin goes high at this moment. The time from when SS begins to rise to
when PGOOD is reported is:
t PG + 1.43 T SS
(3)
OUTPUT VOLTAGE PROGRAMMING
The converter output voltage is programmed by the R1/R2 divider from the output of the differential amplifier. The
center point of the divider is connected to the inverting output of the error amplifier (FB), as shown in Figure 5.
V OUT + 0.7 V
ǒR1
) 1Ǔ
R2
(4)
CURRENT SENSE FAULT PROTECTION
Multiphase controllers with forced current sharing are inherently sensitive to failure of a current sense
component. In the event of such failure, the whole load current can be steered with catastrophic consequences
into a single channel where the fault has happened. The dedicated circuit in the TPS4009x controller prevents it
from starting up if any current sense pin is open or shorted to ground. The current-sense fault detection circuit is
active only during device initialization, and it does not provide protection should a current-sense failure happen
during normal operation.
OVERVOLTAGE PROTECTION
If the voltage at the FB pin (VFB) exceeds VREF by more than 16%, the TPS4009x enters into an overvoltage
state. In this condition, the output signals from the controller to the external drivers is pulled low, causing the
drivers to force all of the upper MOSFETs to the OFF position and all the lower MOSFETs to the ON position. As
soon as VFB returns to regulation, the normal operating state resumes.
10
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OVERCURRENT PROTECTION
The overcurrent function monitors the voltage level separately on each current sense input and compares it to
the voltage on the ILIM pin set by a divider from the controller's reference. In case a threshold of V(ILIM)/2.7 is
exceeded the PWM cycle on the associated phase is terminated. The voltage level on the ILIM pin is determined
by the following expression:
V ILIM + 2.7 I PH(max) R CS
(5)
I PH(max) + I OUT )
ǒVIN * VOUTǓ
2
L
V OUT
f SW
V IN
where:
• IPH(max) is a maximum value of the phase current allowed
• RCS is a value of the current sense resistor used
(6)
If the overcurrent condition continues, each phase's PWM cycle is terminated by the overcurrent signals. This
puts a converter in a constant current mode with the output current programmed by the ILIM voltage. Eventually,
the supply and demand equilibrium on the converter output fails and the output voltage declines. When the
undervoltage threshold is reached, the converter enters a hiccup mode. The controller is stopped and the output
is not regulated any more, the softstart pin function changes. It now serves as a timing capacitor for a fault
control circuit. The soft-start pin is periodically charged and discharged by the fault control circuit. After seven
hiccup cycles expire, the controller attempts to restore normal operation. If the overload condition is not cleared,
the controller stays in the hiccup mode indefinitely. In such conditions, the average current delivered to the load
is roughly 1/8 of the set overcurrent value.
UNDERVOLTAGE PROTECTION
If the FB pin voltage falls lower than the undervoltage protection threshold (84.5%), the controller enters the
hiccup mode as it is described in the Overcurrent Protection section.
FAULT-FREE OPERATION
If the SS pin voltage is prevented from rising above the 1-V threshold, the controller does not execute nor report
most faults and the PGOOD output remains low. Only the overcurrent function and current-sense fault remain
active. The overcurrent protection continues to terminate PWM cycle every time when the threshold is exceeded
but the hiccup mode is not entered.
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SETTING THE SWITCHING FREQUENCY
The clock frequency is programmed by the value of the timing resistor connected from the RT pin to ground.
R RT + KPH
ǒ39.2
10 3
f *1.041
* 7Ǔ
PH
(7)
where:
KPH is a coefficient that depends on the number of active phases. For two-phase and three-phase
configurations, KPH= 1.333. For four-phase configurations, KPH= 1. fPH is a single phase frequency, kHz. The
RT resistor value is returned by the last expression in kΩ.
To calculate the output ripple frequency, use the following equation:
F RPL + NPH f PH
where:
•
NPH is a number of phases used in the converter.
(8)
The switching frequency of the controller can be synchronized to an external clock applied to the EN/SYNC pin.
The external frequency should be somewhat higher than the free-running clock frequency for synchronization to
take place.
SWITCHING FREQUENCY
vs
TIMING RESISTANCE
fSW - Switching Frequency - kHz
10000
100
0
50
100
150
200
250
300
RT - Timing Resistance - kΩ
Figure 3.
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SETTING THE OUTPUT VOLTAGE DROOP
In many applications, the output voltage of the converter is intentionally allowed to droop as load current
increases. This approach (sometimes referred to as active load line programming) allows for better use of the
regulation window and reduces the amount of the output capacitors required to handle the same load current
step. A resistor from the REF pin to the DROOP pin sets the desired value of the output voltage droop.
2500 NPH VDROOP
2500 NPH VDROOP
VREF
R2
R DROOP +
+
VOUT
I OUT RCS
VCS1 ) VCS2 ) VCS3 ) VCS4 R1 ) R2
•
•
•
•
•
where:
VDROOP is the value of droop at maximum load current IOUT
NPH is number of phases
RCS is the current-sense resistor value
2500 Ω is the inversed value of transconductance from the current sense pins to DROOP
VCSx, are the average voltages on the current sense pins
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
GNDS
(9)
Differential
Amplifier
13
VOUT
+
12
VOUT
DIFFO
11
VOUT - Output Voltage - V
VDROOP
COMP
9
R1
I DROOP
C1
Error
Amplifier
R3 FB
10
+
DROOP
R2
0
IOUT(max)
7
I DROOP
RDROOP
REF
+
IOUT - Output Current - A
8
700 mV
Figure 4.
Figure 5.
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FEEDBACK LOOP COMPENSATION
The TPS4009x operates in a peak current mode and the converter exhibits a single pole response with ESR zero
for which Type II compensation network is usually adequate, as shown in Figure 7.
The following equations show where the load pole and ESR zero calculations are situated.
1
1
f OP +
f ESRZ +
2p R OUT C OUT
2p R ESR C OUT
(10)
To achieve desired bandwidth the error amplifier must compensate for modulator gain loss on the crossover
frequency and this is facilitated by placing the zero over the load pole. The ESR zero alters the modulator's -1
slope at higher frequencies. To compensate for that alteration, the pole in-error amplifier transfer function should
be added at frequency of the ESR zero as shown in Figure 6.
Figure 6.
The following equations help in choosing components of the error amplifier compensation network. Fixing the
value of the resistor R1 first is recommended as it simplifies further adjustments of the output voltage without
altering the compensation network.
R2 + R1
10
ǒ
*GOMAG
20
Ǔ;
C1 +
ǒ2p
1
F OP
R2Ǔ
;
C2 +
ǒ2p
1
F ESRZ
R2Ǔ
where:
•
GOMAG is the control to output gain at desired system crossover frequency.
(11)
Introduction of output voltage droop as a measure to reduce amount of filter capacitors changes the transfer
function of the modulator as it is shown in the Figure 8.
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GAIN AND PHASE
vs
FREQUENCY WITH DROOP
GAIN AND PHASE
vs
FREQUENCY WITHOUT DROOP
80
80
Converter Overall
EA
60
40
Type II
G - Gain - dB
G - Gain - dB
40
60
Modulator
20
Droop Zero
20
0
0
Load Pole
Load Pole
ESR Zero
-20
-20
ESR Zero
-40
-40
200
200
150
150
Phase
100
Phase - °
Phase - °
100
50
50
0
0
-50
-50
-100
-100
10
100
1k
10 k
f - Frequency - Hz
100 k
1M
10
100
Figure 7.
1k
10 k
f - Frequency - Hz
100 k
1M
Figure 8.
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The droop function, as well as the output capacitor ESR, introduces zero on some frequency left of the crossover
point.
1
F
+
DROOPZ
2p
Ǔ
ǒ
VDROOP
I OUT(max)
COUT
(12)
To compensate for this zero, pole on the same frequency should be added to the error amplifier transfer function.
With Type II compensation network a new value for the capacitor C2 is required compared to the case without
droop.
C1
C2 +
2p R2 C1 ǒF DROOPZ * 1Ǔ
(13)
When attempting to close the feedback loop at frequency that is near the theoretical limit, use the above
considerations as a first approximation and perform on bench measurements of closed loop parameters as
effects of switching frequency proximity and finite bandwidth of voltage and current amplifiers may substantially
alter them as it is shown in Figure 9.
GAIN AND PHASE
vs
FREQUENCY
60
80
Phase
50
60
30
40
20
10
Phase - °
G - Gain - dB
40
20
Gain
0
0
-10
-20
100
VIN = 12 V
VOUT = 1.5 V
IOUT= 100 A
1k
-20
1M
10 k
100 k
f - Frequency - Hz
Figure 9.
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THERMAL COMPENSATION OF DCR CURRENT SENSING
Inductor DCR current sensing is a known lossless technique to retrieve a current proportional signal. Equation 14
and Equation 15 show the calculation used to determine the DCR voltage drop for any given frequency. (See
Figure 10)
DCR
V DCR + ǒVIN * VOUTǓ
DCR ) w L
(14)
1
V C + ǒVIN * VOUTǓ
w C
R) 1
w C
(15)
ǒ
Ǔ
Voltage across the capacitor is equal to voltage drop across the inductor DCR, VC = VDCR when time constant of
the inductor and the time constant of the R-C network are equal:
DCR
1
L + R C; t
VC +
+
;
DCRL + t RC
DCR ) w L DCR
1
w C
R)
w C
(16)
ǒ
Ǔ
The output signal generated by the network shown in Figure 10 is temperature dependant due to positive thermal
coefficient of copper specific resistance as determined using Equation 17. The temperature variation of the
inductor coil can exceed 100°C in a practical application leading to approximately 40% variation in the output
signal and in turn, respectively move the overcurrent threshold and the load line.
K(T) + 1 ) 0.0039 (T * 25)
(17)
The relatively simple network shown in Figure 11 (made of passive components including one NTC resistor) can
provide almost complete compensation for copper thermal variations.
L
DCR
C
R
R2
R1
RNTC
RTHE
Figure 10.
Figure 11.
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The following algorithm and expressions help to determine components of the network.
1. Calculate the equivalent impedance of the network at 25°C that matches the inductor parameters in
Equation 18. Use of COG type capacitors for this application is recommended. For example, for L = 0.4 μH,
DCR = 1.22 mΩ, C = 10 nF; RE = 33.3 kΩ. It is recommended to keep RE < 50 kΩ as higher values may
produce false triggering of the current sense fault protection.
L
DCR
RE +
C
(18)
2. It is necessary to set the network attenuation value KDIV(25) at 25°C. For example, KDIV(25) = 0.85. The
attenuation values KDIV(25) > 0.9 produces higher values for NTC resistors that are harder to get from
suppliers. Attenuation values lower 0.7 substantially reduce the network output signal.
3. Based on calculated RE and KDIV(25) values, calculate and pick the closest standard value for the resistor R
= RE/KDIV(25). For the given example R = 33 kΩ/ 0.85 = 38.8 kΩ. The closest standard value from 1% line is
R = 39.2 kΩ.
4. Pick two temperature values at which curve fitting is made. For example T1 = 50°C and T2 = 90°C.
5. Find the relative values of RTHE required on each of these temperatures.
R
(T1)
R
(T2)
R THE1 + THE
R THE2 + THE
R THE(25)
R THE(25)
(19)
RT +
K DIV(T)
1 * K DIV(T)
R
K DIV(25)
1 ) 0.0039 (t * 25)
K DIV(T) +
(20)
For the given example RTHE1= 0.606, RTHE2=0.372.
6. From the NTC resistor datasheet get the relative resistance for resistors with desired curve. For the given
example and curve 17 for NTHS NTC resistors from Vishay RNTC1= 0.3507 and RNTC2= 0.08652.
7. Calculate relative values for network resistors including the NTC resistor.
R1 R +
ǒRNTC1 * RNTC2Ǔ
RNTC1
RE1
RE1
R E2 * R NTC1
R E2
ǒ1 * R NTC2Ǔ * RNTC2
ǒ1 * RNTC2Ǔ ) RNTC2 R E1 ǒ1 * RNTC1Ǔ
RE2 ǒ1 * R NTC1Ǔ * ǒR NTC1 * R NTC2Ǔ
(21)
RNTC R +
18
ƫ
ƪ
R NTC1
1
*
1 * R1R RE1 * R1 R
R2 R + ǒ1 * R NTC1Ǔ
ƪǒ1 * R1 Ǔ
R
*1
* ǒR2RǓ
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ƫ
*1
*1
(22)
*1
(23)
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For the given example R1R= 0.281, R2R = 2.079, and RNTCR = 1.1.
8. Calculate the absolute value of the NTC resistor as RTHE(25). In given example RNTC = 244.3 kΩ.
9. Find a standard value for the NTC resistor with chosen curve type. In case the close value does not exist in a
desired form factor or curve type. Chose a different type of the NTC resistor and repeat steps 6 to 9. In the
example, the NTC resistor with the part number NTHS0402N17N2503J with RNTCS(25) = 250 kΩ is close
enough to the calculated value.
10. Calculate a scaling factor for the chosen NTC resistor as a ratio between selected and calculated NTC value
and. In the example k = 1.023.
RNTC S
k+
RNTC C
(24)
11. Calculate values of the remaining network resistors.
R1 C + RTHE(25)
ƪǒ(1 * k) ) k
R1 RǓƫ
(25)
For the given example, R1C= 58.7 kΩ and R2C = 472.8 kΩ. Pick the closest available 1% standard values:
R1 = 39.2 kΩ, and R2 = 475 kΩ, thus completing the design of the thermally compensated network for the
DCR current sensor.
Figure 12 illustrates the fit of the designed network to the required function.
CURRENT SENSE IMPEDANCE
vs
AMBIENT TEMPERATURE
40
r
Measured
RTHE (T5C) - Current Sense Impedance - kΩ
Acquired
30
r
20
10
r
r
10
20
40
60
80
100
TA - Ambient Temperature - °C
120
Figure 12.
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Operation with Output Voltages Higher Than 3.3 V
The TPS40090/91 controllers are designed to operate in power supplies with output voltages ranging from 0.7 V
to 3.3 V. To support higher output voltages, mainly in 12 V to 5 V power supplies, the BP5 voltage needs to be
increased slightly to provide enough headroom to ensure linearity of current sense amplifiers. The simple circuit
on Figure 13 shows a configuration that generates a 6-V voltage source to power the controller with increased
bias voltage. Both the VIN and BP5 pins should be connected to this voltage source. The differential amplifier
normally excessive for higher-output voltages can be disabled by connecting GNDS pin to the BP5 pin.
12 V
TPS4009x
1.1 kW
EN/SYNC
24
13.7 kW
VIN 23
6V
BP5 22
4.7 mF
TLA431
10 kW
Figure 13. Biasing the TPS4009x with a 5-V Power Supply
High-Impedance State of TPS40091 Outputs
The TPS40091 controller has 3-state enabled outputs to interface various gate drivers and DRMOS devices
capable of turning all MOSFETs in the power supply into high-impedance state while remaining active. The
common binary output commands the control MOSFET on when the PWM signal is high. Alternatively, the
synchronous MOSFET is commanded on when the PWM signal is low.
The 3-state output can command both MOSFETs off when the PWM output is in the high-impedance state. This
feature simplifies design of power supplies capable of starting into precharged output or allows in VR modules
use of gate drivers that do not have the enable input to put VR module off line. Some DRMOS devices like the
Philips PIP202 are also compatible with 3-state outputs of the multiphase controller.
The TPS40091 outputs have high impedance when the EN pin is high but the soft-start sequence has not been
initiated yet. The output impedance is also high when controller is in undervoltage fault condition or disabled.
Figure 14 shows a 12-V, 80-A, all-ceramic power supply capable to start into precharged outputs.
DESIGN EXAMPLE
A design example is available. See the TPS40090EVM−001 user’s guide (SLUU175).
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12V
+
+
+
+
+
+
1.2V/100A
www.ti.com
Figure 14. 12-V, 80-A ASIC All-Ceramic, Power Supply
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS40090PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS40090
Samples
TPS40090PWG4
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS40090
Samples
TPS40090PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS40090
Samples
TPS40090RHDR
ACTIVE
VQFN
RHD
28
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
40090
Samples
TPS40090RHDT
ACTIVE
VQFN
RHD
28
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
TPS
40090
Samples
TPS40091PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS40091
Samples
TPS40091PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
TPS40091
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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