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TPS40195
SLUS720F – FEBRUARY 2007 – REVISED JUNE 2019
TPS40195 4.5-V to 20-V Synchronous Buck Controller
With Synchronization and Power Good
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The TPS40195 is a flexible synchronous buck
controller that operates from a nominal 4.5-V to 20-V
supply. This controller implements voltage mode
control with the switching frequency adjustable from
100 kHz to 600 kHz. Flexible features found on this
device
include
selectable
soft-start
time,
programmable short-circuit limit, programmable
undervoltage lockout (UVLO) and synchronization
capability. An adaptive anti-cross conduction scheme
is used to prevent shoot through current in the power
FETs. Overcurrent detection is done by sensing the
voltage drop across the low-side MOSFET when it is
on, and comparing it with a user-programmable
threshold.
1
Input Operating Voltage Range: 4.5 V to 20 V
Output Voltage as Low as 0.591 V ±0.5%
180° Bi-Directional Out-of-Phase Synchronization
Internal 5-V Regulator
High and Low MOSFET Sense Overcurrent
100-kHz to 600-kHz Switching Frequency
Enable and Power Good
Programmable UVLO and Hysteresis
Thermal Shutdown at 150°C
Selectable Soft Start
Prebias Output Safe
Device Information(1)
2 Applications
•
•
•
•
PART NUMBER
Digital TV
Entry-Level and Midrange Servers
Networking Equipment
Non-Isolated DC-DC modules
TPS40195
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
VQFN (16)
4.00 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
TPS40195
1
EN
HDRV 16
2
FB
SW 15
3
COMP
BOOT 14
4
VDD
LDRV 13
5
ULVO
6
RT
SS_SEL 11
7
ILIM
PGOOD 10
8
GND
VOUT
BP 12
SYNC
Power Good
9
UDG-06066
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS40195
SLUS720F – FEBRUARY 2007 – REVISED JUNE 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
5
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
9
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Applications ................................................ 19
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Examples................................................... 32
11 Device and Documentation Support ................. 34
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Device Support......................................................
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
34
35
35
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (July 2012) to Revision F
Page
•
Editorial changes only; no technical revisions ....................................................................................................................... 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table ....................................................................................................................................... 1
Changes from Revision D (November 2008) to Revision E
•
2
Page
Added a new paragraph to the end of the Enable Functionality section.............................................................................. 12
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SLUS720F – FEBRUARY 2007 – REVISED JUNE 2019
5 Description (continued)
The threshold is set with a single external resistor connected from ILIM to GND. Pulse-by-pulse limiting (to
prevent current runaway) is provided by sensing the voltage across the high-side MOSFET when it is on and
terminating the cycle when the voltage drop rises above a fixed threshold of 550 mV. When the controller senses
an output short circuit, both MOSFETs are turned off and a timeout period is observed before attempting to
restart. This provides limited power dissipation in the event of a sustained fault. Synchronization on this device is
bi-directional. Devices can be synchronized 180° out of phase to a chosen master TPS40195 running at a fixed
250 kHz or 500 kHz, or can be synchronized to an outside clock source anywhere in the 100 kHz to 600 kHz
range.
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SLUS720F – FEBRUARY 2007 – REVISED JUNE 2019
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6 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
RGY Package
16-Pin VQFN
Top View
HDRV
EN
16
1
EN
1
16
HDRV
FB
2
15
SW
COMP
3
14
BOOT
SW
15
VDD
4
13
LDRV
BOOT
UVLO
5
12
BP
RT
6
11
SS_SEL
ILIM
7
10
PGOOD
GND
8
9
SYNC
2
FB
14
3
COMP
LDRV
13
4
VDD
BP
12
5
UVLO
SS_SEL
11
6
RT
PGOOD
10
7
ILIM
9
8
SYNC
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
14
I
Gate drive voltage for the high-side N-channel MOSFET. A 100-nF capacitor (typical) must be connected
between this pin and SW.
BP
12
O
Output bypass for the internal regulator. Connect a capacitor of 1-μF (or greater) from this pin to GND.
Larger capacitors, up to 4.7μF will improve noise performance with a low side FET Qg over 25nC. Do not
connect to VDD or drive externally. This regulator is turned off when ENABLE is pulled low
COMP
3
O
Output of the error amplifier.
EN
1
I
Logic level input which starts or stops the controller from an external user command. A high-level turns the
controller on. A weak internal pull-up holds this pin high so that the pin may be left floating if this function is
not used. Observe interface cautions in applications information.
FB
2
I
Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal
reference voltage (591 mV typical)
GND
8
-
Common reference for the device
HDRV
16
O
Gate drive output to the high-side N-channel FET.
ILIM
7
I
Current limit. Sets short circuit protection threshold for low-side MOSFET sensing. Connect a resistor to
GND to set the threshold
LDRV
13
O
Gate drive output for the low side N-channel FET.
PGOOD
10
O
Open drain power good output. Pulls low under any fault condition, soft start is active or if the FB pin voltage
is outside the specified voltage window.
RT
6
I
Switching frequency programming pin. Also determines function of SYNC pin. Connected to GND for 250
kHz operation and using SYNC as an output. Connect to BP for 500-kHz operation and using SYNC as an
output. Connect a resistor to GND to program a frequency and allow SYNC to accept synchronization
pulses. If RT is used to program a switching frequency and SYNC is not to be used to synchronize the
converter to an external clock, connect SYNC to GND.
SS_SEL
11
I
Soft-start timing selection. Can be connected to GND, BP or left floating to select a soft start time that is
proportional to the switching frequency.
SW
15
I
Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying highside MOSFET driver
4
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
Bidirectional synchronization I/O pin. SYNC is an output when the RT pin is connected to BP or GND. The
output is a falling edge signal 180° out-of-phase with the rising edge of HDRV. In this mode SYNC can be
used to drive the SYNC pin of an additional TPS40195 device whose RT pin is tied to GND through a
resistor, providing two converters that operate 180° out-of-phase to one another. SYNC may be used as an
input to synchronize to an external system clock if RT is connected to GND through a resistor as well. The
device synchronizes to the falling edge of the external clock signal. If RT is used to program a switching
frequency and SYNC is not to be used to synchronize the converter to an external clock, connect SYNC to
GND.
SYNC
9
I/O
UVLO
5
I
Programmable UVLO pin for the controller. A resistor divider on this pin to VDD sets the converter turn on
voltage and the hysteresis for turnoff.
VDD
4
I
Power input to the controller. A 100-nF bypass capacitor should be connected closely from this pin to GND.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1)
VDD
SW
Input voltage
MIN
MAX
–0.3
22
–5
25
BOOT
–0.3
30
HDRV
–5
30
BOOT–SW, HDRV–SW (Differential from BOOT or HDRV to
SW)
–0.3
6
EN, FB, BP, LDRV, PGOOD, ILIM, SYNC, UVLO, SS_SEL, RT
–0.3
6
COMP
–0.3
3
TJ
Operating junction temperature
–40
150
Tstg
Storage temperature
–55
150
(1)
UNIT
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
MAX
VVDD
Input voltage
4.5
20
UNIT
V
TJ
Operating junction temperature
–40
125
°C
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7.4 Electrical Characteristics
TJ = –40°C to 85°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0°C ≤ TJ ≤ 85°C
588
591
594
-40°C ≤ TJ ≤ 85°C
585
591
594
UNIT
REFERENCE
VFB
Feedback voltage range
mV
INPUT SUPPLY
VVDD
Input voltage range
4.5
VEN = 3 V
IVDD
Operating current
20
V
4
mA
VEN < 0.6 V, VVDD = 12 V
165
250
VEN < 0.6 V, VVDD = 20 V
230
330
5.3
5.5
V
350
550
mV
μA
ON BOARD REGULATOR
VBP
Output voltage
VVDD > 6 V, IBP ≤ 10 mA
VDO
Regulator dropout voltage, VVDD - VBP
VVDD = 5 V, IBP ≤ 25 mA
ISC
Regulator current limit threshold
IBP
Average current
5.1
75
75
mA
OSCILLATOR
fSW
Switching frequency
VRT = VBP
400
500
580
VRT = 0 V
200
250
290
RRT = 100 kΩ
Ramp amplitude (1)
VRMP
kHz
250
1
V
SYNCHRONIZATION
VINH
High-level input voltage
VINL
Low-level input voltage
2.5
TF(max)
Maximum input fall time (1)
VOH
High-level output voltage
ISYNC = 100 μA, sourcing
VOL
Low-level output voltage
ISYNC = 100 μA, sinking
TF
Output fall time (1)
TR
Output rise time (1)
0.5
100
3.5
0.3
CSYNC =25 pF
10
25
100
300
V
ns
V
ns
PWM
DMAX
Maximum duty cycle (1)
tON(min)
Minimum controlled pulse (1)
tDEAD
Output driver dead time
85%
130
HDRV off to LDRV on
50
LDRV off to HDRV on
25
VSS_SEL = 0 V, fSW = 250 kHz
4.8
VSS_SEL = 0 V, fSW = 500 kHz
2.4
VSS_SEL = Floating, fSW = 250 kHz
2.4
VSS_SEL = Floating, fSW = 500 kHz
1.2
VSS_SEL = VBP, fSW = 250 kHz
1.2
VSS_SEL = VBP, fSW = 500 kHz
0.6
ns
SOFT START
tSS
Soft-start time
ms
ERROR AMPLIFIER
GBWP
Gain bandwidth product (1)
AOL
DC gain (1)
IFB
Input bias current (current out of FB pin)
IEAOP
Output source current
VFB = 0 V
1
IEAOM
Output sink current
VFB = 2 V
1
(1)
6
7
10
MHz
60
dB
100
nA
mA
Specified by design. Not production tested.
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Electrical Characteristics (continued)
TJ = –40°C to 85°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SHORT-CIRCUIT PROTECTION
tPSS(min)
Minimum pulse during short circuit (1)
tBLNK
Blanking time (1)
tOFF
Off-time between restart attempts
IILIM
ILIM pin bias current
VILIMOFST
Low side comparator offset voltage
VILIMH
Short circuit threshold voltage on high-side
MOSFET
250
60
90
120
40
TJ = 25°C
TJ = 25°C
ns
ms
7
9
11
μA
-20
0
20
mV
400
550
650
mV
OUTPUT DRIVERS
RHDHI
High-side driver pull-up resistance
VBOOT - VSW = 4.5 V, IHDRV = -100 mA
3
6
RHDLO
High-side driver pull-down resistance
VBOOT - VSW = 4.5 V, IHDRV = 100 mA
1.5
3.0
RLDHI
Low-side driver pull-up resistance
ILDRV = -100 mA
2.5
5.0
RLDLO
Low-side driver pull-down resistance
ILDRV = 100 mA
0.8
1.5
tHRISE
High-side driver rise time (1)
15
35
tHFALL
High-side driver fall time (1)
10
25
tLRISE
Low-side driver rise time (1)
15
35
tLFALL
Low-side driver fall time (1)
10
25
4.1
4.3
CLOAD = 1 nF
Ω
ns
UVLO
VUVLOBP
BP5 UVLO threshold voltage
VUVLOBPH
BP5 UVLO hysteresis voltage
3.9
VUVLO
Turn-on voltage
IUVLO
UVLO pin hysteresis current
800
1.125
VUVLO = 1.375 V
1.26
V
mV
1.375
5.2
V
μA
SHUTDOWN
VIH
High-level input voltage, EN
VIL
Low-level input voltage, EN
1.9
3
0.6
V
POWER GOOD
VOV
Feedback voltage limit for power good
650
VUV
Feedback voltage limit for power good
530
VPG_HYST
Powergood hysteresis voltage at FB pin
RPGD
Pulldown resistance of PGD pin
VFB < 530 mV or VFB > 650 mV
7
20
Ω
IPDGLK
Leakage current
530 mV ≤ VFB ≤ 650 mV VPGOOD = 5V
7
12
μA
Bootstrap diode forward voltage
IBOOT = 5 mA
0.8
1.2
V
mV
30
BOOT DIODE
VDFWD
0.5
THERMAL SHUTDOWN
TJSD
Junction shutdown temperature
TJSDH
(2)
Hysteresis
(2)
150
(2)
°C
20
Specified by design. Not production tested.
7.5 Dissipation Ratings
Power Rating (W)
TA = 25°C
Power Rating (W)
TA = 85°C
0 (Natural Convection)
110
0.90
0.36
0 (Natural Convection)
49.2
2.0
0.81
200
41.2
2.4
0.97
400
37.7
2.6
1.0
AIRFLOW (LFM)
PW
RGY
(1)
RθJA High-K Board (1)
(°C/W)
PACKAGE
Ratings based on JEDEC High Thermal Conductivity (High K) Board. For more information on the test method, see TI Technical Brief
SZZA017.
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7.6 Typical Characteristics
400
3.0
VVDD = 20 V
IDD - Operating Current in Shutdown - mA
VVDD = 20 V
IDD - Input Current - mA
2.5
2.0
VVDD = 12 V
1.5
1.0
0.5
VVDD = 12V
350
300
250
200
VVDD = 12 V
150
100
50
VVDD = 20V
0
-40 -25 -10
5
20
35
50
65
80
VVDD = 12V
VVDD = 20V
0
-40 -25 -10 5 20
95 110 125
Figure 1. Input Current vs junction Temperature
VILIMOFST - Current Limit Offset Voltage - mV
IPGDLK - Powergood Leakage Current - mA
95 110 125
VFB = 590 mV
7
6
5
4
3
2
1
5
20
35
50
65
80
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-40 -25 -10
95 110 125
5
20
35
50
65
80
95 110 125
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 3. Powergood Leakage Current vs Junction
Temperature
Figure 4. Current Limit Offset Voltage vs Junction
Temperature
5.0
3.0
4.5
VIN, VIL - Enable Thresholds Voltage - V
IOC - Relative Overcurrent Trip Point - A
80
0
VPGOOD = 5 V
0
-40 -25 -10
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.4
0.6
0.8
1.0
1.2
1-D - Freewheel Time - ms
1.4
1.6
2.5
On
2.0
1.5
1.0
Off
0.5
On
Off
0
-40 -25 -10
5
20
35
50
65
80
95 110 125
TJ - Junction Temperature - °C
Figure 5. Relative Overcurrent Trip Point vs Freewheel Time
8
65
Figure 2. Operating Current in Shutdown vs Junction
Temperature
10
8
50
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
9
VEN = 0 V
35
Figure 6. EN Threshold Voltages vs Junction Temperature
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Typical Characteristics (continued)
6
100
99
4
2
0
BP
100 kW
-2
98
IBP - Short Circuit Current - mA
fSW - Switching Frequency Change - %
GND
-4
-6
BP
97
96
95
94
93
92
GND
-8
91
100 kW
-10
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ - Junction Temperature - °C
Figure 7. Switching Frequency Change vs Junction
Temperature
90
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ - Junction Temperature - °C
Figure 8. BP Short Circuit Current vs Junction Temperature
1.30
450
VDO - Dropout Voltage - V
400
350
300
250
200
150
100
VVDD = 5 V
ILOAD = 25 mA
50
0
-40 -25 -10
5
20
35
50
65
80
95 110 125
VUVLO - Undervoltage Lockout Threshold - V
500
1.29
1.28
1.27
1.26
1.25
-40 -25 -10
TJ - Junction Temperature - °C
6.0
IUVLO - Hysteresis Current - mA
20
35
50
65
80
95 110 125
VUVLO = 1.375 V
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ - Junction Temperature - °C
Figure 11. Undervoltage Lockout Hysteresis Vs Junction
Temperature
Figure 10. Undervoltage Lockout Threshold vs Junction
Temperature
VUVLOBP - Bypass Undervoltage Lockout Voltage - V
Figure 9. BP Dropout Voltage vs Junction Temperature
5.8
5
TJ - Junction Temperature - °C
4.2
4.1
4.0
Turn On
3.9
3.8
3.7
3.6
3.5
Turn Off
3.4
3.3
3.2
-40 -25 -10
5
20
35
50
65
80
95 110 125
TJ - Junction Temperature - °C
Figure 12. BP Undervoltage Lockout Voltage vs Junction
Temperature
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Typical Characteristics (continued)
25
VFB - Feedback Voltage Reference Change - %
0.5
IFB - Feedback Bias Current - nA
20
15
10
5
0
-5
-10
-15
-20
-40 -25 -10 5 20 35 50 65 80 95 110 125
TJ - Junction Temperature - °C
0.4
VFB = 591 mV (typ)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-40 -25 -10
Figure 13. Feedback Bias Current vs Junction Temperature
5
20
35
50
65
80
95 110 125
Figure 14. Relative Feedback Voltage Change vs Junction
Temperature
900
fOSC - Oscillator Frequency - kHz
800
700
600
500
400
300
200
100
0
0
50
100
150
200
250
RRT - TIming Resistance - kW
Figure 15. Oscillator Frequency vs Timing Resistance
10
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8 Detailed Description
8.1 Overview
The TPS40195 is a flexible controller providing all the necessary features to construct a high performance DCDC converter while keeping costs to a minimum. Support for pre-biased outputs eliminates concerns about
damaging sensitive loads during startup. Strong gate drivers for the high side and rectifier N channel FETs
decrease switching losses for increased efficiency. Adaptive gate drive timing minimizes body diode conduction
in the rectifier FET, also increasing efficiency. Selectable short circuit protection thresholds and hiccup recovery
from a short circuit increase design flexibility and minimize power dissipation in the event of a prolonged output
fault. A dedicated enable pin (EN) allows the converter to be placed in a low quiescent current shutdown mode.
8.2 Functional Block Diagram
SS_SEL
11
VDD
1.5 MW
EN
BP
Overtemperature
CLK
1
Fault
Controller
SD
Soft Start
Ramp
Generator
SD
UVLO
9 mA
7
BUF
SS
SC_LOW
ILIM
+
550 mV
5V
Regulator
4
+
VDD
+
SC_HIGH
VDD
BP
BP, 5 V
BP 12
14 BOOT
5.2 mA
UVLO
16 HDRV
5
+
1.26 V
RT
FAULT
6
9
COMP
3
2
GND
8
SS
+
BP
15 SW
13 LDRV
+
591 mV
FB
UVLO
CLK
Oscillator
SYNC
PWM Logic
and
Anti-Cross
Conduction
Error
Amplifier
SD
10 PGOOD
0.65 V
+
FAULT
SD
Powergood
SS
Control
750
kW
+
0.53 V
SS ACTIVE
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8.3 Feature Description
8.3.1 Enable Functionality
The TPS40195 has a dedicated device enable (EN) pin. This simplifies user level interface design since no
multiplexed functions exist. Another benefit is a true low power shutdown mode of operation. When the EN pin is
pulled to GND, all unnecessary functions inside the IC, including the BP regulator, are turned off and the
TPS40195 consumes a typical 165-μA of current. A functionally equivalent circuit to the enable circuitry on the
TPS40195 is shown in Figure 16.
VDD
4
1.5 MW
200 kW
1 kW
EN
1
To
Enable
Chip
200 W
1 kW
300 kW
GND
8
UDG-07005
Figure 16. TPS40195 EN Pin Internal Circuitry
If the EN pin is left floating, the chip starts automatically. The pin must be pulled to less than 600 mV for the
TPS40195 to be in shutdown mode. Note that the EN pin is relatively high impedance. In some situations, there
could be enough noise nearby to cause the EN pin to swing below the 600 mV threshold and give erroneous
shutdown commands to the rest of the device. There are two solutions to this problem should it arise.
1. Place a capacitor from EN to GND. A side effect of this is to delay the start of the converter while the
capacitor charges past the enable threshold
2. Place a resistor from VDD to EN. This causes more current to flow in the shutdown mode, but does not delay
converter startup. If a resistor is used, the total current into the EN pin should be limited to no more than 500
μA.
The ENABLE pin is self-clamping. The clamp voltage can be as low as 1 V with a 1-kΩ ground impedance. Due
to this self-clamping feature, the pull-up impedance on the ENABLE pin should be selected to limit the sink
current to less than 500 μA. Driving the ENABLE pin with a low-impedance source voltage can result in damage
to the device. Because of the self-clamping feature, it requires care when connecting multiple ENABLE pins
together. For enabling multiple TPS4019x devices (TPS40190, TPS40192, TPS40193, TPS40195, TPS40197),
see the Application Report SLVA509.
12
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Feature Description (continued)
EN
(1 V /div)
VOUT
(1 V /div)
PGOOD
(2 V /div)
HDRV
(2 V /div)
T - Time - 500 ms/div
Figure 17. TPS40195 EN Pin Start-up
8.3.2 Voltage Reference
The band gap cell is designed with a trimmed 0.591-V output. The 0.5% tolerance on the reference voltage
allows the user to design a very accurate power supply.
8.3.3 Oscillator and Synchronization
The TPS40195 has a programmable switching frequency of 100 kHz to 600 kHz using a resistor connected from
the RT pin to GND. The relationship between switching frequency and the resistor from RT to GND is given in
Equation 1.
4
fSW =
2.5 ´ (10 )
RRT
where
•
•
fSW is the switching frequency in kHz
RRT is the resistor connected from RT to GND in kΩ
(1)
When the oscillator is programmed using this method, the SYNC pin is configured as an input. The device may
be synchronized to a higher frequency than the free running frequency by applying a pulse train to the SYNC pin.
For best results, limit the frequency of the pulse train applied to SYNC to 20% more than the free running
frequency. The TPS40195 will synchronize to the falling edge of the pulse train applied to the SYNC pin.
The SYNC pin can also function as an output. To get this functionality, the RT pin must be connected to either
GND or to BP. When this is done the oscillator will run at either 250 kHz or 500 kHz. SYNC can then be
connected to other TPS40195 controllers (with their SYNC pins configured as an input) and the two or more
controllers will synchronize to the same switching frequency. The output waveform on SYNC will be
approximately a 50% duty cycle pulse train. The pull up is relatively weak, but the pull down is strong to insure
that a good clean signal is presented to any devices that are to be synchronized. A summary is shown in
Table 1.
Table 1. RT Connection and SYNC Pin Function
RT CONNECTION
SYNC PIN FUNCTION
SWITCHING FREQUENCY
Resistor to GND
Input
See Equation 1
GND
Output
250 kHz
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Feature Description (continued)
Table 1. RT Connection and SYNC Pin Function (continued)
RT CONNECTION
SYNC PIN FUNCTION
SWITCHING FREQUENCY
BP
Output
500 kHz
Using the TPS40195 with its RT pin connected to BP or to GND as a master clock source for another TPS40195
with a resistor connected from its RT pin to GND results in the two controllers operating at the same frequency
but 180° out of phase.
External SYNC
(5 V /div)
SW Master
(10 V /div)
SW
(2 V /div)
SW Slave
(10 V /div)
SYNC
Out-of-Phase
from Master
LDRV
(5 V/div)
T - Time - 1 ms/div
T - Time - 1 ms/div
Figure 18. TPS40195 Synchronized to External SYNC Pin
Pulse (Negative Edge Triggered)
Figure 19. TPS40195 SYNC Pin Master/Slave
Configuration. 180° Out-of-Phase Operation
8.3.4 Undervoltage Lockout (UVLO)
There are two separate UVLO circuits in the TPS40195. Both must be satisfied before the controller starts. One
circuit detects the BP voltage and the other circuit detects voltage on the UVLO pin. The voltage on the BP pin
(VBP) must be above 4.3 V in order for the device to start up.
The UVLO pin is generally used to provide a higher UVLO voltage than that which the BP UVLO circuit provides.
This level is programmed using a resistor divider from VIN to GND with the tap connected to the UVLO pin of the
TPS40195. Hysteresis is provided by a 5.2-μA current source that is turned on when the UVLO pin reaches the
1.26 V turn on threshold. The turnon level is determined by the divider ratio, and the hysteresis level is
determined by the divider equivalent impedance.
To determine the resistor values for the UVLO circuit, a turnon voltage and turn off voltage must be known. Once
these are known the resistors can be calculated in Equation 2 and Equation 3. The functional schematic is
shown in Figure 20.
V - VOFF
R1 = ON
IUVLO
R2 = R1 ´
(2)
VUVLO
VON - VUVLO
where
•
•
•
•
14
VON is the desired turnon voltage of the converter
VOFF is the desired turn off voltage for the converter, must be less than VON
IUVLO is the hysteresis current generated by the device, 5.2 μA (typical)
VUVLO is the UVLO pin threshold voltage, 1.26 V (typical)
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VIN
BP
IUVLO
5.2 mA (typ)
R1
+
5
UVLO
1.26 V
R2
UDG-07002
Figure 20. Undervoltage Lockout
8.3.5 Soft Start
The TPS40195 uses a digital closed loop soft start system. The soft-start ramp is generated internally by a
counter and digital-to-analog converter (DAC) that ramps up the effective reference voltage to the error amplifier.
The DAC supplies a voltage to the error amp that is used as the reference until that supplied voltage becomes
greater than the 591-mV reference voltage. At that point soft start is complete and the 591-mV reference controls
the output voltage. The ramp rate is dependent on the oscillator frequency as each step in the DAC takes one
clock cycle from the oscillator. The user can choose from three ramp rates, or DAC counter widths depending on
viewpoint, for any given switching frequency by connecting the SS_SEL pin to GND, BP pin or letting the pin
float. The possibilities are summarized in Table 2.
Table 2. Soft-Start Clock Cycles
SS_SEL CONNECTION
CLOCK CYCLES IN 1-V RAMP (NDAC)
GND
2048
Floating
1024
BP
512
The ramp output from the soft-start DAC is 1 V in amplitude. Since the soft start is closed loop and reference
voltage of the device is actually 591 mV, the actual ramp time is less than the time it takes for the SS ramp to
finish and reach 1 V. The actual soft-start time is the amount of time that it takes for the internal soft-start ramp to
reach the 591-mV reference level. The soft-start time can be found using Equation 4.
N
tSS = 0.591´ DAC
fSW
where
•
•
NDAC is the number of 1-V DAC ramp cycles from Table 2
fSW is the switching frequency in Hz
(4)
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8.3.6 Selecting the Short Circuit Threshold
An over current is detected by sensing a voltage drop across the low-side FET when it is on, and across the
high-side FET when it is on. If the voltage drop across either FET exceeds the short circuit threshold in any given
switching cycle, a counter increments one count. If the voltage across the high-side FET was higher that the
short circuit threshold, that FET is turned off early. If the voltage drop across either FET does not exceed the
short circuit threshold during a cycle, the counter is decremented for that cycle. If the counter fills up (a count of
7) a fault condition is declared and the drivers turn off both MOSFETs. After a timeout of approximately 40 ms,
the controller attempts to restart. If a short circuit remains present at the output, the current quickly ramps up to
the short circuit threshold and another fault condition is declared and the process of waiting for the 40 ms and
attempting to restart repeats.
The current limit threshold for the low-side FET is programmable by the user. To set the threshold a resistor is
connected from the ILIM pin to GND. A current source inside the IC connected to the ILIM pin and this resistor
set a voltage that is the threshold used for the overcurrent detection threshold. The low side threshold will
increase as the low side on time decreases due to blanking time and comparator response time. See Figure 5 for
changes in the threshold as the low-side FET conduction time decreases. Refer to Figure 21 for details on the
functional equivalent schematic.
BP
IILIM
9 mA
ILIM
+
tBLNK
7
LDRV On
RILIM
R
VDD
+
3-Bit Counter
R
UP/DN
Q
S
HDRV
SW
Q0
Q
R
15
CLK
+
Q1
Fault
+
Q2
VDD
LDRV
550 mV
tBLNK
HDRV On
UDG-07001
Figure 21. Overcurrent
ISCP(min ) =
ISCP(max ) =
IILIM(min ) ´ RILIM(min ) + VILIMOFST(min )
RDS(on )(max )
(5)
IILIM(max )´ RILIM(max ) + VILIMOFST(max )
RDS(on)(min )
where
•
•
•
•
•
16
IS.P. is the short circuit current
IILIM is ILIM pin bias current, 9 μA (typical)
RILIM is the resistance connected from ILIM to GND
VILIMOFST is the offset voltage of the low side current sense comparator, ±20 mV
RDS(on) is the channel resistance of the low-side MOSFET
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The short circuit protection threshold for the high-side MOSFET is fixed at 550-mV typical, 400-mV minimum with
a 4000 ppm/°C temperature coefficient to help compensate for changes in the high side FET channel resistance
as temperature increases. This threshold is in place to provide a maximum current output in the case of a fault.
The maximum amount of current that can be sourced from a converter can be found by Equation 7.
IOUT(max ) =
VILIMH(min )
RDS(on)(max )
where
•
•
•
IOUT(max) is the maximum current that the converter is specified to source
VILIMH(min) is the short circuit threshold for the high-side MOSFET (400 mV)
RDS(on)max is the maximum resistance of the high-side MOSFET
(7)
If the required current from the converter is greater than the calculated IOUT(max), a lower resistance high-side
MOSFET must be chosen.
The length of time between restart attmepts after an output fault can be found from Equation 8.
tOFF =
7 ´ NDAC
fSC
where
•
•
NDAC is the number of 1-V DAC ramp cycles from Table 2.
f SW is the switching frequency in Hz
(8)
8.3.7 5-V Regulator
This device has an on board 5-V regulator that allows the parts to operate from a single voltage feed. No
separate 5-V feed to the part is required. This regulator requires a minimum of 1 μF of capacitance on the BP pin
for stability. A ceramic capacitor is suggested for this purpose. Noise performance can be improved by increasing
this capacitance to 4.7 μF when driving FETs with more than 25-nC gate charge requirements.
This regulator can also be used to supply power to nearby circuitry, eliminating the need for a separate LDO in
some cases. If this pin is used for external loads, be aware that this is the power supply for the internals of the
TPS40195. While efforts have been made to reduce sensitivity, any noise induced on this line has an adverse
effect on the overall performance of the internal circuitry and shows up as increased pulse jitter, or skewed
reference voltage. Note that when the EN pin is pulled low, the BP regulator will be turned off and not available
to supply power to external loads.
The amount of power available from this pin varies with the size of the power MOSFETs that the drivers must
operate. Larger MOSFETs require more gate drive current and reduces the amount of power available on this pin
for other tasks.
8.3.8 Prebias Start-up
The TPS40195 contains a unique circuit to prevent current from being pulled from the output during start-up in
the condition the output is prebiased. When the soft-start commands a voltage higher than the pre-bias level
(internal soft-start becomes greater than feedback voltage [VFB]), the controller slowly activates synchronous
rectification by starting the first LDRV pulses with a narrow on-time. It then increments that on-time on a cycleby-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensures that the out voltage (VOUT) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation with minimal disturbance to the output voltage. The amount of time from the start of
switching until the low-side MOSFET is turned on for the full 1-D interval is defined by 32 clock cycles.
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8.3.9 Drivers
The drivers for the external HDRV and LDRV MOSFETs are capable of driving a gate-to-source voltage of 5 V.
The LDRV driver switches between VDD and GND, while HDRV driver is referenced to SW and switches
between BOOT and SW. The drivers have non-overlapping timing that is governed by an adaptive delay circuit to
minimize body diode conduction in the synchronous rectifier. The drivers are capable of driving MOSFETS that
are appropriate for a 15-A converter if power dissipation requirements are met.
8.3.10 Power Good
The TPS40195 provides an indication that output power is good for the converter. This is an open-drain signal
and pulls low when any condition exists that would indicate that the output of the supply might be out of
regulation. These conditions include:
• VFB > ±10% from nominal
• soft-start is active
• a undervoltage condition exists for the device
• a short circuit condition has been detected
• die temperature is over (150°C)
NOTE
When there is no power to the device, PGOOD is not able to pull close to GND if an
auxiliary supply is used for the power good indication. In this case, a built in resistor
connected from drain to gate on the PGOOD pull down device makes the PGOOD pin
look approximately like a diode to GND.
8.3.11 Thermal Shutdown
Thermal shutdown If the junction temperature of the device reaches the thermal shutdown limit of 150°C, the
PWM and the oscillator is turned off and HDRV and LDRV are driven low, turning off both FETs. When the
junction cools to the required level (130°C nominal), the PWM initiates soft start as during a normal power up
cycle.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS40195 is a flexible controller providing all the necessary features to construct a high performance DCDC converter while keeping costs to a minimum. The threshold is set with a single external resistor connected
from ILIM to GND.
9.2 Typical Applications
9.2.1 Typical Application 1
This section discusses basic buck converter design. Designers already familiar with the design of buck
converters can skip to the next section Component Selection of this design example.
Figure 22. TPS40195 Design Example Schematic
9.2.1.1 Design Requirements
Table 3. Example Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10.8
12.0
13.2
V
1.7
1.8
INPUT
VIN
IIN
Input voltage
Input current
VIN = 12 V, IOUT= 10 A
No load, VIN = 12 V, IOUT= 0 A
5
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Typical Applications (continued)
Table 3. Example Electrical Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0 A ≤ IOUT ≤ 10 A
5.4
6.0
6.6
Undervoltage lockout turn on threshold
0 A ≤ IOUT ≤ 10 A
6.6
7.0
7.6
Input voltage range
VIN = 12 V, IOUT= 5
1.75
1.80
Line regulation
10.8 ≤ VIN ≤ 13.2 V
0.5%
Load regulation
0 A ≤ IOUT ≤ 10 A
0.5%
VOUT(ripple)
Output voltage ripple
VIN = 12 V, IOUT= 10 A
IOUT
Output current
10.8 ≤ VIN ≤ 13.2 V
IOCP
Output overcurrent inception point
VIN = 12 V, VOUT= (VOUT- 5)
ΔI
Transient response load step
10 A ≤ IOUT(max) ≤ 0.2 × ( IOUT(max) )
VIN_
Undervoltage lockout turn off threshold
UVLO_OFF
VIN_UVLO
_ON
UNIT
V
OUTPUT
VOUT
1.85
100
0
5
10
14
20
43
Transient response load slew rate
Transient response overshoot
Transient response settling time
V
mVP-
P
A
8
A
5
A/μs
200
mV
1
ms
SYSTEM
fSW
Switching frequency
ηPK
Peak efficiency
VIN = 12 V, 0 A ≤ IOUT ≤ 10 A
240
η
Efficiency at full load
VIN = 12 V, IOUT = 10 A
TOP
Operating temperature range
10.8 ≤ VIN ≤ 13.2 V, 0 A ≤ IOUT ≤ 10 A
300
360
kHz
85
°C
90%
87%
-40
25
MECHANICAL
W
Width
1.6
L
Length
3.5
h
Height
0.26
in
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Output Inductor, LOUT
Equation 9 can be used to calculate LOUT.
LOUT =
(VIN(max) - VOUT ) 1.8 V
VOUT
(13.2 V - 1.8 V)
´
=
´
= 2.59 mH
fSW ´ IRIPPLE
VIN(max)
13.2 V
300kHz ´ 2.0
where
•
IRIPPLE = the allowable ripple current in the inductor, 20% of maximum IOUT
(9)
For this design a 2.5-μH inductor from Coilcraft is used. IRIPPLE is recalculated using Equation 10 and a 2.5-μH
inductor value to give a new estimate of IRIPPLE of 2.1 A .
IRIPPLE =
(VIN(max) - VOUT )
VOUT
´
fSW ´ LOUT
VIN(max)
=
1.83 V
(13.2 V - 1.83 V)
´
= 2.10 A
13.2 V
300kHz ´ 2.5 mH
(10)
With this IRIPPLE value, the RMS and peak current flowing in LOUTcan be calculated.
ILOUT _RMS =
IPK = IOUT +
20
(IOUT )2 +
(IRIPPLE )2
12
=
(10 )2 +
(2.10 )2
12
= 10.02 A
IRIPPLE
2.10
= 10 +
= 11.05 A
2
2
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9.2.1.2.2 Output Capacitor, COUT
The capacitance value is selected to be greater than the largest value calculated from Equation 13 and
Equation 14.
2
COUT =
(
2 ´ VUNDER ´ DMAX ´ VIN(min) - VOUT
2
COUT =
2
LOUT ´ (ISTEP )
LOUT ´ (ISTEP )
2 ´ VOVER ´ VOUT
=
)
=
2.5 mH ´ (8 )
2 ´ 200mV ´ 90% ´ (10.8 V - 1.8 V )
= 71.68 mF
2.5 mH ´ 82
= 222.2 mF
2 ´ 200mV ´ 1.8 V
(13)
(14)
V
100mV
ESR = RIPPLE =
= 47mW
IRIPPLE
2.1A
(15)
From Equation 13, Equation 14 and Equation 15, the capacitance for COUT should be greater than 223 μF and its
ESR should be less than 47 mΩ. Three 100-μF, 6.3-V, X5R ceramic capacitors are chosen. Each capacitor has
an ESR of 5 mΩ .
9.2.1.2.3 Input Capacitor, CIN
The input capacitor is selected to handle the ripple current of the buck stage. A relatively large capacitance is
used to keep the ripple voltage on the supply line low. This is especially important were the supply line has a
high impedance. It is recommended that the supply line impedance be kept low. The input capacitor RMS current
can be calculated using Equation 16.
2
2
éæ
ö
ö æ
ö
(IRIPPLE )2 ùú VOUT æ VOUT
VOUT
V
ê
ICAP(RMS) = ç IOUT ´ IOUT ÷ +
´
+ç
´ IOUT ÷ ´ ç 1 - OUT ÷
êè
ú
VIN
12
V
V
V
IN
IN ø
ø
è IN
ø è
ë
û
(16)
The RMS current in the input capacitor is 3.56 A. Two 22-μF, size 1206 capacitors using X7R material has a
typical dissipation factor of 5%. For a 22-μF capacitor at 300 kHz the ESR is approximately 5 mΩ. Two of these
capacitors are used in parallel. The power dissipation in each capacitor is less than 16 mW. A 470-μF, 25-V
electrolytic is added to maintain the voltage on the input rail.
9.2.1.2.4 Switching MOSFET, QSW
The following key parameters must be met by the selected MOSFET.
• Drain-to-source voltage, VDS, must be able to withstand the input voltage plus spikes that may be on the
switching node. For this design a VDS rating of between 25 V and 30 V is recommended.
IQSW(rms) =
•
2
æ
2 (IRIPPLE )
VOUT
ç
´ IOUT(max) +
VIN(min) ç
12
è
(
)
ö
÷
÷
ø
(17)
For this design IDD should be greater than 4.1 A
Gate source voltage, Vgs, must be able to withstand the gate voltage from the control device. For the
TPS40195 this is 5 V.
Target efficiency for this design is 90%. Based on 1.8-V output and 10-A operating current this equates to a
power loss in the module of 1.8 W. The design allocates this power budget equally between the two power FETS
and the inductor The equations below are used to calculate the power loss, PQSW, in the switching MOSFET.
PGATE = Qg(TOT) ´ Vg ´ fSW
(18)
PQSW = PCON + PSW + PGATE
(19)
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(
PCON = RDS(on) ´ IQSW(rms)
)
2
www.ti.com
= RDS(on) ´
éæ
IRIPPLE ö
´ Qgs1 + Q gd
ê ç IOUT +
2 ÷ø
è
ê
= VIN ´ fS ´
ê
Ig
ê
ë
(
PSW
2
VOUT æç
2 (IRIPPLE )
´ (IOUT ) +
ç
VIN
12
è
ö
÷
÷
ø
(20)
ù
)ú
ú
ú
ú
û
where
•
•
•
•
•
•
•
•
PCON is conduction losses
PSW is switching losses
PGATE is gate drive losses
Qgd is drain source charge or miller charge
Qgs1 is gate source post threshold charge
Ig is gate drive current
Qg(TOT) is total gate charge from 0 V to the gate voltage
Vg is gate voltage
(21)
Equation 22 and Equation 23 describe the preliminary values for RDS(on) and (Qgs1 + Qgd). Note output losses due
to QOSS and gate losses have been ignored here. Once a MOSFET is selected these parameters can be added.
The switching MOSFET for this design should have an RDS (on) of less than 20 mΩ . The sum of Qgd and Qgs1
should be approximately 14.8 nC. . The Vishay SI7860ADP was selected for this design. This device has an
RDS(on) of 9 mΩ and a (Qgs1+Qgd) of 13 nC. The estimated conduction losses are 0.135 W and the switching
losses are 0.297 W. This gives a total estimated power loss of 0.432 W versus 0.6 W for our initial boundary
condition. Note this does not include gate losses of approximately 10 mW.
9.2.1.2.5 Rectifier MOSFET, QSR
Similar criteria as used above apply to the rectifier MOSFET. One significant difference however, is that the
rectifier MOSFET switches with nearly zero voltage across its drain and source so its switching losses are nearly
zero. There are losses from the source to drain body diode that occur as it conducts during the delay before the
FET turns on. The equations used to calculate the losses in the rectifier MOSFET are shown below.
PQSR = PCON + PBD + PGATE
(
PCON = RDS(on) ´ IQSW(rms)
(22)
)
2
= RDS(on) ´
2
VOUT æç
2 (IRIPPLE )
´ (IOUT ) +
ç
VIN
12
è
PGATE = Qg(TOT) ´ Vg ´ fSW
ö
÷
÷
ø
(23)
(24)
PBD = Vf ´ IOUT ´ (t1 + t 2 )´ fS
where
•
•
•
•
PBD is the body diode loss
t1 is the body diode conduction prior to turn-on of channel (57nS)
t2 is the body diode conduction after turn-off of channel (14nS)
Vf is the body diode forward voltage
(25)
Estimating the body diode losses based on a forward voltage of 1.0 V yields 0.162 W. The gate losses are
unknown at this time so assume 0.1 W gate losses. This leaves 0.338 W for conduction losses. Using this figure
a target RDS(on) of 4.0 mΩ was calculated. The SI7886ADP has an RDS(on) maximum of 4.8 mΩ and was used for
this design.
22
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Using the parameters from its data sheet the actual expected power losses were calculated. Conduction loss is
0.394 W, body diode loss is 0.210 W and the gate loss was 0.063 W. This totals 0.667 W associated with the
rectifier MOSFET.
The ratio between Cgs and Cgd should be greater than one. The Si7886 capacitor meets this criterion and helps
reduce the risk of dv/dt induced turn on of the rectifier MOSFET. If this is likely to be a problem a small resistor
may be added in series with the boost capacitor, CBOOST. to slow the turn on speed of QSW at the expense of
increased switching losses in that device.
9.2.1.2.6 Component Selection for the TPS40195
9.2.1.2.6.1 Timing Resistor, RT
The timing resistor is calculated using the following equation.
7
RT =
2.5 ´ (10 )
fS
7
=
2.5 ´ (10 )
300
= 83.3kW
(26)
A standard value resistor of 82.5 kΩ is used.
9.2.1.2.6.2 Setting UVLO
The equations below are used to set the UVLO voltages.
RUVLO1 =
VON - VOFF
7-6
=
= 192.3kW
-6
IUVLO
5.2 ´ (10 )
RUVLO2 = RUVLO1 ´
(27)
VUVLO
1.26
= 192.3kW ´
= 42.2kW
7
- 1.26
V
V
( ON UVLO )
(28)
The UVLO threshold voltage ( VUVLO) is 1.26 V. The module has a turn on voltage of 7 V and a turn off voltage of
6 V. This sets RUVLO1to 191 kΩ, the nearest standard value. The second resistor RUVLO2 is 42.2 kΩ.
9.2.1.2.6.3 Setting the Soft-Start Time
The selection of the soft start time should be greater than the time constant of the output filter, LOUT and COUT.
This time is given in Equation 29 and Equation 30.
tSTART ³ 2p ´ LOUT ´ COUT
-6
tSTART ³ 6.28 ´ 2.5 ´ (10 )
(29)
-6
´ 300 ´ (10 )
= 0.172ms
(30)
The soft-start time is determined using Equation 31 . The TPS40195 uses a counter operating at the clock
frequency that increments an internal DAC until it reaches the turn on threshold voltage of 0.591 V. The number
of counts required to reach this threshold is determined by one of three settings on the SS pin. In this case, the
pin is floating (with a small bypass capacitor) which sets the clock count (NDAC) to 1024 and the soft-start time is
2.0 ms
t SS = 0.591 ´
NDAC
1024
= 0.591 ´
= 2.0 ms
300
fSW
(31)
9.2.1.2.6.4 Short-Circuit Protection, RILIM
Short-circuit protection is programmed using the RILIM resistor. Selection of this resistor depends on the RDS(on) of
the switching MOSFET and the required short circuit current trip point, ISCP. The minimum ISCP must exceed the
sum of the output current, the peak ripple current, and the output capacitor charging current during start up.
Equation 30 gives this minimum.
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-6
300 ´ (10 ) ´ 1.8
´ VOUT
C
+ IPK =
+ 11.05 = 11.32 A
ISCP ³ OUT
-3
t START
2 ´ (10 )
(32)
The minimum short circuit current trip point for this design is set to 14 A. Equation 33 is then used to calculate
the minimum RILIM value.
RILIM(min ) =
RDS(on )(max) ´ ISCP(min ) - VILIMOFSET(min )
I LIM(min)
-3
=
(4.88 ´ (10 )
´ 14) + 20mV
-6
7.0 ´ (10 )
= 12.6kW
(33)
RILIM is calculated to be 12.6 kΩ . The closest standard value of 12.7 kΩ is used. The minimum and maximum
short circuit current can be calculated using Equation 34 and Equation 35 .
IILIM(min ) ´ RILIM(min ) + VILIMOFST(min )
ISCP(min ) =
RDS(on )(max )
ISCP(max ) =
(34)
IILIM(max )´ RILIM(max ) + VILIMOFST(max )
RDS(on)(min )
(35)
The minimum ISCP is 14 A and the maximum is 46 A.
9.2.1.2.6.5 Voltage Decoupling Capacitors, CBP, and CVDD
Two pins on the TPS40195 have DC voltages. It is recommended to add small decoupling capacitors to these
pins. Below are the recommended values.
• CBP = 4.7 μF
• CVDD = 0.1 μF
9.2.1.2.6.6 Boost Voltage, CBOOST and DBOOST (optional)
Selection of the boost capacitor is based on the total gate charge of the switching MOSFET and the allowable
ripple on the boost voltage, VBOOST. A ripple of 0.2 V is assumed for this design. Using these two parameter and
equation (26) the minimum value for CBOOST can be calculated.
CBOOST >
Qg(TOT )
ΔVBOOST
(36)
The total gate charge of the switching MOSFET is 13.3 nC. A minimum CBOOST of 0.066-μF is required. A 0.1-μF
capacitor was chosen. This capacitor must be able to withstand the maximum input voltage plus the maximum
voltage on BP. This is 16 V plus 5.4 V which is 21.4 V. A 50-V capacitor is used.
To reduce losses in the TPS40195 and to increase the available gate voltage for the switching MOSFET an
external diode can be added between the BP pin and the BOOST pin of the device. A small signal schottky
should be used here, such as the BAT54.
9.2.1.2.6.7 Closing the Feedback Loop RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2 AND CPZ1
A graphical method is used to select the compensation components. This is a standard feedforward buck
converter. Its PWM gain is given by the following equation.
K PW M @
VIN
VRAMP
(37)
The gain of the output LC filter is given in Equation 38.
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KLC =
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(1 + s´ ESR´ COUT )
æL
ö
2
1 + s ´ ç OUT ÷ + (s ) ´ LOUT ´ COUT
R
è OUT ø
(38)
The equation for the PWM and LC gain is:
Ge (s) = KPWM ´ KLC =
VIN
VRAMP
´
(1 + s´ ESR´ COUT )
æL
1 + s´ ç OUT
è ROUT
ö
2
÷ + (s ) ´ LOUT ´ COUT
ø
(39)
To plot this on a Bode plot the DC gain must be expressed in dB. The DC gain is equal to KPWM. To express this
in dB we take its LOG and multiple by 20. For this converter the DC gain is:
æ VIN ö
DC gain = 20 ´ LOG ç
÷ = 20 ´ LOG(12) = 21.6 dB
è VRAMP ø
(40)
Also calculate the pole and zero frequencies. A double pole is associated with the LC and a zero is associated
with the ESR of the output capacitance. The frequency at where these occur can be calculated using
Equation 41.
fLC_Pole =
1
2p ´ LOUT ´ COUT
fESR_Zero =
= 5.8k Hz
(41)
1
= 318 k Hz
2 p ´ ESR´ C OUT
(42)
A Bode plot of the PWM and LC filter is shown in Figure 23.
30
Double
Pole
20
10
Gain − dB
0
−10
L−C Slope
−40 dB/decade
−20
−30
−40
−50
−60
100
1k
10 k
100 k
1M
f − Frequency − Hz
Figure 23. PWM and L-C Filter Gain
A Type-III compensation network, shown in Figure 24, is used for this design. A typical bode plot of a Type-III
compensation network is shown below in Figure 25.
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CPZ1
40
TPS40195
RZ1
VOUT
2
FB
30
High−Frequency
Gain
CZ2
CP2
3
COMP
Gain − dB
20
RPZ2
10
RSET
0
Figure 24. Type III Compensation Schematic
−10
−20
100
1 k fZ1
fZ2
fP1
fP2
1M
f − Frequency − Hz
Figure 25. Type-III Compensation Network Typical Bode
Plot
The output voltage, the high-frequency gain and the break (pole and zero) frequencies are calculated using the
following equations.
RSET =
R SET =
(VREGF ´ RZ1 )
(VOUT - VREF )
(43)
0.591 ´ 51k W
= 24.9 k W
1.8 - 0.591
(44)
æ
æ
öö
1
RPZ2 ´ ç R Z1 + RP1 + ç
÷ ÷÷
ç
è 2pfc ´ CPZ1 ø ø
è
Gain =
æ
ö
1
R Z1 ç RP1 +
÷
2
f
C
p
´
C
PZ1 ø
è
fP1 =
fP 2 =
fZ1 =
fZ 2 =
1
2p ´ RP1´ CPZ1
(45)
(46)
CP 2 + CZ 2
1
»
2p ´ RPZ 2 ´ CP 2 ´ CZ 2 2p ´ RPZ 2 ´ CP 2
(47)
1
2p ´ R Z1´ CPZ1
(48)
1
1
»
2 p ´ (R PZ 2 + R P1 ) ´ C Z 2
2 p ´ R PZ 2 ´ C Z 2
(49)
Steps in closing the feedback loop.
1. Place one zero well below the L-C double pole at 5.8 kHz (fZ1=2.1 kHz)
2. Place the second zero near the double pole fZ2 at 5.8 kHz.
3. Place one pole well above the desired cross over frequency, selected as one sixth the switching frequency,
fCO1 = 50 kHz, fP1 = 300 kHz
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4. Place the second pole near the ESR zero of the output capacitors of 318 kHz. fP2 = 318 kHz
5. The high frequency gain must be such that the over all system has 0 dB at the required crossover frequency.
This gain is -1 times the sum of the modulator gain and the gain of the output stage at the crossover
frequency of 50 kHz.
Using these values and the above equations calculate the setpoint and the Rs and Cs around the compensation
network using the following procedure.
1. Set RZ1 = 51 kΩ
2. Calculate RSET using Equation 43. For this module RSET = a standard 1% value = 24.9 kΩ.
3. Using Equation 48 and fZ1 = 1.8 kHz, CPZ1 can be calculated to be 1500 pF, FP1 and Equation 46 yields RP1
to be 363 Ω and the standard value 357 Ω is used.
4. From Figure 23, the required gain is calculated at 15.8 dB. Equation 45 sets the value for RPZ2. A resistor for
RPZ2 with value of 12.7 kΩ is used. CZ2 is calculated using Equation 49 and the desired frequency for the
second zero, CZ2 = 1475 pF. A 2200 pF capacitor is used.
5. CP2 is calculated using the second pole frequency and Equation 47, CP2 = 37 pF. A 33-pf capacitor is used.
9.2.1.2.7 Application Curve
80
180
60
PHASE
135
90
20
GAIN
0
45
Phase - °
Gain - dB
40
-20
0
-40
-60
10
100
1000
10000
100000
-45
1000000
Frequency - Hz
Figure 26. Final Bode Plot
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9.2.2 Typical Application 2
This example demonstrates the performance of the TPS40195 in a design that produces 5 A of output current at
a voltage of 3.3 V. The input for this design is 12 V ±10%.
+
Figure 27. Design Example 2 Schematic
9.2.2.1 Design Requirements
Table 4. Design Example 2 Bill of Materials
Size
Part Number
MFR
1
QTY
C1
RefDes
25 μF
Value
Capacitor, Aluminun, 25V, SM ±20%
Description
0.406 in ×
0.457 in
EEVFK1E471P
Panasonic
2
C2
22 μF
Capacitor, Ceramic, 16V, XR5, 20%
0603
Std
Std
1
C4
8.2 nF
Capacitor, Ceramic, 16V, X7R, 10%
0603
Std
Std
1
C5
220 pF
Capacitor, Ceramic, 16V, X7R, 10%
0603
Std
Std
3
C6, C7,
C13
100 nF
Capacitor, Ceramic, 16V, X7R, 10%
0603
Std
Std
1
C8
1 nF
Capacitor, Ceramic, 50V, X7R,10%
0805
Std
Std
1
C9
47 μF
Capacitor, Ceramic, 6.3V, X5R, 20%
1210
C3225X5R0J476M
TDK
1
C12
4.7 μF
Capacitor, Ceramic, 10V, X5R, 10%
Std
Std
1
C14
1 nF
Capacitor, Ceramic, 16V, X7R, 10%
1
L1
800 nH
Inductor, SMT, 31A
1-
Q1
Si7860DP
1
Q2
3
0603
Std
Std
0.512 × 0.571
inch
PG0077.801
Pulse
MOSFET, N-Ch, 30V, 15A, 11mΩ
SOT-8
PWRPAK
Si7860DP
Vishay
Si7868DP
MOSFET, N-Ch, 20V, 2.75 mΩ, 25 A
SOT-8
PWRPAK
Si7868DP
Vishay
R2, R3,
R6
2.32 kΩ
Resistor, Chip, 1/16W, 5%
0603
Std
Std
1
R5
2.2 kΩ
Resistor, Chip, 1/16W, 5%
0603
Std
Std
1
R7
7.5 kΩ
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R9
100 kΩ
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R10
49.9 kΩ
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R11
10 kΩ
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
U1
TPS40195PW
4.5-V to 20-V Synchronous Buck
Controller
TSSOP-16
TPS40195PW
TI
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9.2.2.2 Detailed Design Procedure
See Detailed Design Procedure.
9.2.2.3 Application Curves
100
3.316
90
3.315
80
VOUT - Output Voltage - V
h - Efficiency - %
70
60
50
40
30
VIN
3.313
3.312
3.311
3.310
3.309
3.308
3.307
10.8 V
12.0 V
13.2 V
10
13.2 V
12.0 V
10.8 V
3.314
VOUT = 3.3 V
20
VIN
3.306
3.305
0
0
2
4
6
IOUT - Load Current - A
8
Figure 28. Efficiency vs Load Current
10
0
2
4
6
IOUT - Load Current - A
8
10
Figure 29. Output Voltage vs Load Current
9.2.3 Typical Application 3
This design delivers 1 A to 3 A from a 10-V supply. The output voltage may be adjusted from 1 V to 5 V with a
single resistor. The part has 57° of phase margin at a crossover frequency of 59 kHz. The design is built on a
double sided PC board with an active area of 1.5 cm × 3 cm.
Figure 30. Design Example 3 Schematic
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9.2.3.1 Design Requirements
Table 5. Example 3 Bill of Materials
QTY
RefDes
Value
Description
Size
Part Number
MFR
1
C1
22 μF
Capacitor, Aluminun, 16V, X7R, 20%
1210
Std
TDK
2
C2
22 μF
Capacitor, Ceramic, 16V, XR5, 20%
1210
Std
TDK
1
C4
4700 pF
Capacitor, Ceramic, 25V, X7R, 20%
0402
Std
Std
1
C5
10 pF
Capacitor, Ceramic, 25V, X7R, 20%
0402
Std
Std
2
C6, C7
100 nF
Capacitor, Ceramic, 25V, X7R, 20%
0603
Std
Std
1
C8
2.2 nF
Capacitor, Ceramic, 25V, X7R, 20%
0402
Std
Std
1
C12
4.7 μF
Capacitor, Ceramic, 6.3V, X5R, 20%
0603
Std
Std
1
C13
10 pF
Capacitor, Ceramic, 25V, X7R, 20%
0603
Std
Std
1
C14
470 pF
Capacitor, Ceramic, 25V, X7R, 20%
0402
Std
Std
4
C15
10 μF
Capacitor, Ceramic, 6.3V, X5R, 20%
0805
C2012X5R0J106M
TDK
1
L2
15 μH
Inductor, SMT, 4.2A, 24 mΩ,
0.394 × 0.3941
inch
SLF120565T-150M4R2-PF
TDK
1
Q1
SP8K4
XSTR, MOSFET, Dual N-Ch,30V, 9A
SOP-8
SP8K4
Rohm
1
Q2
2N7002DICT
MOSFET, N-Ch, 60V, 115mA, 1.2Ω
SOT-23
2N7002DICT
Vishay
1
R2
24.3 kΩ
Resistor, Chip, 1/16W, x%
0402
Std
Std
1
R3
178 kΩ
Resistor, Chip, 1/16W, x%
0402
Std
Std
1
R5
11 kΩ
Resistor, Chip, 1/16W, x%
0402
Std
Std
1
R7
10.1 kΩ
Resistor, Chip, 1/16W, x%
0402
Std
Std
1
R9
39 kΩ
Resistor, Chip, 1/16W, x%
0402
Std
Std
1
R10
2.2 kΩ
Resistor, Chip, 1/16W, x%
0402
Std
Std
2
R11,
R13
51 kΩ
Resistor, Chip, 1/16W, x%
0402
Std
Std
1
R14
20 kΩ
Resistor, Chip, 1/16W, x%
0402
Std
Std
1
U1
TPS40195PW
4.5-V to 20-V Synchronous Buck
Controller
TSSOP-16
TPS40195PW
TI
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9.2.3.2 Detailed Design Procedure
See Detailed Design Procedure.
9.2.3.3 Application Curves
100
60
120
50
100
90
80
60
50
40
PHASE
GAIN
30
60
20
40
Phase - °
80
40
Gain - dB
h - Efficiency - %
70
30
VIN
20
9V
10 V
11 V
10
0
100
0
0
0.5
1.0
1.5
2.0
2.5
IOUT - Load Current - A
3.0
20
10
3.5
1k
10 k
100 k
0
100 k
fSW - Switching Frequency - Hz
Figure 32. Gain And Phase vs Frequency
Figure 31. Efficiency vs Load Current
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
Keep the input switching current loop as small as possible.
Place the input capacitor (CIN) close to the top switching FET The output loop current loop should also be
kept as small as possible.
Keep the SW node as physically small as possible to minimize parasitic capacitance and to minimize radiated
emissions Kelvin connections should be brought from the output to the feedback pin (FB) of the device.
Keep analog and non-switching components away from switching components.
The gate drive trace should be as close to the power FET’s gate as possible.
Make a single point connection from the signal ground to power ground.
Do not allow switching current to flow under the device.
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10.2 Layout Examples
Vin
Signal Components
Power Components
TPS40195
1
EN
Cin
HDRV 16
See note 1.
2
3
FB
SW 15
COMP
See
note 1.
L
CBOOT
Vout
BOOT 14
See note 1.
See note 2.
See note 1.
4
5
VDD
LDRV 13
UVLO
BP 12
Cout
See
note 1.
CBP
CVDD
6
RT
SS_SEL 11
7
ILIM
PGOOD 10
8
GND
SYNC 9
Signal Ground Plane
See note 3.
Power Ground Plane
See note 3.
1. Keep these loops as short as possible. Run out and return lines close together.
2. Keep the switch node area as small as possible
3. Keep Signal and Power Grounds separate. Connect into a general power plane on one layer.
Figure 33. Layout Suggestion
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Layout Examples (continued)
Input capacitors near
DRAIN of top FET
Analog signal
components away
from Power Switching
elements
Small switch node ares
Kelvin Feedback
connection
Figure 34. Board Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Device Support
11.2.1 Related Parts
The following parts have characteristics similar to the TPS40195 and may be of interest.
Table 6. Related Parts
DEVICE
DESCRIPTION
TPS40100
Midrange Input Synchronous Controller with Advanced Sequencing and Output Margining
TPS40075
Wide Input Synchronous Controller with Voltage Feed Forward
TPS40190
Low Pin Count Synchronous Buck Controller
TPS40192/3
4.5V to 18V Input, Low Pin Count, Synchronous Buck Controller with Power Good
11.3 Documentation Support
11.3.1 Related Documentation
These references may be found on the web at www.power.ti.com under Technical Documents. Many design
tools and links to additional references, including design software, may also be found at www.power.ti.com
• Under The Hood Of Low Voltage DC/DC Converters, SEM 1500 Topdevice 5, 2002 Seminar Series
• Understanding Buck Power Stages in Switch-mode Power Supplies, SLVA057, March 1999
• Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400, 2001 Seminar Series
• Designing Stable Control Loops, SEM 1400, 2001 Seminar Series
• Additional PowerPADTM information may be found in Applications Briefs SLMA002 and SLMA004
• QFN/SON PCB Attachment, Texas Instruments Literature Number SLUA271, June 2002
11.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.5 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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SLUS720F – FEBRUARY 2007 – REVISED JUNE 2019
11.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2007–2019, Texas Instruments Incorporated
Product Folder Links: TPS40195
35
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS40195PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
40195
TPS40195PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
40195
TPS40195RGYR
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40195
TPS40195RGYT
ACTIVE
VQFN
RGY
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40195
TPS40195RGYTG4
ACTIVE
VQFN
RGY
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
40195
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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