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TPS40200-Q1
SLUS739F – SEPTEMBER 2006 – REVISED JANUARY 2016
TPS40200-Q1 Wide-Input-Range Nonsynchronous Voltage-Mode Controller
1 Features
3 Description
•
•
The TPS40200-Q1 is a flexible, nonsynchronous
controller with a built-in 200-mA driver for P-channel
FETs. The circuit operates with inputs up to 52 V,
with a power-saving feature that turns off driver
current once the external FET has been turned on
fully. This feature extends the flexibility of the device,
allowing it to operate with an input voltage up to 52 V
without dissipating excessive power. The circuit
operates with voltage-mode feedback and has feedforward input-voltage compensation that responds
instantly to input voltage change. The integral
700-mV reference is trimmed to 2%, providing the
means to accurately control low voltages. The
TPS40200-Q1 is available in an 8-pin SOIC package
and supports many of the features of more complex
controllers. Clock frequency, soft start, and
overcurrent limit are each easily programmed by a
single, external component. The device has
undervoltage lockout (UVLO) and can be easily
synchronized to other controllers or a system clock to
satisfy
sequencing
and/or
noise-reduction
requirements.
1
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
– Device HBM ESD Classification Level 1B
– Device CDM ESD Classification Level C6
Input Voltage Range 4.5 V to 52 V
Output Voltage (700 mV to 90% VIN)
200-mA Internal P-channel FET Driver
Voltage Feed-Forward Compensation
Undervoltage Lockout (UVLO)
Programmable Fixed-Frequency (35-kHz to
500-kHz) Operation
Programmable Short-Circuit Protection
Hiccup Overcurrent Fault Recovery
Programmable Closed-Loop Soft Start
700-mV 1% Reference Voltage
External Synchronization
Small 8-Pin SOIC (D) Package
2 Applications
•
•
•
Device Information(1)
PART NUMBER
Automotive Controls
Automotive Power Supplies
Distributed Power Systems
3.91 mm × 4.90 mm
Typical Efficiency of Application Circuit
100
VIN
R5
VOUT = 5 V
90
C1
RSENSE
2 SS
ISNS 7
C5
3 COMP GDRV 6
4 FB
Q1 L1
GND 5
VOUT
Efficiency (%)
TPS40200
1 RC
VDD 8
C4
R3
BODY SIZE (NOM)
SOIC (8)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
C3
PACKAGE
TPS40200-Q1
80
70
VIN (V)
C2
D1
R4
R1
R2
16
12
8
60
C6
50
0
0.5
1.0
1.5
2.0
2.5
Load Current (A)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS40200-Q1
SLUS739F – SEPTEMBER 2006 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
3
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 18
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Applications ................................................ 19
9 Power Supply Recommendations...................... 33
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 34
11 Device and Documentation Support ................. 35
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
35
12 Mechanical, Packaging, and Orderable
Information ........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (July 2013) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Changed VIN to VDD throughout the document for consistency .............................................................................................. 3
•
Added footnote for reference to Minimum Controllable Pulse Width vs Frequency section .................................................. 5
•
Changed TPS40200 to TPS40200-Q1 throughout document ............................................................................................. 10
•
Added note for typical values of internal resistor and voltages ........................................................................................... 10
•
Changed voltage to 8 V (typical) in MOSFET Gate Drive .................................................................................................... 11
•
Changed Programming the Operating Frequency to Selecting the Operating Frequency ................................................. 11
•
Changed equation 4 ............................................................................................................................................................. 15
•
Changed Programming the Soft-Start Time to Calculating the Soft-Start Time................................................................... 16
•
Changed equation 5 ............................................................................................................................................................. 16
•
Deleted Bill of Materials tables ............................................................................................................................................. 20
•
Added designators Q2 and D2 to Detailed Design Procedure............................................................................................. 21
•
Added designator L1 to Detailed Design Procedure ............................................................................................................ 23
•
Added clarification for different values for capacitor C11 and C12 in schematic, which are for the EVM. Modified for
use in applications per equations ........................................................................................................................................ 23
•
Changed RRC to R3 in equation definition in Switching Frequency for consistency and clarity ........................................... 24
•
Changed RILM to 31 mΩ in Calculating the Overcurrent Threshold Level and added clarifiying information....................... 24
•
Added capacitor designator C6 in Soft-Start Capacitor........................................................................................................ 25
Changes from Revision D (July 2011) to Revision E
•
2
Page
Deleted TA test condition and values from Feedback voltage parameter in Electrical Characteristics .................................. 5
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SLUS739F – SEPTEMBER 2006 – REVISED JANUARY 2016
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
RC
1
8
VDD
SS
2
7
ISNS
COMP
3
6
GDRV
FB
4
5
GND
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
RC
I
Switching frequency setting RC network. Connect a capacitor from RC pin to GND pin and a resistor from VIN pin
to RC pin. The device may be synchronized to an external clock by connecting an open-drain output to this pin
and pulling it to GND. The pulse width for synchronization should not be excessive (see Detailed Description).
2
SS
I
Soft-start programming. Connect capacitor from SS to GND to program soft-start time. Pulling this pin below
150 mV causes the output switching to stop, placing the device in a shutdown state. The pin also functions as a
restart timer for overcurrent events.
3
COMP
O
Error amplifier output. Connect control loop compensation network from COMP to FB.
Error amplifier inverting input. Connect feedback resistor network center tap to this pin.
4
FB
I
5
GND
—
Device ground
6
GDRV
O
Driver output for external P-channel MOSFET
7
ISNS
I
Current-sense comparator input. Connect a current sense resistor between ISNS and VDD in order to set desired
overcurrent threshold.
8
VDD
I
System input voltage. Connect local bypass capacitor from VDD to GND.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage
Output voltage
(1)
MIN
MAX
VDD, ISNS
–0.3
52
RC, FB
–0.3
5.5
SS
–0.3
9
COMP
–0.3
9
GDRV
VDD – 10
VDD
Lead temperature 1,6 mm (1/16 in) from case for 10 s
Tstg
(1)
Storage temperature
–55
UNIT
V
V
260
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic discharge
(1)
UNIT
±1000
Charged-device model (CDM), per AEC Q100-011
±1500
Machine model (MM)
±100
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
MIN
MAX
VDD
Input voltage
4.5
52
UNIT
V
TA
Operating temperature
–40
125
°C
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
TPS40200-Q1
THERMAL METRIC (1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
115.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
64.2
°C/W
RθJB
Junction-to-board thermal resistance
56
°C/W
ψJT
Junction-to-top characterization parameter
17.7
°C/W
ψJB
Junction-to-board characterization parameter
55.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLUS739F – SEPTEMBER 2006 – REVISED JANUARY 2016
6.5 Electrical Characteristics
–40°C < TA < 125°C, VDD = 12 V, fOSC = 100 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
676
696
712
mV
VOLTAGE REFERENCE
VFB
Feedback voltage
COMP = FB , 4.5 V < VDD < 52 V, –40°C < TA <
125°C
GATE DRIVER
Isrc
Gate driver pullup current
125
300
Isnk
Gate driver pulldown current
200
300
VGATE
Gate driver output voltage
5.6
8
10
V
1.5
3
mA
4.25
4.55
VGATE = (VDD – VGDRV), 12 V < VDD < 52 V
mA
mA
QUIESCENT CURRENT
Iqq
Device quiescent current
fOSC = 300 kHz, Driver not switching,
4.5 V < VDD < 52 V
UNDERVOLTAGE LOCKOUT (UVLO)
VUVLO(on) Turn-on threshold
–40°C < TA < 125°C
3.8
VUVLO(off) Turn-off threshold
VUVLO(HY
4.05
Hysteresis
V
V
110
200
275
mV
65
105
170
kΩ
ST)
SOFT START
RSS(chg)
Internal soft-start pullup
resistance
RSS(dchg)
Internal soft-start pulldown
resistance
190
305
485
kΩ
VSSRST
Soft-start reset threshold
100
150
200
mV
50
100
140
mV
OVERCURRENT PROTECTION
VILIM
Overcurrent threshold
OCDF
Overcurrent duty cycle (1)
VILIM(rst)
Overcurrent reset threshold
4.5 V < VDD < 52 V, –40°C < TA < 125°C
2%
100
150
200
mV
500
kHz
OSCILLATOR
Oscillator frequency range (1)
fOSC
Oscillator frequency
Frequency line regulation
VRMP
Ramp amplitude
35
RRC = 200 kΩ, CRC = 470 pF
85
100
118
RRC = 68.1 kΩ, CRC = 470 pF
210
300
345
12 V < VDD < 52 V
–9%
0%
4.5 V < VDD < 12 V
–21%
0%
4.5 V < VDD < 52 V
VDD / 10
kHz
V
PULSE-WIDTH MODULATOR
tMIN
Minimum controllable
pulse width (2)
DMAX
Maximum duty cycle
KPWM
Modulator and power-stage
DC gain
VDD = 12 V
200
540
VDD = 30 V
100
200
ns
Fosc = 100 kHz, CL = 470 pF
93%
95%
Fosc = 300 kHz, CL = 470 pF
90%
93%
8
10
12
V/V
100
250
nA
ERROR AMPLIFIER
IIB
Input bias current
(1)
AOL
Open loop gain
GBWP
Unity gain bandwidth (1)
ICOMP(src) Output source current
ICOMP(snk
)
(1)
(2)
Output sink current
60
80
dB
1.5
3
MHz
VFB = 0.6 V, COMP = 1 V
100
250
μA
VFB = 1.2 V, COMP = 1 V
1
2.5
mA
Specified by design
See Figure 21 for typical tMIN vs fOSC at various input voltages.
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6.6 Typical Characteristics
3
1.66
1.65
2.5
1.64
2
1.62
IDD - mA
IDD - mA
1.63
1.61
1.6
1.5
1
1.59
1.58
VDD = 12 V
0.5
1.57
0
1.56
-50
-25
0
25
50
75
100
5
125
10
15
20
Temp - °C
4.3
156
4.25
155.5
155
154.5
154
VDD = 12 V
153.5
-50
-25
25
50
75
100
40
45
50
55
Turn On
4.2
4.15
4.1
Turn Off
4.05
0
30 35
VDD - V
Figure 2. Quiescent Current vs VDD
156.5
UVLO Turn On - V
Reset Threshold - mV
Figure 1. Quiescent Current vs Temperature
25
4
125
-50
-25
0
Temp - °C
25
50
Temp - °C
75
100
125
Figure 4. UVLO Turn On and Turn Off vs Temperature
Figure 3. Soft-Start Threshold vs Temperature
103
98
96
102.5
VDD = 4.5 V
102
R = 202 kW
C = 470 pF
92
ILIM threshold - mV
Frequency (kHz)
94
90
88
VDD = 12 V
86
84
80
-50
-25
0
25
50
75
100
101
100.5
125
99.5
-50
Temp (°C)
-25
0
25
50
75
100
125
Temp - °C
Figure 5. Oscillator Frequency vs Temperature
6
VDD = 12 V
100
VDD = 52 V
82
101.5
Figure 6. Current-Limit Threshold vs Temperature
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Typical Characteristics (continued)
275
21.00
R = 68.1 kW
C = 470 pF
TJ = 25°C
265
TJ = 25°C
20.50
260
255
Gain - dB
Oscillator Frequency (kHz)
270
250
245
20.00
240
235
19.50
230
225
220
19.00
5
10
15
20
25
30 35
VDD (V)
40
45
50
55
5
10
Figure 7. Oscillator Frequency vs VDD
15
20
25
30 35
VDD - V
40
45
50
55
Figure 8. Power-Stage Gain vs VDD
20.50
20.50
20.30
20.45
VDD = 24 V
VDD = 4.5 V
20.40
VDD = 12 V
19.90
Gain - dB
Gain - dB
20.10
19.70
20.35
VDD = 52 V
20.30
19.50
20.25
-50
-25
0
25
50
75
100
125
-50
-25
0
Temp - °C
Figure 9. Power-Stage Gain vs Temperature
2.6
VDD = 24 V
Vramp - V
Vramp - V
2.2
2
1.8
1.6
VDD = 12 V
1.2
1
-50
-25
0
25
50
75
100
125
Figure 10. Power-Stage Gain vs Temperature
2.8
1.4
50
Temp °C
3
2.4
25
75
100
125
6
5.8
5.6
5.4
5.2
5
4.8
4.6
4.4
4.2
4
3.8
3.6
3.4
3.2
3
VDD = 52 V
VDD = 36 V
-50
Temp - °C
-25
0
25
50
75
100
125
Temp - °C
Figure 11. Modulator Ramp Amplitude vs Temperature
Figure 12. Modulator Ramp Amplitude vs Temperature
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Typical Characteristics (continued)
160
6
TJ = 25°C
140
5
120
4
IIB - nA
VRAMP - V
100
3
80
60
2
40
1
20
0
0
5
10
15
20
25
30
35
VDD - V
40
45
50
55
-50
0
25
75
100
125
Figure 14. Feedback Amplifier Input Bias Current
vs Temperature
3.5
300
3
Output Current - mA
250
200
150
100
50
2.5
2
1.5
1
0.5
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
Temp - °C
50
75
100
125
Temp - °C
Figure 15. Comp Source Current vs Temperature
Figure 16. Comp Sink Current vs Temperature
8.4
8
VDD = 12 V
7.8
VJ = 25°C
8.2
7.6
VGATE - V
50
Temp - °C
Figure 13. Modulator Ramp Amplitude vs VDD
Output Current - mA
-25
8
7.4
7.8
7.2
7.6
7
7.4
6.8
7.2
6.6
6.4
-50
8
-25
0
25
50
75
100
125
7
Temp - °C
5
10
30 35
VDD - V
Figure 17. Gate Drive Voltage vs Temperature
Figure 18. Gate Drive Voltage vs VIN
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15
20
25
40
45
50
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720
720
718
718
716
716
714
714
712
VFB - mV
VFB - mV
Typical Characteristics (continued)
VDD = 24 V
710
708
706
712
710
VDD = 4.5 V
708
706
VDD = 50 V
704
704
702
702
700
VDD = 12 V
700
-50
-25
0
25
50
75
100
125
-50
-25
Temp - °C
25
50
75
100
125
Temp - °C
Figure 19. Reference Voltage vs Temperature
Figure 20. Reference Voltage vs Temperature
700
100
600
95
Maximum Duty Cycle (%)
VDD = 4.5 V
500
Pulse Width - ns
0
400
300
VDD = 24 V
VDD = 12 V
200
100 VDD = 36 V
80
75
fOSC (kHz)
500
200
100
50
70
60
0
100
85
65
VDD = 52 V
0
90
200
300
400
500
0
10
20
30
40
50
Input Voltage (V)
Frequency - kHz
Figure 21. Minimum Controllable Pulse Width vs Frequency
Figure 22. Maximum Duty Cycle vs Input Voltage
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7 Detailed Description
7.1 Overview
The TPS40200-Q1 is a nonsynchronous controller with a built-in 200-mA driver designed to drive high-speed
P-channel FETs up to 500 kHz. Its small size combined with complete functionality makes the device both
versatile and easy to use.
The controller uses a low-value current-sensing resistor in series with the input voltage and the source
connection of the power FET to detect switching current. When the voltage drop across this resistor exceeds
100 mV, the device enters a hiccup fault mode at approximately 2% of the operating frequency.
The device uses voltage feedback to an error amplifier that is biased by a precision 700-mV reference. Feedforward compensation from the input keeps the PWM gain constant over the full input voltage range, eliminating
the need to change frequency compensation for different input voltages.
The device also incorporates a soft-start feature, where the output follows a slowly rising soft-start voltage,
preventing output-voltage overshoot.
7.2 Functional Block Diagram
TPS40200
COMP 3
FB 4
E/A and SS
Reference
SS 2
+ 700 mV
Soft-Start
and
Overcurrent
8 VDD
PWM
Logic
Enable E/A
ISNS 7
+
GDRV voltage swing
limited to (VDD ± 8V) typical
Driver
RC 1
6 GDRV
OSC
5 GND
UVLO
NOTE
In this block diagram and the following sections, the internal R resistor values and
capacitor mV reference values are typical. Resistor and reference voltage values will vary
based on process, temperature, and supply voltage of the device. Please see Electrical
Characteristics for tolerances, where applicable.
10
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7.3 Feature Description
7.3.1 MOSFET Gate Drive
The output-driver sinking current is approximately 200 mA and is designed to drive P-channel power FETs.
When the driver pulls the gate charge of the FET, it is controlling to 8 V (typical), the drive current folds back to
a low level so that high-power dissipation only occurs during the turn-on period of the FET. This feature is
particularly valuable when turning on a FET at high input voltages, where leaving the gate drive current on would
otherwise cause unacceptable power dissipation.
7.3.2 Undervoltage Lockout Protection
Undervoltage lockout (UVLO) protection ensures proper start-up of the device only when the input voltage has
exceeded minimum operating voltage. UVLO protection incorporates hysteresis that eliminates hiccup starting in
cases where input supply impedance is high.
TPS40200
545 kW
VDD
8
Run
+
+
200 kW
1.3 V
36 kW
GND
5
UDG-05082
Figure 23. Undervoltage Lockout
Undervoltage protection ensures proper startup of the device only when the input voltage has exceeded
minimum operating voltage. The UVLO level is measured at the VDD pin with respect to GND. Start-up voltage is
typically 4.3 V with approximately 200 mV of hysteresis. The device shuts off at a nominal 4.1 V. As shown in
Figure 23, when the input VDD voltage rises to 4.3 V, the 1.3-V comparator threshold voltage is exceeded a d a
RUN signal occurs. Feedback from the output closes the switch and shunts the 200-kΩ resistor, so that an
approximately 200-mV lower voltage, or 4.1 V, is required before the device shuts down.
7.3.3 Selecting the Operating Frequency
The operating frequency of the controller is determined by an external resistor RRC that is connected from the RC
pin to VDD and a capacitor attached from the RC pin to ground. This connection and the two oscillator
comparators inside the device are shown in Figure 24. The oscillator frequency can be calculated using
Equation 1.
1
f SW =
R RC ´ C RC ´ 0.105
where
•
•
•
fSW = clock frequency
RRC = timing resistor value in Ω
CRC = timing capacitor value in F
(1)
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Feature Description (continued)
RRC must be kept large enough that the current through it does not exceed 750 μA when the internal switch
(shown in Figure 24) is discharging the timing capacitor. This condition may be expressed using Equation 2.
VIN
£ 750 mA
R RC
(2)
TPS40200
VDD
8
VIN
+
S
Q
R
Q
CLK
RRC
External Frequency
Synchronization
(optional)
RC
+
1
+
CRC
150 mV
GND
5
UDG-05070
Figure 24. Oscillator Functional Diagram
7.3.4 Synchronizing the Oscillator
Figure 24 shows the functional diagram of the TPS40200-Q1 oscillator. When synchronizing the oscillator to an
external clock, the RC pin must be pulled below 150 mV for 20 ns or more. The external clock frequency must
also be higher than the free-running frequency of the converter. When synchronizing the controller, if the RC pin
is held low for an excessive amount of time, erratic operation may occur. The maximum amount of time that the
RC pin should be held low is the lesser of the following:
• 50% of a nominal output pulse, or
• 10% of the period of the synchronization frequency
Under circumstances where the input voltage is high and the duty cycle is less than 50%, a Schottky diode
connected from the RC pin to an external clock may be used to synchronize the oscillator (see Figure 25). The
cathode of the diode is connected to the RC pin. The trip point of the oscillator is set by an internal voltage
divider to be 1/10 of the input voltage. The clock signal must have an amplitude higher than this trip point. When
the clock goes low, it allows the reset current to restart the RC ramp , synchronizing the oscillator to the external
clock. This provides a simple, single-component method for clock synchronization.
12
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Feature Description (continued)
TP S40200
VDD
8
VIN
+
Amplitud e >
V IN
10
RC
R
Q
CLK
+
1
Frequency > Controller Frequency
Q
RC
RRC
Duty cycle < 50%
S
+
CRC
150 mV
GND
5
Figure 25. Diode-Connected Synchronization
7.3.5 Current-Limit Resistor Selection
As shown in Figure 28, a resistor in series with the power MOSFET sets the overcurrent protection level. Use a
low-inductance resistor to avoid ringing signals and nuisance tripping. When the FET is on and the controller
senses 100 mV or more drop from the VDD pin to the ISNS pin, an overcurrent condition is declared. When this
happens, the FET is turned off and, as shown in Figure 26, the soft-start capacitor is discharged. When the softstart capacitor reaches a level below 150 mV, the converter clears the overcurrent condition flag and attempts to
restart. If the condition that caused the overcurrent event to occur is still present on the output of the converter
(see Figure 27), another overcurrent condition is declared and the process repeats indefinitely. Figure 27 shows
the soft-start capacitor voltage during an extended output fault condition. The overall duty cycle of current
conduction during a persistent fault is approximately 2%.
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Feature Description (continued)
VSS
TPS40200
100 mV
SS
+
Fault
S
7
R
2
+
Reset Fault
Q
Q
Latched
Fault
100 kW
300 mV
+
ISNS
8
+
VDD
300 kW
SS Reference
Error Amplifier
Enable
Error Amplifier
+
150 mV
GND
5
UDG-10077
Figure 26. Current-Limit Reset
Figure 27. Typical Soft-Start Capacitor and VOUT During Overcurrent
If necessary, a small RC filter can be added to the current sensing network to reduce nuisance tripping due to
noise pickup. This filter can also be used to trim the overcurrent trip point to a higher level with the addition of a
single resistor (see Figure 28). The nominal overcurrent trip point using the circuit of Figure 28 is described using
Equation 3.
14
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Feature Description (continued)
IOC =
VILIM R F1 + R F2
´
R ILIM
R F2
where
•
•
•
•
IOC = overcurrent trip point, peak current in the inductor
VILIM = overcurrent threshold voltage for the TPS40200-Q1, typically 100 mV
RILIM = value of the current sense resistor in Ω
RF1 and RF2 = values of the scaling resistors in Ω
(3)
The value of the capacitor is determined by the nominal pulse width of the converter and the values of the
scaling resistors RF1 and RF2. It is best not to have the time constant of the filter longer than the nominal pulse
width of the converter, otherwise a substantial increase in the overcurrent trip point occurs. Using this constraint,
the capacitor value may be bounded using Equation 4.
VO
VIN × fSW
CF ”
(RF1 × RF2)
(RF1 + RF2)
where
•
•
•
•
•
Cf = value of the current limit filter capacitor in F
VO = output voltage of the converter
VIN = input voltage to the converter
fSW = converter switching frequency
RF1 and RF2 = values of the scaling resistors in Ω
(4)
VIN
VDD
8
CF
RF2
RILIM
RF1
ISNS
7
GDRV
6
TPS40200
UDG-05071
Figure 28. Current-Limit Adjustment
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Feature Description (continued)
CAUTION
The current limit resistor, RILM, and its associated circuitry protect the device if the
ISNS pin (pin 7) and the VDD pin (pin 8) are shorted or have other high-current load
conditions. RILM and associated current-limiting circuitry may be eliminated if the
supply input current is limited elsewhere in the application. However, by removing the
current limit function, damage to the device or PCB during an overcurrent event may
occur. The recommendation is to use the current limit.
7.3.6 Calculating the Soft-Start Time
An external capacitor (CSS) connected from the SS pin to ground controls the TPS40200-Q1 soft-start interval.
An internal charging resistor connected to VDD produces a rising reference voltage that is connected through a
700-mV offset to the reference input of the TPS40200-Q1 error amplifier. When the soft-start capacitor voltage
(VCSS) is below 150 mV, there is no switching activity. When VCSS rises above the 700-mV offset, the error
amplifier starts to follow VSST – 700 mV and uses this rising voltage as a reference. When VCSS reaches 1.4 V,
the internal reference takes over, and further increases have no effect. An advantage of initiating a slow start in
this fashion is that the controller cannot overshoot, because its output follows a scaled version of the controller
reference voltage. A conceptual drawing of the circuit that produces these results is shown in Figure 29. A
consequence of the 700-mV offset is that the controller does not start switching until the VCSS has charged up to
700 mV. The output remains at 0 V during the resulting delay. When VCCS exceeds the 700-mV offset, the
TPS40200-Q1 output follows the soft-start time constant. Once above 1.4 V, the 700-mV internal reference takes
over, and normal operation begins.
TPS40200
VSST
SS
2
700 mV
VSST(offset)
Ideal
Diodes
+
105 kW
Error Amplifier
+
CSS
FB
+
700 mV
4
COMP
3
UDG-05083
Figure 29. Soft-Start Circuit
The slow-start time should be longer (slower) than the time constant of the output LC filter. This time constraint
may be expressed as:
tS ³ 2p ´ LOUT ´ COUT
(5)
The calculation of the soft-start interval is simply the time it takes the RC network to exponentially charge from
0 V to 1.4 V. An internal 105-kΩ charging resistor is connected from the SS pin to VSST. For applications where
the voltage is above 8 V, an internal regulator clamps the maximum charging voltage to 8 V.
16
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Feature Description (continued)
The result of this is a formula for the start up time, as given by Equation 6.
ö
æ VSST
÷
t SS = R c ´ CSS ´ ln çç
÷
è VSST - 1.4 ø
where
•
•
•
•
tSS = required soft-start time in seconds
CSS = soft-start capacitor value in F
Rc = internal soft-start charging resistor (105 kΩ nominal)
VSST = input voltage up to a maximum of 8 V
(6)
7.3.7 Voltage Setting and Modulator Gain
Since the input current to the error amplifier is negligible, the feedback impedance can be selected over a wide
range. Knowing that the reference voltage is 708 mV, choose a convenient value for R1 and then calculate the
value of R2 using Equation 7.
VOUT = 0.708 × 1 +
R2
R1
(7)
Vg
L
VOUT
d
KPWM
COUT
RLOAD
VC
R2
+
VREF
R1
UDG-10220
Figure 30. System Gain Elements
The error amplifier has a DC open-loop gain of at least 60 dB with a minimum of a 1.5-MHz gain bandwidth
product, which gives the user flexibility with respect to the type of feedback compensation to use for the
particular application. The gain selected by the user at the crossover frequency is set to provide an overall unity
gain for the system. The crossover frequency should be selected so that the error amplifier open-loop gain is
high with respect to the required closed-loop gain. This ensures that the amplifier response is determined by the
passive feedback elements.
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7.4 Device Functional Modes
7.4.1 Operation Near Minimum Input Voltage
The TPS40200-Q1 is designed to operate with input voltages above 4.5 V. The typical VDD UVLO threshold is
4.25 V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the
actual UVLO voltage, the device will not switch. When VVDD passes the UVLO threshold, the device will become
active. Switching is enabled and the soft-start sequence is initiated. The TPS40200-Q1 will ramp up the output
voltage at the rate determined by the external capacitor at the soft-start pin.
7.4.2 Operation With SS Pin
The SS pin has a 150-mV threshold, which can be used to disable the TPS40200-Q1. With SS forced below this
threshold voltage, the device is disabled and switching is inhibited even if VVDD is above its UVLO threshold. If
the SS voltage is allowed to increase above the threshold while VVDD is above its UVLO threshold, the device
becomes active. Switching is enabled and the soft-start sequence is initiated. The TPS40200-Q1 will ramp up the
output voltage at the rate determined by the external capacitor at the soft-start pin.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS40200-Q1 is a 4.5-V to 52-V buck controller with an integrated gate driver for a high-side p-channel
MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum
output current set by an external current sense resistor. In higher current applications, the maximum output
current can also be limited by the thermal performance of the external MOSFET and rectifying diode switch. Use
the following design procedure to select external components for the TPS40200-Q1. The design procedure
illustrates the design of a typical buck regulator with the TPS40200-Q1.
8.2 Typical Applications
8.2.1 Buck Regulator, 8-V to 12-V Input, 3.3-V or 5-V Output at 2.5 A
The buck regulator design shown in Figure 31 shows the use of the TPS402000-Q1. It delivers 2.5 A at either
3.3 V or 5 V as selected by a single feedback resistor. It achieves approximately 90% efficiency at 3.3 V and
94% at 5 V. A discussion of design tradeoffs and methodology is included to serve as a guide to the successful
design of forward converters using the TPS40200-Q1.
The efficiency from boards built from this design is shown in Figure 39 and Figure 40. Additional application
information is available from Texas Instruments.
+
+
Notes
D3 : Do not populate. SOT 23 Common Cathode Dual Schottky
R6 =26.7k for 3.3 Vout, R6 = 16.2k for 5.0 Vout
Figure 31. 8-V to 16-V VIN Step-Down Buck Converter
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Typical Applications (continued)
8.2.1.1 Design Requirements
Table 1 shows the design parameters for this example application.
Table 1. Design Parameters
PARAMETER
TEST CONDITIONS
VIN
Input voltage
VOUT
Output voltage
IOUT at 2.5 A
Line regulation
MIN
NOM
MAX
UNIT
8
12
16
V
3.2
3.3
3.4 (1)
V
Approximately 0.2 % VOUT
3.293
3.3
3.307
V
Load regulation
Approximately 0.2% VOUT
3.293
3.3
3.307
V
Output voltage
IOUT at 2.5 A
4.85
5
5.15 (1)
V
Line regulation
Approximately 0.2% VOUT
4.99
5
5.01
V
Load regulation
Approximately 0.2% VOUT
4.99
5
5.01
V
VRIPPLE
Output ripple voltage
At maximum output current
60
mV
VOVER
Output overshoot
For 2.5-A load transient from 2.5 A to 0.25 A
100
mV
VUNDER
Output undershoot
For 2.5-A load transient from 0.25 A to 2.5 A
60
mV
IOUT
Output current
ISCP
Short-circuit current trip point
VOUT
At nominal input voltage and maximum output
current
Efficiency
FS
(1)
Switching frequency
0.125
2.5
A
3.75
5
A
90%
300
kHz
Set-point accuracy is dependent on external resistor tolerance and the device reference voltage. Line and load regulation values are
referenced to the nominal design output voltage.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 FET Selection Criteria
1. The maximum input voltage for this application is 16 V. Switching the inductor causes overshoot voltages
that can equal the input voltage. Because the RDS(on) of the FET rises with breakdown voltage, select a FET
with the lowest breakdown voltage possible. In this case, a 30-V FET was selected.
2. Selecting the size of a power FET requires knowing both the switching losses and DC losses in the
application. AC losses are all frequency dependent and directly related to device capacitances and device
size. However, DC losses are inversely related to device size. The result is an optimum where the two types
of losses are equal. Because device size is proportional to RDS(on), begin by selecting a device with an RDS(on)
that results in a small loss of power relative to package thermal capability and overall efficiency objectives.
3. In this application, the efficiency target is 90% and the output power 8.25 W. This gives a total power-loss
budget of 0.916 W. Total FET losses must be small relative to this number.
The DC conduction loss in the FET is given by Equation 8.
PDC = IRMS 2 × RDS(on)
(8)
The RMS current is given by Equation 9.
1
2
é æ
DIpp ö÷ù 2
2
ú
Irms = êD ´ ç IOUT +
ê ç
12 ÷ú
øû
ë è
where
•
•
•
•
•
•
20
ΔIpp = ΔV × D × (ts/LI)
ΔV = VIN – VOUT – (DCR + RDS(on)) × IOUT
RDS(on) = FET on-state resistance
DCR = inductor DC resistance
D = duty cycle
tS = reciprocal of the switching frequency
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Using the values in this example, the DC power loss is 129 mW. The remaining FET losses are as follows:
• PSW – The power dissipated while switching the FET on and off
• PGATE – The power dissipated driving the FET gate capacitance
• PCOSS – The power switching the FET output capacitance
The total power dissipated by the FET is calculated using Equation 10.
PFET = PSW + PGATE + PCOSS + PRDS(on)
(10)
The P-channel FET, Q2, used in this application is a FDC654P with the following characteristics:
• tRISE = 13 × 10–9
• tFALL = 6 × 10–9
• RDS(on) = 0.1 Ω
• QGD = 1.2 × 10–9
• COSS = 83 × 10–12
• QG = 9 nC
• VGATE = 1.9 V
• QGS = 1 × 10–9
Using these device characteristics and the following formulas, PSW is calculated using Equation 11:
æ
ö f
f
PSW = S ´ çç VIN ´ Ipk ´ t CHON ÷÷ + S VIN ´ Ipk ´ t CHOFF
= 10 mW
2 è
ø 2
(
t CHON =
where
)
Q ´ RG
Q GD ´ R G
t CHOFF = GD
VIN - VTH and
VIN
are the switching times for the power FET.
PGATE = Q G × VGATE × f S = 22 mW
(11)
(12)
2
PCOSS =
C OSS × VIN _ MAX × f S
2
= 2 mW
(13)
The gate current is IG = QG × fS = 2.7 mA.
The sum of the switching losses is 34 mW and is comparable to the 129-mW DC losses. At added expense, a
slightly larger FET is better, because the DC loss drops and the AC losses increase, with both moving toward the
optimum point of equal losses.
8.2.1.2.2 Rectifier Selection Criteria
•
•
Rectifier breakdown voltage:
The rectifier must withstand the maximum input voltage, which in this case is 16 V. To allow for switching
transients that can approach the switching voltage, a 30-V rectifier was selected.
Diode size:
The importance of power losses from the Schottky rectifier (D2) is determined by the duty cycle. For a low
duty-cycle application, the rectifier conducts most of the time and the current that flows through it times its
forward drop can be the largest component of loss in the entire controller. In this application, the duty cycle
ranges from 20% to 40%, which in the worst case means that the diode conducts 80% of the time. Where
efficiency is of paramount importance, choose a diode with a minimum forward drop. In more cost-sensitive
applications, size may be reduced to the point of the thermal limitations of the diode package.
The device in this application is large relative to the current required by the application. In a more costsensitive application, a smaller diode in a less-expensive package will provide a less-efficient but appropriate
solution.
The device used, D2, has the following characteristics:
• Vf = 0.3 V at 3 A
• Ct = 300 pF (Ct = effective reverse voltage capacitance of the synchronous rectifier, D2)
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The two components of the losses from the diode D2 are calculated using Equation 14.
(
PCOND = Vf × IOUT +
(
IRIPPLE
× (1 – D) = 653 mW
4
where
•
•
•
•
•
D = duty cycle
IRIPPLE = ripple current
IOUT = output current
VF = forward voltage
PCOND = conduction power loss
(14)
The switching capacitance of this diode adds an AC loss, given by Equation 15.
1
2
PSW =
C × (VIN + Vf ) × f = 6.8 mW
2
This additional loss raises the total loss to 660 mW.
[
]
(15)
At an output voltage of 3.3 V, the application runs at a nominal duty cycle of 27% with the diode conducting
72.5% of the time. As the output voltage is moved up to 5 V, the on time increases to 46% with the diode
conducting only 54% of the time during each clock cycle. This change in duty cycle proportionately reduces
the conduction power losses in the diode. This reduction may be expressed as Equation 16.
660 ×
0.54
= 491 mW
0.725
(16)
for a savings in power of 660 – 491 = 169 mW.
To illustrate the relevance of this power savings, measure the full-load module efficiency for this application at
3.3 V and 5 V. The 5-V output efficiency is 92% versus 89% for the 3.3-V design. This difference in efficiency
represents a 456-mW reduction in loss between the two conditions. This 169-mW power-loss reduction in the
rectifier represents 37% of the difference.
8.2.1.2.3
Inductor Selection Criteria
The TPS40200-Q1 P-FET driver facilitates switching the power FET at a high frequency. In turn, this enables the
use of smaller less-expensive inductors as illustrated in this 300-kHz application. Ferrite, with its good highfrequency properties, is the material of choice. Several manufacturers provide catalogs with inductor saturation
currents, inductance values, and LSRs (internal resistance) for their various-sized ferrites.
In this application, the device must deliver a maximum current of 2.5 A. This requires that the saturation current
of the output inductor is above 2.5 A plus one-half the ripple current caused during inductor switching. The value
of the inductor determines this ripple current. A low value of inductance has a higher ripple current that
contributes to ripple voltage across the resistance of the output capacitors. The advantages of a low inductance
are a higher transient response, lower DCR, a higher saturation current, and a smaller less-expensive device.
Too low an inductor, however, leads to higher peak currents, which ultimately are bounded by the overcurrent
limit set to protect the output FET or by output ripple voltage. Fortunately, with low-ESR ceramic capacitors on
the output, the resulting ripple voltage for relatively high ripple currents can be small.
For example, a single 1-μF 1206-sized 6.3-V ceramic capacitor has an internal resistance of 2 Ω at 1 MHz. For
this 2.5-A application, a 10% ripple current of 0.25 A produces a 50-mV ripple voltage. This ripple voltage may be
further reduced by additional parallel capacitors.
The other bound on inductance is the minimum current at which the controller enters discontinuous conduction.
At this point, inductor current is zero. The minimum output current for this application is specified at 0.125 A. This
average current is one-half the peak current that must develop during a minimum on time. The conditions for
minimum on time are high line and low load.
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LMIN is calculated using Equation 17.
V í VOUT
LMIN = IN
× t ON = 32 µH
IPEAK
where
•
•
•
•
VIN = 16 V
VOUT = 3.3 V
IPEAK = 0.25 A
tON = 0.686 μs
•
3. 3 V
1
´
tON is given by 300 kHz 16 V
(17)
The inductor used in the circuit, L1, is the closest standard value of 33 μH. This is the minimum inductance that
can be used in the converter to deliver the minimum current while maintaining continuous conduction.
8.2.1.2.4 Output Capacitance
In order to satisfy the output voltage overshoot and undershoot specifications, there must be enough output
capacitance to keep the output voltage within the specified voltage limits during load current steps.
In a situation where a full load of 2.5 A within the specified voltage limits is suddenly removed, the output
capacitor must absorb energy stored in the output inductor. This condition may be described by realizing that the
energy in the stored in the inductor must be suddenly absorbed by the output capacitance. This energy
relationship is written using Equation 18.
1
1
2
2
2
´ L OIO £ ´ C O VOS - VO
2
2
[ (
)]
where
•
•
•
•
•
VOS = allowed overshoot voltage above the output voltage
LO = inductance
IO = output current
CO = output capacitance
VO = output voltage
(18)
In this application, the worst-case load step is 2.25 A, and the allowed overshoot is 100 mV. With a 33-μH output
inductor, this implies an output capacitance of 249 μF for a 3.3-V output and 165 μF for a 5-V output.
When the load increases from minimum to full load, the output capacitor must deliver current to the load. The
worst case is for a minimum on time that occurs at 16 VIN, 3.3 VOUT, and minimum load. This corresponds to an
off time of (1 – 0.2) times the period 3.3 μs and is the worst-case time before the inductor can start supplying
current. This situation may be represented using Equation 19.
t
DVO < DIO ´ OFFMAX
CO
where
•
•
•
ΔVO = undershoot specification of 60 mV
ΔIO = load current step
tOFFMAX = maximum off time
(19)
This condition produces a requirement of 100 μF for the output capacitance. The larger of these two
requirements becomes the minimum value of output capacitance. In the schematic, an output capacitor of 220 µF
(C12) in parallel with 1 µF (C11) is shown. This is from the EVM to balance both 3.3-V and 5-V output use cases.
For fixed voltage output, modify the C11 and C12 values per the equations.
The ripple current develops a voltage across the ESR of the output capacitance, so another requirement on this
component is that ESR be small relative to the ripple voltage specification.
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8.2.1.2.5 Switching Frequency
The TPS40200-Q1 has a built-in 8-V, 200-mA, P-channel FET-driver output that facilitates using P-channel
switching FETs. A clock frequency of 300 kHz was chosen as a switching frequency that represents a
compromise between a high frequency that allows the use of smaller capacitors and inductors, and one that is
not so high as to cause excessive transistor switching losses. As previously discussed, an optimum frequency
can be selected by picking a value where the DC and switching losses are equal.
The frequency is set by using the design formula given in FET Selection Criteria.
1
RRC ´ CRC =
0.105 ´ fSW
where
•
•
•
RRC = timing resistor value in Ω or R3 = 68.1 kΩ
CRC = timing capacitor value in F or C5 = 470 pF
fSW = desired switching frequency in Hz, which in this case is 297 kHz
(20)
At a worst case of 16 V, the timing resistor draws about 250 μA, which is well below the 750-μA maximum that
the circuit can pull down.
8.2.1.2.6
Calculating the Overcurrent Threshold Level
The current limit in the TSP40200-Q1 is triggered by a comparator with a 100-mV offset whose inputs are
connected across a current-sense resistor between VDD and the source of the high-side switching FET. When
current in this resistor develops more than 100 mV, the comparator trips and terminates the output gate drive.
In this application, the current-limit resistor is set by the peak output stage current, which consists of the
maximum load current plus one-half the ripple current. In this case, 2.5 + 0.125 = 2.625 A. To accommodate
tolerances, a 25% margin is added, giving a 3.25-A peak current. Using the equation for IILIM, Figure 32 yields a
value for RILIM of 31 mΩ. In the schematic, a 20-mΩ resistor, R2, was used for RILIM, which sets the current limit
to 5 A. This schematic is from the EVM where evaluation at a higher current was allowed.
Current sensing in a switching environment requires attention to both circuit board traces and noise pickup. In the
design shown, a small RC filter has been added to the circuit to prevent switching noise from tripping the currentsense comparator. The requirements of this filter are board dependent, but with the layout used in this
application, no spurious overcurrent is observed.
VIN
TPS40200
VDD
8
CF
RF2
RF1
ISNS
7
GDRV
6
RILIM
IILIM =
0.1
RILIM
UDG-11200
Figure 32. Overcurrent Trip Circuit for RF2 Open
24
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8.2.1.2.7 Soft-Start Capacitor
The soft-start interval is given (in pF) by Equation 21.
t SS
C SS =
´ 10 3
æ VSST ö
÷
R ´ ln çç
÷
è VSST - 1.4 ø
where
•
•
•
R = internal 105-kΩ charging resistor
VCC = input voltage up to 8 V, where the charging voltage is internally clamped to 8 V maximum
VOS = 700 mV, and (because the input voltage is 12 V) VSST = 8 V
(21)
The oscilloscope (Figure 33) shows the expected delay at the output (middle trace) until the soft-start node
(bottom trace) reaches 700 mV. At this point, the output rises following the exponential rise of the soft-start
capacitor voltage until the soft-start capacitor reaches 1.4 V and the internal 700-mV reference takes over. This
total time is approximately 1 ms, which agrees with the calculated value of 0.95 ms when the soft-start
capacitance is 0.047 μF, C6.
A.
Channel 1 is the output voltage rising to 3.3 V.
B.
Channel 2 is the soft-start pin.
Figure 33. Soft Start Showing Output Delay and Controlled Rise to Programmed Output Voltage
8.2.1.2.8 Frequency Compensation
The four elements that determine the system overall response are discussed in this section. The gain of the error
amplifier (KEA) is the first of these elements. Its output develops a control voltage that is the input to the PWM.
The TPS40200-Q1 has a unique modulator that scales the peak-to-peak amplitude of the PWM ramp to be
0.1 times the value of the input voltage. Because modulator gain is given by VIN divided by VRAMP, the modulator
gain is 10 and is constant at 10 (20 dB) over the entire specified input-voltage range.
The last two elements that affect system gain are the transfer characteristic of the output LC filter and the
feedback network from the output to the input to the error amplifier.
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These four elements may be expressed using Equation 22 that represents the system transfer function as shown
in Figure 34.
TV(S) = KFB × KEA(S) × KPWM × XLC(S)
where
•
•
•
•
KFB = output voltage setting divider
KEA = error amplifier feedback
KPWM = modulator gain
XLC = filter transfer function
(22)
vg
Vref
+
KEA
-
vc
d
KPWM
XLC
vo
Tv(s)
KFB
Figure 34. Control Loop
Figure 35 shows the feedback network used in this application. This is a Type II compensation network, which
gives a combination of good transient response and phase boost for good stability. This type of compensation
has a pole at the origin, causing a –20-dB/decade (–1) slope, followed by a zero that causes a region of flat gain,
followed by a final pole that returns the gain slope to –1. The Bode plot in Figure 36 shows the effect of these
poles and zeros.
The procedure for setting up the compensation network is as follows:
1. Determine the break frequency of the output capacitor.
2. Select a zero frequency well below this break frequency.
3. From the gain bandwidth of the error amplifier, select a crossover frequency at which the amplifier gain is
large relative to expected closed-loop gain.
4. Select a second zero well above the crossover frequency that returns the gain slope to a –1 slope.
5. Calculate the required gain for the amplifier at crossover.
Be prepared to iterate this procedure to optimize the pole and zero locations as needed.
C7
C8
R8
R10
+
R6
VREF
Figure 35. Error Amplifier Feedback Elements
26
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The frequency response of this converter is largely determined by two poles that arise from the LC output filter
and a higher-frequency zero caused by the ESR of the output capacitance. The poles from the output filter cause
a 40-dB/decade rolloff with a phase shift approaching 180 degrees, followed by the output capacitor zero that
reduces the roll off to –20 dB and gives a phase boost back toward 90 degrees. In other nomenclature, this is a
–2 slope followed by a –1 slope. The two zeros in the compensation network act to cancel the double pole from
the output filter. The two poles of the compensation network produce a region in which the error amplifier is flat
and can be set to a gain such that the overall gain of the system is 0 dB. This region is set so that it brackets the
system crossover frequency.
P1
Gain (dB)
Slope = –1
Z1
P2
f1
f2
Frequency
Figure 36. Error Amplifier Bode Plot
To properly compensate this system, it is necessary to know the frequencies of its poles and zeros.
8.2.1.2.8.1 Step 1
The break frequency of the output capacitor is given by Equation 23.
1
fESR =
2p ´ RESR ´ COUT
where
•
•
COUT = the output capacitor
RESR = the ESR of the capacitors
(23)
Because of the ESR of the output capacitor, this output filter has a single-pole response above the 1.8-kHz break
frequency of the output capacitor and its ESR. This simplifies compensation since the system becomes
essentially a single-pole system.
8.2.1.2.8.2 Step 2
The first zero is placed well below the 1.8-kHz break frequency of the output capacitor and its ESR. Phase boost
from this zero is shown in Figure 38.
1
fZ1 =
2p ´ R8 ´ C8
where
•
•
•
R8 = 300 kΩ
C8 = 1500 pF
fZ1 = 354 Hz
(24)
8.2.1.2.8.3 Step 3
From a minimum gain bandwidth product of 1.5 MHz, and knowing it has a 20-dB/decade rolloff, the open-loop
gain of the error amplifier is 33 dB at 35 kHz. This approximate frequency is chosen for a crossover frequency to
keep the amplifier gain contribution to the overall system gain small, as well as following the convention of
placing the crossover frequency between 1/6 to 1/10 the 300-kHz switching frequency.
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8.2.1.2.8.4 Step 4
The second pole is placed well above the 35-kHz crossover frequency.
1
fP2 =
× (C7 + C8)
2π × C 7 × C 8 × R 8
where
•
•
•
•
R8 = 300 kΩ
C7 = 10 pF
C8 = 1500 pF
fP2 = 53 kHz
(25)
8.2.1.2.8.5 Step 5
Use Equation 26 to calculate the gain elements in the system to determine the gain required by the error
amplifier to make the overall gain 0 dB at 35 kHz.
TV (S ) = K FB ´ K EA (S)´ K PWM ´ X LC (S)
where
•
•
•
•
KFB is the output voltage setting divider
KEA is the error amplifier feedback
KPWM is the modulator gain
XLC is the filter transfer function
(26)
With reference to Figure 37, the transfer characteristic XLC(S) of the output filter can be estimated by
Equation 27.
L
RSW
VIN
D
VSW
VOUT
1-D
RSR
RLOAD
COUT
Figure 37. Output Filter Analysis
X LC (S) =
Z OUT (S)
Z OUT (S) + Z L (S) + R SW ´ D + R SR ´ (1 - D)
where
•
•
•
•
To
•
•
•
•
ZOUT is the parallel combination of output capacitor(s) and the load
RSW is the RDS(on) of the switching FET plus the current-sense resistor
RSR is the resistance of the synchronous rectifier
D is the duty cycle estimated as 3.3 / 12 = 0.27
(27)
evaluate XLC(S) at 35 kHz, use Equation 28.
ZOUT(S) at 35 kHz, which is dominated by the output capacitor's ESR; estimated to be 400 mΩ
ZL(S) at 35 KHz is 7.25 Ω
RSW = 0.95 mΩ, including the RLIM resistance
RSR = 100 mΩ
Using these numbers, XLC(S) = 0.04 or –27.9 dB.
28
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The feedback network has a gain to the error amplifier given using Equation 28.
R
K fb = 10
R6
where
•
for 3.3 VOUT, R6 = 26.7 kΩ
(28)
Using the values in this application, Kfb = 11.4 dB.
The modulator has a gain of 10 that is flat to well beyond 35 kHz, so KPWM = 20 dB.
To acheive 0-dB overall gain, the amplifier and feedback gain must be set to 7.9 dB (20 dB - 27.9 dB).
The amplifier gain, including the feedback gain, Kfb, can be approximated using Equation 29.
A VOL
VOUT
(S ) =
R10 R10
VIN
1+
+
´ (1 + A VOL )
R 8 ZFS
where
•
•
ZFS is the parallel combination of C7 in parallel with the sum of R8 and the impedance of C8
AVOL is the open-loop gain of the error amplifier at 35 kHz, which is 44.6 or 33 dB
(29)
Figure 38 shows the result of the compensation. The crossover frequency is 35 kHz, and the phase margin is
45°. The response of the system is dominated by the ESR of the output capacitor and is exploited to produce an
essentially single-pole system with simple compensation.
50
180
40
Gain
160
Phase
140
30
120
10
100
0
80
–10
60
–20
–30
40
–40
20
–50
0.1
Phase (°)
Gain (dB)
20
1
10
100
Crossover Frequency (kHz)
0
1000
Figure 38. Overall System Gain and Phase Response
Figure 38 also shows the phase boost that gives the system a crossover phase margin of 47°.
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8.2.1.3 Application Curves
100
100
VOUT = 5 V
VOUT = 3.3 V
90
Efficiency (%)
Efficiency (%)
90
80
70
80
70
VIN (V)
VIN (V)
16
12
8
60
16
12
8
60
50
50
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.5
1.0
2.0
2.5
Load Current (A)
Load Current (A)
VOUT = 5 V
VOUT = 3.3 V
Figure 39. Full-Load Efficiency
Figure 40. Full-Load Efficiency
8.2.2 Application 2: 18-V to 50-V Input, 16-V Output at 1 A
This is an example of using the TPS40200-Q1 in a higher voltage application. The output voltage is 16 V at 1 A
with an 18-V to 50-V input. Module boards built to this schematic and a test report are available.
The efficiency and load regulation from boards built from this design are shown in Figure 42 and Figure 43.
Further information and support material is available.
+
+
Figure 41. Buck Converter: VIN = 18 V to 50 V, VOUT = 16 V at 1 A
30
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8.2.2.1 Design Requirements
Table 2 shows the design parameters for this example application.
Table 2. Design Parameters
PARAMETER
VIN
Input voltage
VOUT
Output voltage
IOUT
Output current
ISCP
Short circuit current trip point
FS
Switching frequency
MIN
NOM
MAX
18
50
16
UNIT
V
V
1
2
A
A
200
kHz
8.2.2.2 Detailed Design Procedure
For the detailed design procedure, see the Detailed Design Procedure section for Buck Regulator, 8-V to 12-V
Input, 3.3-V or 5-V Output at 2.5 A.
8.2.2.3 Application Curves
16.50
100
16.45
95
Output Voltage (V)
Efficiency (%)
16.40
90
85
80
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
16.25
VIN (V)
24
48
16.15
70
0.1
16.30
16.20
VIN (V)
24
48
75
16.35
1.0
16.10
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Load Current (A)
Load Current (A)
Figure 42. Efficiency vs Load
Figure 43. Load Regulation, Two Input Voltage Extremes
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8.2.3 Application 3: Wide-Input-Voltage LED Constant-Current Driver
This application uses the TPS40200-Q1 as a buck controller that drives a string of LED diodes. The feedback
point for this circuit is a sense resistor in series with this string. The low 0.7-V reference minimizes power wasted
in this resistor and maintains the LED current at a value given by 0.7 V/RSENSE. As the input voltage is varied, the
duty cycle changes to maintain the LED current at a constant value, so that the light intensity does not change
with large input-voltage variations.
+
+
Figure 44. Wide-Input-Voltage Range LED Driver
8.2.3.1 Design Requirements
Table 3 shows the design parameters for this example application.
Table 3. Design Parameters
PARAMETER
MIN
NOM
12
MAX
30
UNIT
VIN
Input voltage
ILED
LED current
ISCP
Short circuit current trip point
3.3
A
FS
Switching frequency
300
kHz
0.25
V
A
8.2.3.2 Detailed Design Procedure
For the detailed design procedure, see the Detailed Design Procedure section for Buck Regulator, 8-V to 12-V
Input, 3.3-V or 5-V Output at 2.5 A.
32
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8.2.3.3 Application Curve
100
Efficiency (%)
90
80
70
60
50
10
15
20
Input Voltage (V)
25
30
Figure 45. Efficiency vs Input Voltage
9 Power Supply Recommendations
The TPS40200-Q1 is designed to operate from an input voltage supply range between 4.5 V and 52 V. This input
supply should be well regulated. If the input supply is located more than a few inches from the buck power stage
controlled by the TPS40200-Q1, additional bulk capacitance may be required in addition to the ceramic-bypass
capacitors. An electrolytic capacitor with a value of 100 µF is a typical choice.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
Keep AC current loops as short as possible. For the maximum effectiveness from C3, place it near the VDD
pin of the controller and design the input AC loop consisting of C1-RSENSE-Q1-D1 to be as short as possible.
Excessive high-frequency noise on VDD during switching degrades overall regulation as the load increases.
The output loop A (D1-L1-C2) should also be kept as small as possible. Otherwise, the output noise
performance of the application will be degraded.
TI recommends that traces carrying large AC currents not be connected through a ground plane. Instead, use
PCB traces on the top layer to conduct the AC current, and use the ground plane as a noise shield. Split the
ground plane as necessary to keep noise away from the TPS40200-Q1 and noise-sensitive areas, such as
feedback resistors R6 and R10.
Keep the SW node as physically small as possible to minimize parasitic capacitance and to minimize radiated
emissions.
For good output-voltage regulation, Kelvin connections should be brought from the load to R6 and R10.
The trace from the R6-R10 junction to the TPS40200-Q1 should be short and kept away from any noise
source, such as the SW node.
The gate drive trace should be as close to the power FET gate as possible.
The TPS40200-Q1 is encapsulated in a standard plastic SOIC-8 package.
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10.2 Layout Example
R3
R1
Input
C5
C3
TPS40200
C6
RSENSE
VDD
1 RC
8
C4
Q1
R5
ISEN
2 SS
C1
L1
Output
7
R4
GDRV 6
3 COMP
C2
D1
C7
C8
Ground
GND
4 FB
5
R8
R9
C9
R6
R10
U D G-07045
R3
C5
TPS40200
C3
R1
VDD
C4
R5
SS
ISEN
COMP
GDRV
FB
GND
R4
RSENSE
Switch node
R8
R6
Low current Control
Components
R9
R10
Q1
C1
High current
Power stage components
L1
D1
C9
C7
RC
C8
C6
Input
Output
C2
Ground
Kelvin Ground
Kelvin Voltage Sense
Figure 46. PCB Layout Recommendations
34
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Related Products
• TPS4007/9 Low-Input Synchronous Buck Controller
• TL5001 Wide-Input-Range Controller
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Under the Hood of Low-Voltage DC/DC Converters, SEM1500 Topic 5, 2002 Seminar Series (SLUP206)
• Understanding Buck Power Stages in Switch-Mode Power Supplies (SLVA057)
• Automotive Infotainment Guide (SSAY002)
• Designing Stable Control Loops, SEM 1400, 2001 Seminar Series (http://power.ti.com)
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS40200QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
40200Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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