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TPS40345
SLUSD62 – DECEMBER 2017
TPS40345 3-V to 20-V Input Synchronous Buck Controller
1 Features
3 Description
•
•
•
•
The TPS40345 is a synchronous buck controller that
operates from 3-V to 20-V input and which can be
used in cost-optimized applications. The controller
implements a voltage-mode control architecture with
input-voltage
feed-forward
compensation
that
responds instantly to a change in input voltage. The
switching frequency is fixed at 600 kHz.
1
•
•
•
•
•
•
•
Input Voltage Range From 3 V to 20 V
600-kHz Switching Frequency
High- and Low-Side FET RDS(on) Current Sensing
Programmable Thermally Compensated OCP
Levels
Programmable Soft-Start
600-mV, 1.3% Reference Voltage
Voltage Feed-Forward Compensation
Supports Prebiased Output
Frequency Spread Spectrum
Thermal Shutdown Protection at 145°C
10-Pin 3-mm × 3-mm VSON Package With
Ground Connection to Thermal Pad
The frequency spread spectrum (FSS) feature adds
to the switching frequency, significantly reducing the
peak EMI noise and making it much easier to comply
with EMI standards.
The TPS40345 offers design with a variety of userprogrammable
functions,
including
soft-start,
overcurrent protection (OCP) levels, and loop
compensation.
OCP level may be programmed by a single external
resistor connected from the LDRV pin to circuit
ground. During initial power on, the TPS40345 enters
a calibration cycle, measures the voltage at the LDRV
pin, and sets an internal OCP voltage level. During
operation, the programmed OCP voltage level is
compared to the voltage drop across the low-side
FET when it is on to determine whether there is an
overcurrent condition. The TPS40345 then enters a
shutdown and restart cycle until the fault is removed.
2 Applications
•
•
•
•
POL Modules
Printers
Digital TVs
Telecom
Device Information(1)
PART NUMBER
TPS40345
PACKAGE
VSON (10)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
VOUT
VIN
TPS40345
5
FB
BOOT
6
4
COMP
HDRV
7
3
PGOOD
SW
8
2
EN/SS LDRV/OC
9
1
VDD
VOUT
SD
VIN
GND
BP 10
PAD
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS40345
SLUSD62 – DECEMBER 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8
8.1 Application Information............................................ 13
8.2 Typical Applications ................................................ 13
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description .............................................. 9
7.1
7.2
7.3
7.4
Application and Implementation ........................ 13
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................... 9
Device Functional Modes........................................ 12
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2017
*
Initial release
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5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
FB COMP PGOOD EN/SS VDD
5
4
3
2
1
8
9
10
SW
LDRV/
OC
BP
Thermal Pad
6
7
BOOT HDRV
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
6
I
Gate drive voltage for the high-side N-channel MOSFET. A 0.1-µF capacitor (typical) must be connected
between this pin and SW. For low input voltage operation, an external Schottky diode from BP to BOOT is
recommended to maximize the gate drive voltage for the high-side.
BP
10
O
Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor of 1 µF or greater from
this pin to GND.
COMP
4
O
Output of the error amplifier and connection node for loop feedback components.
EN/SS
2
I
Logic level input which starts or stops the controller via an external user command. Letting this pin float turns
the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A
capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an
internal current source of 10 µA. The resulting voltage ramp of this pin is also used as a second non-inverting
input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is controlled by the
internal level shifted voltage ramp until that voltage reaches the internal reference voltage of 600 mV – the
voltage ramp of this pin reaches 1.4 V (typical). Optionally, a 267-kΩ resistor from this pin to BP enables the
FSS feature.
FB
5
I
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal
reference voltage.
PGOOD
3
O
Open-drain power good output.
HDRV
7
O
Bootstrapped gate drive output for the high-side N-channel MOSFET.
LDRV/OC
9
O
Gate drive output for the low-side synchronous rectifier N-channel MOSFET. A resistor from this pin to GND
is also used to determine the voltage level for OCP. An internal current source of 10 µA flows through the
resistor during initial calibration and that sets up the voltage trip point used for OCP.
VDD
1
I
Power input to the controller. Bypass VDD to GND with a low ESR ceramic capacitor of at least 1 µF close to
the device.
SW
8
O
Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying highside FET driver.
Thermal
Pad
—
Ground connection to the controller. This is also the thermal pad used to conduct heat from the device. This
connection serves a twofold purpose. The first is to provide an electrical ground connection for the device.
The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be
tied externally to a ground plane.
GND
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VDD
–0.3
22
V
SW
–3
27
V
–5
V
–0.3
30
V
SW (< 100 ns pulse width, 10 µJ)
BOOT
HDRV
–5
30
V
BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW)
–0.3
7
V
COMP, PGOOD, FB, BP, LDRV, EN/SS
–0.3
7
V
Operating junction temperature, TJ
–40
145
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
Input voltage, VDD
Operating junction temperature, TJ
NOM
MAX
UNIT
3
20
V
–20
125
°C
6.4 Thermal Information
TPS40345
THERMAL METRIC (1)
DRC (VSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
44.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.1
°C/W
RθJB
Junction-to-board thermal resistance
19.2
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
19.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
TJ = –20°C to 125°C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TJ = 25°C, 3 V < VVDD < 20 V
597
600
603
–20°C < TJ < 125°C, 3 V < VVDD < 20 V
592
600
608
UNIT
VOLTAGE REFERENCE
VFB
FB input voltage
mV
INPUT SUPPLY
VVDD
Input supply voltage range
20
V
IDDSD
Shutdown supply current
VEN/SS < 0.2 V
3
70
100
µA
IDDQ
Quiescent, nonswitching
Let EN/SS float, VFB = 1 V
2.5
3.5
mA
ENABLE/SOFT-START
VIH
High-level input voltage,
EN/SS
0.55
0.7
1
V
VIL
Low-level input voltage,
EN/SS
0.27
0.3
0.33
V
ISS
Soft-start source current
VSS
Soft-start voltage level
8
10
12
µA
0.4
0.8
1.3
V
6.2
6.5
6.8
V
70
110
mV
kHz
BP REGULATOR
VBP
Output voltage
IBP = 10 mA
VDO
Regulator dropout voltage,
VVDD – VBP
IBP = 25 mA, VVDD = 3 V
OSCILLATOR
fSW
PWM frequency
540
600
660
VRAMP (1)
Ramp amplitude
VVDD/6.6
VVDD/6
VVDD/5.4
fSWFSS
Frequency spread-spectrum
frequency deviation
fMOD
Modulation frequency
12%
V
fSW
25
kHz
PWM
DMAX
(1)
tON(min)
(1)
tDEAD
Maximum duty cycle
VFB = 0 V, 3 V < VVDD < 20 V
90%
Minimum controllable pulse
width
70
HDRV off to LDRV on
5
25
35
LDRV off to HDRV on
5
25
30
Gain bandwidth product
10
24
Open loop gain
60
Output driver dead time
ns
ns
ERROR AMPLIFIER
GBWP
AOL
(1)
(1)
IIB
Input bias current (current
out of FB pin)
VFB = 0.6 V
IEAOP
Output source current
VFB = 0 V
2
IEAOM
Output sink current
VFB = 1 V
2
MHz
dB
75
nA
mA
PGOOD
VOV
Feedback upper voltage limit
for PGOOD
655
675
700
VUV
Feedback lower voltage limit
for PGOOD
500
525
550
VPGD-HYST
PGOOD hysteresis voltage
at FB
25
40
RPGD
PGOOD pulldown resistance VFB = 0 V, IFB = 5 mA
30
70
Ω
IPGDLK
PGOOD leakage current
10
20
µA
(1)
550 mV < VFB < 655 mV,
VPGOOD = 5 V
mV
Ensured by design. Not production tested.
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Electrical Characteristics (continued)
TJ = –20°C to 125°C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT DRIVERS
RHDHI
High-side driver pullup
resistance
VBOOT – VSW = 5 V, IHDRV = –100 mA
0.8
1.5
2.5
Ω
RHDLO
High-side driver pulldown
resistance
VBOOT – VSW = 5 V, IHDRV = 100 mA
0.5
1
2.2
Ω
RLDHI
Low-side driver pullup
resistance
ILDRV = -100 mA
0.8
1.5
2.5
Ω
RLDLO
Low-side driver pulldown
resistance
ILDRV = 100 mA
0.35
0.6
1.2
Ω
High-side driver rise time
CLOAD = 5 nF
(1)
tHRISE
15
ns
tHFALL (1)
High-side driver fall time
12
ns
(1)
Low-side driver rise time
15
ns
Low-side driver fall time
10
ns
tLRISE
tLFALL (1)
OVERCURRENT PROTECTION
tPSSC(min) (1)
Minimum pulse time during
short circuit
250
ns
tBLNKH (1)
Switch leading-edge
blanking pulse time
150
ns
VOCH
OC threshold for high-side
FET
TJ = 25°C
360
450
580
mV
IOCSET
OCSET current source
TJ = 25°C
9.5
10
10.5
µA
VLD-CLAMP
Maximum clamp voltage at
LDRV
260
340
400
mV
VOCLOS
OC comparator offset
voltage for low-side FET
TJ = 25°C
–8
8
mV
VOCLPRO (1)
Programmable OC range for
low-side FET
TJ = 25°C
12
300
mV
VTHTC (1)
OC threshold temperature
coefficient (both high-side
and low-side)
3000
ppm
tOFF
OC retry cycles on EN/SS
pin
4
Cycle
BOOT DIODE
Bootstrap diode forward
voltage
VDFWD
IBOOT = 5 mA
0.8
V
145
°C
20
°C
THERMAL SHUTDOWN
Junction shutdown
temperature
TJSD (1)
TJSDH
6
(1)
Hysteresis
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6.6 Typical Characteristics
625
2.24
620
Switching Frequency (kHz)
2.22
Quiescent Current (mA)
615
610
605
VDD = 3 V
VDD = 12 V
VDD = 20 V
600
595
590
2.2
2.18
2.16
2.14
585
580
-20
5
30
55
80
Temperature (qC)
105
2.12
-20
125
14
70
13
68
66
64
62
30
55
80
Temperature (qC)
105
125
iddq
Figure 2. Quiescent Current vs Junction Temperature
72
OCSET Current Source (PA)
Shutdown Current (PA)
Figure 1. Switching Frequency vs Junction Temperature
60
12
11
10
9
8
7
58
-20
5
30
55
80
Temperature (qC)
105
6
-20
125
Figure 3. Shutdown Current vs Junction Temperature
600.4
600.2
600
599.8
599.6
5
30
55
80
Temperature (qC)
105
125
105
125
iocs
740
720
700
680
660
640
620
-20
vfb_
Figure 5. Feedback Reference Voltage vs Junction
Temperature
30
55
80
Temperature (qC)
Figure 4. OCSET Current Source vs Junction Temperature
Enable High-Level Threshold Voltage (mV)
600.6
599.4
-20
5
D003
600.8
Feedback Reference Voltage (mV)
5
D001
5
30
55
80
Temperature (qC)
105
125
D006
Figure 6. Enable High-Level Threshold Voltage vs Junction
Temperature
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303
600
High-Side Overcurrent Threshold (mV)
Enable Low-Level Threshold Voltage (mV)
Typical Characteristics (continued)
302.5
302
301.5
301
300.5
300
-20
5
30
55
80
Temperature (qC)
105
450
400
5
D007
30
55
80
Temperature (qC)
105
125
D008
Figure 8. High-Side Overcurrent Threshold vs Junction
Temperature
1000
800
Overvoltage
Undervoltage
750
975
950
700
Soft-Start Voltage (mV)
Power Good Threshold Voltage (mV)
500
350
-20
125
Figure 7. Enable Low-Level Threshold Voltage vs Junction
Temperature
650
600
550
500
925
900
875
850
825
800
450
400
-20
775
5
30
55
80
Temperature (qC)
105
125
750
-20
D009
Figure 9. Power Good Threshold Voltage vs Junction
Temperature
8
550
5
30
55
80
Temperature (qC)
105
125
D010
Figure 10. Soft-Start Voltage vs Junction Temperature
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7 Detailed Description
7.1 Overview
The TPS40345 is a cost-optimized synchronous buck controller providing high-end features to construct highperformance DC–DC converters. Prebias capability eliminates concerns about damaging sensitive loads during
start-up. Programmable overcurrent protection levels and hiccup overcurrent fault recovery maximize design
flexibility and minimize power dissipation in the event of a prolonged output short. The frequency spread
spectrum (FSS) feature reduces peak EMI noise by spreading the initial energy of each harmonic along a
frequency band, thus giving a wider spectrum with lower amplitudes.
7.2 Functional Block Diagram
+
10 mA
Soft Start
SS
0.6 VREF + 12.5%
SS
EN/SS
2
+
SD
BP
10
COMP
4
FB
6-V
Regulator
1
+
References
0.6 VREF –12.5%
OC
SD
Spread
Spectrum
Oscillator
Clock
PWM
Logic
5
7
HDRV
8
SW
9
LDRV/OC
BP
Anti-Cross
Conduction
and
Pre-Bias
Circuit
+
10 mA
0.6 VREF
SS
BOOT
PWM
+
PGOOD
6
0.6 VREF
BP
Calibration
Circuit
BP
Fault
Controller
Clock
VDD
FB
Thermal
Shutdown
750 kW
3
OC
Threshold
Setting
Fault Controller
OC
PAD
GND
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7.3 Feature Description
7.3.1 Voltage Reference
The 600-mV bandgap cell is internally connected to the noninverting input of the error amplifier. The reference
voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final
regulation voltage. The 1.3% tolerance on the reference voltage allows the user to design a very accurate power
supply.
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Feature Description (continued)
7.3.2 Enable Functionality, Start-Up Sequence and Timing
After input power is applied, an internal current source of 40 µA starts to charge up the soft-start capacitor
connected from EN/SS to GND. When the voltage across that capacitor increases to 0.7 V, it enables the internal
BP regulator followed by a calibration. The total calibration time is about 1.9 ms. See Figure 11. During the
calibration, the device performs in the following way. It disables the LDRV drive and injects an internal 10-µA
current source to the resistor connected from LDRV to GND. The voltage developed across that resistor is then
sampled and latched internally as the OCP trip level until one cycles the input or toggles the EN/SS.
2.0
VIN – Input Voltage – V
VEN/SS
1.6
Calibration
Time
1.9 ms
1.3 V
1.2
0.8
0.7 V
0.4
VSS_INT
0
t – Time – ms
UDG-09159
Figure 11. Start-Up Sequence and Timing
The voltage at EN/SS is internally clamped to 1.3 V before and/or during calibration to minimize the discharging
time once calibration. The discharging current is from an internal current source of 140 µA and it pulls the voltage
down to 0.4 V. The discharging current then initiates the soft-start by charging up the capacitor using an internal
current source of 10 µA. The resulting voltage ramp on this pin is used as a second noninverting input to the
error amplifier after an 800 mV (typical) downward level-shift; therefore, actual soft-start does not occur until the
voltage at this pin reaches 800 mV.
If EN/SS is left floating, the controller starts automatically. EN/SS must be pulled down to less than 270 mV to
ensure that the chip is in shutdown mode.
7.3.3 Soft-Start Time
The soft-start time of the TPS40345 is user programmable by selecting a single capacitor. The EN/SS pin
sources 10 µA to charge this capacitor. The actual output ramp-up time is the amount of time that it takes for the
10 µA to charge the capacitor through a 600-mV range. There is some initial lag due to calibration and an offset
(800 mV) from the actual EN/SS pin voltage to the voltage applied to the error amplifier.
The soft-start is done in a closed-loop fashion, meaning that the error amplifier controls the output voltage at all
times during the soft-start period and the feedback loop is never open as occurs in duty cycle limit soft-start
schemes. The error amplifier has two non-inverting inputs, one connected to the 600-mV reference voltage, and
the other connected to the offset EN/SS pin voltage. The lower of these two voltages is what the error amplifier
controls the FB pin. As the voltage on the EN/SS pin ramps up past approximately 1.4 V (800-mV offset voltage
plus the 600 mV reference voltage), the 600-mV reference voltage becomes the dominant input and the
converter has reached its final regulation voltage.
The capacitor required for a given soft-start ramp time for the output voltage is given by Equation 1.
æI
CSS = ç SS
è VFB
10
ö
÷ ´ t SS
ø
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Feature Description (continued)
where
•
•
•
•
CSS is the required capacitance on the EN/SS pin. (F)
ISS is the soft-start source current (10 µA).
VFB is the feedback reference voltage (0.6 V).
tSS is the desired soft-start ramp time (s).
(1)
7.3.4 Oscillator and Frequency Spread Spectrum (FSS)
The oscillator frequency is internally fixed. The TPS40345 operating frequency is 600 kHz.
Connecting a resistor with a value of 267 kΩ ±10% from BP to EN/SS enables the FSS feature. When the FSS is
enabled, it spreads the internal oscillator frequency over a minimum 12% window using a 25-kHz modulation
frequency with triangular profile. By modulating the switching frequency, side-bands are created. The emission
power of the fundamental switching frequency and its harmonics is distributed into smaller pieces scattered
around many sideband frequencies. The effect significantly reduces the peak EMI noise and makes it much
easier for the resultant emission spectrum to pass EMI regulations.
7.3.5 Overcurrent Protection
Programmable OCP level at LDRV is from 6 mV to 150 mV at room temperature with 3000 ppm temperature
coefficient to help compensate for changes in the low-side FET channel resistance as temperature increases.
With a scale factor of 2, the actual trip point across the low-side FET is in the range of 12 mV to 300 mV. The
accuracy of the internal current source is ±5%. Overall offset voltage, including the offset voltage of the internal
comparator and the amplifier for scale factor of 2, is limited to ±8 mV.
Maximum clamp voltage at LDRV is 340 mV to avoid turning on the low-side FET during calibration and in a
prebiased condition. The maximum clamp voltage is fixed and it does not change with temperature. If the voltage
drop across ROCSET reaches the 340-mV maximum clamp voltage during calibration (no ROCSET resistor
included), it disables OC protection. Once disabled, there is no low-side or high-side current sensing.
OCP level at HDRV is fixed at 450 mV with 3000-ppm temperature coefficient to help compensate for changes in
the high-side FET channel resistance as temperature increases. OCP at HDRV provides pulse-by-pulse current
limiting.
OCP sensing at LDRV is a true inductor valley current detection, using sample and hold. Equation 2 can be used
to calculate ROCSET:
ææ
ö
æI
öö
ç ç IOUT(max ) - ç P-P ÷ ÷ ´ RDS(on ) - VOCLOS ÷
è 2 øø
ç
÷
ROCSET = ç è
÷
2 ´ IOCSET
ç
÷
ç
÷
è
ø
where
•
•
•
•
•
•
IOCSET is the internal current source.
VOCLOS is the overall offset voltage.
IP-P is the peak-to-peak inductor current.
RDS(on) is the drain to source ON-resistance of the low-side FET.
IOUT(max) is the trip point for OCP.
ROCSET is the resistor used for setting the OCP level.
(2)
To avoid overcurrent tripping in normal operating load range, calculate ROCSET using Equation 2 with:
• The maximum RDS(ON) at room temperature
• The lower limit of VOCLOS (–8 mV) and the lower limit of IOCSET (9.5 µA) from the Electrical Characteristics
table.
• The peak-to-peak inductor current IP-P at minimum input voltage
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Feature Description (continued)
Overcurrent is sensed across both the low-side FET and the high-side FET. If the voltage drop across either FET
exceeds the OC threshold, a count increments one count. If no OC is detected on either FET, the fault counter
decrements by one count. If three OC pulses are summed, a fault condition is declared which cycles the softstart function in a hiccup mode. Hiccup mode consists of four dummy soft-start timeouts followed by a real one if
overcurrent condition is encountered during normal operation, or five dummy soft-start timeouts followed by a
real one if overcurrent condition occurs from the beginning during start. This cycle continues indefinitely until the
fault condition is removed.
7.3.6 Drivers
The drivers for the external high-side and low-side MOSFETs can drive a gate-to-source voltage of VBP. The
LDRV driver for the low-side MOSFET switches between BP and GND, while the HDRV driver for the high-side
MOSFET is referenced to SW and switches between BOOT and SW. The drivers have nonoverlapping timing
that is governed by an adaptive delay circuit to minimize body diode conduction in the synchronous rectifier.
7.3.7 Prebias Start-Up
The TPS40345 contains a circuit to prevent current from being pulled from the output during start-up in the
condition the output is prebiased. There are no PWM pulses until the internal soft-start voltage rises above the
error amplifier input (FB pin), if the output is prebiased. Once the soft-start voltage exceeds the error amplifier
input, the controller slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow
on time. The controller then increments that on time on a cycle-by-cycle basis until it coincides with the time
dictated by (1-D), where D is the duty cycle of the converter. This approach prevents the sinking of current from
a prebiased output, and ensures the output voltage start-up and ramp to regulation is smooth and controlled.
7.3.8 Power Good
The TPS40345 provides an indication that output is good for the converter. This is an open-drain signal and pulls
low when any condition exists that would indicate that the output of the supply might be out of regulation. These
conditions include the following:
• VFB is more than ±12.5% from nominal.
• Soft-start is active.
• A short-circuit condition has been detected.
NOTE
When there is no power to the device, PGOOD is not able to pull close to GND if an
auxiliary supply is used for the power good indication. In this case, a built-in resistor
connected from drain to gate on the PGOOD pulldown device makes the PGOOD pin look
approximately like a diode to GND.
7.3.9 Thermal Shutdown
If the junction temperature of the device reaches the thermal shutdown limit of 145°C, the PWM and the oscillator
are turned off and HDRV and LDRV are driven low. When the junction cools to the required level (125°C typical),
the PWM initiates soft-start as during a normal power-up cycle.
7.4 Device Functional Modes
7.4.1 Modes of Operation
7.4.1.1 UVLO
In UVLO, VDD is less than UVLO_ON, the BP6 regulator is off, and the HDRV and LDRV are held low by
internal passive discharge resistors.
7.4.1.2 Disable
Disable is forced by holding SS/EN below 0.4 V. In disable, the BP6 regulator is off, and both HDRV and LDRV
are held low by passive discharge resistors.
12
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Device Functional Modes (continued)
7.4.1.3 Calibration
Each enable of the TPS40345 device requires a calibration which lasts approximately 2 ms. During calibration
the TPS40345 device LDRV and HDRV are held off by its pulldown drivers while the device configures as
detailed in Enable Functionality, Start-Up Sequence and Timing.
7.4.1.4 Converting
When calibration completes, the TPS40345 ramps its reference voltage as described in Soft-Start Time, and the
states of the LDRV and HDRV drivers are dictated by the COMP pin to regulate the FB pin equal to the internal
reference.
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS40345 a cost-optimized synchronous buck controllers providing high-end features to construct highperformance DC-DC converters. Prebias capability eliminates concerns about damaging sensitive loads during
start-up. Programmable overcurrent protection levels and hiccup overcurrent fault recovery maximize design
flexibility and minimize power dissipation in the event of a prolonged output short. frequency spread spectrum
(FSS) feature reduces peak EMI noise by spreading the initial energy of each harmonic along a frequency band,
thus giving a wider spectrum with lower amplitudes.
8.2 Typical Applications
For this 20-A, 12-V to 1.2-V design, the 600-kHz TPS40345 was selected for a balance between small size and
high efficiency.
+
+
1
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Figure 12. TPS40345 Design Example Schematic
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Typical Applications (continued)
8.2.1 Design Requirements
For this example, follow the design parameters listed in Table 1.
Table 1. Design Example Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
8
MAX
VIN
Input voltage
VINripple
Input ripple
IOUT = 20 A
VOUT
Output voltage
0 A ≤ IOUT ≤ 20 A
Line regulation
8 V ≤ VIN ≤ 14 V
0.5%
Load regulation
0 A ≤ IOUT ≤ 20 A
0.5%
VRIPPLE
Output ripple
IOUT = 20 A
VOVER
Output overshoot
5 A ≤ IOUT ≤ 15 A
VUNDER
Output undershoot
5 A ≤ IOUT ≤ 15 A
IOUT
Output current
8 V ≤ VIN ≤ 14 V
tSS
Soft-start time
VIN = 12 V
ISCP
Short-circuit current trip point
fSW
Switching frequency
1.164
1.2
14
V
0.5
V
1.236
V
36
100
mV
mV
100
0
UNIT
mV
20
A
1.5
ms
600
kHz
26
A
Size
1.5
in2
8.2.2 Detailed Design Procedure
8.2.2.1 Selecting the Switching Frequency
To achieve the small size for this design the TPS40345, with fSW = 600 kHz, is selected for minimal external
component size.
8.2.2.2 Inductor Selection (L1)
Synchronous buck power inductors are typically sized for approximately 30% peak-to-peak ripple current
(IRIPPLE).
Given this target ripple current, the required inductor size can be calculated in Equation 3.
VIN(max) - VOUT
V
1
14V - 1.2V 1.2V
1
L»
´ OUT ´
=
´
´
= 305nH
0.3 ´ IOUT
VIN(max) FSW
0.3 ´ 20A 14V 600kHz
(3)
Selecting a standard 300-nH inductor value, solve for IRIPPLE = 6 A
The RMS current through the inductor is approximated by Equation 4.
I Lrms = I Lavg2 +
2
1 I
12 RIPPLE
=
I OUT2 +
2
1 I
12 RIPPLE
= 202 + 112 62 = 20.07 A
(4)
8.2.2.3 Output Capacitor Selection (C12)
The selection of the output capacitor is typically driven by the output transient response. Equation 5 and
Equation 6 overestimate the voltage deviation to account for delays in the loop bandwidth and can be used to
determine the required output capacitance.
2
I
I
I
I
´L
´L
VOVER < TRAN ´ DT = TRAN ´ TRAN
= TRAN
COUT
COUT
VOUT
VOUT ´ COUT
VUNDER <
(5)
ITRAN2
´L
´L
ITRAN
I
I
´ DT = TRAN ´ TRAN
=
COUT
COUT VIN - VOUT (VIN - VOUT )´ COUT
(6)
If VIN(min) > 2 × VOUT, use overshoot (Equation 5) to calculate minimum output capacitance. If VIN(min) < 2 × VOUT,
use undershoot (Equation 6) to calculate minimum output capacitance.
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COUT(MIN) =
ITRAN(MAX)2 ´ L
(VOUT )´ VOVER
=
102 ´ 300nH
= 250mF
1.2 ´ 100mV
(7)
With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is
approximated by Equation 8.
ESRmax =
VRIPPLE(Total) - VRIPPLE(CAP)
IRIPPLE
æ
ö
IRIPPLE
æ
ö
6A
VRIPPLE(total) - ç
÷ 36mV - ç
8 ´ COUT ´ FSW ø
8 ´ 250mF ´ 600kHz ÷ø
è
è
=
=
= 5.2mW
IRIPPLE
6A
(8)
Two 47-µF and one 220-µF capacitors are selected to provide more than 250 µF of minimum capacitance and
5.2 mΩ of ESR.
8.2.2.4 Peak Current Rating of Inductor
With output capacitance, it is possible to calculate the charge current during start-up and determine the minimum
saturation current rating for the inductor. The start-up charging current is approximated by Equation 9.
ICHARGE =
VOUT × COUT 1.2 V(2 × 47 mF + 220 m F)
= 0.251 A
=
TSS
1.5 ms
IL _ PEAK = I OUT(max) +
1
2 IRIPPLE + I CHARGE
= 20 A
+1
2
(9)
× 6 A + 0.2512 A = 23.25 A
(10)
Table 2. Inductor Requirements
PARAMETER
VALUE
UNIT
L
Inductance
300
nH
IL(rms)
RMS current (thermal rating)
20.07
A
IL(peak)
Peak current (saturation rating)
23.25
A
8.2.2.5 Input Capacitor Selection (C8)
The input voltage ripple is divided between capacitance and ESR. For this design VRIPPLE(cap) = 150 mV and
VRIPPLE(esr) = 150 mV. The minimum capacitance and maximum ESR are estimated by Equation 11.
ILOAD ´ VOUT
20 ´ 1.2V
=
= 33.3uF
CIN(min) =
VRIPPLE(CAP) ´ VIN ´ FSW 150mV ´ 8V ´ 600kHz
(11)
ESRMAX =
VRIPPLE(ESR)
ILOAD +
1 I
2 RIPPLE
=
150 mV
= 6.5 mW
23A
(12)
The RMS current in the input capacitors is estimated by Equation 13.
IRMS _ CIN = ILOAD ´ D ´ (1 – D) = 20 A ´ 0.15 ´ (1 - 0.15) = 7.14 Arms
(13)
Three 1210, 10-µF, 25-V, X5R ceramic capacitors are selected. Higher voltage capacitors are selected to
minimize capacitance loss at the DC bias voltage to ensure the capacitors allow sufficient capacitance at the
working voltage.
8.2.2.6 MOSFET Switch Selection (Q1 and Q2)
Reviewing available TI NexFET MOSFETs using the TI NexFET MOSFET selection tool, the CSD16410Q5A and
CSD16321Q5 5-mm × 6-mm MOSFETs are selected.
These two FETs have maximum total gate charges of 5 nC and 10 nC, respectively.
8.2.2.7 Bootstrap Capacitor (C6)
To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to less than
50 mV.
CBoost = 20 ´ QG1 = 20 ´ 5 nC = 100 nF
(14)
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8.2.2.8 VDD Bypass Capacitor (C7)
Per this TPS40345 data sheet, select a 1-uF X5R or better ceramic bypass capacitor for VDD.
8.2.2.9 BP Bypass Capacitor (C5)
Per the TPS40345 data sheet, a minimum 1-uF ceramic capacitance is required to stabilize the BP regulator. To
limit regulator noise to less than 10 mV, the value of the bypass capacitor is calculated in Equation 15.
CBP = 100 ´ MAX(QG1,QG2 )
(15)
Because Q2 is larger than Q1, and the total gate charge of Q2 is 10 nC, a BP capacitor of 1 µF is calculated. A
standard value of 1 µF is selected to limit noise on the BP regulator.
8.2.2.10 Short-Circuit Protection (R11)
The TPS40345 uses the negative drop across the low-side FET at the end of the OFF-time to measure the
inductor current. Allowing for 30% over maximum load and 20% rise in RDS(on)Q1 for self-heating, the voltage drop
across the low-side FET at current limit is given by Equation 16.
VOC = (1.3 ´ ILOAD - 21 Iripple ) ´ 1.2 ´ RDSONG2 = (1.3 ´ 20 A- 21 6 A) ´ 1.2 ´ 4.6 mW = 127 mV
(16)
The TPS40345 internal temperature coefficient helps compensate for the MOSFET’s RDS(on) temperature
coefficient, so the current limit programming resistor is selected by Equation 17.
RCS =
VOC - VOCLOS(min)
2 ´ IOCSET(min)
=
127 mV - (– 8 mV)
= 7.1 kW
2 ´ 9.5 mA
(17)
8.2.2.11 Feedback Divider (R4, R5)
The TPS40345 controller uses a full operational amplifier with an internally fixed 0.6-V reference. R4 is selected
between 10 kΩ and 50 kΩ for a balance of feedback current and noise immunity. With R4 set to 10 kΩ, The
output voltage is programmed with a resistor divider given by Equation 18.
VFB ´ R4
0.600 V ´ 10.0 kW
R7 =
=
= 10 kW
VOUT - VFB
1.2 V - 0.600 V
(18)
8.2.2.12 Compensation: (C2, C3, C4, R3, R6)
Using the TPS40k Loop Stability Tool for 100-kHz bandwidth and 60° phase margin with a R4 value of 10.0 kΩ,
the following values are returned.
• C4 = 680 pF
• C5 = 100 pF
• C6 = 680 pF
• R1 = 10 kΩ
• R2 = 1.5 kΩ
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8.2.3 Application Curves
95
100
225
80
180
VIN = 8 V
90
Phase
60
135
40
90
20
45
0
0
75
VIN = 12 V
70
65
60
–20
–45
Gain
55
Phase – °
VIN = 14 V
80
Gain – dB
h – Efficiency – %
85
–40
–90
50
0
5
10
15
20
–60
1k
ILOAD – Load Current – A
10 k
100 k
–135
1M
f – Frequency – Hz
Figure 13. Efficiency vs Load Current
Figure 14. Gain and Phase vs Frequency
Figure 15. Output Ripple 10 mV/div, 2-µs/div, 20-MHz Bandwidth
9 Power Supply Recommendations
The TPS40345 device is designed to operate from an input voltage supply between 3 V and 20 V. This input
supply must remain within the input voltage supply range. This supply must be well regulated.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
18
For MOSFET or power block layout, follow the layout recommendations provided for the MOSFET or power
block selected.
Connect VDD to VIN as close as possible to the drain connection of the high-side FET to avoid introducing
additional drop, which could trigger short-circuit protection.
Place VDD and BP to GND capacitors within 2 mm of the device and connected to the thermal pad (GND).
Connect the FB to GND resistor to the thermal tab (GND) with a minimum 10-mil wide trace.
Place VOUT to FB resistor within 2 mm of the FB pin.
Connect the EN/SS-to-GND capacitor to the thermal tab (GND) with a minimum 10-mil-wide trace. It may
share this trace with FB to GND.
If a BJT or MOSFET is used to disable EN/SS, place it within 5 mm of the device.
If a COMP to GND resistor is used, place it within 5 mm of the device.
All COMP and FB traces should be kept minimum line width and as short as possible to minimize noise
coupling.
EN/SS should not be routed more than 20 mm from the device.
If multiple layers are used, extend GND under all components connected to FB, COMP and EN/SS to reduce
noise sensitivity.
HDRV and LDRV must provide short, low inductance paths of 5 mm or less to the gates of the MOSFETs or
power block.
Place no more than 1 Ω of resistance between HDRV or LDRV and their MOSFET or power block gate pins.
LDRV / OC to GND current limit programming resistor may be placed on the far side of the MOSFET if
necessary to ensure a short connection from LDRV to the gate of the low-side MOSFET.
Place the BOOT to SW resistor and capacitor within 4 mm of the device using a minimum of 10-mil-wide
trace. The full width of the component pads are preferred for trace widths if design rules allow.
If via must be used between the HDRV, SW and LDRV pins and their respective MOSFET or power block
connections, use a minimum of two vias to reduce parasitic inductance
Refer to the land pattern data for the preferred layout of thermal vias within the thermal pad.
TI recommends extending the top-layer copper area of the thermal pad (GND) beyond the package a
minimum 3 mm between pins 1 and 10 and 5 and 6 to improve thermal resistance to ambient of the device.
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10.2 Layout Example
Figure 16. Top Copper With Components
..
..
Figure 17. Top Internal Copper Layout
..
..
Figure 18. Bottom Internal Copper Layout
Figure 19. Bottom Copper Layer
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
These references, design tools and links to additional references, including design software, may be found at
http://power.ti.com
1. Additional PowerPAD™ information may be found in Applications Briefs (SLMA002) and (SLMA004).
2. Understanding Buck Power Stages in Switchmode Power Supplies
3. Under The Hood Of Low Voltage DC/DC Converters – SEM1500 Topic 5 – 2002 Seminar Series
4. Designing Stable Control Loops – SEM 1400 – 2001 Seminar Series
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS40345DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-20 to 85
0345
TPS40345DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-20 to 85
0345
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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