SLVS025B − APRIL 2002 − REVISED JULY 2004
DESCRIPTION
FEATURES
D Switching Mode Step-Down dc-to-dc
D
D
D
D
D
D
D
D
D
The TPS5110 provides one PWM-mode synchronous
buck regulator controller (SBRC) and one low drop-out
(LDO) regulator controller. The TPS5110 supports a
low-voltage/high-current power supply for I/O and other
peripherals in modern digital systems. The SBRC of the
TPS5110 automatically adjusts from PWM mode to
SKIP mode to maintain high efficiency under all load
conditions. The LDO controller drives an external
N-channel power MOSFET that realizes fast response
and ultra-low dropout voltage. A unique overshoot
protection circuit prevents a voltage hump at fast load
decreasing transients. The current protection circuit for
SBRC detects the drain-to-source voltage drop across
the low-side and high-side power MOSFET while it is
conducting. Also, the current protection circuit has a
temperature coefficient to compensate for the RDS(on)
variation of the MOSFET. This resistor-less current
protection simplifies the system design and reduces the
external parts count. The LDO controller includes
current-limit protection. Other features, such as
undervoltage lockout, power good, overvoltage,
undervoltage,
and
programmable
short-circuit
protection promote system reliability.
Controller With Fast LDO Controller
Input Voltage Range
Switcher: 4.5 V to 28 V
LDO: 1.1 V to 3.6 V
Output Voltage Range
Switcher: 0.9 V to 3.5 V
LDO: 0.9 V to 2.5 V
Synchronous for High Efficiency
Precision VREF (±1 %)
PWM Mode Control: Max. 500-kHz Operation
High-Speed Error Amplifier
Overcurrent Protection With Temperature
Compensation Circuit
Overvoltage and Undervoltage Protection
Programmable Short-Circuit Protection
APPLICATIONS
D Notebook PCs, PDAs
D Consumer Game Systems
D DSP Application
SIMPLIFIED APPLICATION
LDO Load Transient Response
TPS5110PW
1
INV
VIN
COUT = 47 µF
LH 24
OUT_u 23
LL 22
6
GND
VO1
VOUT = 1.5 V
(50 mV/ div)
OUT_d 21
5V
INPUT
REG5V_IN 17
LDO_IN 16
LDO_CUR 15
12 INV_LDO
LDO_GATE 14
LDO_OUT 13
VO2
IOUT = 0 A to 3 A
(1 A/ div)
t− time 100 µs/div
UDG-02052
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Copyright 2002, Texas Instruments Incorporated
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1
SLVS025B − APRIL 2002 − REVISED JULY 2004
ORDERING INFORMATION
PW PACKAGE
(TOP VIEW)
PACKAGED DEVICES(1)
TA
PLASTIC TSSOP (PW)
−40°C to 85°C
TPS5110PW (24)
(1) The PW package is also available taped and reeled. Add an R
suffix to the device type (i.e. TPS5110PWR)
2
INV
FB
SOFTSTART
PWM_SEL
CT
GND
REF
STBY
STBY_LDO
FLT
POWERGOOD
INV_LDO
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1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LH
OUT_u
LL
OUT_d
OUTGND
TRIP
VIN_SENSE
REG5V_IN
LDO_IN
LDO_CUR
LDO_GATE
LDO_OUT
SLVS025B − APRIL 2002 − REVISED JULY 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS5110
Input voltage range, VI
Output voltage range, VO
UNIT
VIN_SENSE, STBY, STBY_LDO, TRIP, LL
INV, SOFTSTART, PWM_SEL, CT, FLT,
INV_LDO, LDO_OUT, LDO_CUR, LDO_IN,
REG5V_IN
−0.3 to 30
LH
−0.3 to 35
REF
−0.3 to 3
V
FB, POWERGOOD, OUT_d
−0.3 to 7
V
LDO_GATE
−0.3 to 9
V
OUT_u
−0.3 to 35
V
Continuous total power dissipation
−0.3 to 7
V
See dissipation rating table
Operating ambient temperature range, TA
−40 to 85
Storage temperature range, Tstg
−55 to 150
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
GND.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
Supply voltage
REG5V_IN
4.5
5.5
Supply voltage
LDO_IN
1.1
3.6
VIN_SENSE
4.5
28
INV, INV_LDO, CT, PWM_SEL, SOFTSTART, FLT
−0.1
6
POWERGOOD, FB, OUT_d
−0.1
5.5
LDO_CUR, LDO_OUT
−0.1
3.5
STBY, STBY_LDO, LL
−0.1
28
OUT_u, LH
−0.1
33
TRIP
−0.1
28
LDO_GATE
−0.1
Input voltage, VI
Oscillator frequency, fOSC
−40
V
8
300
Operating free-air temperature, TA
UNIT
500
kHz
85
_C
DISSIPATION RATINGS (THERMAL RESISTANCE = °C/W)
PACKAGE(1)
DERATING FACTOR ABOVE
TA = 25°C
TA ≤ 25°C POWER
RATING
TA = 85°C POWER
RATING
24-PW
11.24 mW/°C
1404 mW
730 mW
(2) These devices are mounted on a JEDEC high-k board (2 oz. traces on surface, 2-layer 1-oz plane inside).
(Assume the maximum junction temperature is 150°C)
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3
SLVS025B − APRIL 2002 − REVISED JULY 2004
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, VVIN_SENSE = 12 V and VREG5V_IN = 5 V (unless otherwise specified).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.9
1.4
mA
0.001
10.00
µA
SUPPLY CURRENT SECTION
ICC
Supply current
ICC(S)Shutdown current
REG5V_IN current, TA = 25_C,
VLDO_IN = 3.6 V,
VCT = VINV = VINV_LDO = VPWM_SEL = 0 V
REG5V_IN current,
VSTBY = VSTBY_LDO = 0 V
UNDERVOLTAGE LOCKOUT SECTION
V(TLH)Low-to-high threshold voltage
REG5V_IN voltage
3.6
4.2
V(TLL)High-to-low threshold voltage
REG5V_IN voltage
3.5
4.1
VHYS Hysteresis
REG5V_IN voltage
30
200
V
mV
REFERENCE VOLTAGE SECTION
VREF Reference voltage
VREF(tol)
Reference voltage tolerance
0.85
V
TA = 25_C,
IREF = 50 µA
−1%
1%
0_C ≤ TA ≤ 85_C,
IREF = 50 µA
-1.5%
1.5%
−40_C ≤ TA ≤ 85_C,
IREF = 50 µA
−2%
2%
Reg(line)
Line regulation
IREF = 50 µA,
4.5 V ≤ V(REG5V_IN) ≤ 5.5 V
0.05
5
mV
Reg(load)
Load regulation
0.1 µA ≤ IREF ≤ 1 mA
0.15
5
mV
CONTROL SECTION
VIH
High-level input voltage
STBY, STBY_LDO, PWM_SEL
VIL
Low-level input voltage
STBY, STBY_LDO, PWM_SEL
2.2
0.3
V
OUTPUT VOLTAGE MONITOR SECTION
OVP comparator threshold voltage
SBRC, LDO
0.91
0.95
0.99
UVP comparator threshold voltage
SBRC, LDO
0.51
0.55
0.59
Powergood comparator 1, 4 threshold voltage
0.75
0.79
0.81
Powergood comparator 2, 3 threshold voltage
0.88
0.91
0.94
Powergood propagation delay from INV and
INV_LDO to POWERGOOD
Timer latch current source
POWERGOOD high-to-low
1.2
POWERGOOD low-to-high
4
V
µss
UVP protection
−1.5
−2.3
−3.1
OVP protection
−80
−125
−180
µA
A
OSCILLATOR SECTION
fOSC Oscillator frequency
PWM mode,
TA = 25_C
dc
VOH CT high-level output voltage
4
300
1.0
fOSC = 300 kHz
dc
VOL CT low-level output voltage
CCT = 44 pF
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1.2
1.17
0.4
fOSC = 300 kHz
1.1
kHz
0.5
0.43
0.6
V
SLVS025B − APRIL 2002 − REVISED JULY 2004
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, VVIN_SENSE = 12 V and VREG5V_IN = 5 V (unless otherwise specified).
SBRC ERROR AMPLIFIER SECTION
VIO
Input offset voltage
TA = 25_C
2
Open loop voltage gain
10
50
Unity gain bandwidth
mV
dB
2.5
ISNK Output sink current
VFB = 1 V
0.2
0.7
ISRC Output source current
VFB = 1 V
−0.2
−0.9
MHz
mA
DUTY CONTROL SECTION
DUTY Maximum duty control
fOSC = 300 kHz,
VINV = 0 V
82%
OUTPUT DRIVERS SECTION
OUT_u sink current
VOUT_u − VLL = 3 V
1.2
OUT_u source current
VLH − VOUT_u = 3 V
−1.2
OUT_d sink current
VOUT_d = 3 V
1.5
OUT_d source current
VOUT_d = 2 V
−1.5
LDO_GATE sink current
VLDO_GATE = 2 V
1.5
LDO_GATE source current
VLDO_GATE = 2 V
−1.4
ITRIP TRIP current
TA = 25_C
A
mA
11.5
13.0
14.5
µA
−1.6
−2.3
−2.9
µA
2
10
mV
SOFT-START SECTION
ISOFT Soft-start current
LDO ERROR AMPLIFIER SECTION
VIO
Input offset voltage
TA = 25_C,
Open loop voltage gain
VLDO_IN = 3.3 V
Unity-gain bandwidth
VLDO_IN = 3.3 V,
VLDO_IN = 3.3 V
50
CLOAD = 2000 pF
dB
1.4
MHz
LDO CURRENT LIMIT SECTION
Current limit comparator threshold voltage
VLDO_IN = 3.3 V
40
50
60
mV
LDO OVERSHOOT PROTECTION SECTION
LDO_OUT sink current
VLDO_OUT = VLDO_GATE = 1.5 V
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25
mA
5
SLVS025B − APRIL 2002 − REVISED JULY 2004
Terminal Functions
TERMINAL
NAME
CT
NO.
5
I/O
DESCRIPTION
I/O
External capacitor from CT to GND adjusts frequency of the triangle oscillator.
FB
2
O
Feedback output of error amplifier
FLT
10
I/O
Fault latch timer pin. An external capacitor is connected between FLT and GND to set the FLT enable time
up.
GND
6
−
Signal GND
INV
1
I
Inverting input of the SBRC error amplifier, skip comparator, OVP/UVP comparators and POWERGOOD
comparator
INV_LDO
12
I
Inverting input of the LDO regulator, OVP/UVP comparators and POWERGOOD comparator
LDO_CUR
15
I
Current sense input of the LDO regulator.
LDO_GATE
14
O
Gate control output of an external MOSFET for LDO
LDO_OUT
13
I/O
LDO regulator’s output connection. If output voltage causes an over shoot at output current changes high
to low quickly, it pulls out electrical charge from this pin.
LDO_IN
16
I
LH
24
I/O
Bootstrap capacitor connection for high-side gate driver
LL
22
I/O
High side gate driving return. Connect this pin to the junction of the high side and low side MOSFET(s) for
floating drive configuration. This pin also is an input terminal for current comparator.
OUT_d
21
O
Gate drive output for low-side MOSFET(s)
OUT_u
23
O
Gate drive output for high-side MOSFET(s).
OUTGND
20
−
Ground for FET drivers. It is connected to the current limiting comparator’s negative input.
POWERGOOD
11
O
Power good open-drain output. PG comparators monitor both SBRC’s and LDO’s over voltage and under
voltage. The threshold is ±7%. When either output is beyond this condition, POWERGOOD output goes
low. When STBY or STBY_LDO goes high, the POWERGOOD pin’s output starts with high. POWERGOOD also monitors REG5V_IN’s UVLO output.
PWM_SEL
4
I
PWM or auto PWM/SKIP modes select.
H: auto PWM/SKIP
L: PWM fixed
REF
7
O
0.85-V reference voltage output. This 0.85-V reference voltage is used for setting the output voltage and
the voltage protections. This reference voltage is regulated from REG5V_IN power supply.
REG5V_IN
17
I
External 5-V input. This input is a supply voltage for internal circuits.
SOFTSTART
3
I/O
STBY
8
I
Standby control input for SBRC. SBRC can be switched into standby mode by grounding the STBY pin.
STBY_LDO
9
I
Standby control input for LDO regulator. LDO regulator can be switched into standby mode by grounding
the STBY_LDO pin.
TRIP
19
I
External resistor connection for SBRC’s output current protection control.
VIN_SENSE
18
I
SBRC supply voltage monitor. Input range is 4.5 V to 28 V. This pin is for reference of current limit.
6
Input of LDO regulator and current sense input of LDO regulator
External capacitor between SOFTSTART and GND sets SBRC soft−start time.
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SLVS025B − APRIL 2002 − REVISED JULY 2004
FUNCTIONAL BLOCK DIAGRAM
LH
SOFTSTART
SOFT START
OUT_u
Skip Comp.
−
Delay
LL
−
+
PWM Comp.
+
OUT_d
Delay
FB
OUTGND
INV
+
Current Comp.1
PWM
−
+
SKIP
−
control
Err. Amp.
+
Current
0.85 V
CT
SOFT
START
OSC
−
UVLO
Signal
Protection
Trigger
− (VIN_SENSE − TRIP)
VIN_SENSE
STBY
TRIP
OVP SBRC
−
+
0.85 V +12 %
Current Comp.2
+
INV
PWM_SEL
−
FLT
TIMER
0.85 V −35 %
PG Comp.1
POWERGOOD
0.85 V −7 %
OVP LDO
INV
−
+
+
+
UVP SBRC
PG Comp.2
0.85 V +7 %
PG Comp.3
−
−
INV_LDO
UVP LDO
STBY
+
+
INV_LDO
0.85 V +7 %
UVLO STBY_LDO
Signal
−
PG Comp.4
0.85 V −7 %
STBY_LDO
REG5V_IN
VREF
REF
UVLO
Signal
0.85 V
−
OVP LDO
Err. Amp.
VIN
sense
−
+
UVLO Comp.
+
−
0.85 V +12 %
LDO_GATE
+
INV_LDO
Clamp
0.85 V
LDO_IN
+
GND
UVP LDO
Current Limit
LDO_CUR
LDO Overshoot
LDO_OUT
−
0.85 V −35 %
Protection
Figure 1. Block Diagram
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7
SLVS025B − APRIL 2002 − REVISED JULY 2004
DETAILED DESCRIPTION
PWM operation
The SBRC block has a high-speed error amplifier to regulate the output voltage of the synchronous buck
converter. The output voltage of the SBRC is fed back to the inverting input (INV) of the error amplifier. The
noninverting input is internally connected to a 0.85 V precise band gap reference circuit. The unity-gain
bandwidth of the amplifier is 2.5 MHz. This decreases the amplifier delay during fast-load transients and
contributes to a fast response. Loop gain and phase compensation is programmable by an external C, R
network between the FB and INV pins. The output signal of the error amplifier is compared with a triangular wave
to achieve the PWM control signal. The oscillation frequency of this triangular wave sets the switching frequency
of the SBRC and is determined by the capacitor connected between the CT and GND pins. The PWM mode
is used for the entire load range if the PWM_SEL pin is set LOW, or used in high-output current condition if auto
PWM/SKIP mode is selected by setting the same pin to HIGH.
SKIP mode operation
The PWM_SEL pin selects either the auto PWM/SKIP mode or fixed PWM mode. If this pin is lower than 0.3 V,
the SBRC operates in the fixed PWM mode. If 2.5 V (min.) or higher is applied, it operates in auto PWM/SKIP
mode. In the auto PWM/SKIP mode, the operation changes from constant frequency PWM mode to an
energy-saving SKIP mode automatically in accordance with load conditions. Using a MOSFET with ultra-low
RDS(on) if the auto SKIP function is implemented is not recommended. The SBRC block has a hysteretic
comparator to regulate the output voltage of the synchronous buck converter during SKIP mode. The delay from
the comparator input to the driver output is typically 1.2 µs. In the SKIP mode, the frequency varies with load
current and input voltage.
high-side driver
The high-side driver is designed to drive high current and low RDS(on) N-channel MOSFET(s). The current rating
of the driver is 1.2 A at source and sink. When configured as a floating driver a 5-V bias voltage is delivered from
external REG5V_IN supply. The instantaneous-drive current is supplied by the flying capacitor between the LH
and LL pins since a 5-V power supply does not usually have low impedance. It is recommended to add a 5-Ω
to 10-Ω resistor between the gate of the high-side MOSFET(s) and the OUT_u pin to suppress noise. The
maximum voltage that can be applied between the LH and OUTGND pins is 33 V. When selecting the
high-current rating MOSFET(s), it is important to pay attention to both gate-drive power dissipation and the
rise/fall time against the dead-time between high-side and low-side drivers. The gate-drive power is dissipated
from the controller device and it is proportional to the gate charge at Vgs = 5 V, PWM switching frequency and
the numbers of all MOSFETs used for low-side and high-side switches. This gate drive loss should not exceed
the maximum power dissipation of the device.
low-side driver
The low-side driver is designed to drive high-current and low RDS(on) N-channel MOSFET(s). The maximum
drive voltage is 5 V from REG5V_IN pin. The current rating of the driver is typically 1.5 A at source and sink.
Gate resistance is not necessary for the low-side MOSFET for switching noise suppression since it turns on after
the parallel diode is turned on (ZVS). It needs the same dissipation consideration when using high-current rating
MOSFET(s). Another issue that needs precaution is the gate threshold voltage. Even though the OUT_d pin
is shorted to the OUTGND pin with low resistance when the low-side MOSFET(s) is OFF, high dv/dt at the LL
pin during turnon of the high side arm generates voltage peak at the OUT_d pin through the drain to gate
capacitance, Cdg, of the low-side MOSFET(s). To prevent a short period shoot-through during this switching
event, the application designer should select MOSFET(s) with adequate threshold voltage.
8
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SLVS025B − APRIL 2002 − REVISED JULY 2004
DETAILED DESCRIPTION
dead time
The internally defined dead-time prevents shoot-through current flowing through the main power MOSFETs
during switching transitions. Typical value of the dead-time is 100 ns.
standby
The SBRC and the LDO controller can be switched into standby mode separately by grounding the STBY pin
and/or SYBY_LDO pins. The standby-mode current, when both controllers are off, can be as low as 1 nA.
Table 1. Standby Logic (VREG5V_IN > 4 V){
STBY
STBY_LDO
SBRC
LDO
POWERGOOD
L
L
OFF
OFF
OFF
L
H
OFF
ON
OFF
H
L
ON
OFF
OFF
H
H
ON
ON
ON
soft start
Soft-start ramp up of the SBRC is controlled by the SOFTSTART pin voltage. After the STBY pin is raised to
a HIGH level, an internal current source charges up an external capacitor connected between the SOFTSTART
and GND pins. The output voltage ramps up as the SOFTSTART pin voltage increases from 0 V to 0.85 V. The
soft-start time is easily calculated by the supply current and the capacitance value (see application information).
The soft-start timing circuit for the LDO is integrated into the device. The soft-start time is fixed and can be as
short as 600 µs. This is observed when the LDO is turned on separately from the SBRC. Simultaneous start
up of the two outputs is also possible. Tie the LDO input to the SBRC’s output and let both STBY_LDO and STBY
voltages rise to the HIGH level simultaneously, then the LDO’s output follows the ramp of the SBRC’s output.
over current protection
Over current protection (OCP) is achieved by comparing the drain-to-source voltage of the high-side and
low-side MOSFET to a set-point voltage, which is defined by both the internal current source, ITRIP, and the
external resistor connected between the VIN_SENSE and TRIP pins. ITRIP has a typical value of 13 µA at 25°C.
When the drain-to-source voltage exceeds the set-point voltage during low-side conduction, the high-side
current comparator becomes active, and the low-side pulse is extended until this voltage comes back below
the threshold. If the set-point voltage is exceeded during high-side conduction in the following cycle, the
current-limit circuit terminates the high-side driver pulse. Together this action has the effect of decreasing the
output voltage until the under voltage protection circuit is activated to latch both the high-side and low-side
drivers OFF. In the TPS5110, trip current ITRIP also has a temperature coefficient of 3400 ppm/°C in order to
compensate for temperature drift of the MOSFET on-resistance.
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SLVS025B − APRIL 2002 − REVISED JULY 2004
DETAILED DESCRIPTION
OCP for the LDO
To achieve the LDO current limit, a sense resistor must be placed in series with the N-channel MOSFET drain,
connected between the LDO_IN and LDO_CUR pins (see reference schematic). If the voltage drop across this
sense resistor exceeds 50 mV, the output voltage is reduced to approximately 22% of the nominal value, thus
activates UVP to start the FLT latch timer. When the time is up, the LDO_GATE pin is pulled LOW to makes the
LDO regulator shutdown. Note that the SBRC is also latched OFF at the same time since the LDO and the SBRC
share the same FLT capacitor.
overvoltage protection
For over voltage protection (OVP), the TPS5110 monitors the INV and INV_LDO pin voltages. When the INV
or INV_LDO pin voltage is higher than 0.95 V (0.85 V +12%), the OVP comparator output goes low and the FLT
timer starts to charge an external capacitor connected to FLT pin. After a set time, the FLT circuit latches the
high-side and low-side MOSFET drivers and the LDO. The latched state of each block is summarized in Table 2.
The timer-source current for the OVP latch is 125 µA(typ.), and the time-up voltage is 1.185 V (typ.). The OVP
timer is designed to be 50 times faster than the undervoltage protection timer described below.
Table 2. Overvoltage Protection Logic
OVP OCCURS AT
HIGH-SIDE
MOSFET DRIVER
LOW-SIDE
MOSFET DRIVER
LDO
SBRC
LDO
OFF
ON
OFF
OFF
OFF
OFF
undervoltage protection
For under voltage protection (UVP), the TPS5110 monitors the INV and INV_LDO pin voltages. When the INV
or INV_LDO pin voltage is lower than 0.55 V (0.85 V − 35 %), the UVP comparator output goes low, and the
FLT timer starts to charge the external capacitor connected to FLT pin. Also, when the current comparator
triggers the OCP, the UVP comparator detects the under-voltage output and starts the FLT capacitor charge,
too. After a set time, the FLT circuit latches all of the MOSFET drivers to the OFF state. The timer-latch source
current for UVP is 2.3 µA (typ.), and the time-up voltage is also 1.185 V (typ.). The UVP function of the LDO
controller is disabled when voltage across the pass transistor is less than 0.23 V (typ.).
FLT
When an OVP or UVP comparator output goes low, the FLT circuit starts to charge the FLT capacitor. If the FLT
pin voltage goes beyond a constant level, the TPS5110 latches the MOSFET drivers. At this time, the state of
MOSFET is different depending on the OVP alert and the UVP alert, see Table 2. The enable time used to latch
the MOSFET drivers is decided by the value of the FLT capacitor. The charging constant current value depends
on whether it is an OVP alert or a UVP alert as shown in the following equation:
FLTsource current (OVP) + FLTsource current (UVP)
10
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50
SLVS025B − APRIL 2002 − REVISED JULY 2004
DETAILED DESCRIPTION
undervoltage lockout (UVLO)
When the REG5V_IN voltage decreases below about 4 V, the output stages of both the SBRC and the LDO are
turned off. This state is not latched and the operation recovers immediately after the input voltage becomes
higher than the turn-on value again. The typical hysteresis voltage is 100 mV.
UVLO for LDO
The LDO_IN voltage is monitored with a hysteretic comparator. When this voltage is less than 1 V, the UVLO
circuit disables the UVP/OVP comparators that monitor the INV_LDO voltage. In case the SBRC over current
protection is activated prior to that of the LDO’s, this protection function may also be observed.
LDO control
The LDO controller can drive an external N-channel MOSFET. This realizes a fast response as well as an
ultra-low dropout voltage regulator. For example, it is easy to configure both a 1.8-V and a 1.5-V high-current
power supply for core and I/O of modern digital processors, one from the SBRC and the other from the LDO.
The LDO_IN voltage range is from 1.1 V to 3.6 V, and the output voltage is adjustable from 0.9 V to 2.5 V by
an external resistor divider. Gain and phase of the high-speed error amplifier for this LDO control is internally
compensated and is connected to the 0.85-V band-gap reference circuit. The gate driver buffer is supplied by
VIN_SENSE voltage. In the relatively high-output voltage applications, make sure that output voltage plus
threshold voltage of the pass transistor is less than the minimum VIN. More precisely,
V
VIN_SENSE
* 0.7 V w V
THN
)V
LDO_OUT
where VTHN is the threshold voltage of N-channel MOSFET.
The LDO controller is also equipped with OVP, UVP, over current limit and overshoot protection functions.
overshoot protection − LDO
In the event that load current changes from high to low very quickly, the LDO regulator output voltage may start
to overshoot. In order to resist this phenomenon, the LDO controller has an overshoot protection function. If the
LDO regulator output overshoots, the controller draws electrical charge out from LDO_OUT pin to hold it stable.
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11
SLVS025B − APRIL 2002 − REVISED JULY 2004
DETAILED DESCRIPTION
powergood
A single powergood circuit monitors the SBRC output voltage, LDO output voltage and REF5V_IN voltage. The
POWERGOOD pin is an open-drain output. When INV or INV_LDO voltage go beyond +/− 7% of 0.85 V or the
REG5V_IN voltage is lower than 4 V, the POWERGOOD pin is pulled down to the LOW level. POWERGOOD
propagation delay is minimal, 1 µs to 4 µs.
Table 3. Powergood Logic{
STBY
STBY_LDO
0.79 V ≤ VINV ≤ 0.91 V
0.79 V ≤ VINV_LDO ≤ 0.91 V
VREG5V_IN > 4 V
POWER
GOOD
L
L
X
X
X
L
H
L
X
X
X
L
L
H
X
X
X
L
H
H
FALSE
X
X
L
H
H
X
FALSE
X
L
H
H
X
X
FALSE}
L
H
H
TRUE
TRUE
TRUE
H
† X = True OR False
‡ The logic circuit is under normal operation
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT (SHUTDOWN)
vs
JUNCTION TEMPERATURE
2.0
200
1.5
VSTBY = 0 V
VINV = V INV_LDO = VCT = VPWM_SEL= 0 V
ICC − Supply Current − nA
ICC − Supply Current − mA
VLDO_IN = 3.6 V
1.0
0.5
100
0
0
50
100
150
T − Junction Temperature − °C
J
−50
0
50
100
T − Junction Temperature − °C
J
Figure 2
Figure 3
NOTE: VVIN_SENSE = 12 V, VREG5V_IN = 5 V unless otherwise noted.
12
VSTBY_LDO= 0 V
50
0.0
−50
150
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150
SLVS025B − APRIL 2002 − REVISED JULY 2004
TYPICAL CHARACTERISTICS
FLT (OVP) SOURCE CURRENT
vs
JUNCTION TEMPERATURE
FLT (UVP) SOURCE CURRENT
vs
JUNCTION TEMPERATURE
−160
−3.0
−140
−2.5
−120
Current − µA
Current − µA
−2.0
−100
−80
−60
−1.5
−1.0
−40
V
−20
LDO_IN = 3.6 V, V INV = 1.0 V, V FLT
V
−0.5
= 0.5 V
LDO_IN
= 3.6 V,
V INV = 0.5 V, V FLT= 0.5 V
0
0.0
−50
0
50
100
150
−50
0
50
100
150
T − Junction Temperature − °C
J
T − Junction Temperature − °C
J
Figure 5
Figure 4
TRIP CURRENT
vs
JUNCTION TEMPERATURE
LDO_GATE SINK CURRENT
vs
OUTPUT VOLTAGE
2.0
25
ISNK − Sink Current − mA
ITRIP − Trip Current − µA
20
15
10
1.5
1.0
V
0.5
V
5
VTRIP = VVIN_SENSE − 0.1 V
0
−50
INV_LDO = 2.0 V
0
50
LDO_IN
=V
LDO_CUR = 3.3 V
0.0
100
150
TJ − Junction Temperature − °C
0
2
4
Voltage − V
6
8
Figure 7
Figure 6
NOTE: VVIN_SENSE = 12 V, VREG5V_IN = 5 V unless otherwise noted.
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13
SLVS025B − APRIL 2002 − REVISED JULY 2004
TYPICAL CHARACTERISTICS
LDO_GATE SOURCE CURRENT
vs
OUTPUT VOLTAGE
OVER VOLTAGE PROTECTION THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
960
VO − Output Voltage − mV
ISRC − Source Current − mA
−2.0
−1.5
−1.0
V INV_LDO = 0 V,
−0.5
955
950
945
V LDO_IN = V LDO_CUR = 3.3 V
0.0
940
0
2
4
6
8
−50
0
50
100
150
T − Junction Temperature − °C
J
Ouput Voltage − V
Figure 9
Figure 8
OSCILLATOR FREQUENCY
vs
CAPACITANCE
OUTPUT MAXIMUM DUTY CYCLE
vs
JUNCTION TEMPERATURE
88
1000
87
CCT = 44 pF,
V PWM_SEL = V FLT = V LL= V INV = 0 V
Duty Cycle − %
Frequuency − kHz
86
100
85
VREG5V_IN = 4.5 V
84
83
5.0 V
82
5.5 V
TJ = 25 °C
81
80
10
10
50
100
150
200
250
300
350
Capacitance − pF
0
50
100
T − Junction Temperature − °C
J
Figure 10
Figure 11
NOTE: VVIN_SENSE = 12 V, VREG5V_IN = 5 V unless otherwise noted.
14
−50
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150
SLVS025B − APRIL 2002 − REVISED JULY 2004
TYPICAL CHARACTERISTICS
FLT DELAY TIME (OVP)
vs
CAPACITANCE
FLT DELAY TIME (UVP)
vs
CAPACITANCE
100000
VINV = 0.85 to 1.05 V,
TJ = 25 °C
10000
UVP − Delay Time − µs
OVP − Delay Time − µs
10000
100000
1000
100
10
1
VINV = 0.65 to 0.50 V,
TJ = 25 °C
1000
100
10
1
0.1
0.1
10
100
1000
10
10000
100
1000
10000
Capacitance − pF
Capacitance − pF
Figure 12
Figure 13
SOFT-START TIME
vs
CAPACITANCE
LDO CURRENT LIMIT THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
100000
60
LDO − Threshold Voltage − mV
TJ = 25 °C
10000
Time − µs
1000
100
10
50
40
30
20
10
VLDO_IN = 3.3 V, V INV_LDO = 0.5 V
1
0
1
10
100
1000
Capacitance − °C
10000
100000
Figure 14
−50
0
50
100
TJ − Junction Temperature − °C
150
Figure 15
NOTE: VVIN_SENSE = 12 V, VREG5V_IN = 5 V unless otherwise noted.
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15
SLVS025B − APRIL 2002 − REVISED JULY 2004
TYPICAL CHARACTERISTICS
LDO UVLO THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
1.2
VTLH
Threshold Voltage − V
1.0
0.8
VTHL
0.6
0.4
0.2
VINV_LDO = 0.50 V
0.0
−50
0
50
100
150
T − Junction Temperature − °C
J
Figure 16
NOTE: VVIN_SENSE = 12 V, VREG5V_IN = 5 V unless otherwise noted.
APPLICATION INFORMATION
The design shown in this application information is a reference design for a notebook PC application. An
evaluation module (EVM) is available for customer testing and evaluation. This information allows a customer
to fully evaluate the given design using the plug-in EVM shown in Figure17. For subsequent board revisions,
the EVM design can be copied onto the system PCB to shorten the design cycle.
The following key design procedures aid in the design of the notebook PC power supply using TPS5110. An
optional circuit composed of Q04, R16, R22 and R24 can be used to increase temperature coefficient of the
trip current, which is at the top in the page 18.
16
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2
1
2
1
JP03
JP02
3
3
R10
C08
R11
12
11
10
9
8
7
6
5
TPS5110PW
INV_LDO
R23
0 ohm
POWERGOOD
FLT
STBY_LDO
STBY
REF
GND
CT
PWM_SEL
SOFTSTART
FB
LDO_OUT
LDO_GATE
LDO_CUR
LDO_IN
REG5V_IN
VIN_SENSE
TRIP
OUTGND
OUT_d
LL
OUT_u
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R16
R24
13
14
15
16
17
18
19
20
21
22
23
24
R15
0 ohm
C12
R13
4
R22
Q04
NPN_2SC4617
Q03A
R14
8
7
6
5
PWR_GOOD
R09
R08
C07
C06
C05
4
3
LH
C24
4
Q03B
Q02A
4
Q02B
Q01B
R12C
R12B
R12A
4
4
8
7
6
5
2
INV
C13
Q01A
1
2
3
C04
1
D01
8
7
6
5
JP01
C03
R04
U01
R07
0 ohm
1
2
3
R05
R02
R01B
R03
C02
8
7
6
5
3
D02
JP04
1
2
L01
C25
8
7
6
5
3
OUT
4
GND
UA78M05
C16
IN
1
C17
D03
C26
R01A
R15B
C10
C01C
C19
R15A
R15C
C15
C14(DUMMY)
EXGND
EX5V
VO2
VOGND
VO1
VINGND
VIN
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
1
2
3
1
2
3
1
2
3
Figure 17. EVM Typical Design
17
C11
C09
C01B
C01A
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Table 4. EVM Input and Outputs
VIN{
REG5V_IN
Vo1 (SBRC)
Io1 (SBRC)
Vo2 (LDO)
Io2 (LDO)
8 V to 20 V
5V
1.8 V
6A
1.5 V
3A
† Recommended operation voltage for the EVM
output voltage setpoint calculation
The reference voltage and the voltage divider set the output voltage. In the TPS5110, the reference voltage is
0.85 V, and the divider is composed of three resistors in the EVM design that are R01A, R01B and R03 for
switching regulator output; R10, R11 and R09 for LDO regulator output.
V
O
+
R1
V
R2
REF ) V
REF
or R2 +
R1
V
V
REF
*V
REF
O
where R1 is the top resistor (kΩ) (R01A + R01B or R10 + R11); R2 is the bottom resistor (kΩ) (R03 or R09);
VO is the required output voltage (V); VREF is the reference voltage (0.85 V in TPS5110). The value for R1 is
set as a part of the compensation circuit and the value of R2 may be calculated to achieve the desired output
voltage. In the EVM design, the value of R1 was determined as R01A = R01B = 10 kΩ for VO1, and R10 = 6.8 kΩ
and R11 = 820 Ω for VO2 considering stability. For VO1:
R03 + 20 kW 0.85 + 17.89 kW
1.8 * 0.85
Use 18 kΩ.
For VO2:
R09 +
(6.8 kW ) 820) 0.85
+ 9.96 kW
1.5 * 0.85
Use 10 kΩ.
The values of R01A, R01B, R10 and R11 are chosen so that the calculated values of R03 and R09 are those
of standard value resistor and the VO setpoint maintains the highest precision. This can be best accomplished
by combining two resistor values. If a standard value resistor can not be applied such as R10 and R11, use a
value for R10 that is just slightly less than the desired total. A small value resistor in the range of tens or hundreds
of ohms for R11 can then be added to generate the desired final value.
18
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
output inductor selection
The required value for the output-filter inductor can be calculated by using the equation:
L
OUT
+
ǒVIN * VOǓ
k
I
OUT
V
O
VIN
1
f
S
Where LOUT is output filter inductor value (H), VIN is the input voltage (V), Iout is the maximum output current
(A), fS is the switching frequency (Hz). Constant value k, a ratio of ripple current to output current, is typically
in the range 0.2 to 0.3. For VO1, the calculation for the maximum input voltage of 20 V, yields a value for L01
of 3.03 µH, and for minimum input voltage of 8 V, 2.58 µH. For the EVM, a value of 2.8 µH is used for L01.
output inductor ripple current
The output-inductor current can affect not only the efficiency, but also the output voltage ripple. The equation
is exhibited below:
VIN * V
I
RIPPLE
+
O
*I
O
L
ǒRDS(on) ) RIǓ
OUT
V
O
VIN
1
f
S
where IRIPPLE is the peak-to-peak ripple current (A) through the inductor; IO is the output current; RDS(on) is the
on-time resistance of MOSFET (Ω); Rl is the inductor dc resistance (Ω). From the equation, it can be seen that
the current ripple can be adjusted by changing the output inductor value. For the EVM design, the worst-case
output ripple occurs with VIN = 20 V:
Example: VIN = 20 V; VO = 1.8 V; IO = 6 A; RDS(on) = 25 mΩ; Rl = 10 mΩ; Fs = 300 kHz; LOUT = 2.8 µH.
Then, the ripple current IRIPPLE = 1.93 A
output capacitor selection (SBRC)
Selection of the output capacitor is basically dependent on the amount of peak-to-peak ripple voltage allowed
on the output and the ability of the capacitor to dissipate the RMS ripple current. Assuming that the ESR of the
output filter sees the entire inductor-ripple current then:
V
PP
+I
RIPPLE
R
ESR
And a suitable capacitor must be chosen so that the peak-to-peak output ripple is within the limits allowable for
the application.
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
output capacitor RMS current (SBRC)
Assuming the inductor-ripple current totally goes through the output capacitor to ground, the RMS current in
the output capacitor can be calculated as:
I
I
+ RIPPLE
O(rms)
Ǹ12
where IO(rms) is maximum RMS current in the output capacitor (A); IRIPPLE is the peak-to-peak inductor-ripple
current (A).
Example: IRIPPLE = 1.93 A, therefore, IO(rms) = 0.56 A
input capacitor RMS current (SBRC)
Assuming the input current totally goes into the input capacitor to the power ground, the RMS current in the input
capacitor can be calculated as:
I
i(rms)
+
ǸIO2
D
(1 * D) ) 1 D
12
I
RIPPLE
where Ii(rms) is the input RMS current in the input capacitor (A); IO is the output current (A); IRIPPLE is the
peak-to-peak output inductor-ripple current; D is the duty cycle and defined as VO/VI in this case. From the
equation, it can be seen that the highest input RMS current usually occurs at the lowest input voltage, so it is
the worst case design for input capacitor ripple current.
Example: IO = 6 A; D = 22.5 %; IRIPPLE = 1.6 A then, Ii(rms) = 2.5 A
The input capacitors must be chosen so that together they can safely handle the input-ripple current. Depending
on the input filtering and the dc input voltage source, not all the ripple current flows through the input capacitors,
but some may be present on the input leads to the EVM.
soft start
The soft-start timing can be adjusted by selecting the soft-start capacitor value. The equation is;
C
SOFT
+ 2.3
10 −6
T
SOFT
0.85
where C(soft) is the soft-start capacitor (µF) (C04 in EVM design): TSOFT is the start-up time (s).
Example: TSOFT = 5 ms, therefore, CSOFT = 0.0135 µF.
20
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
current protection (SBRC)
The current limit in TPS5110 is set using an internal current source and an external resistor (R13). The current
limit protection circuit compares the drain-to-source voltage of the high-side and low-side drivers with respect
to the set-point voltage. If the voltage up exceeds the limit during high-side conduction, the current-limit circuit
terminates the high-side driver pulse. If the set point voltage is exceeded during low-side conduction, the
low-side pulse is extended through the next cycle. Together this action has the effect of decreasing the output
voltage until the under voltage protection circuit is activated and the fault latch is set and both the high and
low-side MOSFET drivers are shut off. The equation below should be used for calculating the external resistor
value for current protection set point:
R
R
CL
DS(on)
+
ǒ
13
I
Ǔ
I
) RIPPLE
TRIP
2
10 −6
where RCL is the external current limit resistor (R13); RDS(on) is the low-side MOSFET(Q02) on-time resistance.
ITRIP is the required current limit.
Example: RDS(on) = 25 mΩ, ITRIP = 6 A, IRIPPLE = 1.93 A, therefore, RCL = 13.4 kΩ.
It should be noted that RDS(on) of a FET is highly dependent on temperature, so to insure full output at maximum
operating temperature, the value of RDS(on) in the above equation should be adjusted. For maximum stability,
it is recommended that the high-side MOSFET(s) has same, or slightly higher RDS(on) than the low-side
MOSFET(s). If the low-side MOSFET(s) has a higher RDS(on), in certain low duty cycle applications it may be
possible for the device to regulate at an output current higher than that set by the above equation by increasing
the high side conduction time to compensate for the missed conduction cycle caused by the extension of the
previous low-side pulse.
timer latch
The TPS5110 includes fault latch function with a user adjustable timer to latch the MOSFET drivers in case of
a fault condition. When either the OVP or UVP comparator detect a fault condition, the timer starts to charge
FLT capacitor (C07), which is connected with FLT pin 10. The circuit is designed so that for any value of FLT
capacitor, the under-voltage latch time t(uvplatch) is about 50 times larger than the over-voltage latch time
t(ovplatch). The equations needed to calculate the required value of the FLT capacitor for the desired over and
under-voltage latch delay times are:
C
LAT
+ 2.3
10 *6
t
(uvplatch)
1.185
and
C
LAT
+ 125
10 *6
t
(ovplatch)
1.185
where CLAT is the external capacitor, t(uvplatch) is the time from UVP detection to latch. t(ovplatch) is the time from
OVP detection to latch.
For the EVM, t(uvplatch) = 5 ms and t(ovplatch) = 0.1 ms, so CLAT = 0.01 µF
If the voltage on the FLT pin reaches 1.185 V, the fault latch is set, and the MOSFET drivers are set as follows:
under-voltage protection
The under-voltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the
voltage at either pin falls below 65% of the 0.85-V reference, the timer begins to charge the FLT capacitor. If
the fault condition persists beyond the time t(uvplatch), the fault latch is set and both the high side and low-side
drivers, and LDO regulator drivers are forced OFF.
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
short circuit protection
The short circuit protection circuitry uses the UVP circuit to latch the MOSFET drivers. When the current-limit
circuit limits the output current, then the output voltage goes below the target-output voltage and UVP
comparator detects a fault condition as described above.
over voltage protection
The over-voltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage
at either pin rises above 112% of the 0.85-V reference, the timer begins to charge the FLT capacitor. If the fault
condition persists beyond the time t(ovplatch), the fault latch is set and the high-side drivers are forced OFF, while
the low-side drivers are forced ON, and LDO regulator drivers are forced OFF.
CAUTION: Do not set the FLT pin to a lower voltage (or GND) while the device is timing out an OVP
or UVP event. If the FLT pin is manually set to a lower voltage during this time, output overshoot
may occur. The TPS5110 must be reset by grounding STBY and STBY_LDO, or dropping down
REG5V_IN.
disablement of the protection function
If it is necessary to inhibit the protection functions of the TPS5110 for troubleshooting or other purposes, the
OCP, OVP and UVP circuits may be disabled.
•
•
•
OCP(SBRC): Remove the current-limit resistors R13 to disable the current limit function.
OCP(LDO): Short-circuit R12 to disable the current limit function.
OVP, UVP: Grounding the FLT pin can disable OVP and UVP.
output capacitor selection for LDO
To keep stable operation of the LDO, capacitance of more than 33 µF and RESR of more than 30 mΩ are
recommended for the output capacitor.
power MOSFET selection for LDO
Also, to keep stable operation of the LDO, lower input capacitance is recommended for the external power
MOSFET. However, too small input capacitance may lead the feedback loop into unstable region. In such a
case, the gate resistor of several hundred ohms keeps the LDO operation in the stable state.
current protection for LDO
If excess output current flows through sense resistor (R12) and the voltage drop exceeds 50 mV, the output
voltage is reduced to approximately 22% of the nominal value, thus activates UVP to start the FLT latch timer.
When the set current is 4 A, the value of R12 is 12.5 mΩ.
22
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
layout guidelines
Good power supply results only occur when care is given to proper design and layout. Layout affects noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milli-amps to tens of amps, good power supply layout is much more difficult than most general
PCB designs. The general design should proceed from the switching node to the output, then back to the driver
section and, finally, parallel the low-level components. Below are specific points to consider before the layout
of a TPS5110 design begins.
•
•
•
•
A four-layer PCB design is recommended for design using the TPS5110. For the EVM design, the top
layer contains the interconnection to the TPS5110, plus some additional signal traces. Layer 2 is fully
devoted to the DRVGND plane. Layer 3 mainly has wide VIN and VO1 pattern. The bottom layer is
almost devoted to other GND plane including ANAGND, and the rest is to wide signal trace for VO2.
All sensitive analog components such as INV, REF, CT, GND, FLT and SOFTSTART should be
reference to ANAGND.
Ideally, all of the area directly under the TPS5110 chip should also be ANAGND.
ANAGND and DRVGND should be isolated as much as possible, with a single point connection
between them.
TPS5110PW
1
INV
2
FB
LH
24
OUT_u
23
3
SOFTSTART
V O1
LL
22
4
PWM_SEL
OUT_d
21
5
CT
6
GND
7
REF
8
STBY
OUTGND
ANAGND
20
DRVGND
9
STBY_LDO
TRIP
19
V OGND
VIN_SENSE
18
VIN
REG5V_IN
17
LDO_IN
16
EX5V
10
FLT
LDO_CUR
15
11
POWERGOOD
LDO_GATE
14
INV_LDO
13
12
LDO_OUT
V O2
UDG−02069
Figure 18. Four-Layer PCB Diagram
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23
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
low-side MOSFET(s)
•
•
•
•
The source of low-side MOSFET(s) should be referenced to DRVGND, otherwise ANAGND is subject
to the noise of the outputs.
DRVGND should be connected to the main ground plane close to the source of the low-side FET.
OUTGND should be placed close to the source of low-side MOSFET(s).
The Schottky diode anode, the returns for the high-frequency bypass capacitor for the MOSFETs, and
the source of the low-side MOSFET(s) traces should be routed as close together as possible.
TPS5110PW
1
INV
2
FB
LH
24
OUT_u
23
3
SOFTSTART
V O1
LL
22
4
PWM_SEL
5
CT
6
GND
7
REF
8
STBY
OUT_d
21
OUTGND
ANAGND
9
TRIP
STBY_LDO
20
DRVGND
19
V OGND
VIN_SENSE
18
VIN
REG5V_IN
17
LDO_IN
16
EX5V
10
FLT
LDO_CUR
15
11
POWERGOOD
LDO_GATE
14
INV_LDO
13
12
LDO_OUT
V O2
UDG−02070
Figure 19. Low-Side MOSFETs Diagram
24
www.ti.com
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
connections
•
•
Connections from the drivers to the gate of the power MOSFETs should be as short and wide as
possible to reduce stray inductance. This becomes more critical if external gate resistors are not being
used. In addition, as for the current limit noise issue, use of a gate resistor on the high-side MOSFET(s)
considerably reduce the noise at the LL node, improving the performance of the current limit function.
The connection from LL to the power MOSFETs should be as short and wide as possible.
TPS5110PW
1
INV
2
FB
LH
24
OUT_u
23
3
SOFTSTART
V O1
LL
22
4
PWM_SEL
5
CT
6
GND
7
REF
8
STBY
OUT_d
21
OUTGND
ANAGND
9
STBY_LDO
TRIP
20
DRVGND
19
V OGND
VIN_SENSE
18
VIN
REG5V_IN
17
LDO_IN
16
EX5V
10
FLT
LDO_CUR
15
11
POWERGOOD
LDO_GATE
14
INV_LDO
13
12
LDO_OUT
V O2
UDG−02071
Figure 20. Connections From the Drivers to the Gate Diagram
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25
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
bypass capacitor
•
•
•
The bypass capacitor for VIN_SENSE should be placed close to the TPS5110.
The bulk-storage capacitors across VIN should be placed close to the power MOSFETs.
High-frequency bypass capacitors should be placed in parallel with the bulk capacitors and connected
close to the drain of the high-side MOSFET(s) and to the source of the low-side MOSFET(s).
For aligning phase between the drain of high-side MOSFET(s) and the TRIP pin, and for noise
reduction, a 0.1-µF capacitor should be placed in parallel with the trip resistor.
TPS5110PW
1
INV
2
FB
LH
24
OUT_u
23
3
SOFTSTART
4
PWM_SEL
V O1
LL
22
OUT_d
21
5
CT
6
GND
7
REF
8
STBY
OUTGND
ANAGND
9
TRIP
STBY_LDO
20
DRVGND
19
V OGND
VIN_SENSE
18
VIN
REG5V_IN
17
LDO_IN
16
EX5V
10
FLT
LDO_CUR
15
11
POWERGOOD
LDO_GATE
14
INV_LDO
13
12
LDO_OUT
V O2
UDG−02072
Figure 21. Bypass Capacitor Diagram
26
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
bootstrap capacitor
•
•
•
The bootstrap capacitor (connected from LH to LL) should be placed close to the TPS5110.
LH and LL should be routed close to each other to minimize differential-mode noise coupling to these
traces.
LH and LL should not be routed near the control pin area (ex. INV, FB, REF, etc.).
TPS5110PW
1
INV
2
FB
LH
24
OUT_u
23
3
SOFTSTART
4
PWM_SEL
V O1
LL
22
OUT_d
21
5
CT
6
GND
7
REF
8
STBY
OUTGND
ANAGND
9
TRIP
STBY_LDO
20
DRVGND
19
V OGND
VIN_SENSE
18
VIN
REG5V_IN
17
LDO_IN
16
EX5V
10
FLT
LDO_CUR
15
11
POWERGOOD
LDO_GATE
14
INV_LDO
13
12
LDO_OUT
V O2
UDG−02073
Figure 22. Bootstrap Capacitor Diagram
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27
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
output voltage
•
•
•
•
•
The output voltage sensing trace should be isolated by either ground plane.
The output voltage sensing trace should not be placed under the inductors on same layer.
The feedback components should be isolated from output components, such as, MOSFETs, inductors,
and output capacitors. Otherwise the feedback signal line is susceptible to output noise.
The resistors for set up output voltage should be referenced to ANAGND.
The INV trace should be as short as possible.
TPS5110PW
1
INV
2
FB
LH
24
OUT_u
23
3
SOFTSTART
V O1
LL
22
4
PWM_SEL
5
CT
6
GND
7
REF
8
STBY
OUT_d
21
OUTGND
ANAGND
9
STBY_LDO
TRIP
20
DRVGND
19
V OGND
VIN_SENSE
18
VIN
REG5V_IN
17
LDO_IN
16
EX5V
10
FLT
LDO_CUR
15
11
POWERGOOD
LDO_GATE
14
INV_LDO
13
12
LDO_OUT
V O2
UDG−02074
Figure 23. Output Voltage Diagram
28
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
AUTO SKIP MODE EFFICIENCY
vs
OUTPUT CURRENT
PWM MODE EFFICIENCY
vs
OUTPUT CURRENT
100
100
VIN = 8 V
VIN = 20 V
80
Efficiency − %
Efficiency − %
80
VIN = 12 V
60
40
VIN = 12 V
VIN = 8 V
60
40
VIN = 20 V
20
20
f OSC = 300 kHz,
V
O 1 = 1.8 V
VO1 = 1.8 V
0
0
0.01
1
0.1
10
0.01
1
0.1
Output Current − A
10
Output Current − A
Figure 24
Figure 25
SBRC OUTPUT LINE REGULATION
LDO OUTPUT LINE REGULATION
1.802
1.492
IO1 = 6 A
VO1 = V LDO_IN= 1.8 V
1.801
VO − Output Voltage − V
VO − Output Voltage − V
IO 2 = 3 A
1.800
1.799
1.491
1.490
1.489
1.798
1.488
5
10
15
20
15
VIN − Input Voltage − V
5
10
15
20
15
VIN − Input Voltage − V
Figure 26
Figure 27
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29
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
SBRC OUTPUT LOAD REGULATION
LDO OUTPUT LOAD REGULATION
1.510
1.810
Output Voltage − V
Output Voltage − V
1.505
VIN = 12 V
1.805
1.800
1.795
1.790
1.500
1.495
1.490
1.785
1.485
1.780
1.480
0
1
2
3
4
5
VO 1 = V LDO_IN = 1.8 V
0.0
6
0.5
Figure 29
Figure 28
SBRC OUTPUT VOLTAGE RIPPLE
SBRC OUTPUT VOLTAGE RIPPLE
IOUT = 0 A
20 mV/div.
20 mV/div.
4A
I OUT= 0 A
20 mV/div.
4A
6A
6A
VIN = 4.5 V, V O1 = 1.8 V
30
1.5
Output Current − A
Output Current − A
20 mV/div.
1.0
VIN = 20 V, V O1 = 1.8 V
t − time − 1 µs/div.
t − time − 1 µs/div.
Figure 30
Figure 31
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2.0
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
LDO OUTPUT VOLTAGE RIPPLE
LDO OUTPUT VOLTAGE RIPPLE
IOUT = 0 A
IOUT = 0 A
1A
10 mV/div.
10 mV/div.
1A
3A
3A
VIN = 20 V, VLDO_IN = 1.8 V, V O 2 = 1.5 V
VIN = 8 V, VLDO_IN = 1.8 V, V O 2 = 1.5 V
t − time − 1 µs/div.
t − time − 1 µs/div.
Figure 32
Figure 33
SBRC LOAD TRANSIENT RESPONSE
SBRC LOAD TRANSIENT RESPONSE
VOUT
VOUT
20 mV/div.
20 mV/div.
IOUT
2 A/div.
IOUT
2 A/div.
VIN = 8 V, V
O
1 = 1.8 V
0A
100 ms/div.
t − time − 100 µs/div.
VIN = 20 V, V
O 1 = 1.8 V
0A
t − time − 100 µs/div.
Figure 34
Figure 35
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31
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
LDO LOAD TRANSIENT RESPONSE
SBRC-LDO SIMULTANEOUS START-UP
VOUT
0.5 V/div.
50 mV/div.
VO1(SBRC)
IOUT
1 A/div.
VO2(LDO)
0A
O
2 = 1.5 V
t − time − 1 µs/div.
t − time − 100 µs/div.
Figure 36
Figure 37
SBRC GAIN AND PHASE
LDO GAIN AND PHASE
80
240
Phase Margin = 48 Degree
Vo1 = 1.8 V, Io1 = 6 A
120
20
60
0
−20
VIN = 12 V
−40
100
1k
10 k
100 k
Gain
−20
−120
−40
100
0
−60
VLDO_IN = 1.8 V
−120
1k
10 k
100 k
Frequency − Hz
Figure 38
32
60
−60
Frequency − Hz
Figure 39
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120
20
0
1M
180
Phase
40
0
Gain
240
Phase Margin = 81 Degree
Vo2 = 1.5 V, Io2 = 3 A
60
Gain − dB
Phase
40
Gain − dB
180
Phase − Degree
60
80
1M
Phase − Degree
VIN = 12 V, VLDO_IN = 1.8 V, V
0V
I O1 = 4 A, I
2=3A
O
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Table 5. Bill of Materials
Reference
Capacitor
Qty
1
SP−VCAP, 22 µF, 27 V, 8.3x8.3mm
C02, C03
2
Ceramic, 4700 pF, 10%, 2.0x1.25mm
C05
1
Ceramic, 47 pF, 5%, 2.0x1.25mm
C04, C07
2
Ceramic, 0.01 µF, 2.0x1.25mm
C09
1
SPCAP, 47 µF, 6.3 V, 7.3x4.3mm
C01B, C06, C11,
C12, C13, C19
6
Ceramic, 0.1 µF, 2.0x1.25mm
C15
1
C16, C17
2
C24
1
C01C, C08, C10,
Manufacturer
Part Number
Panasonic
EEFWA27220P
Panasonic
EEFCD0J470R
2.2 µF, 35 V, 3.2x2.5mm
Taiyo-Yuden
GMK325BJ225MN−B
SPCAP, 150 µF, 2.5 V, 7.4x4.3mm
Panasonic
EEFUD0E151R
Ceramic, 10 µF, 25 V
Taiyo-Yuden
TMK325BJ106MM
Susumu
RL1220T−R022−J
Removed
C14, C25, C26
Resistor
Description
C01A
R01A, R01B, R09
1
10 kΩ, 1%, 2.0x1.25mm
R02
1
1.2 kΩ, 2.0x1.25mm
R03
1
18 kΩ, 1%, 2.0x1.25mm
R04
1
4.7 kΩ, 2.0x1.25mm
R05, R08
2
100 kΩ, 2.0x1.25mm
R10
1
6.8 kΩ, 1%, 2.0x1.25mm
R11
1
820 Ω, 1%, 2.0x1.25mm
R12A, R12B
2
22 m, 5%, 2.0x1.25mm
R13
1
10 kΩ, 2.0x1.25mm
R14
1
10 Ω, 2.0x1.25mm
R12C, R15A, R15B,
Removed
R15C, R16, R22, R24
Inductor
L01
1
2.8 µH, 12.5X12.5mm
Sumida
CEP125−2R8MC−H
Diode
D01
1
2.5x1.25mm
Hitachi
HSU119
Rohm
RB160L−40
D02
Nch MOSFET
Removed
D03
1
2.6x4.5mm
Q01B
1
30 V, SOT−8
Q02B
1
30 V, SOT−8
Q03A
1
30 V, SOT−8
Q01A, Q02A,
Q03B, Q04
FDS6612A
Fairchild
FDS6690S*
FD6612A
Removed
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33
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Bill of Materials (continued)
IC
IC01
1
IC02
SSOP−24
TI
TPS5110PW
Removed
Jumper
Header, straight, 2-pin
JP01
1
JP02, JP03
2
JP04
1
22−28−4023
Morex
Jumper, shunt
SW, 7x4.5mm
15−29−1025
Nikkai
G−12AP
Header, straight, 3-pin
Contact
22−28−4033
Morex
Jumper, shunt
15−29−1025
EX5V, EXGND
4
VIN, VINGND
VO1, VO2, VOGND
Phoenix
3
MKDS1.5/3−5.08
NOTE: Since the FDS6690S (Q02B) includes an integrated Schottky diode, D02 can be removed.
test setup
A
VIN
+
Power
V
Supply
VINGND
−
A
VO1
+
SBRC
V
Load
−
TPS5110
VOGND
EVM
−
LDO
V
VO2
Load
A
+
−
EXGND
5V
Power
V
EX5V
+
Figure 40. Schematic Diagram of the Test Setup
34
MKDS1.5/2−5.08
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Supply
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Figure 41. EVM Board Top Layer
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35
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Figure 42. EVM Board Second Layer
36
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SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Figure 43. EVM Board Third Layer
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37
SLVS025B − APRIL 2002 − REVISED JULY 2004
APPLICATION INFORMATION
Figure 44. EVM Board Bottom Layer
38
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PACKAGE OPTION ADDENDUM
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14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS5110PW
ACTIVE
TSSOP
PW
24
60
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PS5110
Samples
TPS5110PWR
ACTIVE
TSSOP
PW
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PS5110
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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