TPS51216MRUKREP

TPS51216-EP SLUSCA7A – NOVEMBER 2015 – REVISED JULY 2022 TPS51216-EP Complete DDR2, DDR3 and DDR3L Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered Reference 1 Features 3 Description • The TPS51216-EP provides a complete power supply for DDR2, DDR3 and DDR3L memory systems in the lowest total cost and minimum space. It integrates a synchronous buck regulator controller (VDDQ) with a 2-A sink/source tracking LDO (VTT) and buffered low noise reference (VTTREF). The TPS51216-EP employs D-CAP™ mode coupled with 300 kHz/400 kHz frequencies for ease-of-use and fast transient response. The VTTREF tracks VDDQ/2 within excellent 0.8% accuracy. The VTT, which provides 2-A sink/source peak current capabilities, requires only 10-μF of ceramic capacitance. In addition, a dedicated LDO supply input is available. • • • • Synchronous buck controller (VDDQ) – Conversion voltage range: 3 to 28 V – Output voltage range: 0.7 to 1.8 V – 0.8% VREF accuracy – D-CAP™ mode for fast transient response – Selectable 300-kHz/400-kHz switching frequencies – Optimized efficiency at light and heavy loads with auto-skip function – Supports soft-off in S4/S5 states – OCL/OVP/UVP/UVLO protections – Powergood output 2-A LDO (VTT), buffered reference (VTTREF) – 2-A (peak) sink and source current – Requires only 10-μF of ceramic output capacitance – Buffered, low noise, 10-mA VTTREF output – 0.8% VTTREF, 20-mV VTT accuracy – Support high-z in S3 and soft-off in S4/S5 Thermal shutdown 20-Pin, 3 mm × 3 mm, WQFN Package Supports Defense, Aerospace, and Medical Applications – Controlled baseline – One assembly/test site – One fabrication site – Available in military (–55°C to 125°C) temperature range 1 – Extended product life cycle – Extended product-change notification – Product traceability The TPS51216-EP provides rich useful functions as well as excellent power supply performance. It supports flexible power state control, placing VTT at high-Z in S3 and discharging VDDQ, VTT, and VTTREF (soft-off) in S4/S5 state. Device Information PART NUMBER(1) TPS51216-EP (1) WQFN (20) BODY SIZE (NOM) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. VIN 5VIN PGND 2 Applications • • PACKAGE PGND TPS51216 VBST 15 12 V5IN S3 17 S3 S5 16 S5 VDDQ DRVH 14 SW 13 DRVL 11 6 VREF PGND 10 PGOOD 20 DDR2/DDR3/DDR3L memory power supplies SSTL_18, SSTL_15, SSTL_135, and HSTL termination 8 REFIN 7 GND 19 MODE 18 TRIP AGND VDDQSNS 9 VLDOIN 2 VTT 3 VTTSNS 1 VTTGND 4 VTTREF 5 Powergood VTT VTTREF AGND PGND UDG-10138 Application Diagram 1 Additional temperature ranges available - contact factory An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS51216-EP www.ti.com SLUSCA7A – NOVEMBER 2015 – REVISED JULY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Description (continued).................................................. 3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings........................................ 5 7.2 ESD Ratings............................................................... 5 7.3 Recommended Operating Conditions.........................6 7.4 Thermal Information....................................................6 7.5 Electrical Characteristics.............................................7 7.6 Typical Characteristics.............................................. 10 8 Detailed Description......................................................15 8.1 Overview................................................................... 15 8.2 Functional Block Diagram......................................... 15 8.3 Feature Description...................................................15 8.4 Device Functional Modes..........................................18 9 Application and Implementation.................................. 19 9.1 Application Information............................................. 19 9.2 Typical Application.................................................... 22 10 Power Supply Recommendations..............................25 11 Layout........................................................................... 26 11.1 Layout Guidelines................................................... 26 11.2 Layout Example...................................................... 27 12 Device and Documentation Support..........................28 12.1 Receiving Notification of Documentation Updates..28 12.2 Support Resources................................................. 28 12.3 Trademarks............................................................. 28 12.4 Electrostatic Discharge Caution..............................28 12.5 Glossary..................................................................28 13 Mechanical, Packaging, and Orderable Information.................................................................... 28 4 Revision History Changes from Revision * (November 2015) to Revision A (July 2022) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated resistor numbers in Equation 7 to match description......................................................................... 23 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS51216-EP TPS51216-EP www.ti.com SLUSCA7A – NOVEMBER 2015 – REVISED JULY 2022 5 Description (continued) Programmable OCL with low-side MOSFET RDS(on) sensing, OVP/UVP/UVLO and thermal shutdown protections are also available. The TPS51216-EP is available in a 20-pin, 3 mm × 3 mm, WQFN package and is specified for junction temperature from –55°C to 125°C. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS51216-EP 3 TPS51216-EP www.ti.com SLUSCA7A – NOVEMBER 2015 – REVISED JULY 2022 PGOOD MODE TRIP S3 S5 6 Pin Configuration and Functions 20 19 18 17 16 VTTSNS 1 15 VBST VLDOIN 2 14 DRVH VTT 3 13 SW VTTGND 4 12 V5IN VTTREF 5 11 DRVL 8 GND REFIN 9 10 PGND 7 VDDQSNS 6 VREF Thermal Pad Figure 6-1. RUK Package 20-Pin WQFN Top View Table 6-1. Pin Functions PIN 4 I/O DESCRIPTION NAME NO. DRVH 14 DRVL GND MODE 19 I PGND 10 — Gate driver power ground. RDS(on) current sensing input (+). PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range. REFIN 8 I Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for stable operation. SW 13 S3 17 I S3 signal input. (See Table 8-1.) S5 16 I S5 signal input. (See Table 8-1.) TRIP 18 I Connect resistor to GND to set OCL at VTRIP / 8. Output 10-μA current at room temperature, TC = 4700 ppm/°C. VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin. VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF. VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application. VREF 6 O 1.8-V reference output. VTT 3 O VTT 2-A LDO output. Need to connect 10 μF or larger capacitance for stability. VTTGND 4 — Power ground for VTT LDO. VTTREF 5 O Buffered VTT reference output. Need to connect 0.22 μF or larger capacitance for stability. VTTSNS 1 I VTT output voltage feedback. V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers. Thermal pad — — O High-side MOSFET gate driver output. 11 O Low-side MOSFET gate driver output. 7 — Signal ground. Connect resistor to GND to configure switching frequency and discharge mode. (See Table 8-2.) I/O High-side MOSFET gate driver return. RDS(on) current sensing input (–). Connect to GND Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS51216-EP TPS51216-EP www.ti.com SLUSCA7A – NOVEMBER 2015 – REVISED JULY 2022 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX VBST –0.3 36 VBST(3) –0.3 6 –5 30 VLDOIN, VDDQSNS, REFIN –0.3 3.6 VTTSNS –0.3 3.6 PGND, VTTGND –0.3 0.3 V5IN, S3, S5, TRIP, MODE –0.3 6 SW Input voltage(2) DRVH Output voltage(2) –5 36 DRVH(3) –0.3 6 DRVH(3) (duty cycle < 1%) –2.5 6 VTTREF, VREF –0.3 3.6 VTT –0.3 3.6 DRVL –0.3 6 DRVL (duty cycle < 1%) –2.5 6 PGOOD UNIT V V –0.3 6 Junction temperature, TJ –55 135 °C Storage temperature, Tstg –55 150 °C (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. Voltage values are with respect to the SW terminal. 7.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC V(ESD) (1) (2) Electrostatic discharge JS-001(1) Charged-device model (CDM), per JEDEC specification JESD22C101(2) UNIT ±2000 ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS51216-EP 5 TPS51216-EP www.ti.com SLUSCA7A – NOVEMBER 2015 – REVISED JULY 2022 7.3 Recommended Operating Conditions MIN Supply voltage MAX V5IN 4.5 5.5 VBST –0.1 33.5 VBST(2) –0.1 5.5 -3 28 SW Input voltage range NOM SW(1) –4.5 28 VLDOIN, VDDQSNS, REFIN –0.1 3.5 VTTSNS –0.1 3.5 PGND, VTTGND –0.1 0.1 S3, S5, TRIP, MODE –0.1 5.5 –3 33.5 DRVH DRVH(2) –0.1 5.5 DRVH(1) –4.5 33.5 VTTREF, VREF –0.1 3.5 VTT –0.1 3.5 DRVL –0.1 5.5 PGOOD –0.1 5.5 TJ Operating junction temperature –55 125 (1) (2) This voltage should be applied for less than 30% of the repetitive period. Voltage values are with respect to the SW terminal. Output voltage range UNIT V V V °C 7.4 Thermal Information TPS51216-EP THERMAL METRIC(1) RUK (WQFN) UNIT 20 PINS RθJA Junction-to-ambient thermal resistance 94.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 58.1 °C/W RθJB Junction-to-board thermal resistance 64.3 °C/W ψJT Junction-to-top characterization parameter 31.8 °C/W ψJB Junction-to-board characterization parameter 58.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 5.9 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS51216-EP TPS51216-EP www.ti.com SLUSCA7A – NOVEMBER 2015 – REVISED JULY 2022 7.5 Electrical Characteristics TJ = –55°C to 125°C, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE = 0 V, VS3 = VS5 = 5 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT IV5IN(S0) V5IN supply current, in S0 TJ = 25°C, No load, VS3 = VS5 = 5 V 590 IV5IN(S3) V5IN supply current, in S3 TJ = 25°C, No load, VS3 = 0 V, VS5 = 5 V 500 μA IV5INSDN V5IN shutdown current TJ = 25°C, No load, VS3 = VS5 = 0 V 1 μA IVLDOIN(S0) VLDOIN supply current, in S0 TJ = 25°C, No load, VS3 = VS5 = 5 V 5 μA IVLDOIN(S3) VLDOIN supply current, in S3 TJ = 25°C, No load, VS3 = 0 V, VS5 = 5 V 5 μA IVLDOINSDN VLDOIN shutdown current TJ = 25°C, No load, VS3 = VS5 = 0 V 5 μA μA VREF OUTPUT VVREF Output voltage IVREFOCL Current limit IVREF = 30 μA, TJ = 25°C 0 μA ≤ IVREF