TPS51217
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SLUS947B – JUNE 2009 – REVISED APRIL 2012
HIGH PERFORMANCE, SINGLE SYNCHRONOUS STEP-DOWN
CONTROLLER FOR NOTEBOOK POWER SUPPLY
Check for Samples: TPS51217
FEATURES
DESCRIPTION
•
•
•
•
•
The TPS51217 is a small-sized single buck controller
with adaptive on-time D-CAP™ mode. The device is
suitable for low output voltage, high current, PC
system power rail and similar point-of-load (POL)
power supply in digital consumer products. A small
package with minimal pin-count saves space on the
PCB, while a dedicated EN pin and pre-set frequency
minimize design effort required for new designs. The
skip-mode at light load condition, strong gate drivers
and low-side FET RDS(on) current sensing supports
low-loss and high efficiency, over a broad load range.
The TRAN pin provides freedom of masking
overvoltage protection, undervoltage protection and
power-good signal during the transition period of
dynamic output voltage change for modern GPU
power supply applications. The conversion input
voltage which is the high-side FET drain voltage
ranges from 3 V to 28 V and the output voltage
ranges from 0.6 V to 2.6 V. The device requires an
external 5-V supply. The TPS51217 is available in a
10-pin SON package specified from –40°C to 85°C.
1
2
•
•
•
•
•
•
•
•
•
•
•
Wide Input Voltage Range: 3 V to 28 V
Output Voltage Range: 0.6 V to 2.6 V
Wide Output Load Range: 0 to 20A+
Built-in 0.5% 0.6 V Reference
D-CAP™ Mode with 100-ns Load Step
Response
Adaptive On Time Control Architecture with
Fixed 340kHz Operation
Dynamic Output Voltage Change Capability
4700 ppm/°C RDS(on) Current Sensing
Internal 0.9-ms Voltage Servo Softstart
Pre-Charged Start-up Capability
Built-in Output Discharge
Power Good Output
Integrated Boost Switch
Built-in OVP/UVP/OCP
Thermal Shutdown (Non-latch)
SON-10 (DSC) Package
APPLICATIONS
•
•
•
Notebook Computers
I/O Supplies
System Power Supplies
TYPICAL APPLICATION CIRCUIT
VIN
V5IN
TPS51217
1 PGOOD VBST 10
2 TRIP
EN
VID1
VID0
3 EN
4 VFB
DRVH 9
SW 8
VOUT
V5IN 7
5 TRAN
DRVL 6
GND
VOUT_GND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2012, Texas Instruments Incorporated
TPS51217
SLUS947B – JUNE 2009 – REVISED APRIL 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
TA
PACKAGE
–40°C to 85°C
Plastic SON PowerPAD
ORDERING DEVICE NUMBER
PINS
OUTPUT SUPPLY
MINIMUM
QUANTITY
TPS51217DSCR
10
Tape and reel
3000
TPS51217DSCT
10
Mini reel
250
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
Input voltage range (2)
MIN
MAX
VBST
–0.3
37
VBST (3)
–0.3
7
–5
30
SW
V5IN, EN, TRIP, VFB, TRAN
–0.3
7
–5
37
DRVH (3)
–0.3
7
DRVH (3), pulse wiidth < 20 ns
–2.5
7
DRVL
–0.5
7
DRVL, pulse width < 20 ns
–2.5
7
PGOOD
–0.3
DRVH
Output voltage range (2)
(1)
(2)
(3)
V
V
7
Junction temperature range, TJ
Storage temperature range, TSTG
UNIT
–55
150
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
Voltage values are with respect to the SW terminal.
DISSIPATION RATINGS
2-oz. trace and copper pad with solder.
(1)
2
PACKAGE
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
10 pin DSC (1)
1.54 W
15 mW/°C
0.62 W
Enhanced thermal conductance by thermal vias is used beneath thermal pad as shown in Land Pattern information.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
Input voltage range
6.5
VBST
–0.1
34.5
SW
–1
28
SW (1)
–4
28
VBST (2)
–0.1
6.5
EN, TRIP, VFB, TRAN
–0.1
6.5
–1
34.5
DRVH (1)
-4
34.5
DRVH (2)
–0.1
6.5
DRVL
–0.3
6.5
PGOOD
–0.1
6.5
–40
85
Operating free-air temperature, TA
(1)
(2)
MAX
4.5
DRVH
Output voltage range
TYP
V5IN
UNIT
V
V
V
°C
This voltage should be applied for less than 30% of the repetitive period.
Voltage values are with respect to the SW terminal.
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, V5IN = 5V. (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
320
500
μA
1
μA
SUPPLY CURRENT
I(V5IN)
V5IN supply current
V5IN current, TA = 25°C, No Load,
V(EN) = 5 V, V(VFB) = 0.63 V
ISD(V5IN)
V5IN shutdown current
V5IN current, TA = 25°C, No Load, V(EN) = 0 V
INTERNAL REFERENCE VOLTAGE
VFB voltage, CCM condition (1)
V(VFB)
I(VFB)
VFB regulation voltage
VFB input current
0.6000
V
TA = 25°C, skip mode
0.6000
0.6030
0.6060
TA = 0°C to 85°C, skip mode
0.5974
0.6030
0.6086
TA = –40°C to 85°C, skip mode
0.5960
0.6030
0.6100
0.01
0.2
V(VFB) = 0.63 V, TA = 25°C, skip mode
V
μA
OUTPUT DISCHARGE
IDischg
Output discharge current from
SW pin
V(EN) = 0 V, V(SW) = 0.5 V
5
13
mA
OUTPUT DRIVERS
R(DRVH)
DRVH resistance
R(DRVL)
DRVL resistance
tD
Dead time
Source, I(DRVH) = –50 mA
1.5
3
Sink, I(DRVH) = 50 mA
0.7
1.8
Source, I(DRVL) = –50 mA
1.0
2.2
Sink, I(DRVL) = 50 mA
0.5
1.2
DRVH-off to DRVL-on
7
17
30
DRVL-off to DRVH-on
10
22
35
Ω
ns
BOOT STRAP SWITCH
V(FBST)
Forward voltage
V(V5IN-VBST), IF = 10 mA, TA = 25°C
Ilkg
VBST leakage current
V(VBST) = 34.5 V, V(SW) = 28 V, TA = 25°C
0.1
0.2
V
0.01
1.5
μA
260
400
DUTY AND FREQUENCY CONTROL
tOFF(min)
Minimum off-time
TA = 25°C
tON(min)
Minimum on-time
VIN = 28 V, VOUT = 0.6 V, TA = 25°C (1)
fSW
Switching frequency
TA = 25°C (2)
(1)
(2)
150
86
312
340
368
ns
kHz
Specified by design. Not production tested.
Not production tested. Test condition is VIN = 8 V, VOUT = 1.1 V, IOUT = 10A using the application circuit shown in Figure 26.
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ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, V5IN = 5V. (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFTSTART
tSS
Internal soft-start time
From V(EN) = high to VOUT = 95%
0.9
ms
POWERGOOD
V(THPG)
PG threshold
PG in from lower
92.5%
95%
97.5%
PG in from higher
107.5%
110%
112.5%
2.5%
5%
7.5%
3
6
0.8
1
PG hysteresis
I(PG)max
PG sink current
V(PGOOD) = 0.5 V
tPGDEL
PG delay
Delay for PG in
mA
1.2
ms
LOGIC THRESHOLD AND SETTING CONDITIONS
V(EN)
EN voltage
I(EN)
EN input current
V(TRAN)
TRAN voltage
Enable
1.8
Disable
0.5
V(EN) = 5V
1.0
TRAN open
1.83
1.88
1.93
Mask PG, OVP and UVP, high side
2.03
2.08
2.13
Mask PG, OVP and UVP, low side
1.62
1.67
1.72
Hysteresis
I(TRAN)
TRAN input current
V
μA
V
0.05
V(TRAN) = 5 V, TA = 25°C
2.5
3.8
5
V(TRAN) = 0 V, TA = 25°C
–5
–3.8
–2.5
9
10
11
μA
PROTECTION: CURRENT SENSE
TRIP source current
V(TRIP) = 1V, TA = 25°C
TRIP current temperature
coefficient
On the basis of 25°C
V(TRIP)
Current limit threshold setting
range
V(TRIP-GND) voltage
0.2
V(TRIP) = 3 V
355
375
395
VOCL
Current limit threshold
V(TRIP) = 1.6 V
185
200
215
V(TRIP) = 0.2 V
17
25
33
V(TRIP) = 3 V
–395
–375
–355
V(TRIP) = 1.6 V
–215
–200
–185
V(TRIP) = 0.2 V
–33
–25
–17
3
15
I(TRIP)
VOCLN
Negative current limit threshold
VAZCADJ
Adaptive zero cross adjustable
range
4700
Positive
Negative
μA
ppm/°C
3
V
mV
mV
mV
–15
–3
115%
120%
125%
65%
70%
75%
0.8
1
1.2
ms
1
1.2
1.4
ms
Wake up
4.20
4.38
4.50
Shutdown
3.7
3.93
4.1
PROTECTION: UVP AND OVP
V(OVP)
OVP trip threshold
OVP detect
tOVPDEL
OVP propagation delay time
50-mV overdrive
V(UVP)
Output UVP trip threshold
UVP detect
tUVPDEL
Output UVP propagation delay
tUVPEN
Output UVP enable delay time
μs
1
From Enable to UVP workable
UVLO
V5IN UVLO threshold
V
THERMAL SHUTDOWN
TSDN
(3)
4
Thermal shutdown threshold
Shutdown temperature
(3)
Hysteresis (3)
145
10
°C
Specified by design. Not production tested.
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DEVICE INFORMATION
DSC PACKAGE
(TOP VIEW)
PGOOD
1
10
VBST
TRIP
2
9
DRVH
EN
3
TPS51217DSC
8
SW
VFB
4
GND
7
V5IN
TRAN
5
6
DRVL
Thermal pad is used as an active terminal of GND.
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
DRVH
9
O
High-side MOSFET driver output. The SW node referenced floating driver. The gate drive voltage is
defined by the voltage across VBST to SW node bootstrap flying capacitor
DRVL
6
O
Synchronous MOSFET driver output. The GND referenced driver. The gate drive voltage is defined by
V5IN voltage.
EN
3
I
SMPS enable pin. Short to GND to disable the device.
Thermal
Pad
I
Ground
PGOOD
1
O
Power Good window comparator open drain output. Pull up with resistor to 5 V or appropriate signal
voltage. Continuous current capability is 1 mA. PGOOD goes high 1 ms after VFB becomes within
specified limits. Power bad, or the terminal goes low, after a 2- μs delay.
SW
8
I
Switch node. A high-side MOSFET gate drive return. Also used for on time generation and output
discharge.
TRAN
5
I
Dynamic voltage change control. It forces CCM and masks PGOOD, OVP and UVP when this pin's status
is pulled up or pulled down. The masking is terminated 900 μs after TRAN pin voltage returns to normal.
See the DYNAMIC VOLTAGE STEP and PGOOD/OVP/UVP MASK section for a detailed description.
Leave this pin open when dynamic voltage change is not used.
GND
OCL detection threshold setting pin. 10 μA at room temperature, 4700 ppm/°C current is sourced and set
the OCL trip voltage as follows.
TRIP
2
I
VOCL =
V(TRIP)
8
(0.2 V ≤ V(TRIP) ≤ 3 V)
V5IN
7
I
5 V +30% / –10% power supply input.
VBST
10
I
Supply input for high-side MOSFET driver (bootstrap terminal). Connect a flying capacitor from this pin to
the SW pin. Internally connected to V5IN via bootstrap MOSFET switch.
VFB
4
I
SMPS feedback input. Connect the feedback resistor divider.
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FUNCTIONAL BLOCK DIAGRAM
0.2V/0.15V
TRAN
+/-3.8 mA
Delay
Auto-skip / FCCM
0.21 V/0.16 V
1.88 V
PGOOD
0.6 V - 30%
+
0.6V + 10%/15%
UV
-
+
0.6 V + 20%
+
Delay
+
OV
0.6V - 5%/10%
-
VBST
-
Control Logic
DRVH
EN
SW
VFB
+
+
Enable /
Softstart
Control
Ramp
Comp
PWM
0.6V
XCON
10 mA
V5IN
+
OCP
TRIP
X (-1/8)
-
FCCM
X 1/8
Auto-skip
DRVL
+
ZC
-
Ton One -Shot
GND
Auto-skip / FCCM
TPS51217
6
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TYPICAL CHARACTERISTICS
V5IN SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
V5IN SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
800
20
V(V5IN) = 5 V
V(EN) = 5 V
V(VFB) = 0.63 V
No Load
18
ISD(V5IN) – V5IN Shutdown Current – mA
I(V5IN) – V5IN Supply Current – mA
1000
600
400
200
16
V(V5IN) = 5 V
V(EN) = 0 V
No Load
14
12
10
8
6
4
2
0
–50
0
50
100
0
–50
150
0
100
150
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
Figure 1.
Figure 2.
OVP/UVP THRESHOLD
vs
JUNCTION TEMPERATURE
CURRENT SENSE CURRENT, I(TRIP)
vs
JUNCTION TEMPERATURE
150
20
V(V5IN) = 5 V
18
OVP
I(TRIP) – Current Sense Current – mA
V(OVP) / V(UVP) – OVP/UVP Trip Threshold – %
50
100
UVP
50
V(V5IN) = 5 V
V(TRIP) = 1 V
16
14
12
10
8
6
4
2
0
–50
0
50
100
150
0
–50
TJ – Junction Temperature – °C
Figure 3.
0
50
100
150
TJ – Junction Temperature – °C
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
TRAN INPUT CURRENT, I(TRAN)
vs
JUNCTION TEMPERATURE
TRAN INPUT CURRENT, I(TRAN)
vs
JUNCTION TEMPERATURE
-10
10
V(V5IN) = 5 V,
V(TRAN) = 0 V
8
I(TRAN) - Tran Input Current - mA
I(TRAN) - Tran Input Current - mA
V(V5IN) = 5 V,
V(TRAN) = 5 V
6
4
2
0
-50
0
50
100
TJ - Junction Temperature - °C
-6
-4
-2
0
-50
150
Figure 6.
SWITCHING FREQUENCY
vs
INPUT VOLTAGE
SWITCHING FREQUENCY
vs
OUTPUT CURRENT
1000
fsw - Swithching Frequency - kHz
Auto-Skip
VOUT = 1.2 V,
IOUT = 10 A
450
400
350
300
250
200
6
8
0
50
100
TJ - Junction Temperature - °C
Figure 5.
500
fsw - Swithching Frequency - kHz
-8
10
12
14
16
18
VIN - Input Voltage - V
20
22
Auto-Skip
VIN = 12 V,
VOUT = 1.2 V
100
10
1
0.1
0.001
Figure 7.
8
150
0.01
0.1
1
10
IOUT - Output Current - A
100
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
0.9-V OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.2-OUTPUT VOLTAGE
vs
OUTPUT CURRENT
0.92
1.23
Auto-Skip
VIN = 12 V,
VOUT = 1.2 V
1.22
0.91
VOUT - Output Voltage - V
VOUT - Output Voltage - V
Auto-Skip
VIN = 12 V,
VOUT = 0.9 V
0.90
0.89
1.21
1.20
1.19
1.18
0.88
0.001
0.01
0.1
1
10
IOUT - Output Current - A
1.17
0.001
100
0.01
0.1
1
10
IOUT - Output Current - A
Figure 9.
Figure 10.
0.9-OUTPUT VOLTAGE
vs
INPUT VOLTAGE
1.2-V OUTPUT VOLTAGE
vs
INPUT VOLTAGE
100
1.23
0.92
Auto-Skip
VOUT = 1.2 V
Auto-Skip
VOUT = 0.9 V
0.91
VOUT - Output Voltage - V
VOUT - Output Voltage - V
1.22
IOUT = 20 A
0.90
IOUT = 0 A
0.89
1.21
IOUT = 20 A
1.20
1.19
IOUT = 0 A
1.18
0.88
6
8
10
12
14
16
18
VIN - Input Voltage - V
20
22
1.17
6
Figure 11.
8
10
12
14
16
18
VIN - Input Voltage - V
20
22
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
0.9-V EFFICIENCY
vs
OUTPUT CURRENT
1.2-V EFFICIENCY
vs
OUTPUT CURRENT
100
90
100
Auto-Skip
VOUT = 0.9 V
90
80
80
70
VIN = 12 V
h - Efficiency - %
h - Efficiency - %
VIN = 8 V
VIN = 8 V
70
60
VIN = 20 V
50
40
VIN = 12 V
60
50
30
20
20
10
10
0.01
0.1
1
10
IOUT - Output Current - A
100
VIN = 20 V
40
30
0
0.001
Auto-Skip
VOUT = 1.2 V
0
0.001
0.01
0.1
1
10
IOUT - Output Current - A
Figure 13.
Figure 14.
0.9-V START-UP WAVEFORM
PRE-BIASED START-UP WAVEFORM
Auto-Skip
VIN = 12 V,
IOUT = 20 A
EN (5 V/div)
Auto-Skip
VIN = 12 V,
IOUT = 0 A
100
EN (5 V/div)
0.5 V pre-biased
VOUT (0.5 V/div)
PGOOD (5 V/div)
t - Time - 500 ms/div
PGOOD (5 V/div)
t - Time - 500 ms/div
Figure 15.
10
VOUT (0.5 V/div)
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
0.9-V SOFT-STOP WAVEFORM
0.9-V LOAD TRANSIENT RESPONSE
EN (5 V/div)
Auto-Skip
VIN = 12 V,
IOUT = 0 A
Auto-Skip
VIN = 20 V,
IOUT = 1 A-15 A(3A/ms)
VOUT (50 mV/div)
IIND (10 A/div)
VOUT (0.5 V/div)
PGOOD (5 V/div)
DRVL (5 V/div)
IOUT (10 A/div)
t - Time - 100 ms/div
t - Time - 10 ms/div
Figure 17.
Figure 18.
DYNAMIC OUTPUT VOLTAGE TRANSITION
DYNAMIC OUTPUT VOLTAGE TRANSITION
VID1
(5 V/div)
VID1
(5 V/div)
VID0
(5 V/div)
VID0
(5 V/div)
VOUT (0.1 V/div)
1.2 V
1.2 V
VOUT (0.1 V/div)
0.9 V
5V
0.9 V
5V
Auto-Skip
VIN = 12 V,
IOUT = 0 A
PGOOD (5 V/div)
Auto-Skip
VIN = 12 V,
IOUT = 0 A
PGOOD (5 V/div)
t - Time - 1 ms/div
t - Time - 1 ms/div
Figure 19.
Figure 20.
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APPLICATION INFORMATION
GENERAL DESCRIPTION
The TPS51217 is a high-efficiency, single channel, synchronous buck regulator controller suitable for low output
voltage point-of-load applications in notebook computers and similar digital consumer applications. The device
features proprietary D-CAP™ mode control combined with adaptive on-time architecture. This combination is
ideal for building modern low duty ratio, ultra-fast load step response DC/DC converters. The output voltage
ranges from 0.6 V to 2.6 V. The conversion input voltage range is from 3 V to 28 V. The D-CAP™ mode uses the
ESR of the output capacitor(s) to sense current information. An advantage of this control scheme is that it does
not require an external phase compensation network, helping the designer with ease-of-use and realizing low
external component count configuration. Adaptive on-time control tracks the preset switching frequency over a
wide range of input and output voltages, while it increases the switching frequency at step-up of load.
The strong gate drivers of the TPS51217 allow low RDS(on) FETs for high current applications.
ENABLE AND SOFT START
When the EN pin voltage rises above the enable threshold, (typically 1.2 V) the controller enters its start-up
sequence. The first 250 μs is a standby phase. Switching is inhibited during this phase. In the second phase,
internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. This ramping time is 650 μs. Smooth and
constant ramp up of the output voltage is maintained during start up regardless of load current. Connect a 1-kΩ
resistor in series with the EN pin to provide protection.
ADAPTIVE ON-TIME D-CAP™ CONTROL
TPS51217 does not have a dedicated oscillator that determines switching frequency. However, the device runs
with pseudo-constant frequency by feed-forwarding the input and output voltages into its on-time one-shot timer.
The adaptive on-time control adjusts the on-time to be inversely proportional to the input voltage and proportional
to the output voltage (tON ∝ VOUT / VIN ). This makes the switching frequency fairly constant in steady state
conditions over wide input voltage range.
The off-time is modulated by a PWM comparator. The VFB node voltage (the mid point of resistor divider) is
compared to the internal 0.6-V reference voltage added with a ramp signal. When both signals match, the PWM
comparator asserts the set signal to terminate the off-time (turn off the low-side MOSFET and turn on high-side
MOSFET). The set signal becomes valid if the inductor current level is below OCP threshold, otherwise the offtime is extended until the current level to become below the threshold.
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SMALL SIGNAL MODEL
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 21.
Switching Modulator
VIN
DRVH
R1
VFB
PWM
Control
Logic
and
Driver
+
R2
+
DRVL
L
IIND
VOUT
IOUT
IC
0.6 V
ESR
RL
Voltage Divider
VC
CO
Output
Capacitor
UDG-09063
Figure 21. Simplified Modulator Model
The output voltage is compared with internal reference voltage (ramp signal is ignored here for simplicity). The
PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the
comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially
constant.
H(s) =
1
s ´ ESR ´ CO
(1)
For loop stability, the 0-dB frequency, ƒ0, defined in Equation 2 need to be lower than 1/4 of the switching
frequency.
f0 =
f
1
£ SW
2p ´ ESR ´ CO
4
(2)
According to Equation 2, the loop stability of D-CAP™ mode modulator is mainly determined by the capacitor's
chemistry. For example, specialty polymer capacitors (SP-CAP) have CO on the order of several 100 μF and
ESR in range of 10 mΩ. These makes f0 on the order of 100 kHz or less and the loop is stable. However,
ceramic capacitors have an ƒ0 of more than 700 kHz, which is not suitable for this modulator.
RAMP SIGNAL
The TPS51217 adds a ramp signal to the 0.6-V reference in order to improve its jitter performance. As described
in the previous section, the feedback voltage is compared with the reference information to keep the output
voltage in regulation. By adding a small ramp signal to the reference, the S/N ratio at the onset of a new
switching cycle is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is
controlled to start with –6 mV at the beginning of ON-cycle and becomes 0 mV at the end of OFF-cycle in
continuous conduction steady state.
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LIGHT LOAD CONDITION IN AUTO-SKIP OPERATION
The TPS51217 automatically reduces switching frequency at light load conditions to maintain high efficiency. As
the output current decreases from heavy load condition, the inductor current is also reduced and eventually
comes to the point that its rippled valley touches zero level, which is the boundary between continuous
conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor
current is detected. As the load current further decreases, the converter runs in to discontinuous conduction
mode. The on-time is kept almost the same as it was in the continuous conduction mode so that it takes longer
time to discharge the output capacitor with smaller load current to the level of the reference voltage. The
transition point to the light load operation IO(LL) (i.e., the threshold between continuous and discontinuous
conduction mode) can be calculated in Equation 3.
IO(LL ) =
(V - VOUT ) ´ VOUT
1
´ IN
2 ´ L ´ fSW
VIN
where
•
fSW is the PWM switching frequency (340 kHz)
(3)
Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it
decreases almost proportional to the output current from the IO(LL) given in Equation 3. For example, it is 68 kHz
at IO(LL)/5.
ADAPTIVE ZERO CROSSING
The TPS51217 has an adaptive zero crossing circuit which performs optimization of the zero inductor current
detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and
compensates inherent offset voltage of the ZC comparator and delay time of the ZC detection circuit. It prevents
SW-node swing-up caused by too late detection and minimizes diode conduction period caused by too early
detection. As a result, better light load efficiency is delivered.
OUTPUT DISCHARGE CONTROL
When EN is low, the TPS51217 discharges the output capacitor using internal MOSFET connected between SW
and GND while high-side and low-side MOSFETs are kept off. The current capability of this MOSFET is limited to
discharge slowly.
LOW-SIDE DRIVER
The low-side driver is designed to drive high current low RDS(on) N-channel MOSFET(s). The drive capability is
represented by its internal resistance, which are 1.0Ω for V5IN to DRVL and 0.5Ω for DRVL to GND. A dead time
to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and
low-side MOSFET off to high-side MOSFET on. 5-V bias voltage is delivered from V5IN supply. The
instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The average
drive current is equal to the gate charge at Vgs=5V times switching frequency. This gate drive current as well as
the high-side gate drive current times 5V makes the driving power which need to be dissipated from TPS51217
package.
HIGH-SIDE DRIVER
The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). When configured as a
floating driver, 5 V of bias voltage is delivered from V5IN supply. The average drive current is also equal to the
gate charge at Vgs = 5V times switching frequency. The instantaneous drive current is supplied by the flying
capacitor between VBST and SW pins. The drive capability is represented by its internal resistance, which are
1.5 Ω for VBST to DRVH and 0.7 Ω for DRVH to SW.
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POWER-GOOD
The TPS51217 has powergood output that indicates high when switcher output is within the target. The
powergood function is activated after soft-start has finished. If the output voltage becomes within +10%/–5% of
the target value, internal comparators detect power-good state and the power-good signal becomes high after a
1-ms internal delay. If the output voltage goes outside of +15%/–10% of the target value, the powergood signal
becomes low after a 2-μs internal delay. The powergood output is an open-drain output and must be pulled up
externally.
CURRENT SENSE AND OVERCURRENT PROTECTION
TPS51217 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state
and the controller keeps the OFF state during the inductor current is larger than the overcurrent trip level. To
provide both good accuracy and cost effective solution, the TPS51217 supports temperature compensated
MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor,
R(TRIP). The TRIP terminal sources I(TRIP) current, which is 10μA typically at room temperature, and the trip level
is set to the OCL trip voltage V(TRIP) as shown in Equation 4. Note that V(TRIP) is limited up to approximately 3 V
internally.
V(TRIP)(mV) = R(TRIP)(kΩ) × I(TRIP)(μA)
(4)
(4)
The inductor current is monitored by the voltage between GND pad and SW pin so that the SW pin should be
connected to the drain terminal of the low-side MOSFET properly. I(TRIP) has 4700ppm/°C temperature slope to
compensate the temperature dependency of the RDS(on). GND is used as the positive current sensing node so
that GND should be connected to the proper current sensing device, i.e. the source terminal of the low-side
MOSFET.
As the comparison is done during the OFF state, V(TRIP) sets valley level of the inductor current. Thus, the load
current at overcurrent threshold, IOCP, can be calculated in Equation 5
æ V(TRIP) ö IIND(ripple )
V(TRIP)
(V - VOUT ) ´ VOUT
1
÷+
IOCP = ç
=
+
´ IN
ç 8 ´ RDS(on) ÷
2
8 ´ RDS(on) 2 ´ L ´ fSW
VIN
è
ø
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down the
controller.
When the device is operating in the forced continuous conduction mode, the negative current limit (NCL) protects
the external FET from carrying too much current. The NCL detect threshold is set as the same absolute value as
positive OCL but negative polarity. Note that the forced continuous conduction mode appears only during the
Dynamic Voltage Step operation, and the threshold still represents the valley value of the inductor current.
OVER/UNDER VOLTAGE PROTECTION
TPS51217 monitors a resistor divided feedback voltage to detect over and undervoltage. When the feedback
voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit
latches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After a 1-ms delay, TPS51217 latches OFF both highside and low-side MOSFETs drivers. This function is enabled after 1.2 ms following EN has become high.
DYNAMIC VOLTAGE STEP and PGOOD/OVP/UVP MASK
Output voltage of switcher can be dynamically step-up or step-down by controlling bottom resistance of the
output voltage divider. The simplest way is to add a MOSFET switch plus a resistor in parallel with the bottom
resistor. When the MOSFET switch is turned on, the VFB voltage is immediately dropped and comes back
equivalent to the internal reference voltage as the output voltage climbs up to match the new target. If the voltage
step is large, it may cause PGOOD state into 'bad' and also may hit UVP. In the case of voltage step-down, the
same PGOOD bad and OVP hit may happen. TRAN pin helps masking PGOOD, UVP and OVP during the
voltage transition. Combination of weighted capacitances C2 and C3 detect transition of VIDx (Figure 22).
Masking of PGOOD, OVP and UVP start when the TRAN pin voltage goes outside of its window comparator
threshold. At this time, TRAN pin also starts sink or source current. 900μsec after TRAN pin voltage recovers
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within the threshold window, PGOOD, OVP and UVP are released from masking. The TRAN pin operation is
useful for graphics power applications such that switcher output voltage needs to be changed dynamically. At the
transition of output voltage, inductor current has a chance to hit over current limit (OCL) to quickly charge the
output capacitor, which may cause output voltage undershoot or overshoot. Capacitance C1 in parallel with the
top resistor slows down transition slew rate and prevent from hitting OCL. Time constant of the transition is
R1 × C1. From 3.3 V to 5 V is recommended for VIDx input amplitude.
Vout
VID1
C1
R1
TPS51217
VID0
VFB
2.03 V
R4
R3
1.88 V
2.03 V
TRAN
R2
Disable PGOOD
and OVP/UVP
900 ms
900 ms
Disable PGOOD
and OVP/UVP
0.6V ´ (1 +
C2
R5
VID1
TRAN
C3
0.6V ´ (1 +
VOUT
VID0
t = R1´ C1
C2 = 2 ´ C3
R1
)
R2 // R4
R1
)
R2 // R3
0.6V ´ (1 + R1/ R2)
Figure 22. Dynamic Voltage Step Application
UVLO PROTECTION
TPS51217 has V5IN undervoltage lockout protection (UVLO). When the V5IN voltage is lower than UVLO
threshold voltage, the switch mode power supply shuts off. This is non-latch protection.
THERMAL SHUTDOWN
TPS51217 monitors the die temperature. If the temperature exceeds the threshold value (typically 145°C), the
TPS51217 is shut off. This is non-latch protection.
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EXTERNAL COMPONENTS SELECTION
Selecting external components is simple in D-CAP™ mode.
1. Choose the inductor.
The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum
output current. Larger ripple current increases output ripple voltage and improves S/N ratio and helps stable
operation.
L=
1
IIND(ripple) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
3
=
IOUT(max ) ´ fSW
´
(V
IN(max ) - VOUT
)´ V
OUT
VIN(max )
(6)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak
inductor current before saturation. The peak inductor current can be estimated in Equation 7.
IIND(peak) =
V(TRIP)
8 × RDS(on)
+
1
´
L × fSW
(V
IN(max )
- VOUT
)´ V
OUT
VIN(max )
(7)
2. Choose the output capacitor(s).
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. For loop stability,
capacitance and ESR should satisfy Equation 2. For jitter performance, Equation 8 is a good starting point to
determine ESR.
ESR =
VOUT ´ 10 éëmV ûù ´ (1-D ) 10[mV] ´ L ´ ƒSW L ´ ƒSW
=
=
[Ω]
0.6[V] ´ IIND(ripple)
0.6[V]
60
where
D is the duty ratio
the output ripple down slope rate is 10 mV/tSW in terms of VFB terminal voltage as shown in Figure 23
tSW is the switching period
V(VFB) – Feedback Voltage – mV
•
•
•
(8)
tSW x (1-D)
10
VRIPPLE(FB)
0
t – Time
tSW
Figure 23. Ripple Voltage Down Slope
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3. Determine the value of R1 and R2.
The output voltage is programmed by the voltage-divider resistor, R1 and R2, shown in Figure 21. R1 is
connected between the VFB pin and the output, and R2 is connected between the VFB pin and GND. Typical
designs begin with the selection of an R2 value between 10 kΩ and 20 kΩ. Determine R1 using Equation 9.
IIND(ripple) ´ ESR ö
æ
çç VOUT ÷÷ - 0.6
2
è
ø
´ R2
R1 =
0.6
(9)
LAYOUT CONSIDERATIONS
VIN
TRIP
TPS51217
2
V5IN
V OUT
6
110mmF
F
#1
#2
DRVL
VFB
4
5
Thermal Pad
GND
#3
UDG-09066
Figure 24. Ground System of DC/DC Converter Using the TPS51217
Certain points must be considered before starting a layout work using the TPS51217.
• Inductor, VIN capacitor(s), VOUT capacitor(s) and MOSFETs are the power components and should be placed
on one side of the PCB (solder side). Other small signal components should be placed on another side
(component side). At least one inner plane should be inserted, connected to ground, in order to shield and
isolate the small signal traces from noisy power lines.
• All sensitive analog traces and components such as VFB, PGOOD, TRIP and TRAN should be placed away
from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internal
layer(s) as ground plane(s) and shield feedback trace from power traces and components.
• The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to
suppress generating switching noise.
– The most important loop to minimize the area of is the path from the VIN capacitor(s) through the high and
low-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of the VIN
capacitor(s) and the source of the low-side MOSFET at ground as close as possible. (See loop #1 of
Figure 24)
– The second important loop is the path from the low-side MOSFET through inductor and VOUT capacitor(s),
and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET
and negative node of VOUT capacitor(s) at ground as close as possible. (See loop #2 of Figure 24)
– The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side
MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back
to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows
from gate of the low-side MOSFET through the gate driver and GND pad of the device, and back to
source of the low-side MOSFET through ground. Connect negative node of V5IN capacitor, source of the
low-side MOSFET and GND pad of the device at ground as close as possible. (See loop #3 of Figure 24)
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•
•
•
•
SLUS947B – JUNE 2009 – REVISED APRIL 2012
Since the TPS51217 controls output voltage referring to voltage across VOUT capacitor, the top-side resistor of
the voltage divider should be connected to the positive node of VOUT capacitor. In a same manner both
bottom side resistor and GND pad of the device should be connected to the negative node of VOUT capacitor.
The trace from these resistors to the VFB pin should be short and thin. Place on the component side and
avoid via(s) between these resistors and the device.
Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
to a high-voltage switching node.
Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least
0.5 mm (20 mils) diameter along this trace.
The PCB trace defined as switch node, which connects to source of high-side MOSFET, drain of low-side
MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
LAYOUT CONSIDERATIONS TO REMOTE SENSING
VIN
TRIP
TPS51217
2
V5IN
6
VOUT
1
F
10mmF
VFB
DRVL
4
0.1 mF
5
100 W
VTT_SENSE
VSS_SENSE
Thermal Pad
GND
UDG-09067
Figure 25. Remote Sensing of Output Voltage Using the TPS51217
•
•
•
Make a Kelvin connection to the load device.
Run the feedback signals as a differential pair to the device. The distance of these parallel pair should be as
short as possible.
Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane.
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TPS51217 APPLICATION CIRCUIT
V5IN
VIN
4.5 V
to
6.5 V
C1
4.7 nF
R1
10 kW
R6
100 kW
C4
0.1 mF
TPS51217
1
PGOOD
VBST
10
2
TRIP
DRVH
9
8 V to 20V
Q1
FDMS8680
C6
10 mF x 4
R9
EN
R7
1 kW
C2
100 pF
3.3 W
R5
1 kW
VID1
C3
51 pF
R4
30 kW
VID0
Q4
R3
60.4 kW
3
EN
4
VFB
5
TRAN
GND
R2
20.5 kW
R8
30 kW
SW
8
V5IN
7
DRVL
6
L1
0.45 mH
VOUT
0.9 V to 1.2 V
18 A
Q2
FDMS8670AS
C7
330 mF x 4
C5
1 mF
Q3
FDMS8670AS
VOUT_GND
Q5
Figure 26. 0.9-V to 1.2-V/18A Auto-skip mode
Table 1. 0.9-V to 1.2-V/18A Application List of Materials
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURER
PART NUMBER
C6
1
4 × 10 μF, 25 V
Taiyo Yuden
TMK325BJ106MM
C7
1
4 × 330 μF, 2 V, 12 mΩ
Panasonic
EEFCX0D331XR
L1
1
0.45 μH, 25 A, 1.1 mΩ
Panasonic
ETQP4LR45XFC
Q1
1
30 V, 35 A, 8.5 mΩ
Fairchild
FDMS8680
Q2, Q3
2
30 V, 42 A, 3.5 mΩ
Fairchild
FDMS8670AS
20
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REVISION HISTORY
Changes from Original (June 2009) to Revision A
•
Page
Added text - Connect a 1-kΩ resistor in series with the EN pin to provide protection. To the ENABLE AND SOFT
START section. ................................................................................................................................................................... 12
Changes from Revision A (August 2009) to Revision B
Page
•
Added DRVH specification to the ABSOLUTE MAXIMUM RATINGS table for pulse width < 20 ns ................................... 2
•
Added DRVL specification to the ABSOLUTE MAXIMUM RATINGS table for pulse width < 20 ns .................................... 2
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS51217DSCR
ACTIVE
WSON
DSC
10
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
PIYI
TPS51217DSCT
ACTIVE
WSON
DSC
10
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
PIYI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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