TPS51285A
TPS51285B
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SLVSBX0 – APRIL 2013
Ultra-Low Quiescent (ULQ™) Dual Synchronous Step-Down Controller with
5V and 3.3V LDOs
Check for Samples: TPS51285A, TPS51285B
FEATURES
APPLICATIONS
1
•
•
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Range: 5 V to 24 V
• Notebook Computers
Output Voltages: 5 V and 3.3 V (Adjustable
• Tablet Computers
Range ±10%)
DESCRIPTION
Built-in, 100-mA, 5-V and 3.3-V LDOs
The TPS51285A and TPS51285B are cost-effective,
Clock Output for Charge-Pump
dual synchronous buck controllers with 5-V and 3.3-V
±1% Reference Accuracy
LDOs, targeted for notebook system-power supply
Adaptive On-Time D-CAP™ Mode Control
solutions. The device achieves low power
consumption by the use of auto-skip and ULQ™
Architecture with 400 kHz (CH1) and 475 kHz
modes, which is beneficial for long battery life in
(CH2) Frequency
system stand-by mode. The 256-kHz VCLK output is
Auto-skip and ULQ™ modes for long battery
provided to drive an external charge pump,
life in system stand-by mode
generating gate drive voltage for the load switches
Internal 0.8-ms Voltage Servo Soft-Start
with minimum power consumption in the main
converter. The device employs adaptive on-time DLow-Side RDS(on) Current Sensing Scheme
CAP™ mode control which enables fast load
Built-In Output Discharge Function
transient response without external compensation
Separate Enable Input for Switchers
network. The TPS51285A/B operates with supply
input voltage ranging from 5V to 24V and supports
Dedicated OC Setting Terminals
output voltages of 5 V and 3.3 V. The TPS51285A
Power Good Indicator
and TPS51285B are available in a 20-pin 3 x 3 (mm)
OVP, UVP and OCP Protection
QFN package and is specified from -40°C to 85°C.
Non-Latch UVLO and OTP Protection
20-Pin, 3 mm x 3 mm, QFN (RUK)
NEED SOME SPACE
ORDERING INFORMATION (1)
ORDERABLE
DEVICE NUMBER
TPS51285ARUKR
TPS51285ARUKT
TPS51285BRUKR
TPS51285BRUKT
(1)
ALWAYS On-LDO
VREG3
VREG3 and VREG5
OUTPUT SUPPLY
QUANTITY
Tape and Reel
3000
Mini reel
250
Tape and Reel
3000
Mini reel
250
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP, ULQ are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS51285A
TPS51285B
SLVSBX0 – APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TYPICAL APPLICATION DIAGRAMS
VBAT/
VADPTOR
VIN
5V
output
VBST1
VBST2
DRVH1
DRVH2
SW1
DRVL1
3.3 V
output
SW2
DRVL2
VO1
VFB1
VFB2
CS1
CS2
VCLK
EN-5V
Charge pump
output
EN1
VREG5
5 V LDO
PGOOD
PGOOD
EN2
EN 3.3 V
VREG3
3.3-V LDO
GND
Figure 1. TYPICAL APPLICATION DIAGRAM (With Charge Pump)
2
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VBAT/
VADPTOR
VIN
5V
output
VBST1
VBST2
DRVH1
DRVH2
SW1
DRVL1
3.3 V
output
SW2
DRVL2
VO1
VFB1
VFB2
CS1
CS2
VCLK
EN-5V
EN1
VREG5
5 V LDO
PGOOD
PGOOD
EN2
EN 3.3 V
VREG3
3.3-V LDO
GND
Figure 2. TYPICAL APPLICATION DIAGRAM (Without Charge Pump)
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
MAX
VBST1, VBST2
–0.3
32
VBST1, VBST2 (3)
–0.3
6
–6
26
VIN
–0.3
26
EN1, EN2
–0.3
6
VFB1, VFB2
–0.3
3.6
VO1
–0.3
6
DRVH1, DRVH2
–6.0
32
–0.3
6
SW1, SW2
Input voltage (2)
DRVH1, DRVH2 (3)
DRVH1, DRVH2
Output voltage (2)
Electrostatic discharge
(ESD) ratings (4)
(3)
–2.5
6
DRVL1, DRVL2
(duty cycle < 1%)
–0.3
6
DRVL1, DRVL2 (duty cycle < 1%)
–2.5
6
PGOOD, VCLK, VREG5
–0.3
6
VREG3, CS1, CS2
–0.3
3.6
Human Boby Model (HBM)
2
Charged Device Model (CDM)
0.5
Junction temperature, TJ
Storage temperature, TST
(1)
(2)
(3)
(4)
–55
UNIT
V
V
kV
150
°C
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted
Voltage values are with respect to SW terminals.
ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION
THERMAL METRIC (1)
TPS51285A
TPS51285B
UNITS
20-PIN RUK
θJA
Junction-to-ambient thermal resistance
46.2
θJCtop
Junction-to-case (top) thermal resistance
53.6
θJB
Junction-to-board thermal resistance
19.2
ψJT
Junction-to-top characterization parameter
0.6
ψJB
Junction-to-board characterization parameter
19.2
θJCbot
Junction-to-case (bottom) thermal resistance
3.6
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLVSBX0 – APRIL 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
Supply voltage
Input voltage (1)
Output voltage (1)
VIN
TYP MAX
5
24
VBST1, VBST2
–0.1
30
VBST1, VBST2 (2)
–0.1
5.5
SW1, SW2
–5.5
24
EN1, EN2
–0.1
5.5
VFB1, VFB2
–0.1
3.5
VO1
–0.1
5.5
DRVH1, DRVH2
–5.5
30
DRVH1, DRVH2 (2)
–0.1
5.5
DRVL1, DRVL2
–0.1
5.5
PGOOD, VCLK, VREG5
–0.1
5.5
VREG3, CS1, CS2
–0.1
3.5
–40
85
Operating free-air temperature, TA
(1)
(2)
MIN
UNIT
V
V
°C
All voltage values are with respect to the network ground terminal unless otherwise noted.
Voltage values are with respect to the SW terminal.
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VVIN = 12 V, VVO1 = 5 V, VVFB1 = VVFB2 = 2 V, VEN1 = VEN2 = 3.3 V, VCLK: 200 Ω to
GND
(unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVIN1
VIN supply current-1
TA = 25°C, No load, VVO1 = 0 V,
VVFB1 = VVFB2 = 2.06V
84
μA
IVIN2
VIN supply current-2
TA = 25°C, No load, VVFB1 = VVFB2 = 2.06 V
10
μA
IVO1
VO1 supply current
TA = 25°C, No load, VVFB1 = VVFB2 = 2.06 V
70
μA
TA = 25°C, No load, VVO1 = 0 V,
VEN1= VEN2= 0 V
25
IVIN(STBY)
VIN stand-by current
TPS51285A
TPS51285B
μA
28
INTERNAL REFERENCE
VFBx
VFB regulation voltage
IFBx
VFB Leakage Current
TA = 25°C
1.99
2
2.01
1.98
2
2.02
V
0.1
µA
TA = 25°C
V
VREG5 OUTPUT
TA = 25°C, No load, VVO1 = 0 V
4.9
5
5.1
VVIN > 7 V , VVO1= 0 V, IVREG5 < 100 mA
4.85
5
5.1
VVIN > 5.5 V , VVO1= 0 V, IVREG5 < 35 mA
4.85
5
5.1
5.1
VVREG5
VREG5 output voltage
V
VVIN > 5 V, VVO1= 0 V, IVREG5 < 20 mA
4.55
4.75
IVREG5
VREG5 current limit
VVO1 = 0 V, VVREG5= 4.5 V, VVIN = 7 V
100
140
mA
RV5SW
5-V switch resistance
TA = 25°C, VVO1= 5 V, IVREG5= 50 mA
1.8
Ω
VREG3 OUTPUT
VVREG3
VREG3 output voltage
VVIN > 7 V , VVO1= 0 V, IVREG3 < 100 mA
3.217
3.3
3.383
VVIN > 5.5 V , VVO1= 0 V, IVREG3 < 35 mA
3.234
3.3
3.366
0°C ≤ TA ≤ 85°C, VVIN > 5.5 V, VVO1= 0 V,
IVREG3 < 35 mA
3.267
3.3
3.333
0°C ≤ TA ≤ 85°C, VVIN > 5.5 V, IVREG3< 35 mA
3.267
3.3
3.333
VVIN > 5 V , VVO1= 0 V, IVREG3 < 35 mA
3.217
3.3
3.366
IVREG3-1
VREG3 current limit-1
VVO1 = 0 V, VVREG3= 3.15 V, VVIN= 7 V
100
200
IVREG3-2
VREG3 current limit-2
VVREG3 = 3.15 V, VVIN= 7 V
100
200
V
mA
DUTY CYCLE and FREQUENCY CONTROL
fsw1
CH1 frequency (1)
TA = 25°C, VVIN= 20 V
400
fSW2
CH2 frequency (1)
TA = 25°C, VVIN= 20 V
475
tOFF(MIN)
Minimum off-time
TA = 25°C
200
300
kHz
kHz
400
ns
MOSFET DRIVERS
RDRVH
DRVH resistance
RDRVL
DRVL resistance
tD
Dead time
Source, IDRVH = –50 mA, (VVBST – VSW) = 5 V
Sink, IDRVH = 50 mA, (VVBST – VSW) = 5 V
Source, IDRVL = –50 mA, VVREG5 = 5 V
3
Ω
1.9
3
Sink, IDRVL = 50 mA, VVREG5= 5 V
0.9
DRVH-off to DRVL-on
12
DRVL-off to DRVH-on
20
Boost switch on-resistance
TA = 25°C, IVBST = 10 mA
13
VBST leakage current
TA = 25°C
Ω
ns
INTERNAL BOOT STRAP SWITCH
RVBST
(ON)
IVBSTLK
Ω
1
µA
CLOCK OUTPUT
RVCLK
fCLK
(1)
6
VCLK on-resistance (pull-up)
TA = 25°C, VCLK: Open
10
VCLK on-resistance (pull-down)
TA = 25°C, VCLK: Open
10
Clock frequency
TA = 25°C, VCLK: Open
256
Ω
kHz
Specified by design. Not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VVIN = 12 V, VVO1 = 5 V, VVFB1 = VVFB2 = 2 V, VEN1 = VEN2 = 3.3 V, VCLK: 200 Ω to
GND
(unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
OUTPUT DISCHARGE
RDIS1
CH1 discharge resistance
RDIS2
CH2 discharge resistance
TA = 25°C, VVO1 = 0.5 V
VEN1 = VEN2 = 0 V
TPS51285A
TPS51285B
Ω
35
75
TA = 25°C, VSW2 = 0.5 V, VEN1 = VEN2 = 0 V
Ω
70
SOFT START
tSS
Soft-start time (From ENx Hi)
From ENx="Hi" and VVREG5 > VUVLO5 to VOUT = 95%
0.91
ms
tSSRAMP
Soft-start time (ramp-up)
VOUT= 0% to VOUT = 95%, VVREG5 = 5 V
0.78
ms
POWER GOOD
tPGDEL
PG start-up delay
From EN1 = "Hi", EN2 = "Hi", and VVREG5 > VUVLO5
VPGTH
PG threshold
PGOOD in from lower (start-up)
IPGMAX
PG sink current
VPGOOD = 0.5 V
IPGLK
PG leak current
VPGOOD = 5.5 V
1.65
87.5%
90%
ms
92.5%
6.5
mA
1
µA
55
µA
CURRENT SENSING
ICS
CS source current
TCCS
CS current temperature coefficient
VCS
CS Current limit setting range
VAZCADJ
TA = 25°C, VCS = 0.4 V
(2)
45
On the basis of 25°C
50
4500
0.2
Positive
Adaptive zero cross adjustable range
5
Negative
ppm/°C
2
10
–10
–5
V
mV
LOGIC THRESHOLD
VENX(ON)
EN threshold high-level
SMPS on level
VENX(OFF)
EN threshold low-level
SMPS off level
IEN
EN input current
VENx= 3.3 V
1.6
V
1
µA
0.3
V
OUTPUT OVERVOLTAGE PROTECTION
VOVP
OVP trip threshold
tOVPDLY
OVP propagation delay
112.5%
TA = 25°C
115% 117.5%
0.5
µs
OUTPUT UNDERVOLTAGE PROTECTION
VUVP
UVP trip Threshold
VUVP-ST
UVP trip Threshold
tUVPDLY
UVP prop delay
tUVPENDLY
UVP enable delay
Start Up
55%
60%
65%
87.5%
90%
92.5%
From ENx ="Hi", VVREG5 = 5V
250
µs
1.1
ms
UVLO
VUVL0VIN
VUVLO5
VUVLO3
(2)
VIN UVLO Threshold
VREG5 UVLO Threshold
Wake up
4.2
4.58
4.95
V
Shutdown
3.75
4.1
4.45
V
Wake up
4.08
4.38
4.55
V
Shutdown
3.7
4
4.3
V
3
3.15
3.26
V
2.75
3
3.21
V
Wake up
VREG3 UVLO Threshold
Shutdown
Specified by design. Not production tested.
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DEVICE INFORMATION
EN1
VCLK
SW1
VBST1
DRVH1
RUK PACKAGE
20 PINS
(TOP VIEW)
20
19
18
17
16
CS1
1
15
DRVL1
VFB1
2
14
VO1
VREG3
3
13
VREG5
VFB2
4
12
VIN
11
DRVL2
Thermal Pad
6
7
8
9
10
PGOOD
SW2
VBST2
DRVH2
5
EN2
CS2
GND
PIN FUNCTIONS
NAME
PIN NO.
I/O
CS1
1
O
Sets the channel 1 OCL trip level.
CS2
5
O
Sets the channel 2OCL trip level.
DRVH1
16
O
High-side driver output
DRVH2
10
O
High-side driver output
DRVL1
15
O
Low-side driver output
DRVL2
11
O
Low-side driver output
EN1
20
I
Channel 1 enable.
EN2
6
I
Channel 2 enable.
PGOOD
7
O
Power good output flag. Open drain output. Pull up to external rail via a resistor
SW1
18
O
Switch-node connection.
SW2
8
O
Switch-node connection.
VBST1
17
I
VBST2
9
I
Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW
terminal.
VCLK
19
O
Clock output for charge pump.
VFB1
2
I
VFB2
4
I
VIN
12
I
Power conversion voltage input. Apply the same voltage as drain voltage of high-side MOSFETs of
channel 1 and channel 2.
VO1
14
I
Output voltage input, 5-V input for switch-over.
VREG3
3
O
3.3-V LDO output.
VREG5
13
O
5-V LDO output.
Thermal pad (GND)
8
DESCRIPTION
Voltage feedback Input
GND terminal, solder to the ground plane
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FUNCTIONAL BLOCK DIAGRAM
TPS51285A
TPS51285B
VIN
+
OTP
4.58 V/4.1 V
VO1
+
+
+
VREG5
+
2V
+
VREG3
Osc
VCLK
VCLK-OFF
detection
EN1
VBST1
EN2
VDRV
VIN VDD VO_OK
DRVH1
SW1
DRVL1
Switcher
Controller
(CH1)
VFB1
CS1
VDD VDRV VIN
EN
EN
FAULT
PGND
GND
DRVH2
FAULT
REF
REF
PGOOD
Switcher
Controller
(CH2)
PGOOD
DCHG
VBST2
DCHG
SW2
DRVL2
VFB2
GND
PGND
CS2
PGOOD
GND
(Thermal Pad)
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SWITCHER CONTROLLER BLOCK DIAGRAM
TPS51285A
TPS51285B
VDD
VREF ±10%
+
UV
VREF ±40%
PGOOD
+
OV
PGOOD
Control Logic
VREF +15%
VFB
EN
REF
SS Ramp Comp
+
+
PWM
VO_OK
VBST
HS
VIN
DRVH
SW
XCON
OC
CS
50 µA
VDRV
+
+
LS
NOC
One-Shot
+
Discharge
GND
DRVL
PGND
DCHG
+
ZC
FAULT
UDG-12093
10
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DETAILED DESCRIPTION
PWM Operations
The main control loop of the switch mode power supply (SMPS) is designed as an adaptive on-time pulse width
modulation (PWM) controller. It supports a proprietary D-CAP™ mode. D-CAP™ mode does not require external
compensation circuits and is suitable for low external component count configuration when used with appropriate
amount of ESR at the output capacitor(s).
At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or enters the ON state. This
MOSFET is turned off, or enters the ‘OFF state, after the internal, one-shot timer expires. The MOSFET is turned
on again when the feedback point voltage, VVFB, decreased to match the internal 2-V reference. The inductor
current information is also monitored and should be below the overcurrent threshold to initiate this new cycle. By
repeating the operation in this manner, the controller regulates the output voltage. The synchronous low-side
(rectifying) MOSFET is turned on at the beginning of each OFF state to maintain a minimum of conduction loss.
The low-side MOSFET is turned off before the high-side MOSFET turns on at next switching cycle or when the
detecting inductor current decreases to zero. This enables seamless transition to the reduced frequency
operation during light-load conditions so that high efficiency is maintained over a broad range of load current.
Adaptive On-Time/ PWM Frequency Control
Because the device does not have a dedicated oscillator for control loop on board, switching cycle is controlled
by the adaptive on-time circuit. The on-time is controlled to meet the target switching frequency by feedforwarding the input and output voltage into the on-time one-shot timer. To achieve higher duty operation for
lower input voltage application (2-cell battery), the target switching frequency is varied according to the input
voltage. The switching frequency of CH1 (5-V output) is 400kHz during continuous conduction mode (CCM)
operation when VIN = 20 V. The CH2 (3.3-V output) is 475 kHz during CCM when VIN = 20 V.
To improve load transient performance and load regulation in lower input voltage condition, device can extend
the on-time. The maximum on-time extension of CH1 is 5 times. For CH2, it is 2 times. To maintain a reasonable
inductor ripple current during on-time extension, the inductor ripple current should be set to less than half of the
OCL (valley) threshold. The on-time extension function provides high duty cycle operation and shows better DC
(static) performance. AC performance is determined mostly by the output LC filter and resistive factor in the loop.
Light Load Condition in Auto-Skip Operation
The device automatically reduces switching frequency during light-load conditions to maintain high efficiency.
This reduction of frequency is achieved smoothly. A more detailed description of this operation is as follows. As
the output current decreases from heavy-load condition, the inductor current is also reduced and eventually
approaches valley zero current, which is the boundary between continuous conduction mode and discontinuous
conduction mode. The rectifying MOSFET is turned off when this zero inductor current is detected. As the load
current further decreases, the converter runs in discontinuous conduction mode and it takes longer and longer to
discharge the output capacitor to the level that requires the next ON cycle. In reverse, when the output current
increase from light load to heavy load, the switching frequency increases to the preset value as the inductor
current reaches to the continuous conduction. The transition load point to the light load operation IOUT(LL) (that is,
the threshold between continuous and discontinuous conduction mode) can be calculated as shown in n
Equation 1.
IOUT(LL ) =
(VIN - VOUT )´ VOUT
1
´
2 ´ L ´ fSW
VIN
where
•
fSW is the PWM switching frequency
(1)
Switching frequency versus output current during light-load conditions is a function of inductance (L), input
voltage (VIN) and output voltage (VOUT), but it decreases almost proportional to the output current from the
IOUT(LL).
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ULQ™ Mode
To achieve longer battery life in system stand-by mode of mobile devices, the device implements Ultra Low
Quiescent (ULQ) mode. In the ULQ mode, the device consumes low quiescent current (see the ELECTRICAL
CHARACTERISTICS table). Therefore, high efficiency can be obtained in the system stand-by mode. The
TPS51285A/B enters the ULQ mode automatically (no control input signal is required) when both high-side and
low-side MOSFET drivers are OFF state in discontinuous conduction operation. It exits from the ULQ mode when
the PWM comparator detects VFB drops to the internal 2-V VREF and turns on the high-side MOSFET. In the
ULQ mode, all protection functions are active.
D-CAP™ Mode
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 3.
Switching Modulator
VIN
DRVH
R1
L
VFB
PWM
+
R2
+
Control
Logic
and
Divider
VOUT
DRVL
IIND
IC
IOUT
VREF
ESR
RLOAD
Voltage
Divider
VC
COUT
Output
Capacitor
Figure 3. Simplifying the Modulator
The output voltage is compared with internal reference voltage after divider resistors, R1 and R2. The PWM
comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator is
high enough to keep the voltage at the beginning of each ON cycle substantially constant. For the loop stability,
the 0 dB frequency, ƒ0, defined in Equation 2 must be lower than 1/4 of the switching frequency.
f
1
£ SW
f0 =
2p ´ ESR ´ COUT
4
(2)
As ƒ0 is determined solely by the output capacitor characteristics, the loop stability during D-CAP™ mode is
determined by the capacitor chemistry. For example, specialty polymer capacitors have output capacitance in the
order of several hundred micro-Farads and ESR in range of 10 milli-ohms. These yield an f0 value on the order
of 100 kHz or less and the loop is stable. However, ceramic capacitors have ƒ0 at more than 700 kHz, which is
not suitable for this operational mode.
Enable and Power Good
VREG3 is an always-on regulator (TPS51285A and TPS1285B), For TPS51285B, VREG5 is an always-on LDO,
too (See Table 1 and Table 2). When VIN exceeds the VIN-UVLO threshold VREG3 turns on. For TPS51285B,
VREG5 turns on when VREG3 exceeds 2.4V. For TPS51285A, VREG5 turns on when either EN1 or EN2 enters
ON state in addition to the above VREG3 threshold. CH1’s or CH2’s output starts ramping up when the
corresponding EN pin is in the ON state and VREG5 is larger than the VREG5-UVLO. VCLK initiates switching
when EN1 enters ON state. The state controls are shown in Table 1 and Table 2.
12
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TPS51285A and TPS51285B have a PGOOD open drain output. During the start-up, if the feedback voltages for
both CH1 and CH2 exceed 90% of the reference voltage, the PGOOD becomes high with defined PGOOD delay
time. During the operation, if the feedback voltage rise beyond 115%(typ) for either switching regulator, PGOOD
turns low. If the feedback voltage falls below 60%(typ), the PGOOD turns low.
Table 1. Enabling and PGOOD State (TPS51285A; Always-on VREG3)
EN1
EN2
VREG5
VREG3
CH1 (5Vout)
CH2 (3.3Vout)
VCLK
PGOOD
OFF
OFF
OFF
ON
OFF
OFF
OFF
Low
Low
ON
OFF
ON
ON
ON
OFF
ON
OFF
ON
ON
ON
OFF
ON
OFF
Low
ON
ON
ON
ON
ON
ON
ON
High
Table 2. Enabling and PGOOD State (TPS51285B; Always-on VREG3 and VREG5)
EN1
EN2
VREG5
VREG3
CH1 (5Vout)
CH2 (3.3Vout)
VCLK
PGOOD
OFF
OFF
ON
ON
OFF
OFF
OFF
Low
ON
OFF
ON
ON
ON
OFF
ON
Low
OFF
ON
ON
ON
OFF
ON
OFF
Low
ON
ON
ON
ON
ON
ON
ON
High
VIN-UVLO_threshold
VIN
VREG3
EN_threshold
EN1
VREG5-UVLO_threshold
VREG5
95% of VOUT
Soft-Start Time (tSS)
Soft-Start Time
(tSS(ramp))
5-V VOUT
EN_threshold
EN2
95% of VOUT
3.3-V VOUT
Soft-Start Time
(tSS(ramp))
Soft-Start Time (tSS)
PGOOD
PG start-up delay (tPGDLY)
Figure 4. TPS51285A Timing Diagram of Start-up
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VIN-UVLO_threshold
VIN
2.4 V
VREG3
VREG5
EN_threshold
EN1
95% of VOUT
Soft-Start Time (tSS)
Soft-Start Time
(tSS(ramp))
5-V VOUT
EN_threshold
EN2
95% of VOUT
3.3-V VOUT
Soft-Start Time
(tSS(ramp))
Soft-Start Time (tSS)
PG start-up delay (tPGDLY)
PGOOD
Figure 5. TPS51285B Timing Diagram of Start-up
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Soft-Start and Discharge
The TPS51285A and TPS51285B operates an internal, 0.8-ms, voltage servo soft-start for each channel. When
the ENx pin becomes higher than the enable threshold voltage, an internal DAC begins ramping up the reference
voltage to the target (2 V). Smooth control of the output voltage is maintained during start-up. When ENx
becomes lower than the lower level of threshold voltage, the device discharges outputs using internal MOSFETs
through VO1 (CH1) and SW2 (CH2).
VREG5 and VREG3 Linear Regulators
There are two 100-mA standby linear regulators that output 5 V and 3.3 V, respectively. The VREG5 provides
the current for gate drivers. VREG3 functions as the main power supply for the analog circuitry of the device.
A ceramic capacitor with a value of 4.7 µF or larger (X5R grade or better) is required for each of VREG5 and
VREG3. It should be placed close to the VREG5 pin and the VREG3 pin respectively to stabilize the LDOs.
The VREG5 pin switchover function is asserted when three conditions are present:
• CH1 is not in UVP/OVP condition
• CH1 is not in OCL condition
• VO1 voltage is higher than (VREG5 -1V)
In
•
•
•
this switchover condition three things occur:
the internal 5-V LDO regulator is shut off
the VREG5 output is connected to VO1 by internal switchover MOSFET
VREG3 input pass is changed from VIN to VO1
VCLK for Charge Pump
A 256 kHz VCLK signal can be used for the external charge pump circuit. The VCLK signal becomes available
when EN1 enters ON state. VCLK driver circuit is driven by VO1 voltage. In a design that does not require VCLK
output, tie 200 Ω between VCLK pin and GND so that VCLK is turned off.
Overcurrent Protection
TPS51285A and TPS51285B have cycle-by-cycle over current limiting control. The inductor current is monitored
during the OFF state and the controller maintains the OFF state during the inductor current is larger than the
overcurrent trip level. In order to provide both good accuracy and cost effective solution, the device supports
temperature compensated MOSFET RDS(on) sensing. The CSx pin should be connected to GND through the CS
voltage setting resistor, RCS. The CSx pin sources CS current (ICS) which is 50 µA typically at room temperature,
and the CSx terminal voltage (VCS= RCS × ICS) should be in the range of 0.2 V to 2 V over all operation
temperatures. The trip level is set to the OCL trip voltage (VTRIP) as shown in Equation 3.
R ´I
VTRIP = CS CS + 1 mV
8
(3)
The inductor current is monitored by the voltage between GND pin and SWx pin so that SWx pin should be
connected to the drain terminal of the low-side MOSFET properly.The CS pin current has a 4500 ppm/°C
temperature slope to compensate the temperature dependency of the RDS(on). GND is used as the positive
current sensing node so that GND should be connected to the source terminal of the low-side MOSFET.
As the comparison is done during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load
current at the overcurrent threshold, IOCL(DC), can be calculated as shown in Equation 4.
IIND(ripple )
(VIN - VOUT )´ VOUT
V
V
1
IOCL(DC) = TRIP +
= TRIP +
´
RDS(on )
2
RDS(on ) 2 ´ L ´ fSW
VIN
(4)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. Eventually, it ends up with crossing the undervoltage protection threshold and
shutdown both channels.
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Output Overvoltage and Undervoltage Protection
TPS51285A and TPS51285B assert the overvoltage protection (OVP) when VFBx voltage reaches OVP trip
threshold level. When an OVP event is detected, the controller changes the output target voltage to 0 V. This
usually turns off DRVH and forces DRVL to be on. When the inductor current begins to flow through the low-side
MOSFET and reaches the negative OCL, DRVL is turned off and DRVH is turned on. After the on-time expires,
DRVH is turned off and DRVL is turned on again. This action minimizes the output node undershoot due to LC
resonance. When the VFBx reaches 0 V, the driver output is latched as DRVH off and DRVL on. The
undervoltage protection (UVP) latch is set when the VFBx voltage remains lower than UVP trip threshold voltage
for 250 μs or longer. In this fault condition, the controller latches DRVH low and DRVL low and discharges the
outputs through VO1(CH1) and SW2 (CH2). UVP detection function is enabled after 1.1 ms of SMPS operation
to ensure startup. Toggle ENx to clear the fault latch.
Undervoltage Lockout (UVLO) Protection
TPS51285A and B have undervoltage lock out protection at VIN, VREG5 and VREG3. When each voltage is
lower than their UVLO threshold voltage, both SMPS are shut-off. They are non-latch protections.
Over-Temperature Protection
TPS51285A and TPS51285B features an internal temperature monitor. If the temperature exceeds the threshold
value (typically 140°C), the device is shut off including LDOs. This is non-latch protection.
REFERENCE DESIGN
Application Schematic
This session describes a simplified design procedure for 5 V and 3.3 V outputs application using TPS1285A and
TPS1285B. Figure 6 shows the application schematic.
VIN
C2
U1
C1
R7
Q1
C7
R9
L1
12 VIN
C8
17 VBST1
VBST2
16 DRVH1
DRVH2 10
R8
9
R10
VOUT
5V
18 SW1
SW2
Q2
L2
VOUT
3.3 V
8
C4
C3
15 DRVL1
DRVL2 11
14 VO1
R1
R3
R2
2
VFB1
VFB2
4
1
CS1
CS2
5
PGOOD
7
PGOOD
EN2
6
EN 3.3 V
VREG3
3
VREG3
(3.3-V LDO)
19 VCLK
EN 5V
VREG5
(5-V LDO)
R4
R6
20 EN1
13 VREG5
GND
R5
Thermal-Pad
C5
R11
C6
Figure 6. Application Schematic
16
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Table 3. Key External Components
REFERENCE DESIGNATOR
FUNCTION
MANUFACTURER
PART NUMBER
L1
Output Inductor (5-Vout)
ALPS
GLMC3R303A
L2
Output Inductor (3.3-Vout)
ALPS
GLMC2R203A
C3
Output Capacitor (5-Vout)
SANYO
6TPS220MAZB x 2
C4
Output Capacitor (3.3-Vout)
SANYO
6TPS220MAZB x 2
Q1
MOSFET (5-Vout)
TI
CSD87330Q3D
Q2
MOSFET (3.3-Vout)
TI
CSD87330Q3D
C5
Decoupling Capacitance
(VREG5)
MURATA
GRM188B30J475ME84
C6
Decoupling Capacitance
(VREG3)
MURATA
GRM188B30J475ME84
Design Procedure
Step 1. Determine the Specifications:
•
•
•
VIN range = 5.5 V to 20 V
CH1 output: Vout1 = 5 V and Iout1 = 6 A
CH2 output: Vout2 = 3.3 V and Iout2 = 7 A
Step 2. Determine the Value of Voltage Divider Resistors
The output voltage is determined by 2-V internal voltage reference and the resistor dividers (R1 and R2/ R4 and
R5). To achieve higher efficiency at light load condition, for 5 V output, select R2 = 100 kΩ and R1 = 150kΩ for
3.3V output R5 = 200 kΩ and R4 = 130 kΩ. Determine R1 using Equation 5. (for 3.3 V, replace R1 with R4 and
R2 with R5). For applications where signal-to-noise performance is more valuable than light load efficiency, set
R2 (R5) to 10kΩ.
R1 =
(VOUT - 0.5 ´ VRIPPLE - 2.0 ) ´ R2
2.0
(5)
Step 3. Determine Inductance and Choose the Inductor
Smaller inductance yields better transient performance but the consequence is larger ripple and lower efficiency.
Larger value has the opposite characteristics. It is the common practice to limit the inductor ripple current to 25%
to 50% of the maximum output current. In this case, use 50% at VIN = 20 V.
L1 =
1
IIND(ripple) × fSW(CH1)
×
(VIN(max) - VOUT ) × VOUT
VIN(max)
= 3.13 mH
(6)
Where
• IIND(ripple) = 6 A x 0.5, VOUT = 5 V. VIN(MAX) = 20 V, ƒSW(CH2) = 400 kHz
L2 =
1
IIND(ripple) × fSW(CH2)
×
(VIN(max) - VOUT ) × VOUT
VIN(max)
= 1.66 mH
(7)
Where
• IIND(ripple) = 7 A x 0.5, VOUT = 3.3 V. VIN(MAX) = 20 V, ƒSW(CH2) = 475 kHz
For this design, L1 = 3.3 µH and L2 = 2.2 µH are chosen.
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Step 4. Choose Output Capacitor(s)
For the loop stability, the 0 dB frequency, ƒ0, defined in Equation 8 must be lower than 1/4 of the switching
frequency (entire VIN range).
f0 =
f
1
£ sw
2p ´ ESR ´ CO
4
(8)
Determine ESR to meet required ripple voltage below for better jitter performance. A quick approximation is as
shown in Equation 9.
V
´ 20[ mV ] ´ (1 - D ) 20[ mV ] ´ L ´ f SW
ESR = OUT
=
2[V ] ´ I IND( Ripple)
2[V ]
(9)
where
• D as the duty-cycle factor
• the required output ripple voltage slope is approximately 20 mV per tSW (switching period) in terms of VFB
terminal
VVOUT
Slope (1)
Jitter
(2)
Slope (2)
Jitter
20 mV
(1)
VREF
VREF +Noise
tON
tOFF
UDG-12012
Figure 7. Ripple Voltage Slope and Jitter Performance
This design uses 2 x 220 µF (35 mΩ) for each output.
Step 5. Determine Over Current Limit (OCL) Setting Resistors
Use Equation 10 to determine the over current limit setting resistor (R3/ R6) which is connected from CS1/CS2 to
GND.
RCS =
8
´ éë( IOCL( DC ) - I IND( ripple) ´ 0.5) ´ RDS (ON ) - 1mV ùû
ICS
(10)
Confirm CS voltage is within the range of 0.2 V to 2 V over all operation temperature using Equation 11.
VCS = RCS ´ ICS é(25o C - TA ) ´ TC CS ´10-6 + 1ù
úû
ëê
(11)
Where
• TA is an operation temperature
Confirm inductor ripple current is less than half of OCL (valley) using Equation 12
I IND( ripple) <
IOCL(VALLEY )
2
æ RCS ´ ICS
ö
+ 1mV ÷
ç
8
è
ø
=
2 ´ RDS (ON )
(12)
This design uses CSD87330Q3D (low-side RDS(ON) typ = 4.7 mΩ) and R3 (RCS - CH1) = 6.19 kΩ, R6 (RCS - CH2)
= 6.65 kΩ.
18
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Step 6. Select Decoupling Capacitors
Use ceramic capacitors with a value of 4.7 µF or larger (X5R grade or better) for C5 (VREG5) and C6 (VREG3).
For the VIN input capacitors (C1 and C2), 2 x 10 µF (1206, 25V, X5R) MLCC per channel is used in the design.
Tighter tolerances and higher voltage ratings are always appreciated.
Step 7. Peripheral Components
For high-side N-channel MOSFET drive circuit, connect boot strap capacitor between VBSTx and SWx. To
control gate driver strength, adding a resistor (reserved space) is recommended. This design uses 0.1 µF (C7
and C8), 0 Ω (R7 and R8), 6.8 Ω (R9) and 8.2 Ω (R10).
Step 8. Charge Pump Design
Figure 6 shows a circuit design without an external charge pump. Add R11 = 200Ω from VCLK to GND to disable
VCLK signal. Figure 8 shows the design with an external charge pump. D1 (4-in 1 Diode: BAS40DW-04) should
be tied to the 5V switcher output and 4 x 0.1 µF (C9, C10, C11 and C12) is used.
VIN
C2
U1
C1
Q1
R7
C7
R9
L1
12 VIN
C8
17 VBST1
VBST2
16 DRVH1
DRVH2 10
R8
9
Q2
R10
VOUT
5V
18 SW1
SW2
L2
VOUT
3.3 V
8
C4
C3
15 DRVL1
R3
R2
2
VFB1
VFB2
4
1
CS1
CS2
5
PGOOD
7
PGOOD
EN2
6
EN 3.3 V
VREG3
3
VREG3
(3.3-V LDO)
C12
EN 5V
Charge-pump
Output
D1
VREG5
(5-V LDO)
20 EN1
13 VREG5
GND
R5
Thermal-Pad
C5
C10
R4
R6
19 VCLK
C11
C9
DRVL2 11
14 VO1
R1
C6
Figure 8. Application Schematic (with Charge pump)
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Layout Considerations
Good layout is essential for stable power supply operation. Follow these guidelines for an efficient PCB layout.
Placement
• Place voltage setting resistors close to the device pins.
• Place bypass capacitors for VREG5 and VREG3 close to the device pins.
Routing (Sensitive analog portion)
• Use small copper space for VFBx. There are short and narrow traces to avoid noise coupling.
• Connect VFB resistor trace to the positive node of the output capacitor. Routing inner layer away from power
traces is recommended.
• Use short and wide trace from VFB resistor to vias to GND (internal GND plane).
Routing (Power portion)
• Use wider/shorter traces of DRVL for low-side gate drivers to reduce stray inductance.
• Use the parallel traces of SW and DRVH for high-side MOSFET gate drive in a same layer or on adjoin
layers, and keep them away from DRVL.
• Use wider/ shorter traces between the source terminal of the high-side MOSFET and the drain terminal of the
low-side MOSFET
• Thermal pad is the GND terminal of this device. Five or more vias with 0.33-mm (13-mils) diameter connected
from the thermal pad to the internal GND plane should be used to have strong GND connection and help heat
dissipation.
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140
16
120
14
VIN Supply Current 2 (µA)
VIN Supply Current 1 (µA)
TYPICAL CHARACTERISTICS
100
80
60
40
20
12
10
8
6
4
2
0
0
±50
±25
0
25
50
75
100
Junction Temperature (ƒC)
±50
125
±25
0
25
50
75
100
125
Junction Temperature (ƒC)
C003
Figure 9. VIN Supply Current 1 vs. Junction Temperature
C005
Figure 10. VIN Supply Current 2 vs. Junction Temperature
120
50
45
VIN Stand-By Current (µA)
VO1 Supply Current (µA)
100
80
60
40
20
40
35
30
25
20
15
10
TPS51285A
5
0
TPS51285B
0
±50
±25
0
25
50
75
100
Junction Temperature (ƒC)
±50
125
±25
0
25
50
75
100
125
Junction Temperature (ƒC)
C004
C006
Figure 11. VO1 Supply Current 1 vs. Junction Temperature
Figure 12. VIN Stand-By Current vs. Junction Temperature
100
310
80
290
VCLK Frequency (kHz)
CS Source Current (µA)
90
70
60
50
40
30
20
270
250
230
10
0
210
-50
-25
0
25
50
75
Junction Temperature (ƒC)
100
125
-50
-25
Figure 13. CS Source Current vs. Junction Temperature
0
25
50
75
100
125
Junction Temperature (ƒC)
C001
C002
Figure 14. Clock Frequency vs. Junction Temperature
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TYPICAL CHARACTERISTICS (continued)
100
100
VOUT1 = 5 V
98
VOUT2 = 3.3 V
95
96
Efficiency (%)
Efficiency (%)
94
92
90
88
86
VVIN
7.4VV
IN ==7.4
VVIN=11.1V
IN = 11.1 V
VVIN=14.8V
IN = 14.8 V
VVIN=20.5V
IN = 20.5 V
84
82
80
0.001
0.01
0.1
1
85
80
VVIN
7.4VV
IN ==7.4
VVIN=11.1V
IN = 11.1 V
VVIN=14.8V
IN = 14.8 V
VVIN=20.5V
IN = 20.5 V
75
70
0.001
10
Output Current (A)
90
0.01
0.1
1
10
Output Current (A)
C007
Figure 15. Efficiency vs. Output Current
C009
Figure 16. Efficiency vs. Output Current
3.40
5.15
VOUT1 = 5 V
VOUT2 = 3.3 V
Output Voltage (V)
Output Voltage (V)
5.10
5.05
5.00
4.95
7.4VV
VVIN
IN ==7.4
VVIN=11.1V
IN = 11.1 V
VVIN=14.8V
IN = 14.8 V
VVIN=20.5V
IN = 20.5 V
4.90
4.85
0.001
0.01
0.1
1
Output Current (A)
3.35
3.30
7.4VV
VVIN
IN ==7.4
VVIN=11.1V
IN = 11.1 V
VVIN=14.8V
IN = 14.8 V
VVIN=20.5V
IN = 20.5 V
3.25
3.20
0.001
10
0.01
0.1
1
Output Current (A)
C008
Figure 17. Load Regulation
10
C010
Figure 18. Load Regulation
3.40
5.15
VOUT1 = 5 V
VOUT2 = 3.3 V
Output Voltage (V)
Output Voltage (V)
5.10
5.05
5.00
4.95
3.35
3.30
3.25
IIout1=0A
OUT1 = 0A
4.90
IIout1=6A
OUT1 = 6A
4.85
5
10
15
20
Input Voltage (V)
25
IIout1=0A
OUT2 = 0A
IIout1=6A
OUT2 = 7A
3.20
5
C011
Figure 19. Line Regulation
22
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10
15
Input Voltage (V)
20
25
C012
Figure 20. Line Regulation
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TYPICAL CHARACTERISTICS (continued)
600
VIN=7.4V
V
IN = 7.4 V
V
VIN=12V
IN = 12 V
V
VIN=20V
IN = 20 V
500
Switching Frequency (kHz)
Switching Frequency (kHz)
600
400
300
200
100
VIN=7.4V
V
IN = 7.4 V
V
VIN=12V
IN = 12 V
V
VIN=20V
IN = 20 V
500
400
300
200
100
VOUT1 = 5 V
0
0.001
0.01
0.1
1
VOUT2 = 3.3 V
0
0.001
10
Output Current (A)
1
10
C016
Figure 22. Switching Frequency vs. Output Current
600
600
500
500
Switching Frequency (kHz)
Switching Frequency (kHz)
0.1
Output Current (A)
Figure 21. Switching Frequency vs. Output Current
400
300
200
100
0.01
C015
VOUT1 = 5 V
IOUT1 = 6 A
0
400
300
200
100
VOUT2 = 3.3 V
IOUT2 = 7 A
0
5
10
15
20
Input Voltage (V)
25
5
10
15
Figure 23. Switching Frequency vs. Input Voltage
20
25
Input Voltage (V)
C013
C014
Figure 24. Switching Frequency vs. Input Voltage
VIN = 7.4V
VIN = 7.4V
IOUT2 (0.7 6.3A, 0.5A/Ps)
IOUT1 (0.6 5.4A, 0.5A/Ps)
VOUT2 (100mV/div)
VOUT1 (100mV/div)
IOUT1 (2A/div)
100 Ps/div
IOUT2 (2A/div)
Figure 25. Load Transient
100 Ps/div
Figure 26. Load Transient
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS51285A TPS51285B
23
TPS51285A
TPS51285B
SLVSBX0 – APRIL 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
VOUT1 (2V/div)
VOUT1 (2V/div)
VOUT2 (2V/div)
VOUT2 (2V/div)
PGOOD (5V/div)
PGOOD (5V/div)
EN1 = EN2 (5V/div)
EN1 = EN2 (5V/div)
Figure 27. Start-Up
24
Figure 28. Output Discharge
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS51285A TPS51285B
PACKAGE OPTION ADDENDUM
www.ti.com
20-May-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS51285ARUKR
ACTIVE
WQFN
RUK
20
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
1285A
Samples
TPS51285ARUKT
ACTIVE
WQFN
RUK
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
1285A
Samples
TPS51285BRUKR
ACTIVE
WQFN
RUK
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
1285B
Samples
TPS51285BRUKT
ACTIVE
WQFN
RUK
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
1285B
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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