TPS51601ADRBR

TPS51601A www.ti.com SLUSAP3 – MAY 2012 Dual High Efficiency Synchronous MOSFET Driver Check for Samples: TPS51601A FEATURES DESCRIPTION • • • The TPS51601A is a synchronous buck MOSFET driver with integrated boost switch. This highperformance driver is capable of driving high-side and low-side side N-channel FETs with the highest speed and lowest switching loss. Adaptive dead-time control and shoot-through protection are included. 1 • • • • • High Voltage Synchronous Buck Driver Integrated Boost Switch for Bootstrap Action Adaptive Dead Time Control and Shootthrough Protection 0.4-Ω Sink Resistance for Low-side Drive 1.0-Ω Source Resistance for High-side Drive SKIP Pin to Improve Light-Load Efficiency Adaptive Zero-Crossing Detection for Optimal Light-Load Efficiency 8-Pin 3 mm × 3 mm SON (DRB) Package APPLICATIONS • • • • Mobile core regulator products High frequency DC-DC Converters High input voltage DC-DC converters Multiphase DC-DC converters The TPS51601A is available in the space-saving 8pin 3 mm × 3 mm SON package and operates between –40°C and 105°C. This is for graphic spacing. Do not translate. XXXXX XXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX XX XXX XXXXXXXXXXXXXXXXXXXXXXXXXXX This is for graphic spacing. Do not translate. XXXXX XXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX XX XXX XXXXXXXXXXXXXXXXXXXXXXXXXXX SIMPLIFIED APPLICATION VIN TPS51601A BST DRVH VOUT SKIP SKIP SW PWM PWM VDD GND DRVL PGND PGND PGND UDG-11212 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS51601A SLUSAP3 – MAY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) TA PACKAGE –40°C to 105°C Plastic Small Outline No-Lead (SON) (1) (2) ORDERABLE NUMBER PINS TPS51601ADRBT TPS51601ADRBR 8 TRANSPORT MEDIA MINIMUM QUANTITY Tape-and-reel (large) 250 Tape-and-reel (small) 3000 ECO PLAN Green (RoHS and no Sb/Br) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) Input voltage Output voltages MIN MAX VDD -0.3 6 PWM, SKIP -0.3 6 BST to SW -0.3 6 DRVH to SW -0.3 6 DRVL -0.3 6 SW UNIT V V -1 32 -0.3 0.3 V Operating junction temperature, TJ -40 125 °C Storage temperature, Tstg -55 150 °C Ground (1) (2) (3) GND Stresses beyond those listed in this table may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the RECOMMENDED OPERATING CONDITIONS table is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. Voltage values are with respect to the corresponding LL terminal. THERMAL INFORMATION TPS51601 THERMAL METRIC (1) DRB UNITS 8 PINS θJA Junction-to-ambient thermal resistance (2) 42.6 θJCtop Junction-to-case (top) thermal resistance (3) 3.0 (4) θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (5) ψJB Junction-to-board characterization parameter (6) 19.1 (7) 12.7 θJCbot (1) (2) (3) (4) (5) (6) (7) 2 Junction-to-case (bottom) thermal resistance 18.9 62.1 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS51601A TPS51601A www.ti.com SLUSAP3 – MAY 2012 RECOMMENDED OPERATING CONDITIONS MIN Input voltages Output voltages VDD MAX 5.5 PWM, SKIP -0.1 5.5 BST to SW -0.1 5.5 DRVH to SW -0.1 5.5 DRVL -0.1 5.5 -1 30 SW Ground TYP 4.5 GND Operating junction temperature, TJ Product Folder Link(s): TPS51601A V V -0.1 0.1 V -40 105 °C Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated UNIT 3 TPS51601A SLUSAP3 – MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VVDD = 5.0 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX PWM = HI 160 220 PWM = LO 500 PWM = float 50 UNIT SUPPLY, UNDERVOLTAGE LOCKOUT IVDD VDD bias current µA VUVLO(h) VDD UVLO ‘OK’ threshold 3.5 3.7 3.9 V VUVLO(l) VDD UVLO fault threshold 3.3 3.5 3.7 V VUVLO(hys) VDD UVLO hysteresis 0.2 V PWM INPUT VIH(pwm) HIGH-level PWM input VIL(pwm) LOW-level PWM input 4.0 V RVDD-PWM VDD-to-PWM resistance 30 RPWM-GND PWM-to-GND resistance 20 VPWM(tri) PWM tri-state voltage 0.7 PWM floating 1.5 V kΩ kΩ 2.5 V SKIP INPUT VIH(skip) HIGH-level SKIP input logic VIL(skip) LOW-level SKIP input logic ILSKIP-GND SKIP-to-GND leakage 2.2 V VSKIP = 5 V 0.7 V 2 µA GATE DRIVE OUTPUT RDRVH DRVH on resistance RDRVL DRVL on resistance Source resistance, (VBST –VLL) = 5 V, HIGH-state (VBST – VDRVH) = 0.1 V 1.0 2.5 Sink resistance, (VBST –VLL) = 5 V, LOW-state (VDRVH – VLL) = 0.1 V 0.5 1.5 Source resistance, (VVDD – GND) = 5 V, HIGH-state, VVDD – VDRVL) = 0.1V 0.8 1.5 Sink resistance, VDD – GND = 5 V LOW-state, VDRVL – GND = 0.1 V 0.4 1.0 DRVH rising, CDRVH = 3.3 nF 15 35 DRVH falling, CDRVH = 3.3 nF 10 35 DRVL rising, CDRVL = 3.3 nF 15 35 DRVL, falling, CDRVL = 3.3 nF 10 35 Ω Ω TIMING CHARACTERISTICS tDRVH DRVH transition time tDRVL DRVL transition time tNONOVLP Driver non-overlap time tDLY(rise) PWM rising to drive output delay tDLY(fall) tDLY1 DRVH LOW to DRVL HIGH 5 20 DRVL LOW to DRVH HIGH 5 20 ns ns ns DCM mode: PWM rising to DRVH rising 25 CCM mode: PWM rising to DRVL falling 25 PWM falling to drive output delay PWM falling to DRVH falling 25 ns 3-state propagation delay to LOW PWM floating to PWM LOW 40 ns tDLY2 3-state propagation delay to HIGH PWM floating ti PWM HIGH tTS(hold) 3-state hold-off time PWM entering tri-state from HIGH or LOW tSKIP(pdh) ns 50 ns 150 ns SKIP LOW-to-HIGH propagation delay 15 ns tSKIP(pdl) SKIP HIGH-to-LOW propagation delay 15 tDRVH(min) Minimum DRVH width tDRVL(min) Minimum DRVL width Minimum DRVL width before Zero-crossing can turn OFF DRVL ns 80 ns 400 500 ns 10 20 Ω 2 µA BOOT-STRAP SWITCH (BST) RBST BST switch on-resistance IBST = 10 mA IBST(leak) BST switch leakage current VBST = 34 V, VSW = 28 V 4 Submit Documentation Feedback 4 Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS51601A TPS51601A www.ti.com SLUSAP3 – MAY 2012 DEVICE INFORMATION QFN (DRB) PACKAGE 8 PINS (TOP VIEW) BST 1 SKIP 2 8 DRVH 7 SW TPS51601A PWM 3 6 VDD GND 4 5 DRVL PIN FUNCTIONS PIN NAME I/O DESCRIPTION BST I High-side, N-channel FET bootstrap voltage input, supply for high-side driver DRVH O High-side, N-channel FET gate drive output. DRVL O Low-side, synchronous N-channel FET gate drive output GND – Low-side, synchronous N-channel FET gate drive return and device ground. PWM I PWM input. This defines the on-time for the high-side FET of the converter. Input is coming from PWM controller. A 3-state voltage on this pin turns OFF both the high-side (DRVH) and low-side drivers (DRVL) PwrPAD – Thermal pad. This is a non-electrical pad and is recommended to be connected to GND. SKIP I If SKIP is LOW, then the inductor current zero-crossing is active and DRVL turns off when inductor current goes to zero. (discontinuous conduction mode active) If SKIP is HIGH, then the DRVL stays HIGH as long as PWM stays LOW. (forced continuous conduction mode) SW I/O VDD I High-side N-channel FET gate drive return. Also used as input for sensing inductor current for zero-crossing. 5-V power supply input for the device. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS51601A 5 TPS51601A SLUSAP3 – MAY 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM VDD + DRVL BST DRVH Level Shift + + SKIP + VUVLO SW 1V + VDD + PWM 3-State Logic + 1V VDD DRVL GND TPS51601A UDG-11213 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS51601A TPS51601A www.ti.com SLUSAP3 – MAY 2012 TYPICAL CHARACTERISTICS Figure 1. PWM Rising to DRVL Falling Figure 2. DRVL Falling to DRVH rising Figure 3. PWM Falling to DRVH Falling Figure 4. SW-Node Falling to DRVL Rising Figure 5. 3-State Entry on DRVL Figure 6. 3-State Entry on DRVH Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS51601A 7 TPS51601A SLUSAP3 – MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 8 Figure 7. 3-State Exit on DRVL Figure 8. 3-State Exit on DRVH Figure 9. FCCM Exit and SKIP Mode Entry Figure 10. SKIP Mode Exit and FCCM Entry Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS51601A TPS51601A www.ti.com SLUSAP3 – MAY 2012 TYPICAL CHARACTERISTICS For Figure 11 through Figure 16 high-side FET used is CSD17302Q5A and low-side FET used is CSD17303Q5. 95 95 fSW = 380 kHz 90 90 85 85 Efficiency (%) Efficiency (%) fSW = 275 kHz 80 75 70 65 5 10 15 20 Output Current (A) 25 30 75 70 VIN = 9 V VIN = 20 V 0 80 65 35 VIN = 9 V VIN = 20 V 0 Figure 11. Efficiency vs. Output Current 5 10 15 20 Output Current (A) 25 95 fSW = 500 kHz fSW = 600 kHz 90 90 85 85 Efficiency (%) Efficiency (%) 35 Figure 12. Efficiency vs. Output Current 95 80 75 70 65 30 VIN = 9 V VIN = 20 V 0 5 10 15 20 Output Current (A) 25 30 35 80 75 70 65 VIN = 9 V VIN = 20 V 0 5 10 15 20 Output Current (A) 25 30 35 Figure 13. Efficiency vs. Output Current Figure 14. Efficiency vs. Output Current Figure 15. Gate Driver Waveforms Using TPS51640 Controller and TPS51601A Driver at VIN = 9 V Figure 16. Gate Driver Waveforms Using TPS51640 Controller and TPS51601A Driver at VIN = 20 V Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS51601A 9 TPS51601A SLUSAP3 – MAY 2012 www.ti.com DETAILED DESCRIPTION UVLO The TPS51601A includes an undervoltage lockout circuit that disables the driver and external power FETs in an OFF state when the input supply voltage, (VVDD) is insufficient to drive external power FET reliably. During the power-up sequence, both gate drive outputs remain low until the VDD voltage reaches UVLO-H threshold, typically 3.7 V. Once the UVLO threshold is reached, the condition of the gate drive outputs is defined by the input PWM and SKIP signals. During the power-down sequence, the UVLO threshold is set lower, typically 3.5 V. PWM Input Once the input supply voltage is above the UVLO threshold, the gate drive outputs are defined by the PWM input and SKIP input. Prior to PWM going HIGH, both the gate drive outputs, (DRVH and DRVL) are held LOW. The DRVL is LOW until the first PWM HIGH pulse to support pre-biased start-up. Once PWM goes HIGH for the first time, DRVH goes HIGH. Then, when PWM goes LOW, DRVH goes LOW first. After the non-overlap time, DRVL goes HIGH. PWM PWM DRVL tDLY(fall) tDLY(fall) tDLY(rise) 1.0 V DRVL turned OFF by zero-crossing tNONOVLP tNONOVLP 1.0 V DRVH tNONOVLP DRVH 1.0 V UDG-11131 UDG-11129 Figure 17. Continuous Conduction Mode Waveforms tDLY(rise) Figure 18. Discontinuous Conduction Mode Waveforms SKIP/FCCM Mode Operation The TPS51601A can be configured in two ways. When used as the external driver for Phase 1, this pin connects to the corresponding SKIP pin of the PWM controller. The SKIP pin is active low signal. This means when SKIP is low, then the zero crossing detection circuit of the driver is active. When SKIP is high, the zero-crossing detector is disabled and the converter operates in forced continuous conduction mode (FCCM). Adaptive Zero-Crossing The TPS51601A has an adaptive zero-crossing detector. Zero crossing accuracy is detected by checking the switch-node voltage at an appropriate time after the low-side FET is turned OFF by DRVL going low. Then the zero-crossing comparator offset is updated based on previous result. After several zero-crossing events, the comparator offset is optimized to give the best efficiency. Adaptive Dead-Time Control (Anti-Cross Conduction) The TPS51601A has an adaptive dead-time control logic to minimize the non-overlap time between DRVH and DRVL signals. The internal signal to the low-side driver goes HIGH only when the DRVH-SW voltage goes below approximately 1 V and DRVH goes below approximately 1 V to ensure the high-side MOSFET has turned OFF. Additional driver delays ensure that there is some non-overlap time between DRVH falling edge and DRVL rising edge. Similarly, the internal signal to the DRVH goes high only after DRVL-GND goes below 1 V. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS51601A TPS51601A www.ti.com SLUSAP3 – MAY 2012 Integrated Boost-Switch To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the conventional diode from VDD to BST is replaced by a FET which is gated by DRVL signal. APPLICATION INFORMATION Figure 19 shows a typical application. Resistors R1 and R2 can be used if necessary to reduce the switch-node ringing. C5 0.1 mF R1 TPS51601A BST VIN Q1 CSD17302Q5A DRVH L1 0.36 mH 0.82 mW C7 10 mF C8 10 mF C9 10 mF C10 10 mF VOUT R2 SKIP SKIP SW PWM PWM VDD Q2 CSD17303Q5 GND DRVL C1 470 mF C2 470 mF C6 2.2 mF GND GND GND UDG-11214 Figure 19. Typical Application Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS51601A 11 TPS51601A SLUSAP3 – MAY 2012 www.ti.com PCB Layout Guidelines Figure 20 shows the primary current loops in each phase, numbered in order of importance. The most important loop to minimize the area of is Loop 1, the path from the input capacitor through the high-side and low-side FETs, and back to the capacitor through ground. Loop 2 is from the inductor through the output capacitor, ground and Q2. The layout of the low side gate drive (loops 3a and 3b) is important. The guidelines for gate drive layout are: • Make the low-side gate drive as short as possible (1 inch or less preferred). • Make the DRVL width to length ratio of 1:10, wider (1:5) if possible. • If changing layers is necessary, use at least two vias. • Decouple VDD to GND (CD in Figure 20) with at ceramic capacitor with a value of least a 2.2-µF. VBAT CB CIN 1 Q1 4b DRVH L 4a VCORE LL 2 3b Q2 CD COUT DRVL 3a PGND UDG-11040 Figure 20. Minimizing Current Loops 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS51601A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS51601ADRBR ACTIVE SON DRB 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 601A TPS51601ADRBT ACTIVE SON DRB 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 601A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of