TPS53211
www.ti.com
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
Single-Phase PWM Controller with Light-Load Efficiency Optimization
FEATURES
APPLICATIONS
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.5-V to 19-V Conversion Voltage Range
4.5-V to 14-V Supply Voltage Range
Voltage Mode Control
Skip Mode at Light Load for Efficiency
Optimization
High Precision 0.5% Internal 0.8-V Reference
Adjustable Output Voltage from 0.8 V to
0.7×VIN
Internal Soft-Start
Supports Pre-biased Startup
Supports Soft-Stop
Programmable Switching Frequency from
250 kHz to 1 MHz
Overcurrent Protection
Inductor DCR Sensing for Overcurrent
RDS(on) Sensing for Zero Current Detection
Overvoltage and Undervoltage Protection
Open Drain Power Good Indication
Internal Bootstrap Switch
Integrated High-Current Drivers Powered by
VCCDR
Small 3 mm x 3 mm, 16-Pin QFN Package
•
•
•
Server and Desktop Computer Subsystem
Power Supplies
DDR Memory and Termination Supply
Distributed Power Supply
General DC/DC Converter
DESCRIPTION
TPS53211 is a single phase PWM controller with
integrated high-current drivers. It is used for 1.5 V up
to 19 V conversion voltage.
TPS53211 features a skip mode solution that
optimizes the efficiency at light load condition without
compromising the output voltage ripple. The device
provides pre-biased startup, soft-stop, integrated
bootstrap switch, power good function, EN/Input
UVLO protection. It supports conversion voltages up
to 19 V, and output voltages adjustable from 0.8 V to
0.7×VIN.
The TPS53211 is available in the 3 mm × 3 mm, 16pin, QFN package (Green RoHs compliant and Pb
free) and is specified from –40°C to 85°C.
VIN
Power
Enable Good
8
COMP
7
6
5
EN PGOOD UGATE
FB
BOOT
4
10 VSEN
PHASE
3
LGATE
2
VCCDR
1
9
VOUT
TPS53211
11 FBG
12 CSN
CSP
OSC
VCC
GND
13
14
15
16
PVCC
UDG-11173
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS53211
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PACKAGE
–40°C to 85°C
Plastic QFN
(RGT)
ORDERABLE
DEVICE NUMBER
TPS53211RGTR
TPS53211RGTT
PINS
16
OUTPUT SUPPLY
MINIMUM
QUANTITY
Tape and Reel
3000
Mini Reel
250
ECO PLAN
Green (RoHS and
no Pb/Br)
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC, EN
VCCDR
BOOT
BOOT to PHASE
Input voltage range (2)
PHASE
–0.3
7.7
–0.3
36
dc
–0.3
7.7
transient < 200 ns
–5
7.7
dc
–3
26
–5
30
–0.3
3.6
VVCC > 7.5 V
–0.7
6
VVCC ≤ 7.5 V
–0.7
VCC-1.5
–0.3
36
–0.3
7.7
–5
7.7
COMP
–0.3
3.6
PGOOD
–0.3
15
GND
–0.3
0.3
FBG
–0.3
0.3
UGATE
Electrostatic
discharge
15
transient < 200 ns
CSP, CSN
Ground pins
MAX
dc
FB, VSEN, OSC
Output voltage
range (3)
MIN
–0.3
UGATE to PHASE,
LGATE
dc
transient < 200 ns
Human Body Model (HBM)
UNITS
V
V
V
1500
Charged Device Model (CDM)
V
500
Storage junction temperature
–55
150
°C
Operating junction temperature
–40
150
°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
Voltage values are with respect to the SW terminal.
THERMAL INFORMATION
TPS53211
THERMAL METRIC (1)
QFN
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance
51.3
θJCtop
Junction-to-case (top) thermal resistance
85.4
θJB
Junction-to-board thermal resistance
20.1
ψJT
Junction-to-top characterization parameter
1.3
ψJB
Junction-to-board characterization parameter
19.4
θJCbot
Junction-to-case (bottom) thermal resistance
6
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
TPS53211
www.ti.com
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
–0.1
VVCC+0.1
4.5
7
dc
–0.1
34
dc
–0.1
7
transient < 200ns
–3
7
dc
–1
24
transient < 200ns
–3
28
–0.1
3.3
VCCDR
Input voltage range
BOOT to PHASE
PHASE
FB, VSEN, OSC
CSP, CSN
VVCC > 7.5 V
–0.1
5.5
VVCC ≤ 7.5 V
–0.1
VVCC–2
–0.1
34
–0.1
7
UGATE
Output voltage range
UGATE to PHASE, LGATE
MAX
14
EN
BOOT
TYP
4.5
dc
V
–3
7
COMP
–0.1
3.3
PGOOD
–0.1
12
GND
–0.1
0.1
FBG
–0.1
0.1
Junction temperature range, TJ
–40
125
°C
Operating free-air temperature, TA
–40
85
°C
Ground pins
Copyright © 2011–2012, Texas Instruments Incorporated
transient < 200 ns
UNITS
Submit Documentation Feedback
V
3
TPS53211
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (1)
over operating free-air temperature range, VCC = 12V, PGND = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.25
4.4
UNIT
INPUT SUPPLY
VVCC
VCC supply voltage
Nominal input voltage range
4.5
VPOR
VCC POR threshold
Ramp up; EN =’HI’
4.1
VPORHYS
VCC POR hysteresis
VCCDR POR hysteresis
ICC_STBY
Standby current
EN pin is low. VVCC= 12 V
RBoot
Rds(on) of the boot strap switch
12
200
V
V
mV
60
µA
Ω
10
DRIVER SUPPLY
VCCDR
VCCDR Supply voltage
Nominal input voltage range
VPORDR
VCCDR POR threshold
Ramp up; EN =’HI’
VPORHYSDR
VCCDR POR hysteresis
VCCDR POR hysteresis
ICCDR_STBY
Standby current
EN pin is low. VVCC = 12 V
VVREF
VREF
Internal precision reference voltage
TOLVREF
VREF tolerance
Close loop trim. 0°C ≤ TJ ≤ 70°C
4.5
3.15
7.0
3.32
3.50
220
V
V
mV
100
µA
REFERENCE
0.8
–0.5%
V
0.5%
ERROR AMPLIFIER
UGBW (2)
Unity gain bandwidth
14
MHz
AOL (2)
Open loop gain
80
dB
IFB(int)
FB Input leakage current
IEA(max)
Output sinking and sourcing current
SR (2)
Slew rate
Sourced from FB pin
10
nA
2.5
mA
5
V/µs
ENABLE
VENH
EN logic high
VENL
EN logic low
IEN
EN pin current
2.2
V
600
mV
12
µA
SOFT START
tSS_delay
Delay after EN asserting
EN = ‘HI’ to “switching enabled”
1024/fSW
ms
tPGDELAY
PGOOD startup delay time
PG delay after soft-start begins
1560/fSW
ms
Ramp amplitude
4.5V < VVCC < 12 V
RAMP
2
V
PWM
tMIN(on) (2)
Minimum ON time
DMAX (2)
Maximum duty cycle
40
fSW = 1 MHz
ns
70%
SWITCHING FREQUENCY
fSW(typ)
Typical switching frequency
ROSC = 61.9 kΩ
fSW(min)
Minumum switching frequency
ROSC = 250 kΩ
fSW(max)
Maximum switching frequency
ROSC = 14 kΩ
fSW(tol)
Switching frequency tolerance
ROSC > 12.4 kΩ
360
400
440
kHz
250
kHz
1
MHz
–20%
20%
OVERCURRENT
VOC_TH
(1)
(2)
4
CSP-CSN threshold for DCR
sensing
TA = 25°C
17
20
23
mV
See PS pin description for levels.
Ensured by design. Not production tested.
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
TPS53211
www.ti.com
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
ELECTRICAL CHARACTERISTICS(1) (continued)
over operating free-air temperature range, VCC = 12V, PGND = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GATE DRIVERS
RHDHI (3)
High-side driver sourcing resistance
(VBOOT – VPH) forced to 5 V, high state
1
Ω
RHDLO
High-side driver sinking resistance
(VBOOT – VPH) forced to 5 V, low state
0.5
Ω
RLDHI
Low-side driver sourcing resistance
(VCCDR– GND) = 5 V, high state
0.7
Ω
RLDLO
Low-side driver sinking resistance
VCCDR– GND = 5 V, low state
0.33
Ω
87%
89%
113%
116%
POWER GOOD
VPGDL
PG lower threshold
Measured at VSEN w/r/t VREF
VPGDU
PG upper threshold
Measured at VSEN w//rt VREF
VPGHYS
PG hysteresis
Measured at VSEN w/r/t VREF
tOVPGDLY
PG delay time at OVP
Time from VSEN out of +12.5% of VREF to
PG low
2.3
µs
tUVPGDLY
PG delay time at UVP
Time from VSEN out of –12.5% of VREF to
PG low
2.3
µs
VINMINPG
Minimum VCC voltage for valid PG at Measured at VVCC with 1 mA (or 2 mA) sink
startup.
current on PG pin at startup.
1
V
VPGPD
PG pull-down voltage
Pull down voltage with 4 mA sink current
IPGLK
PG leakage current
Hi-Z leakage current, apply 6.5 V in off state
110%
3.5%
0.2
0.4
V
7.8
12
16.2
µA
110%
113%
116%
87%
89%
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTION
VOVth
OVP threshold
Measured at the VSEN wrt. VREF.
VUVth
UVP threshold
Measured at the VSEN wrt. VREF.
tOVPDLY
OVP delay time
Time from VSEN out of +12.5% of VREF to
OVP fault
2.3
µs
tUVPDLY (3)
UVP delay time
Time from VSEN out of –12.5% of VREF to
UVP fault
80
µs
THERMAL SHUTDOWN
THSD (3)
THSDHYS
(3)
(3)
Thermal shutdown
Latch off controller, attempt soft-stop
Thermal shutdown hysteresis
Controller starts again after temperature has
dropped
130
140
150
40
°C
°C
Ensured by design. Not production tested.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
5
TPS53211
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
www.ti.com
DEVICE INFORMATION
VCCDR
1
LGATE
2
GND
VCC
OSC
CSP
TPS53211
16 PINS
(TOP VIEW)
16
15
14
13
12
CSN
11
FBG
TPS53211
BOOT
4
9
FB
5
6
7
8
COMP
VSEN
EN
10
PGOOD
3
UGATE
PHASE
PIN FUNCTIONS
PIN
DESCRIPTION
I/O
NAME
NO.
BOOT
4
I
Supply input for high-side drive (boot strap pin). Connect capacitor from this pin to SW pin
COMP
8
O
Error amplifier compensation terminal. Type III compensation method is generally recommended for stability.
CSN
12
I
Current sense negative input.
CSP
13
I
Current sense positive input
EN
7
I
Enable.
FB
9
I
Voltage feedback. Use for OVP, UVP and PGD determination.
FBG
11
G
Feedback ground for output voltage sense.
GND
16
G
Logic ground and low-side gate drive return.
PHASE
3
O
Output inductor connection to integrated power devices.
LGATE
2
O
Low-side gate drive output.
OSC
14
O
Frequency programming input.
PGOOD
6
O
Power good output flag. Open drain output. Pull up to an external rail via a resistor.
UGATE
5
O
High-side gate drive output.
VCC
15
I
Supply input for analog control circuitry.
VCCDR
1
I/O
VSEN
10
I
6
Bias voltage for integrated drivers.
Output voltage sense
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
TPS53211
www.ti.com
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
FUNCTIONAL BLOCK DIAGRAM
VCCDR
VSEN
LDO
+
VCCDR UVLO
FBG
BOOT
0.8 V
+
0.8 V x 87%
UV/OV
Threshold
Generation
UV
UV
Control
Logic
+
0.8 V x 113%
HDRV
UGATE
OV
PHASE
OV
FB
XCON
PWM
+
E/A
COMP
+
0.8 V
Ramp
PWM
LL One-Shot
Overtemp
VOUT Discharge
+
LDRV
LGATE
SS
OSC
Enable
Control
GND
VCC
UVLO
OCP Logic
VCC
TPS53211
OSC
EN
Copyright © 2011–2012, Texas Instruments Incorporated
CSP
CSN
PGOOD
UDG-11172
Submit Documentation Feedback
7
TPS53211
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS
430
Switching Frequency (kHz)
5
Supply Current (mA)
4
3
2
1
0
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
390
380
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G000
Figure 2. Switching Frequency vs. Junction Temperature
120
Measured at VSEN w/r/t VREF
115
Powergood Threshold (%)
Powergood Hysteresis (%)
400
G000
10
8
7
6
5
4
3
2
1
0
−40 −25 −10
PGOOD Lower Hysteresis
PGOOD Upper Hysteresis
5
20 35 50 65 80
Junction Temperature (°C)
95
Submit Documentation Feedback
110
105
Lower Threshold
Upper Threshold
100
95
90
85
110 125
G000
Figure 3. Power Good Hysteresis vs. Junction Temperature
8
410
370
−40 −25 −10
110 125
Figure 1. VCC Current vs. Junction Temperature
9
420
80
−40 −25 −10
5
20 35 50 65 80
Junction Temperature (°C)
95
110 125
G000
Figure 4. Power Good Threshold vs. Junction Temperature
Copyright © 2011–2012, Texas Instruments Incorporated
TPS53211
www.ti.com
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
DETAILED DESCRIPTION
Introduction
The TPS53211 is a single-channel synchronous buck controller with integrated high-current drivers. The
TPS53211 is used for 1.5 V up to 19 V conversion voltage, and provides output voltage from 0.8 V to 0.7 VIN. It
operates with programmable switching frequency ranging from 250 kHz to 1 MHz.
This device employs a skip mode solution that optimizes the efficiency at light-load condition without
compromising the output voltage ripple. The device provides pre-bias startup, integrated bootstrap switch, power
good function, EN/Input UVLO protection. The TPS53211 is available in the 3 mm by 3mm 16-pin QFN package
and is specified from –40°C to 85°C.
Switching Frequency Setting
The clock frequency is programmed by the value of the resistor connected from the OSC pin to ground. The
switching frequency is programmable from 250 kHz to 1 MHz. The relation between the frequency and the OSC
resistance is given by Equation 1.
fSW = 200 +
106
(ROSC ´ 78.5 ) + 150
where
•
•
ROSC is the resistor connected from the OSC pin to ground in kΩ
fSW is the desired switching frequency in kHz
(1)
Soft-Start Function
The soft-start function reduces the inrush current during the start-up. A slow rising reference voltage is generated
by the soft-start circuitry and sent to the input of the error amplifier. When the soft-start ramp voltage is less than
800 mV, the error amplifier uses this ramp voltage as the reference. When the ramp voltage reaches 800 mV, a
fixed 800 mV reference voltage is utilized for the error amplifier. The soft-start function is implemented only when
VCC and VCCDR are above the respective UVLO thresholds and the EN pin is released.
When the soft-start begins, the device initially waits for 1024 clock cycles and then starts to ramp up the
reference. After the reference voltage begins to rise, the PGOOD signal goes high after a 1560 clock-cycle delay.
UVLO Function
The TPS53211 provides UVLO protection for the input supply (VCC) and driver supply (VCCDR). If the supply
voltage is lower than UVLO threshold voltage minus the hysteresis, the device shuts off. When the voltage rises
above the threshold voltage, the device restarts. The typical UVLO rising threshold is 4.25 V for VCC and 3.32 V
for VCCDR. Hysteresis of 200 mV for VCC and 220 mV for VCCDR are also provided to prevent glitch.
Overcurrent Protection
The TPS53211 continuously monitors the current flowing through the inductor. The inductor DCR current sense
is implemented by comparing and monitoring the difference between the CSP and CSN pins. DCR current
sensing requires time constant matching between the inductor and the sensing network:
L
= R´C
DCR
(2)
TPS53211 has two level OC thresholds: 20 mV and 30 mV for the voltage between the CSP and CSN pins.
If the voltage between the CSP and CSN pins exceeds the 20 mV current limit threshold, an OC counter starts to
increment to count the occurrence of the overcurrent events. The converter shuts down immediately when the
OC counter reaches four (4). The OC counter resets if the detected current is lower than the OC threshold after
an OC event. Normal operation can only be restored by cycling the VCC voltage.
If the voltage between the CSP and CSN pins is higher than 30 mV, the device latches off immediately. Normal
operation can be restored only by cycling the VCC voltage.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
9
TPS53211
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
www.ti.com
The TPS53211 has thermal compensation to adjust the OCP threshold in order to reduce the influence of
inductor DCR variation due to temperature change. The OCP level has a change rate of 0.35%/°C.
Overvoltage and Undervoltage Protection
The TPS53211 monitors the VSEN pin voltage to detect the overvoltage and undervoltage conditions. A resistor
divider with the same ratio as on the FB input is recommended for the VSEN input. The overvoltage and
undervoltage thresholds are set to ±13% of VOUT.
When the VSEN voltage is greater than 113% of the reference, the overvoltage protection is activated. The highside MOSFET turns off and the low-side MOSFET turns on. Normal operation can be restored only by cycling the
VCC pin voltage.
When the VSEN voltage is lower than 87% of the reference voltage, the undervoltage protection is triggered and
the PGOOD signal goes low. After 80 µs, the controller is latched off with both the upper and lower MOSFETs
turned off.
After both the undervoltage and overvoltage events, the device is latched off. Normal operation can be restored
only by cycling the VCC pin voltage.
Power Good
The TPS53211 monitors the output voltage through the VSEN. During start up, the power good signal delay after
the reference begins to rise is 1560 clock cycles. After this delay, if the output voltage is within ±9.5% of the
target value, PGOOD signal goes high.
At steady state, if the VSEN voltage is within 113% and 87% of the reference voltage, the power good signal
remains high. If VSEN voltage is outside of this limit, PGOOD pin is pulled low by the internal open drain output.
The PGOOD output is an open drain and requires an external pull-up resistor.
Over-Temperature Protection
The TPS53211 continuously monitors the die temperature. If the die temperature exceeds the threshold value
(140˚C typical), the device shuts off. When the device temperature lowers to 40˚C below the over-temperature
threshold, it restarts and return to normal operation.
10
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
TPS53211
www.ti.com
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
APPLICATION INFORMATION
The following example illustrates the design process and component selection for a single output synchronous
buck converter using TPS53211. The schematic of a design example is shown in Figure 5. The specifications of
the converter are listed in Table 1.
Table 1. Specification of the Single Output Synchronous Buck Converter
PARAMETER
VIN
Input voltage
VOUT
Output voltage
VRIPPLE
Output ripple
IOUT
Output current
fSW
Switching frequency
TEST CONDITION
MIN
10.8
IOUT = 20 A
TYP
MAX
UNIT
12
13.2
V
1.05
V
1% of VOUT
V
20
A
400
kHz
VIN
Power
Enable Good
8
7
COMP
6
5
EN PGOOD UGATE
FB
BOOT
4
10 VSEN
PHASE
3
11 FBG
LGATE
2
12 CSN
VCCDR
1
9
VOUT
TPS53211
CSP
OSC
VCC
GND
13
14
15
16
PVCC
UDG-11173
Figure 5. Typical 12-V Input Application Circuit
Output Inductor Selection
Determine an inductance value that yields a ripple current of approximately 20% to 40% of maximum output
current. The inductor ripple current is determined by Equation 3:
IL(ripple ) =
(VIN - VOUT )´ VOUT
1
´
L ´ fSW
VIN
(3)
The inductor requires a low DCR to achieve good efficiency, as well as enough room above peak inductor
current before saturation.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
11
TPS53211
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
www.ti.com
Output Capacitor Selection
The output capacitor selection is determined by output ripple and transient requirement. When operating in CCM,
the output ripple has three components:
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL)
(4)
VRIPPLE(C) =
IL(ripple)
8 ´ COUT ´ fSW
(5)
VRIPPLE(ESR) = IL(ripple) ´ ESR
VRIPPLE(ESL)
(6)
V ´ ESL
= IN
L
(7)
When a ceramic output capacitor is chosen, the ESL component is usually negligible. In the case when multiple
output capacitors are used, the total ESR and ESL should be the equivalent of the all output capacitors in
parallel.
When operating in DCM, the output ripple is dominated by the component determined by capacitance. It also
varies with load current and can be expressed as shown in Equation 8.
2
VRIPPLE(DCM) =
(a ´ IL(ripple) - IOUT )
2 ´ fSW ´ COUT ´ IL(ripple)
where
a=
•
α is the DCM On-Time coefficient and can be expressed as
tON(dcm )
tON(ccm )
(8)
IL
VOUT
a x IL(ripple)
VRIPPLE
IOUT
t1
axT
UDG-11174
Figure 6. DCM VOUT Ripple Calculation
12
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
TPS53211
www.ti.com
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
Input Capacitor Selection
The selection of input capacitor should be determined by the ripple current requirement. The ripple current
generated by the converter needs to be absorbed by the input capacitors as well as the input source. The RMS
ripple current from the converter can be expressed as:
IIN(ripple ) = IOUT ´ D ´ (1 - D )
where
•
V
D = OUT
VIN
D is the duty cycle and can be expressed as
(9)
To minimize the ripple current drawn from the input source, sufficient input decoupling capacitors should be
placed close to the device. The ceramic capacitor is recommended due to the inherent low ESR and low ESL.
The input voltage ripple can be calculated as below when the total input capacitance is determined:
´D
I
VIN(ripple ) = OUT
fSW ´ CIN
(10)
Output Voltage Setting Resistors Selection
The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 7. R1 is connected
between FB pin and the output, and R2 is connected between the FB pin and FBG. The recommended value for
R1 is between 1 kΩ and 5 kΩ. Determine R2 using Equation 11.
æ
ö
0.8
R1 = ç
÷ ´ R1
ç (VOUT - 0.8 ) ÷
è
ø
(11)
Compensation Design
The TPS53211 employs voltage mode control. To effectively compensation the power stage and ensures fast
transient response, Type III compensation is typically used.
The control to output transfer function can be described in Equation 12.
1 + s ´ COUT ´ ESR
GCO = 4 ´
æ
ö
L
+ COUT ´ (ESR + DCR) ÷ + s2 ´ L ´ COUT
1+ s ´ ç
è DCR + RLOAD
ø
(12)
The output LC filter introduces a double pole, calculated in Equation 13.
1
fDP =
2 ´ p ´ L ´ COUT
(13)
The ESR zero of can be calculated calculated in Equation 14
1
fESR =
2 ´ p ´ ESR ´ COUT
Copyright © 2011–2012, Texas Instruments Incorporated
(14)
Submit Documentation Feedback
13
TPS53211
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
www.ti.com
Figure 7 shows the configuration of Type III compensation and typical pole and zero locations. Equation 15
through Equation 17 describe the compensator transfer function and poles and zeros of the Type III network.
GEA =
(1 + s ´ C1 ´ (R1 + R3 ))(1 + s ´ R4 ´ C2 )
æ
C ´C ö
(s ´ R1 ´ (C2 + C3 ))´ (1 + s ´ C1 ´ R3 )´ ç 1 + s ´ R4 C 2 + C3 ÷
è
2
3
ø
(15)
1
fZ1 =
2 ´ p ´ R 4 ´ C2
(16)
1
1
fZ2 =
@
2 ´ p ´ (R1 + R3 ) ´ C1 2 ´ p ´ R1 ´ C1
(17)
C3
C1
C2
R4
Gain (dB)
R1
R3
COMP
VREF
R2
+
UGD-11176
fZ1
fZ2
fP2
fP3
Frequency
UDG-11175
Figure 7. Type III Compensation Network
Configuration
fP1 = 0
fP2 =
1
2 ´ p ´ R3 ´ C1
1
1
fP3 =
@
æ C ´ C3 ö 2 ´ p ´ R 4 ´ C3
2 ´ p ´ R4 ´ ç 2
÷
è C2 + C3 ø
Figure 8. Type III Compensation Network
Waveform
(18)
(19)
(20)
The two zeros can be placed near the double pole frequency to cancel the response from the double pole. One
pole can be used to cancel ESR zero, and the other non-zero pole can be placed at half switching frequency to
attenuate the high frequency noise and switching ripple. Suitable values can be selected to achieve a
compromise between high phase margin and fast response. A phase margin higher than 45° is required for
stable operation.
14
Submit Documentation Feedback
Copyright © 2011–2012, Texas Instruments Incorporated
TPS53211
www.ti.com
SLUSAA9A – SEPTEMBER 2011 – REVISED NOVEMBER 2012
Changes from Original (September 2011) to Revision A
Page
•
Changed Input voltage range condition for CSP and CSN pins in ABSOLUTE MAXIMUM RATINGS table from
"VVCC > 6.8" to "VVCC > 7.5" .................................................................................................................................................. 2
•
Changed Input voltage range maximum specification for CSP and CSN pins in ABSOLUTE MAXIMUM RATINGS
table from "5.3 V" to "6 V" ..................................................................................................................................................... 2
•
Changed Input voltage range condition for CSP and CSN pins in ABSOLUTE MAXIMUM RATINGS table from
"VVCC ≤ 6.8" to "VVCC ≤ 7.5" ................................................................................................................................................... 2
•
Changed Input voltage range condition for CSP and CSN pins in RECOMMENDED OPERATING CONDITIONS
table from "VVCC > 6.8" to "VVCC > 7.5" ................................................................................................................................. 3
•
Changed Input voltage range maximum specification for CSP and CSN pins in RECOMMENDED OPERATING
CONDITIONS table from "5 V" to "5.5 V" ............................................................................................................................. 3
•
Changed Input voltage range condition for CSP and CSN pins in RECOMMENDED OPERATING CONDITIONS
table from "VVCC > 6.8" to "VVCC > 7.5" ................................................................................................................................. 3
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS53211RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
53211
TPS53211RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
53211
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
