TPS53511
SLUSBG4B – MARCH 2013 – REVISED AUGUST 2021
4.5-V to 18-V Input, 1.5-A Step-Down Regulator with Integrated Switcher
1 Features
3 Description
•
•
•
•
The TPS53511 is an adaptive on-time D-CAP2™
mode synchronous buck converter. The device
is suitable for points-of-load (POL) in computing
power systems, and provides a cost-effective, low
component count, low standby current solution. The
main control loop for the TPS53511 uses the DCAP2™ mode control to provide a fast transient
response with no external components. The adaptive
on-time control supports seamless operation between
PWM mode during heavy load conditions and reduced
frequency operation during light-load conditions for
high efficiency.
•
•
•
•
•
•
•
•
•
•
•
Continuous 1.5-A output current
4.5-V to 18-V supply voltage range
2-V to 18-V conversion voltage range
DCAP2™ mode control enables fast transient
response
Low output ripple and support all MLCC output
capacitor
Skip mode for light load control
Highly efficient integrated FETs optimized for lower
duty cycle applications
High efficiency, less than 10-µA supply current at
shutdown
Adjustable soft-start time
Support pre-biased soft start
700-kHz switching frequency
Cycle-by-cycle overcurrent limit
Open-drain power-good indication
Internal bootstrap switch
Small 3-mm × 3-mm, 16-pin QFN (RGT) package
2 Applications
•
•
Points-of-load for server
Distributed non-isolated DC-DC converters for
computing power system
The TPS53511 includes a proprietary circuit that
enables the device to adapt to both low equivalent
series resistance (ESR) output capacitors, such as
POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors. The device operates from 4.5-V to 18-V
supply input, and from 2-V to 18-V input power supply
voltage. The device features an adjustable slow-start
time and a power-good function. It also supports prebiased soft start. The TPS53511 is available in a 16pin QFN package, and is designed to operate from
–40°C to 85°C.
Device Information
(1)
+
VIN
–
SGND PGND
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
TPS53511
VQFN (16)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
16
15
14
13
VO
VCC
VIN
VIN
1
VFB
VBST 12
2
VREG5
3
SS
4
GND
PG
EN
5
6
SW 11
TPS53511
+
SW 10
SW
PGND PGND
7
8
Output Signal
Input Signal
9
VOUT
–
UDG-13043
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53511
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................ 8
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................12
8 Application and Implementation.................................. 13
8.1 Application Information............................................. 13
8.2 Typical Application.................................................... 13
9 Power Supply Recommendations................................18
10 Layout...........................................................................19
10.1 Layout Considerations............................................ 19
10.2 Layout Example...................................................... 20
11 Device and Documentation Support..........................21
11.1 Device Support........................................................21
11.2 Receiving Notification of Documentation Updates.. 21
11.3 Support Resources................................................. 21
11.4 Trademarks............................................................. 21
11.5 Electrostatic Discharge Caution.............................. 21
11.6 Glossary.................................................................. 21
12 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2013) to Revision B (August 2021)
Page
• Added the following sections: ESD Ratings, Pin Configuration and Functions, Overview, Functional Block
Diagram, Feature Description, Device Functional Modes, Application and Implementation, Application
Information, Typical Application, Design Requirements, Detailed Design Procedure, Application Curves,
Power Supply Recommendations, Layout, Layout Guidelines, Layout Example, Device and Documentation
Support, Mechanical Packaging, and Orderable Information ............................................................................ 1
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Changed VENH min value to 1.5 V...................................................................................................................... 6
Changes from Revision * (March 2013) to Revision A (May 2013)
Page
• Changed minimum value for Current limit specification in Electrical characteristics table ................................ 6
• Changed Figure 6-3 ...........................................................................................................................................8
• Changed Figure 6-5 ...........................................................................................................................................8
• Changed Figure 6-6 ...........................................................................................................................................8
• Changed Figure 6-7 ...........................................................................................................................................8
• Changed Figure 6-11 ......................................................................................................................................... 8
• Changed Figure 6-12 .........................................................................................................................................8
• Changed Figure 8-1 .........................................................................................................................................13
2
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VFB
VO
VCC
VIN
VIN
5 Pin Configuration and Functions
16
15
14
13
1
12 VBST
TPS53511
GND
4
PowerPAD
TM
10 SW
9
5
6
7
SW
8
PGND
3
PGND
SS
11 SW
EN
2
PG
VREG5
Figure 5-1. 16-Pin RGT Package (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
I/O/P
DESCRIPTION
EN
6
I
GND
4
—
Signal ground pin
PG
5
O
Open-drain power-good output
P
Ground returns for low-side MOSFET. Also serves as inputs of current comparators. Connect PGND and
GND strongly together near the device.
PGND
7
8
SS
3
SW
10
Enable control input
I/O
Soft-start control. An external capacitor should be connected to GND.
I/O
Switch node connection between high-side N-channel FET and low-side N-channel FET. Also serves as
inputs to current comparator.
9
11
VBST
12
I
Supply input for high-side N-channel FET gate driver (boost terminal). Connect a capacitor from this pin to
respective SW terminals. An internal PN diode is connected between the VREG5 and VBST pins.
VCC
15
I
Supply input for 5-V internal linear regulator for the control circuitry.
1
I
Converter feedback input. Connect with feedback resistor divider.
I
Power input and connected to high side N-channel FET drain
VFB
VIN
13
14
VO
16
I
Connect to the output of the converter. This terminal is used for on-time adjustment.
VREG5
2
O
5.5-V power supply output. A capacitor (typical 1-µF) should be connected to GND.
—
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to
PGND.
PowerPAD
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
Input voltage range
MIN
MAX
VIN, VCC, EN
–0.3
20
VBST
–0.3
26
VBST (with respect to SW)
–0.3
6.5
SS, VO, VFB
–0.3
6.5
–2
20
SW
Voltage differential
Output voltage range
Output current
DC
–3
20
GND to PowerPAD
Transient < 10 ns
–0.2
0.2
PG, VREG5
–0.3
6.5
PGND
–0.3
0.3
IOUT
UNIT
V
V
V
1.5
A
Storage junction temperature
–55
150
°C
Operating junction temperature
–40
150
°C
(1)
(2)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal.
6.2 ESD Ratings
VALUE
V (ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
2000
500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
MIN
TYP
MAX
UNIT
VIN
2.0
18.0
VCC
4.5
18.0
EN
–0.1
18.0
VBST
–0.1
24.0
VBST(with respect to SW)
–0.1
5.7
VO, VFB, SS
–0.1
5.5
–1.8
18.0
–3
18
PG, VREG5
–0.1
5.7
PGND
–0.1
0.1
Junction temperature range, TJ
–40
125
°C
Operating free-air temperature, TA
–40
85
°C
Input voltage range
SW
Output voltage range
DC
Transient, < 10 ns
V
V
6.4 Thermal Information
TPS53511
THERMAL METRIC(1)
QFN (RGT)
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance(2)
45.3
θJCtop
Junction-to-case (top) thermal resistance(3)
57.3
resistance(4)
θJB
Junction-to-board thermal
ψJT
Junction-to-top characterization parameter(5)
1.1
ψJB
Junction-to-board characterization parameter(6)
18.4
θJCbot
Junction-to-case (bottom) thermal resistance(7)
3.9
(1)
(2)
(3)
(4)
(5)
(6)
(7)
18.4
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board,
as specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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6.5 Electrical Characteristics
over recommended free-air temperature range, VVIN = 12 V, PGND = GND (unless otherwise noted). (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVCC
Operating, non-switching supply
current
TA = 25°C, VEN = 5 V, VVFB = 0.8 V
850
1300
µA
IVCC(sdn)
Shutdown supply current
TA = 25°C, VEN = 0 V
1.8
10
µA
LOGIC THRESHOLD
VENH
EN high-level input voltage
VENL
EN low-level input voltage
1.5
V
0.4
V
VVFB VOLTAGE AND DISCHARGE RESISTANCE
Voltage light load mode
TA = 25°C, VOUT = 1.05 V, IOUT = 10 mA
771
TA = 25°C, VOUT = 1.05 V
VVFB
757
Threshold voltage, continuous mode TA = 0°C to 85°C, VOUT = 1.05 V(1)
765
mV
773
753
777
TA = –40°C to 85°C, VOUT = 1.05 V(1)
751
779
-0.1
IVFB
Input current
VFB = 0.8 V, TA = 25°C
RDischg
VO discharge resistance
VEN = 0 V, VOUT = 0.5 V, TA = 25°C
mV
0
0.1
µA
50
100
Ω
5.5
5.7
V
20
mV
100
mV
VVREG5 OUTPUT
VVREG5
Output voltage
TA = 25°C, 6 V < VVCC < 18 V, 0 < IVREG5 < 5 mA
VLN5
Line regulation
6 V < VVCC < 18 V, IVREG5 = 5 mA
VLD5
Load regulation
0 < IVREG5 < 5 mA
IVREG5
Output current
Vcc = 6 V, VVREG5 = 4 V, TA = 25°C
RDS(on)H
High-side switch resistance
TA = 25°C, (VBST–VSW) = 5.5 V
RDS(on)L
Low-side switch resistance
TA = 25°C
5.3
70
mA
120
mΩ
70
mΩ
MOSFET
CURRENT LIMIT
IOCL
Current limit
LOUT = 1.5 µH(1)
1.65
2.00
2.75
A
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold
Shutdown temperature(1)
150
Hysteresis(1)
°C
25
ON-TIME TIMER CONTROL
tON
On time
VVIN = 12 V, VOUT = 1.05 V
145
tOFF(min)
Minimum off time
TA = 25°C, VVFB = 0.7 V
260
310
ns
ns
2.6
µA
SOFT-START FUNCTION
ISSC
Soft-start charge current
VSS = 0 V
1.4
2.0
ISSD
Soft-start discharge current
VSS = 0.5 V
0.1
0.2
85%
90%
mA
POWER GOOD
VTHPG(UV)
Power-good undervoltage threshold
VTHPG(OV)
Power-good overvoltage threshold
IPG
Sink current
VVFB rising (good)
VVFB falling (fault)
VVFB rising (fault)
110%
VVFB falling (good)
VPG = 0.5 V
95%
85%
115% 120%
110%
2.5
5.0
mA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
6
VOVP
Output OVP trip threshold
tOVPDEL
Output OVP propagation delay
VUVP
Output UVP trip threshold
OVP detect
110%
115% 120%
5
UVP detect
Hysteresis
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65%
70%
µs
75%
10%
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over recommended free-air temperature range, VVIN = 12 V, PGND = GND (unless otherwise noted). (2)
PARAMETER
tUVPDEL
Output UVP delay
tUVPEN
Output UVP enable delay
TEST CONDITIONS
MIN
TYP
MAX
0.25
Relative to soft-start time
UNIT
ms
tSS × 1.7
UNDERVOLTAGE LOCKOUT
UVLO
(1)
(2)
Wakeup VREG5 voltage threshold
3.55
3.80
4.05
Hysteresis VREG5 voltage threshold
0.23
0.35
0.47
V
Specified by design. Not production tested.
See PS pin description for levels.
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6.6 Typical Characteristics
1200
8
1000
Shutdown Current - mA
Supply Current - mA
6
800
600
400
4
2
200
0
-50
0
50
100
TJ - Junction Temperature - °C
0
-50
150
Figure 6-1. VCC Supply Current vs. Junction
Temperature
1.075
1.075
VO - Output Voltage - V
1.1
Output Voltage (V)
50
100
TJ - Junction Temperature - °C
150
Figure 6-2. VCC Shutdown Current vs. Junction
Temperature
1.100
1.050
0
IO = 10 mA
1.05
IO = 1 mA
1.025
1.025
VIN = 15 V
VIN = 12 V
VIN = 18 V
1
1.000
0
0.25
0.50
0.75
1.00
1.25
1.50
Output Current (A)
Figure 6-3. 1.05-V Output Voltage vs. Output
Current
0
5
10
VI - Input Voltage - V
15
20
Figure 6-4. 1.05-V Output Voltage vs. Input Voltage
VOUT (1 V/div)
VOUT (20 mV/div)
EN (5 mV/div)
IOUT (2 A/div)
IOUT (1 A/div)
PGOOD (5 V/div)
8
Time (200 µs/div)
Time (400 µs/div)
Figure 6-5. Load Transient Response, 1.05 V, 0 A to
1.5 A
Figure 6-6. Start-Up
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95
90
90
85
85
80
80
75
Efficiency (%)
Efficiency (%)
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75
70
70
65
65
60
60
55
VOUT = 1.2 V
VOUT = 1.5 V
VOUT = 1.8 V
VOUT = 2.5 V
VIN = 12 V
1.5-µH Inductor
9.7-uQ Z
55
VIN = 12 V
1.5-µH Inductor
9.7-mΩ DCR
VOUT =
VOUT =
VOUT =
VOUT =
50
10
20
30
40
50
60
70
80
1.2 V
1.5 V
1.8 V
2.5 V
90
100
Output Current (mA)
50
0
0.25
0.50
0.75
1.00
1.25
1.50
Figure 6-8. Light Load Efficiency vs. Output
Current
Output Current (A)
Figure 6-7. Efficiency vs. Output Current
900
900
800
VO = 1.8 V
fsw - Switching Frequency - kHz
fsw - Switching Frequency - kHz
700
800
600
VO = 1.8 V
VO = 2.5 V
500
700
400
300
VO = 3.3 V
600
200
100
500
0
5
10
VI - Input Voltage - V
20
15
Figure 6-9. Switching Frequency vs Input Voltage
VOUT (10 mV/div)
0
0.001
0.01
IO - Output Current - A
0.1
Figure 6-10. Switching Frequency vs Output
Current
VIN (10 mV/div)
SW (5 V/div)
SW (5 V/div)
Time (400 ns/div)
Time (400 ns/div)
Figure 6-11. Output Voltage Ripple
Figure 6-12. Input Voltage Ripple
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7 Detailed Description
7.1 Overview
The TPS53511 is a 1.5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of
low-ESR output capacitors including ceramic and special polymer types.
7.2 Functional Block Diagram
VREF –30%
+
TPS53511
UV
VREG5
VO 16
GND
4
VREG5
2
VFB
1
SS
3
+
OV
VCC
15 VCC
Reference
VREF +15%
Ref
12 VBST
VREG5
14 VIN
UVLO
+
+
VREF
13 VIN
Soft
Start
1-shot
9
XCON
VREF +15%
+
VREG5
11 SW
10 SW
+
VREF –15%
PG
5
+
PGOOD Logic
EN
6
Enable Logic
SW
ZC
+
OCP
SW
UV
PGND
OV
SW
PGND
UVLO
7
PGND
8
PGND
Protection
Logic
TSD
UDG-13088
7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the TPS53511 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot timer is set by the converter input voltage, VVIN, and the output voltage, VVO, to
maintain a pseudo-fixed frequency over the output voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the
need for ESR-induced output ripple from D-CAP2™ mode control.
7.3.2 PWM Frequency and Adaptive On-Time Control
TPS53511 uses an adaptive on-time control scheme and does not have a dedicated on-board oscillator. The
device runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to set
the on-time one-shot timer. The on time is inversely proportional to the input voltage and proportional to the
output voltage. The actual frequency can vary from 700 kHz depending on the off time, which is ended when the
fed back portion of the output voltage falls to the VFB threshold voltage.
10
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7.3.3 Soft Start and Pre-Biased Soft-Start Function
The soft-start time function is adjustable. When the EN pin becomes high, 2-µA current begins charging the
capacitor, which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during
start up. The equation for the slow-start time is shown in Equation 1. The VFB voltage is 0.765 V and SS pin
source current is 2 µA.
tSS(ms ) =
CSS ´ VREF CSS ´ 0.765
=
ISS(mA )
2
(1)
where
•
•
CSS is the value of the capacitor connected between the SS pin and GND.
CSS is expressed in nF.
This unique circuit prevents current from being pulled from the output during start-up if the output is pre-biased.
When the soft start commands a voltage higher than the pre-bias level (internal soft-start voltage becomes
greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting the first
low-side FET gate driver pulses with a narrow on time. It then increments the on time on a cycle-by-cycle
basis until it coincides with the time dictated by (1–D), where D is the duty cycle of the converter. This scheme
prevents the initial sinking of the pre-bias output, and makes sure the output voltage (the VO pin) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.
7.3.4 Power Good
The power-good function is activated after soft start has finished. The power-good function becomes active after
1.7 times soft-start time. When the feedback voltage is within ±10% of the target value, internal comparators
detect power good state and the power-good signal becomes high. The power-good output, PG, is an open-drain
output. When the feedback voltage goes ±15% outside of the target value, the power-good signal becomes low
after a 10-µs internal delay. During an undervoltage condition, when the feedback voltage returns to be within
±10% of the target value, the power-good signal goes HIGH again.
7.3.5 Output Discharge Control
The TPS53511 discharges the output when EN is low, or the controller is turned off by the protection function
(OVP, UVP, UVLO, and thermal shutdown). The output is discharged by an internal 50-Ω MOSFET, which is
connected from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge
operation to avoid the possibility of causing negative voltage at the output.
7.3.6 Current Protection
Output current is limited by cycle-by-cycle overcurrent limiting control. The inductor current is monitored during
the OFF state and the controller keeps the OFF state when the inductor current is larger than the over current
trip level. To provide accuracy and a cost-effective solution, the device supports temperature compensated
internal MOSFET RDS(on) sensing.
The inductor current is monitored by the voltage between the PGND pin and the SW pin. In an overcurrent
condition, the current to the load exceeds the current to the output capacitor; thus, the output voltage tends to fall
off. Eventually the output voltage becomes less than the undervoltage protection threshold and the device shuts
down.
7.3.7 Overvoltage/Undervoltage Protection
The TPS53511 detects overvoltage and undervoltage conditions by monitoring the feedback voltage (the VFB
pin). This function is enabled after approximately 1.7 times the soft-start time. When the feedback voltage
becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit latches
the high-side MOSFET driver turns off and the low-side MOSFET turns on. Normal operation can be restored
only by cycling the VCC or EN pin voltage. When the feedback voltage becomes lower than 70% of the target
voltage, the UVP comparator output goes high and an internal UVP delay counter begins. After 250 µs, the
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device latches off both internal high-side and low-side MOSFET. Similar to the overvoltage protection, the device
is latched off, and normal operation can be restored only by cycling the VCC or EN pin voltage.
7.3.8 UVLO Protection
Undervoltage lockout protection (UVLO) monitors the voltage of the VVREG5 pin. When the VVREG5 voltage is
lower than UVLO threshold voltage, the TPS53511 is shut off. This protection is non-latching.
7.3.9 Thermal Shutdown
Thermal protection is self-activating. If the junction temperature exceeds the threshold value (typically 150°C),
the TPS53511 shuts off. This protection is non-latching.
7.4 Device Functional Modes
7.4.1 Light Load Mode Control
The TPS53511 is designed with Auto-Skip mode to increase light-load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that
its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 2.
IOUT(LL) =
12
(VIN - VOUT )´ VOUT
1
´
2 ´ L ´ fSW
VIN
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The following example illustrates the design process and component selection for a single output synchronous
buck converter using TPS53511. The schematic of a design example is shown in Figure 8-1. The specification of
the converter is listed in Table 8-1.
8.2 Typical Application
VIN
C1
10 PF
C2
10 PF
R1
8.25 k:
SGND
PGND
R2
22.1 k:
C7
1 PF
16
15
14
13
VO
VCC
VIN
VIN
1
VFB
VBST 12
2
VREG5
3
SS
3.3 PH
SW 11
TPS53511
+
C6
3300 pF
R3
100 k:
C3
0.1 PF
SW 10
4
GND
SW
PG
EN
5
6
C4
22 PF
9
PGND PGND
7
C5
22 PF
VOUT
8
±
Output Signal
Input Signal
UDG-13044
Figure 8-1. Typical 12-V Input Application Circuit
8.2.1 Design Requirements
Table 8-1. Specification of the Single Output Synchronous Buck Converter
PARAMETER
TEST CONDITION
MIN
4.5
TYP
VIN
Input voltage
VOUT
Output voltage
VRIPPLE
Output ripple
IOUT
Output current
1.5
A
fSW
Switching frequency
700
kHz
IOUT = 1.5 A
12
MAX UNIT
18
V
1.05
V
3% of
VOUT
V
8.2.2 Detailed Design Procedure
8.2.2.1 Output Inductor Selection
The value of the output filtering inductor determines the magnitude of the current ripple, which also affects the
output voltage ripple for a certain output capacitance value. Increasing the inductance value reduces the ripple
current, and thus, results in reduced conduction loss and output ripple voltage. Alternatively, low inductance
value is needed due to the demand of low profile and fast transient response. Therefore, it is important to obtain
a compromise between the low ripple current and low inductance value.
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In practical application, the peak-to-peak current ripple is usually designed to be between 1/4 to1/2 of the rated
load current. Since the magnitude of the current ripple is determined by inductance value, switching frequency,
input voltage and output voltage, the required inductance value for a certain required ripple ∆I is shown in
Equation 3. Also, the chosen inductor should be rated for the peak current calculated from Equation 4.
L=
(VIN - VOUT )´ VOUT
VIN ´ IRIPPLE ´ fSW
(3)
æI
ö
IL(peak ) = IOUT + ç RIPPLE ÷
2
è
ø
(4)
where
•
•
•
•
VIN is the input voltage.
VOUT is the output voltage.
IRIPPLE is the required current ripple.
ƒSW is the switching frequency.
For this design example, the inductance value is selected to provide approximately 30% peak-to-peak ripple
current at maximum load. For this design, a nearest standard value was chosen: 3.3 µH. For 3.3 µH, the
calculated peak current is 1.71 A.
8.2.2.2 Output Capacitor Selection
The capacitor value and ESR determines the amount of output voltage ripple. It is recommended to use a
ceramic output capacitor. Using Equation 5 to Equation 6, an initial estimate for the capacitor value and ESR
can be calculated. As the load transients are significant, consider using the load step instead of ripple current to
calculate the maximum ESR.
C>
1
1
´
8 ´ fSW VRIPPLE
- ESR
IRIPPLE
ESR <
(5)
VOUT(ripple )
IRIPPLE
(6)
For this design, the minimum required capacitance is 8.45 µF and maximum ESR is 33 mΩ. Therefore, two TDK
C3216JB0J226M 22-µF output capacitors are used. The maximum ESR is 12 mΩ for each capacitor.
8.2.2.3 Input Capacitor Selection
The device requires an input decoupling capacitor and a bulk capacitor. A ceramic capacitor over 10 µF is
recommended for the decoupling capacitor. The capacitor voltage rating must to be greater than the maximum
input voltage. In case of separate VVCC and VVIN, a ceramic capacitor over 10 µF is recommended for the input
voltage. Placing a ceramic capacitor with a value higher than 0.1 µF for the VCC is recommended also.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF capacitor must be connected between the VBST and SW pin for proper operation. A ceramic capacitor
is recommended.
8.2.2.5 VREG5 Capacitor Selection
A 1-µF capacitor must be connected between the VREG5 and SW pin for proper operation. A ceramic capacitor
is recommended.
14
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8.2.2.6 Output Voltage Setting Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Begin by using Equation 7 and Equation 8 to calculate VOUT.
To improve efficiency at light-load condition, use resistors with a relatively larger value. However, too high
resistance value make the circuit more susceptible to noise, and voltage errors from the VFB input current is
more noticeable.
For output voltages from 0.76 V to 2.5 V:
æ æ R1 ö ö
VOUT = 0.765 ´ ç 1 + ç
÷÷
è è R2 ø ø
(7)
For output voltages over 2.5 V:
R1 ö
æ
VOUT = (0.763 + 0.0017 ´ VOUT )´ ç 1 +
÷
è R2 ø
(8)
The required output voltage for this design is 1.05 V. So Equation 7 is used to calculate the value of R1. R2 is
22.1 kΩ, therefore, R1 is 8.25 kΩ.
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8.2.3 Application Curves
1.1
1.1
1.05
VI = 12 V
VI = 5 V
1.05
IO = 1 mA
1.025
1.025
1
1
0
0.5
1
1.5
2
IO - Output Current - A
0
3
2.5
5
10
VI - Input Voltage - V
20
15
Figure 8-3. 1.05-V Output Voltage vs. Input Voltage
Figure 8-4. 1.05-V, 0-A to 3-A Load Transient
Response
Figure 8-5. Start-Up
95
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
Figure 8-2. 1.05-V Output Voltage vs. Output
Current
75
70
65
60
VOUT = 2.5 V
VOUT = 1.8 V
55
50
0
0.5
1
VOUT = 1.5 V
VOUT = 1.2 V
1.5
2
Output Current (A)
DCR = 9.7 mΩ
LOUT = 1.5 µH
fSW =700 kHz
VIN =12 V
2.5
VOUT = 2.5 V
VOUT = 1.8 V
VOUT = 1.5 V
VOUT = 1.2 V
75
70
65
DCR = 9.7 mΩ
LOUT = 1.5 µH
fSW =700 kHz
VIN =12 V
60
55
3
50
0.01
G000
Figure 8-6. Efficiency vs. Output Current
16
IO = 10 mA
1.075
VI = 18 V
VO - Output Voltage - V
VO - Output Voltage - V
1.075
0.02
0.03
0.04 0.05 0.06 0.07
Output Current (A)
0.08
0.09
0.1
G000
Figure 8-7. Light-Load Efficiency vs. Output
Current
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900
900
800
VO = 1.8 V
fsw - Switching Frequency - kHz
fsw - Switching Frequency - kHz
700
800
600
VO = 1.8 V
VO = 2.5 V
500
700
400
300
VO = 3.3 V
600
200
100
500
0
5
10
VI - Input Voltage - V
20
15
Figure 8-8. Switching Frequency vs. Input Voltage
0
0.001
0.01
IO - Output Current - A
0.1
Figure 8-9. Switching Frequency vs. Output
Current
VIN (50 mV/div)
VO (10 mV/div)
SW (5 V/div)
SW (5 V/div)
400 ns/div
400 ns/div
Figure 8-10. Output Voltage Ripple
Figure 8-11. Input Voltage Ripple
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4.5 V and 18 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the TPS53311 converter,
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 100 μF is a typical choice.
18
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10 Layout
10.1 Layout Considerations
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Keep the input switching current loop as small as possible.
Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to
the feedback pin of the device.
Keep analog and non-switching components away from switching components.
Make a single point connection between the signal and power grounds.
Do not allow switching current to flow under the device.
Keep the pattern lines for VIN and PGND broad.
Exposed pad of the device must be connected to PGND with solder.
VREG5 capacitor should be connected to a broad pattern of the PGND.
Output capacitor should be connected to a broad pattern of the PGND.
Voltage feedback loop should be as short as possible, and preferably with ground shield.
Lower resistor of the voltage divider, which is connected to the VFB pin should be tied to SGND.
Providing sufficient via is preferable for VIN, SW and PGND connection.
PCB pattern for VIN, SW, and PGND should be as broad as possible.
If VIN and VCC are shorted, VIN and VCC patterns need to be connected with broad pattern lines.
VIN capacitor should be placed as close as possible to the device.
10.1.1 Thermal Information
This PowerPAD™ package incorporates an exposed thermal pad that is designed to be connected to an external
heat sink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heat sink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heat sink structure designed into the PCB. This design optimizes the heat transfer from the device.
For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating
abilities, refer to the PowerPAD™ Thermally Enhanced Package Technical Brief and the PowerPAD™ Made
Easy Application Brief.
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10.2 Layout Example
Figure 10-1. Layout Example
20
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
DCAP2™ is a trademark of TI.
PowerPAD™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS53511RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
53511
Samples
TPS53511RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
53511
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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