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TPS53515
SLUSBN5B – AUGUST 2013 – REVISED JULY 2015
TPS53515 1.5-V to 18-V (4.5-V to 25-V Bias) Input,
12-A Single Synchronous Step-Down SWIFT™ Converter
1 Features
3 Description
•
The TPS53515 device is a small-sized, synchronous
buck converter with an adaptive on-time D-CAP3
control mode. The device offers ease-of-use and low
external-component count for space-conscious power
systems.
1
•
•
•
•
•
•
•
•
•
•
•
Integrated 13.8-mΩ and 5.9-mΩ MOSFETs With
12-A Continuous Output Current
Supports All Ceramic Output Capacitors
Reference Voltage 600 mV ±0.5% Tolerance
Output Voltage Range: 0.6 V to 5.5 V
D-CAP3™ Control Mode With Fast Load-Step
Response SWIFT™
Auto-Skipping Eco-mode™ for High Light-Load
Efficiency
FCCM for Tight Output Ripple and Voltage
Requirements
Eight Selectable Frequency Settings from
250 kHz to 1 MHz
Precharged Startup Capability
Built-in Output Discharge Circuit
Open-Drain Power-Good Output
3.5 mm × 4.5 mm, 28-Pin, VQFN-CLIP Package
This device features high-performance integrated
MOSFETs, accurate 0.5% 0.6-V reference, and an
integrated boost switch. Competitive features include
very low external-component count, fast loadtransient response, auto-skip mode operation,
internal soft-start control, and no requirement for
compensation.
A forced continuous conduction mode helps meet
tight voltage regulation accuracy requirements for
performance DSPs and FPGAs. The TPS53515
device is available in a 28-pin VQFN-CLIP package
and is specified from –40°C to 85°C ambient
temperature.
Device Information
PART NUMBER
(1)
PACKAGE
BODY SIZE (NOM)
VQFN-CLIP (28)
4.50 mm × 3.50 mm
2 Applications
TPS53515
•
•
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
•
•
Server and Cloud-Computing POLs
Broadband, Networking, and Optical
Communications Infrastructure
I/O Supplies
Supported at the WEBENCH® Design Center
Simplified Schematic
Efficiency
100
PGOOD
VIN
VIN
SW
SW
2
3
4
5
6
7
8
9
90
PGND
14
PGND
13
PGND
12
PGND
11
PGND
10
Efficiency (%)
NC
SW
1
15
VIN
VDD
GND2
TPS53515
SW
28
VREG
GND1
16
N/C
27
17
VBST
DNC
18
GND
26
19
MODE
TRIP
20
EN
25
21
PGOOD
VO
22
RF
24
23
FB
VIN
80
fSW = 500 KHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 H, Mode = Auto-skip
Vout
Vout
VOUT = 0.6 V
V
OUT = 1 V
Vout
Vout
VOUT = 1.2 V
V
OUT = 1.5 V
VOUT = 1.8 V
V
Vout
Vout
OUT = 2.5 V
VOUT = 3.3 V
V
Vout
Vout
OUT = 5 V
70
VOUT
60
Thermal Pad
VREG EN
0
2
4
6
Output Current (A)
8
10
12
C003
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS53515
SLUSBN5B – AUGUST 2013 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 22
8
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application ................................................. 23
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 29
10.3 Thermal Performance ........................................... 30
11 Device and Documentation Support ................. 31
11.1
11.2
11.3
11.4
11.5
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2013) to Revision B
•
Page
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Original (August 2013) to Revision A
Page
•
Added updates to front page graphics ................................................................................................................................... 1
•
Added updates to Electrical Specifications section ................................................................................................................ 6
2
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SLUSBN5B – AUGUST 2013 – REVISED JULY 2015
5 Pin Configuration and Functions
GND2
GND1
DNC
TRIP
VO
RVE Package
28-Pin VQFN-CLIP
Top View
28
27
26
25
24
RF
1
23
FB
PGOOD
2
22
GND
EN
3
21
MODE
VBST
4
20
VREG
19
VDD
TPS53515
NC
5
SW
6
18
NC
SW
7
17
VIN
SW
8
16
VIN
15
VIN
Thermal Pad
10
11
12
13
14
PGND
PGND
PGND
PGND
9
PGND
SW
Pin Functions
PIN
NAME
NO.
I/O (1)
DESCRIPTION
DNC
26
O
Do not connect. This pin is the output of unused internal circuitry and must be floating.
EN
3
I
The enable pin turns on the DC-DC switching converter.
FB
23
I
VOUT feedback input. Connect this pin to a resistor divider between the VOUT pin and GND.
GND
22
G
This pin is the ground of internal analog circuitry and driver circuitry. Connect GND to the PGND
plane with a short trace (For example, connect this pin to the thermal pad with a single trace and
connect the thermal pad to PGND pins and PGND plane).
GND1
27
I
Connect this pin to ground. GND1 is the input of unused internal circuitry and must connect to
ground.
GND2
28
I
Connect this pin to ground. GND2 is the input of unused internal circuitry and must connect to
ground.
MODE
21
I
The MODE pin sets the forced continuous-conduction mode (FCCM) or Skip-mode operation. It also
selects the ramp coefficient of D-CAP3 mode.
5
NC
18
—
Not connected. These pins are floating internally.
G
These ground pins are connected to the return of the internal low-side MOSFET.
10
11
PGND
12
13
14
PGOOD
2
O
Open-drain power-good status signal which provides startup delay after the FB voltage falls within
the specified limits. After the FB voltage moves outside the specified limits, PGOOD goes low within
2 µs.
RF
1
I
RF is the SW-frequency configuration pin. Connect this pin to a resistor divider between VREG and
GND to program different SW frequency settings.
(1)
I = Input, O = Output, P = Supply, G = Ground
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Pin Functions (continued)
PIN
NAME
I/O (1)
NO.
DESCRIPTION
6
7
SW
8
I/O
SW is the output switching terminal of the power converter. Connect this pin to the output inductor.
TRIP is the OCL detection threshold setting pin. ITRIP = 10 µA at room temp, 3000 ppm/°C current is
sourced and sets the OCL trip voltage. See the Current Sense and Overcurrent Protection section
for detailed OCP setting.
9
TRIP
25
I/O
VBST
4
P
VBST is the supply rail for the high-side gate driver (boost terminal). Connect the bootstrap
capacitor from this pin to the SW node. Internally connected to VREG via bootstrap PMOS switch.
VDD
19
P
Power-supply input pin for controller. Input of the VREG LDO. The input range is from 4.5 to 25 V.
P
VIN is the conversion power-supply input pins.
15
VIN
16
17
VREG
20
O
VREG is the 5-V LDO output. This voltage supplies the internal circuitry and gate driver.
VO
24
I
VOUT voltage input to the controller.
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
EN
MAX
–0.3
7.7
DC
–3
30
Transient < 10 ns
–5
32
VBST
–0.3
36
VBST (3)
–0.3
SW
Input voltage range (2)
MIN
6
VBST when transient < 10 ns
UNIT
V
38
VDD
–0.3
28
VIN
–0.3
30
VO, FB, MODE, RF
–0.3
6
PGOOD
–0.3
7.7
VREG, TRIP
–0.3
6
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
Output voltage range
(1)
(2)
(3)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
Voltage values are with respect to the SW terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2500
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Input voltage
Output voltage
EN
–0.1
7
SW
–3
27
VBST
–0.1
28
VBST (1)
–0.1
5.5
VDD
4.5
25
VIN
1.5
18
VO, FB, MODE, RF
–0.1
5.5
PGOOD
–0.1
7
VREG, TRIP
–0.1
5.5
–40
85
Operating free-air temperature, TA
(1)
MAX
UNIT
V
V
°C
Voltage values are with respect to the SW pin.
6.4 Thermal Information
TPS53515
THERMAL METRIC (1)
RVE
(VQFN-CLIP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
37.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
34.1
°C/W
RθJB
Junction-to-board thermal resistance
18.1
°C/W
ψJT
Junction-to-top characterization parameter
1.8
°C/W
ψJB
Junction-to-board characterization parameter
18.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLUSBN5B – AUGUST 2013 – REVISED JULY 2015
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6.5 Electrical Characteristics
over operating free-air temperature range, VREG = 5 V, EN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1350
1850
µA
850
1150
µA
0.5
µA
603
mV
SUPPLY CURRENT
IVDD
VDD bias current
TA = 25°C, No load
Power conversion enabled (no
switching)
IVDDSTBY
VDD standby current
TA = 25°C, No load
Power conversion disabled
IVIN(leak)
VIN leakage current
VEN = 0 V
VREF OUTPUT
VVREF
Reference voltage
VVREFTOL
Reference voltage tolerance
FB w/r/t GND, TA = 25°C
597
600
FB w/r/t GND, 0°C ≤ TJ ≤ 85°C
–0.6%
0.5%
FB w/r/t GND, =–40°C ≤ TJ ≤ 85°C
–0.7%
0.5%
OUTPUT VOLTAGE
IFB
IVODIS
FB input current
VFB = 600 mV
VO discharge current
VVO = 0.5 V, Power Conversion
Disabled
10
50
100
nA
12
15
mA
SMPS FREQUENCY
VO switching frequency (1)
fSW
VIN = 12 V, VVO = 3.3 V, RDR < 0.041
250
VIN = 12 V, VVO = 3.3 V, RDR = 0.096
300
VIN = 12 V, VVO = 3.3 V, RDR = 0.16
400
VIN = 12 V, VVO = 3.3 V, RDR = 0.229
500
VIN = 12 V, VVO = 3.3 V, RDR = 0.297
600
VIN = 12 V, VVO = 3.3 V, RDR = 0.375
750
VIN = 12 V, VVO = 3.3 V, RDR = 0.461
850
VIN = 12 V, VVO = 3.3 V, RDR > 0.557
1000
tON(min)
Minimum on-time
TA = 25°C (2)
tOFF(min)
Minimum off-time
TA = 25°C
kHz
60
175
ns
240
310
ns
INTERNAL BOOTSTRAP SW
VF
Forward Voltage
VVREG–VBST, TA = 25°C, IF = 10 mA
0.15
0.25
V
IVBST
VBST leakage current
TA = 25°C, VVBST = 33 V, VSW = 28 V
0.01
1.5
µA
1.4
1.5
V
1.2
1.3
V
1
µA
LOGIC THRESHOLD
VENH
EN enable threshold voltage
1.3
VENL
EN disable threshold voltage
1.1
VENHYST
EN hysteresis voltage
VENLEAK
EN input leakage current
0.22
–1
0
V
SOFT START
tSS
Soft-start time
1
ms
PGOOD COMPARATOR
PGOOD in from higher
VPGTH
IPG
VDDQ PGOOD threshold
PGOOD sink current
tPGDLY
PGOOD delay time
IPGLK
PGOOD leakage current
(1)
(2)
6
104%
108%
111%
PGOOD in from lower
89%
92%
96%
PGOOD out to higher
113%
116%
120%
PGOOD out to lower
80%
84%
87%
VPGOOD = 0.5 V
Delay for PGOOD going in
4
6
0.8
1.0
Delay for PGOOD coming out
VPGOOD = 5 V
mA
1.2
2
–1
0
ms
µs
1
µA
Resistor divider ratio (RDR) is described in Equation 1.
Specified by design. Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VREG = 5 V, EN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10.1
12
13.9
7.2
9.1
11.0
–15.3
–11.9
–8.5
–12
–9
–6
UNIT
CURRENT DETECTION
RTRIP
TRIP pin resistance range
20
RTRIP = 52.3 kΩ
IOCL
Current limit threshold, valley
IOCLN
Negative current limit threshold, RTRIP = 52.3 kΩ
valley
RTRIP = 38 kΩ
VZC
Zero cross detection offset
RTRIP = 38 kΩ
70
0
kΩ
A
A
mV
PROTECTIONS
Wake-up
3.25
3.34
3.41
Shutdown
3.00
3.12
3.19
Wake-up (default)
4.15
4.25
4.35
Shutdown
3.95
4.05
4.15
116%
120%
124%
VVREGUVLO
VREG undervoltage-lockout
(UVLO) threshold voltage
VVDDUVLO
VDD UVLO threshold voltage
VOVP
Overvoltage-protection (OVP)
threshold voltage
OVP detect voltage
tOVPDLY
OVP propagation delay
With 100-mV overdrive
VUVP
Undervoltage-protection (UVP)
threshold voltage
UVP detect voltage
tUVPDLY
UVP delay
UVP filter delay
300
64%
68%
V
V
ns
71%
1
ms
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold (2)
Shutdown temperature
140
Hysteresis
°C
40
LDO VOLTAGE
VREG
LDO output voltage
VIN = 12 V, ILOAD = 10 mA
VDOVREG
LDO low droop drop-out
voltage
VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C
ILDOMAX
LDO overcurrent limit
VIN = 12 V, TA = 25°C
4.65
5
5.45
365
170
200
V
mV
mA
INTERNAL MOSFETS
RDS(on)H
High-side MOSFET onresistance
TA = 25°C
13.8
15.5
RDS(on)L
Low-side MOSFET onresistance
TA = 25°C
5.9
7.0
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mΩ
mΩ
7
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SLUSBN5B – AUGUST 2013 – REVISED JULY 2015
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100
100
90
90
Efficiency (%)
Efficiency (%)
6.6 Typical Characteristics
80
fSW = 500 KHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 H, Mode = Auto-skip
Vout
Vout
VOUT = 0.6 V
V
OUT = 1 V
Vout
Vout
VOUT = 1.2 V
V
OUT = 1.5 V
VOUT = 1.8 V
V
Vout
Vout
OUT = 2.5 V
VOUT = 3.3 V
V
Vout
Vout
OUT = 5 V
70
60
0
2
4
6
8
10
80
fSW = 500 KHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 H, Mode = FCCM
Vout
Vout
VOUT = 0.6 V
V
OUT = 1 V
Vout
Vout
VOUT = 1.2 V
V
OUT = 1.5 V
VOUT = 1.8 V
V
Vout
Vout
OUT = 2.5 V
VOUT = 3.3 V
V
Vout
Vout
OUT = 5 V
70
60
12
Output Current (A)
0
2
C003
90
90
80
fSW = 1 MHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 H, Mode = Auto-Skip
Vout
V
OUT = 0.6 V
V
Vout
OUT = 1.2 V
V
Vout
OUT = 1.8 V
V
Vout
= 3.3
3.3 V
V
OUT =
50
0
2
4
6
Vout
1V
V
OUT = 1
V
Vout
1.5 V
OUT = 1.5
V
Vout
2.5 V
OUT = 2.5
V
Vout
= 55 V
V
OUT =
8
10
Output Current (A)
70
50
12
0
2
4
6
Vout
1V
V
OUT = 1
V
Vout
1.5 V
OUT = 1.5
V
Vout
2.5 V
OUT = 2.5
V
Vout
= 55 V
V
OUT =
8
C006
1.3
fSW = 1 MHz
VDD = 5 V
VOUT = 1.2 V
TA = 25°C
LOUT = 1 H
Mode = Auto-skip
1.25
1.2
1.15
V
VIN
IN ==55VV
V
VIN
IN ==55VV
VIN
12VV
V
IN ==12
VIN
= 18 V
V
IN = 18 V
0
2
4
6
8
10
Output Current (A)
8
12
VIN
12VV
V
IN ==12
VIN
= 18 V
V
IN = 18 V
1.1
0
2
4
6
8
10
Output Current (A)
C007
Figure 5. Output Voltage vs. Output Current
12
Figure 4. Efficiency vs. Output Current
1.2
1.1
10
Output Current (A)
VOUT (V)
VOUT (V)
C004
Vout
V
OUT = 0.6 V
V
Vout
OUT = 1.2 V
V
Vout
OUT = 1.8 V
V
Vout
= 3.3
3.3 V
V
OUT =
60
fSW = 500 KHz
VDD = 5 V
VOUT = 1.2 V
TA = 25°C
LOUT = 1 H
Mode = Auto-skip
1.15
12
fSW = 1 MHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 H, Mode = FCCM
Figure 3. Efficiency vs. Output Current
1.25
10
80
C005
1.3
8
Figure 2. Efficiency vs. Output Current
100
Efficiency (%)
Efficiency (%)
Figure 1. Efficiency vs. Output Current
60
6
Output Current (A)
100
70
4
12
C008
Figure 6. Output Voltage vs. Output Current
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Typical Characteristics (continued)
fSW = 500 KHz
VDD = 5 V
TA = 25°C
LOUT = 1 H
Mode = FCCM
VOUT = 1.2 V
VOUT (V)
1.25
1.2
1.15
1.3
fSW = 1 MHz
VDD = 5 V
TA = 25°C
LOUT = 1 H
Mode = FCCM
VOUT = 1.2 V
1.25
VOUT (V)
1.3
1.2
1.15
V
VIN
IN ==55VV
V
VIN
IN ==55VV
VIN
12VV
V
IN ==12
VIN
12VV
V
IN ==12
VIN
= 18 V
V
IN = 18 V
1.1
0
2
4
6
8
10
Output Current (A)
VIN
= 18 V
V
IN = 18 V
1.1
12
0
2
4
6
8
Figure 7. Output Voltage vs. Output Current
C010
fSW = 500 kHz
VDD = 5 V
VOUT = 1.2 V
TA = 25°C
LOUT = 1 H
Mode = FCCM
VIN = 12 V, VDD = 5 V, TA = 25°C
LOUT = 1 H, Mode = FCCM, VOUT = 1.2 V
1000
550
Frequency (KHz)
Frequency (KHz)
12
Figure 8. Output Voltage vs. Output Current
600
1200
Fsw
250KHz
KHz
fSW ==250
Fsw
500KHz
KHz
fSW ==500
fSW ==11MHz
Fsw
MHz
800
10
Output Current (A)
C009
600
500
450
400
V
VIN
IN ==55VV
VIN
12VV
V
IN ==12
200
2
3
4
5
6
7
8
9
10
11
1
12
Output Current (A)
Ta (°C)
VIN = 12 V
3
4
5
6
7
Iout (Amps)
8
4
9
10
11
12
6
7
8
9
10
11
12
C012
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
200LFM
Nat conv
0
1
2
D001
Switching frequency
= 600kHz
5
Figure 10. Switching Frequency vs. Output Current
Ta (ºC)
200LFM
Nat conv
2
3
Output Current (A)
Figure 9. Switching Frequency vs. Output Current
1
2
C011
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
0
VIN
= 18 V
V
IN = 18 V
400
1
VIN = 12 V
Figure 11. Safe Operating Area, VO = 1.2 V
3
4
5
6
7
Iout (Amps)
8
9
10
11
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D002
Switching frequency
= 600kHz
Figure 12. Safe Operating Area, VO = 5 V
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Typical Characteristics (continued)
VIN = 12 V
fSW = 1 MHz
VOUT = 1.2 V IOUT = 0 A
Mode = Auto-skip
Figure 13. Auto-Skip Mode Steady-State Operation
VIN = 12 V
fSW = 1 MHz
VOUT = 1.2 V IOUT = 0.1 A
Mode = Auto-skip
Figure 15. Auto-Skip Mode Steady-State Operation
VIN = 12 V
fSW = 1 MHz
VOUT = 1.2 V IOUT = 6 A
Mode = Auto-skip
Figure 17. Auto-Skip Mode Steady-State Operation
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VIN = 12 V
fSW = 1 MHz
VOUT = 1.2 V IOUT = 0 A
Mode = FCCM
Figure 14. FCCM Steady-State Operation
VIN = 12 V
fSW = 1 MHz
VOUT = 1.2 V IOUT = 0.1 A
Mode = FCCM
Figure 16. FCCM Steady-State Operation
VIN = 12 V
fSW = 1 MHz
VOUT = 1.2 V IOUT = 6 A
Mode = FCCM
Figure 18. FCCM Steady-State Operation
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Typical Characteristics (continued)
fSW = 1 MHz
VIN = 12 V
IDYN = 0 A to 6 A
VOUT = 1.2 V
Mode = Auto-skip
Figure 19. Auto-Skip Mode Load Transient
fSW = 1 MHz
VIN = 12 V
I
= 0 A to 6 A
VOUT = 1.2 V DYN
Mode = FCCM
Figure 20. FCCM Load Transient
VIN = 12 V
VOUT = 1.2 V
fSW = 1 MHz
IOUT = 0 A
Mode = FCCM
VIN = 12 V
VOUT = 1.2 V
fSW = 1 MHz
IOUT = 0 A
Mode = Auto-skip
Figure 21. Auto-Skip Mode Start-Up
Figure 22. FCCM Start-Up
VIN = 12 V
VOUT = 1.2 V
fSW = 1 MHz
IOUT = 6 A
Mode = Auto-skip
Figure 23. Auto-Skip Mode Start-Up
VIN = 12 V
VOUT = 1.2 V
fSW = 1 MHz
IOUT = 6 A
Mode = FCCM
Figure 24. FCCM Start-Up
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Typical Characteristics (continued)
VIN = 12 V
VOUT = 1.2 V
fSW = 1 MHz
IOUT = 0 A
Mode = Auto-skip
Figure 25. Auto-Skip Mode Shutdown Operation
VIN = 12 V
VOUT = 1.2 V
fSW = 1 MHz
IOUT = 6 A
Mode = Auto-skip
Figure 27. Auto-Skip Mode Shutdown Operation
VIN = 12 V
VOUT = 1.2 V
fSW = 1 MHz
IOUT = 0 A
Pre-bias = 0.6 V
Mode = Auto-skip
Figure 26. FCCM Shutdown Operation
VIN = 12 V
VOUT = 1.2 V
fSW = 1 MHz
IOUT = 6 A
Mode = FCCM
Figure 28. FCCM Shutdown Operation
VIN = 12 V
VOUT = 1.2 V
fSW = 500 kHz
IOUT = 0 A
Mode = Auto-skip
Figure 30. Overvoltage Protection
Figure 29. Prebias Operation
12
VIN = 12 V
VOUT = 1.2 V
fSW = 1 MHz
IOUT = 0 A
Mode = FCCM
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Typical Characteristics (continued)
VIN = 12 V
VOUT = 1.2 V
fSW = 500 kHz
Mode = FCCM
fSW = 500 kHz
IO = 12 A
SNB = 3 Ω+ 470 pF
Inductor:
PCMC135T-1R0MF
VI = 12 V
VO = 5 V
COUT= 10 x 22 µF
( 1206, 6.3 V, X5R)
RBOOT= 0 Ω
LOUT = 1 µH
2.1 mΩ (typ)
12.6 mm × 13.8 mm × 5 mm
Figure 32. SP1: 75.6℃
℃, SP2: 57.7℃
℃ (Inductor)
Figure 31. Overcurrent Protection
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7 Detailed Description
7.1 Overview
The TPS53515 device is a high-efficiency, single-channel, synchronous-buck converter. The device suits lowoutput voltage point-of-load applications with 12-A or lower output current in computing and similar digital
consumer applications. The TPS53515 device features proprietary D-CAP3 mode control combined with adaptive
on-time architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response DC-DC
converters in an ideal fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage
ranges from 1.5 V to 18 V and the VDD input voltage ranges from 4.5 V to 25 V. The D-CAP3 mode uses
emulated current information to control the modulation. An advantage of this control scheme is that it does not
require a phase-compensation network outside which makes the device easy-to-use and also allows low-external
component count. Adaptive on-time control tracks the preset switching frequency over a wide range of input and
output voltage while increasing switching frequency as needed during load-step transient.
7.2 Functional Block Diagram
0.6 V + 8/16%
0.6 V±32%
+
UV
PGOOD
+
Delay
Delay
+
+
OV
0.6 V ± 8/16%
0.6 V+20%
Internal
Ramp
0.6 V
SS
VREG
Control Logic
UVP and
OVP
Logic
+
+ PWM
RF
VBST
VFB
10 µA
VIN
+
GND
TRIP
1 SHOT
+ OCP
LL
SW
XCON
+
ZC
PGND
Control
Logic
PGND
SW
FCCM / SKIP
RC time Constant
GND1
GND2
+
EN
GND
1.4 V / 1.2 V
x
x
x
x
x
x
On/Off time
Minimum On/Off
Light load
OVP/UVP
FCCM/SKIP
Soft-Start
VO
Fault
Shut Down
LDO
VREG
+
MODE
VREGOK
VDDOK
Enable
THOK
3.34 V /
3.12 V
+
+ 140°C /
100°C
VDD
4.3 V /
4.03 V
DNC
TPS53515
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7.3 Feature Description
7.3.1 5-V LDO and VREG Start-Up
The TPS53515 device has an internal 5-V LDO feature using input from VDD and output to VREG. When the
VDD voltage rises above 2.8 V, the internal LDO is enabled and outputs voltage to the VREG pin. The VREG
voltage provides the bias voltage for the internal analog circuitry. The VREG voltage also provides the supply
voltage for the gate drives.
2.8 V
VDD
VREG
EN
0.6 V
VREF/VDAC
~ 400 µs
tSS (1 ms)
VOUT
Figure 33. Power-up Sequence Waveforms
7.3.2 Enable, Soft Start, and Mode Selection
The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin.
When the EN pin voltage rises above the enable threshold voltage (typically 1.4 V), the controller enters its startup sequence. The controller then uses the first 400 μs to calibrate the switching frequency setting resistance
attached to the RF pin and stores the switching frequency code in internal registers. During this period, the
MODE pin also senses the resistance attached to this pin to determine the operation mode. In the second phase,
an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. the ramping up time is 1 ms. The
device maintains smooth and constant ramp-up of the output voltage during start-up regardless of load current.
7.3.3 Frequency Selection
TPS53515 device lets users select the switching frequency by using the RF pin. Table 1 lists the divider ratio and
some example resistor values for the switching frequency selection. The 1% tolerance resistors with a typical
temperature coefficient of ±100 ppm/ºC are recommended. If the design requires a tighter noise margin for more
reliable SW-frequency detection, use higher performance resistors.
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Table 1. Switching Frequency Selection
(1)
SWITCHING
FREQUENCY
(fSW) (kHz)
RESISTOR
DIVIDER RATIO (1)
(RDR)
1000
850
EXAMPLE RF FREQUENCY COMBINATIONS
RRF_H (kΩ)
RRF_L (kΩ)
> 0.557
1
300
0.461
180
154
750
0.375
200
120
600
0.297
249
105
500
0.229
240
71.5
400
0.16
249
47.5
300
0.096
255
27
250
< 0.041
270
11.5
Resistor divider ratio (RDR) is described in Equation 1.
space
RDR =
RRF _ L
(RRF _ L + RRF _ H )
where
•
•
RRF_L is the low-side resistance of the RF pin resistor divider
RRF_H is the high-side resistance of the RF pin resistor divider
(1)
7.3.4 D-CAP3 Control and Mode Selection
RR
SW
To comparator
CR
VOUT
Figure 34. Internal RAMP Generation Circuit
The TPS53515 device uses D-CAP3 mode control to achieve fast load transient while maintaining the ease-ofuse feature. An internal RAMP is generated and fed to the VFB pin to reduce jitter and maintain stability. The
amplitude of the ramp is determined by the R-C time-constant as shown in Figure 34. At different switching
frequencies, (fSW) the R-C time-constant varies to maintain relatively constant RAMP amplitude.
16
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7.3.4.1 D-CAP3 Mode
From small-signal loop analysis, a buck converter using the D-CAP3 mode control architecture can be simplified
as shown in Figure 35.
VO
CC1
CC2
RC2
SW
RC1
VIN
Sample
and Hold
DRVH
PWM
Comparator
RFBH
G
VRAMP
FB
+
+
+
VREF
Lx
Control
Logic
and
Driver
VOUT
DRVL
RCO
COUT
RFBL
RLOAD
Figure 35. D-CAP3 Mode
The D-CAP3 control architecture includes an internal ripple generation network enabling the use of very low-ESR
output capacitors such as multilayered ceramic capacitors (MLCC). No external current sensing network or
voltage compensators are required with D-CAP3 control architecture. The role of the internal ripple generation
network is to emulate the ripple component of the inductor current information and then combine it with the
voltage feedback signal to regulate the loop operation. For any control topologies supporting no external
compensation design, there is a minimum and/or maximum range of the output filter it can support. The output
filter used with the TPS53515 device is a lowpass L-C circuit. This L-C filter has double pole that is described in
Equation 2.
1
fP =
2 ´ p ´ LOUT ´ COUT
(2)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS53515 device. The low frequency L-C double pole has a 180 degree in phase. At the output filter
frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and increases the phase to 90 degree one decade above the zero frequency.
The inductor and capacitor selected for the output filter must be such that the double pole of Equation 2 is
located close enough to the high-frequency zero so that the phase boost provided by the high-frequency zero
provides adequate phase margin for the stability requirement.
Table 2. Locating the Zero
SWITCHING
FREQUENCIES
(fSW) (kHz)
ZERO (fZ) LOCATION (kHz)
250 and 300
6
400 and 500
7
600 and 750
9
850 and 1000
12
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After identifying the application requirements, the output inductance should be designed so that the inductor
peak-to-peak ripple current is approximately between 25% and 35% of the ICC(max) (peak current in the
application). Use Table 2 to help locate the internal zero based on the selected switching frequency. In general,
where reasonable (or smaller) output capacitance is desired, Equation 3 can be used to determine the necessary
output capacitance for stable operation.
1
= fZ
fP =
2 ´ p ´ LOUT ´ COUT
(3)
If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design.
For example, when using an MLCC with specifications of 10-µF, X5R and 6.3 V, the deratings by DC bias and
AC bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this
case is 40% and 4-µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be
used in the system/applications.
Table 3 shows the recommended output filter range for an application design with the following specifications:
• Input voltage, VIN = 12 V
• Switching frequency, fSW = 600 kHz
• Output current, IOUT = 8 A
The minimum output capacitance is verified by the small-signal measurement conducted on the EVM using the
following two criteria:
• Loop crossover frequency is less than one-half the switching frequency (300 kHz)
• Phase margin at the loop crossover is greater than 50 degrees
For the maximum output capacitance recommendation, simplify the procedure to adopt an unrealistically high
output capacitance for this type of converter design, then verify the small-signal response on the EVM using the
following one criteria:
• Phase margin at the loop crossover is greater than 50 degrees
As indicated by the phase margin, the actual maximum output capacitance (COUT(max)) can continue to go higher.
However, small-signal measurement (bode plot) should be done to confirm the design.
Select a MODE pin configuration as shown in Table 4 to in double the R-C time-constant option for the maximum
output capacitance design and application. Select a MODE pin configuration to use single R-C time constant
option for the normal (or smaller) output capacitance design and application.
The MODE pin also selects skip-mode or FCCM-mode operation.
Table 3. Recommended Component Values
COUT(min)
(µF)
CROSSOVER
(kHz)
0.36
PIMB065T-R36MS
3 × 100
247
70
48
62
10
0.68
PIMB065T-R68MS
9 × 22
207
53
25
84
31.6
1.2
PIMB065T-1R2MS
4 × 22
185
57
11
63
3.3
45.3
1.5
PIMB065T-1R5MS
3 × 22
185
57
9
59
5.5
82.5
2.2
PIMB065T-2R2MS
2 × 22
185
51
7
58
VOUT
(V)
RUPPER
(kΩ)
LOUT
(µH)
0.6
0
1.2
2.5
(1)
18
RLOWER
(kΩ)
10
(1)
PHASE COUT(max) INTERNAL
MARGIN
(µF)
RC SETTING
(1)
(°)
(µs)
40
30 x 100
80
40
30 x 100
80
40
30 x 100
80
40
30 x 100
80
40
30 x 100
80
INDUCTOR
ΔI/ICC(max)
ICC(max)
(A)
33%
33%
34%
8
33%
28%
All COUT(min) and COUT(max) capacitor specifications are 1206, X5R, 10 V.
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For higher output voltage at or above 2.0 V, additional phase boost might be required to secure sufficient phase
margin due to phase delay/loss for higher output voltage (large on-time (tON)) setting in a fixed on time topology
based operation.
A feedforward capacitor placing in parallel with RUPPER is found to be very effective to boost the phase margin at
loop crossover. Refer to TI application note SLVA289 for details.
Table 4. Mode Selection and Internal RAMP R-C Time Constant
MODE
SELECTION
RMODE
(kΩ)
ACTION
R-C TIME
CONSTANT (µs)
60
250
and
300
50
400
and
500
40
600
and
750
30
850
and
1000
120
250
and
300
100
400
and
500
80
600
and
750
60
850
and
1000
60
250
and
300
50
400
and
500
40
600
and
750
30
850
and
1000
120
250
and
300
100
400
and
500
80
600
and
750
60
850
and
1000
120
250
and
300
100
400
and
500
80
600
and
750
60
850
and
1000
0
Skip Mode
Pull down to GND
150
20
Connect to
PGOOD
FCCM (1)
150
FCCM
(1)
Connect to VREG
0
SWITCHING
FREQUENCIES
fSW (kHz)
Device goes into Forced CCM (FCCM) after PGOOD becomes high.
7.3.4.2 Sample and Hold Circuitry
CSP
Sampled_CSP
Buffer 1
C1
C2
Buffer 2
Figure 36. Sample and Hold Logic Circuitry
The sample and hold circuitry is the difference between D-CAP3 and D-CAP2. The sample and hold circuitry,
which is an advance control scheme to boost output voltage accuracy higher on the device, is one of features of
the device. The sample and hold circuitry generates a new DC voltage of CSN instead of the voltage which is
produced by RC2 and CC2 which allows for tight output-voltage accuracy and makes the device more competitive.
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CSP
CSN
CSN_NEW
(sample at valley of CSP)
CSP
CSN
CSN_NEW
(sample at valley of CSP)
Figure 37. Continuous Conduction Mode (CCM) With
Sample and Hold Circuitry
Figure 38. Discontinuous Conduction Mode (DCM) With
Sample and Hold Circuitry
CSP
CSN
CSP
CSN
Figure 40. Discontinuous Conduction Mode (DCM) Without
Sample and Hold Circuitry
1.25
1.25
1.23
1.23
1.21
1.21
1.19
1.17
1.15
VOUT (V)
VOUT (V)
Figure 39. Continuous Conduction Mode (CCM) Without
Sample and Hold Circuitry
VIN = 12 V
VDD = 5 V
VOUT = 1.2 V
fSW = 500 kHz
TA = 25°C
LOUT = 1 H
Mode = FCCM
1
2
3
1.19
1.17
D-CAP3
D-CAP2
1.15
4
5
6
7
8
9
10
11
Output Current (A)
12
VIN = 12 V
VDD = 5 V
VOUT = 1.2 V
fSW = 500 kHz
TA = 25°C
LOUT = 1 H
Mode = Auto-skip
1
2
4
D-CAP2
5
6
7
8
9
10
11
Output Current (A)
C013
Figure 41. Output Voltage vs Output Current
3
D-CAP3
12
C014
Figure 42. Output Voltage vs Output Current
7.3.4.3 Adaptive Zero-Crossing
The TPS53515 device uses an adaptive zero-crossing circuit to perform optimization of the zero inductor-current
detection during skip-mode operation. This function allows ideal low-side MOSFET turn-off timing. The function
also compensates the inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit.
Adaptive zero-crossing prevents SW-node swing-up caused by too-late detection and minimizes diode
conduction period caused by too-early detection. As a result, the device delivers better light-load efficiency.
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7.3.5 Power-Good
The TPS53515 device has power-good output that indicates high when switcher output is within the target. The
power-good function is activated after the soft-start operation is complete. If the output voltage becomes within
±8% of the target value, internal comparators detect the power-good state and the power-good signal becomes
high after a 1-ms internal delay. If the output voltage goes outside of ±16% of the target value, the power-good
signal becomes low after a 2-μs internal delay. The power-good output is an open-drain output and must be
pulled-up externally.
7.3.6 Current Sense and Overcurrent Protection
The TPS53515 device has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during
the OFF state and the controller maintains the OFF state during the period that the inductor current is larger than
the overcurrent trip level. To provide good accuracy and a cost-effective solution, the TPS53515 device supports
temperature compensated MOSFET RDS(on) sensing. Connect the TRIP pin to GND through the trip-voltage
setting resistor, RTRIP. The TRIP pin sources ITRIP current, which is 10 μA typically at room temperature, and the
trip level is set to the OCL trip voltage VTRIP as shown in Equation 4.
VTRIP = RTRIP ´ ITRIP
where
•
•
•
VTRIP is in mV
RTRIP is in kΩ
ITRIP is in µA
(4)
The inductor current is monitored by the voltage between the GND pin and SW pin so that the SW pin is properly
connected to the drain pin of the low-side MOSFET. ITRIP has a 3000-ppm/°C temperature slope to compensate
the temperature dependency of RDS(on). The GND pin acts as the positive current-sensing node. Connect the
GND pin to the proper current sensing device, (for example, the source pin of the low-side MOSFET.)
Because the comparison occurs during the OFF state, VTRIP sets the valley level of the inductor current. Thus,
the load current at the overcurrent threshold, IOCP, is calculated as shown in Equation 5.
IIND(ripple)
(VIN - VOUT )´ VOUT
VTRIP
VTRIP
1
IOCP =
+
=
+
´
2
2 ´ L ´ fSW
VIN
8 ´ RDS(on)
8 ´ RDS(on)L
(
)
(
)
where
•
•
RDS(on)L is the on-resistance of the low-side MOSFET
RTRIP is in kΩ
(5)
Equation 5 calculates the typical DC OCP level (typical low-side on-resistance [RDS(on)] of 5.9 mΩ should be
used); to design for worst case minimum OCP, maximum low-side on-resistance value of 8 mΩ should be used.
During an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the
output voltage tends to decrease. Eventually, the output voltage crosses the undervoltage-protection threshold
and shuts down.
For the TPS53515 device, the overcurrent protection maximum is recommended up to 14 A only.
7.3.7 Overvoltage and Undervoltage Protection
The TPS53515 device monitors a resistor-divided feedback voltage to detect overvoltage and undervoltage.
When the feedback voltage becomes lower than 68% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After 1 ms, the TPS53515 device latches OFF both
high-side and low-side MOSFETs drivers. The UVP function enables after soft-start is complete.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching
a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side
FET is turned on again for a minimum on-time. The TPS53515 device operates in this cycle until the output
voltage is pulled down under the UVP threshold voltage for 1 ms. After the 1-ms UVP delay time, the high-side
FET is latched off and low-side FET is latched on. The fault is cleared with a reset of VDD or by retoggling the
EN pin.
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7.3.8 Out-of-Bounds Operation
The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower
overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so
the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltageprotection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning
on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output
capacitor thus causing the output voltage to fall quickly toward the setpoint. During the operation, the cycle-bycycle negative current limit is also activated to ensure the safe operation of the internal FETs.
7.3.9 UVLO Protection
The TPS53515 device monitors the voltage on the VDD pin. If the VDD pin voltage is lower than the UVLO offthreshold voltage, the switch mode power supply shuts off. If the VDD voltage increases beyond the UVLO onthreshold voltage, the controller turns back on. UVLO is a nonlatch protection.
7.3.10 Thermal Shutdown
The TPS53515 device monitors internal temperature. If the temperature exceeds the threshold value (typically
140°C), TPS53515 device shuts off. When the temperature falls approximately 40°C below the threshold value,
the device turns on. Thermal shutdown is a nonlatch protection.
7.4 Device Functional Modes
7.4.1 Auto-Skip Eco-mode Light Load Operation
While the MODE pin is pulled to GND directly or through 150-kΩ resistor, the TPS53515 device automatically
reduces the switching frequency at light-load conditions to maintain high efficiency. This section describes the
operation in detail.
As the output current decreases from heavy load condition, the inductor current also decreases until the rippled
valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction
and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is
detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM).
The on-time is maintained to a level approximately the same as during continuous-conduction mode operation so
that discharging the output capacitor with a smaller load current to the level of the reference voltage requires
more time. The transition point to the light-load operation IO(LL) (for example: the threshold between continuousand discontinuous-conduction mode) is calculated as shown in Equation 6.
IOUT(LL ) =
(VIN - VOUT )´ VOUT
1
´
2 ´ L ´ fSW
VIN
where
•
fSW is the PWM switching frequency
(6)
Using only ceramic capacitors is recommended for Auto-skip mode.
7.4.2 Forced Continuous-Conduction Mode
When the MODE pin is tied to the PGOOD pin through a resistor, the controller operates in continuous
conduction mode (CCM) during light-load conditions. During CCM, the switching frequency maintained to an
almost constant level over the entire load range which is suitable for applications requiring tight control of the
switching frequency at the cost of lower efficiency.
22
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS53515 device is a high-efficiency, single-channel, synchronous-buck converter. The device suits lowoutput voltage point-of-load applications with 12-A or lower output current in computing and similar digital
consumer applications.
8.2 Typical Application
This design example describes a D-CAP3-mode, 8-A synchronous buck converter with integrated MOSFETs.
The device provides a fixed 1.2-V output at up to 8 A from a 12-V input bus.
R1
6.65 N
PGOOD
Thermal
Pad
C3
1 µF
C4
1 µF
23
22
21
20
19
18
17
16
GND
MODE
VREG
VDD
NC
VIN
VIN
VIN
FB
R6
150 N
SCL
28
SCL
SW
SDA
SW
27
PGND
14
PGND
13
PGND
12
PGND
11
PGND
10
TPS53515
SW
ALERT
SW
26
N/C
R8 ALERT
64.9 N
SDA
VBST
TRIP
EN
25
PGOOD
VO
ADDR
24
CIN
CIN
2.2 nF 3 × 22 µF
15
VIN
R2
2 k
1
2
3
4
5
6
7
8
9
PIMB065T±1R0MS-63
R4
249 N
R10
100 N
Thermal Pad
R5
VREG
105 N
VOUT
R7
0
C2
0.1 µF
1 µH
R3
3
COUT
6 × 22 µF
COUT
4 × 10 µF
EN
C1
470 pF
Figure 43. Application Circuit Diagram
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Typical Application (continued)
8.2.1 Design Requirements
This design uses the parameters listed in Table 5.
Table 5. Design Example Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
12
18
UNIT
INPUT CHARACTERISTIC
VIN
Voltage range
IMAX
Maximum input current
VIN = 5 V, IOUT = 8 A
5
No load input current
VIN = 12 V, IOUT = 0 A with auto skip mode
2.5
V
A
1
mA
OUTPUT CHARACTERISTICS
VOUT
Output voltage
1.2
Output voltage regulation
VRIPPLE
Output voltage ripple
ILOAD
Output load current
IOVER
Output over current
tSS
Soft-start time
Line regulation,
5 V ≤ VIN ≤ –14 V with FCCM
0.2%
Load regulation,
VIN = 12 V, 0 A ≤ IOUT ≤ 8 A with FCCM
0.5%
VIN = 12 V, IOUT = 8 A with FCCM
V
10
mVPP
0
12
11
A
1
ms
1
MHz
SYSTEMS CHARACTERISTICS
fSW
Switching frequency
η
Peak efficiency
VIN = 12 V, VOUT = 1.2 V, IOUT = 4 A
88.5%
η
Full load efficiency
VIN = 12 V, VOUT = 1.2 V, IOUT = 8 A
86.9%
TA
Operating temperature
25
ºC
8.2.2 Detailed Design Procedure
The external components selection is a simple process using D-CAP3 mode. Select the external components
using the following steps
8.2.2.1 Choose the Switching Frequency
The switching frequency is configured by the resistor divider on the RF pin. Select one of eight switching
frequencies from 250 kHz to 1 MHz. Refer to Table 1 for the relationship between the switching frequency and
resistor-divider configuration.
8.2.2.2 Choose the Operation Mode
Select the operation mode using Table 4.
8.2.2.3 Choose the Inductor
Determine the inductance value to set the ripple current at approximately ¼ to ½ of the maximum output current.
Larger ripple current increases output ripple voltage, improves signal-to-noise ratio, and helps to stabilize
operation.
L=
=
1
IIND(ripple ) ´ fSW
´
(V
IN(max ) - VOUT
)´V
OUT
VIN(max )
=
3
IOUT(max ) ´ fSW
(12 V - 1.2 V ) ´ 1.2 V
3
´
= 1.08 mH
6 ´ 500kHz
12 V
´
(V
IN(max ) - VOUT
)´V
OUT
VIN(max)
(7)
The inductor requires a low DCR to achieve good efficiency. The inductor also requires enough room above peak
inductor current before saturation. The peak inductor current is estimated using Equation 8.
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IIND(peak ) =
)
(
VIN(max ) - VOUT ´ VOUT 10 mA ´ R
(12 V - 1.2 V ) ´ 1.2 V
VTRIP
1
1
TRIP
+
´
=
+
´
8 ´ RDS(on ) L ´ fSW
VIN(max )
8 ´ 5.9mW
1mH ´ 500kHz
12 V
(8)
8.2.2.4 Choose the Output Capacitor
The output capacitor selection is determined by output ripple and transient requirement. When operating in CCM,
the output ripple has two components as shown in Equation 9. Equation 10 and Equation 11 define these
components.
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR)
(9)
VRIPPLE(C ) =
IL(ripple )
8 ´ COUT ´ fSW
(10)
VRIPPLE(ESR ) = IL(ripple ) ´ ESR
(11)
8.2.2.5 Determine the Value of R1 and R2
The output voltage is programmed by the voltage-divider resistors, R1 and R2, shown in Equation 12. Connect
R1 between the VFB pin and the output, and connect R2 between the VFB pin and GND. The recommended R2
value is from 1 kΩ to 20 kΩ. Determine R1 using Equation 12.
- 0.6
V
1.2 V - 0.6
´ R2 =
´ 10kW = 10kW
R1 = OUT
0.6
0.6
(12)
100
1.3
90
1.25
VOUT (V)
Efficiency (%)
8.2.3 Application Curves
80
fSW = 500 KHz, VIN = 12 V, VDD = 5 V
TA = 25°C, L OUT = 1 H, Mode = FCCM
Vout
Vout
VOUT = 0.6 V
V
OUT = 1 V
Vout
Vout
VOUT = 1.2 V
V
OUT = 1.5 V
VOUT = 1.8 V
V
Vout
Vout
OUT = 2.5 V
VOUT = 3.3 V
V
Vout
Vout
OUT = 5 V
70
60
0
2
4
6
8
10
Output Current (A)
1.2
1.15
V
VIN
IN ==55VV
VIN
12VV
V
IN ==12
VIN
= 18 V
V
IN = 18 V
1.1
12
0
2
4
C004
fSW = 500 KHz
VDD = 5 V
TA = 25°C
LOUT = 1 H
Mode = FCCM
VOUT = 1.2 V
1.25
1.2
1.15
8
10
C008
600
fSW = 500 kHz
VDD = 5 V
VOUT = 1.2 V
TA = 25°C
LOUT = 1 H
Mode = FCCM
550
500
450
V
VIN
IN ==55VV
V
VIN
IN ==55VV
VIN
12VV
V
IN ==12
VIN
= 18 V
V
IN = 18 V
1.1
0
2
4
6
8
10
Output Current (A)
12
VIN
12VV
V
IN ==12
VIN
= 18 V
V
IN = 18 V
400
1
2
3
4
5
6
7
8
9
10
11
Output Current (A)
C009
Figure 46. Output Voltage vs. Output Current
12
Figure 45. Output Voltage vs. Output Current
Frequency (KHz)
1.3
6
Output Current (A)
Figure 44. Efficiency vs. Output Current
VOUT (V)
fSW = 1 MHz
VDD = 5 V
VOUT = 1.2 V
TA = 25°C
LOUT = 1 H
Mode = Auto-skip
12
C012
Figure 47. Switching Frequency vs. Output Current
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PGOOD
PGOOD
VOUT
VOUT
50%
SW
50%
50%
SW
CTNL
CTNL
ILOAD = 6 A
ILOAD = 6 A
Figure 48. Start-Up Sequence
Figure 49. Shutdown Sequence
VOUT
VOUT
SW
SW
IOUT
IOUT
ILOAD from 0 A to 6 A
ILOAD from 6A to 0 A
Figure 50. Load Transient
Figure 51. Load Transient
VOUT
VOUT
SW
SW
IOUT
ILOAD from 0 A to 6A to 0 A
ILOAD = 0 A
Figure 52. Full Cycle Load Transient
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Figure 53. Output Voltage Ripple
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PGOOD
VOUT
VOUT
SW
SW
EN
ILOAD = 6 A
Preset VOUT = 0.5 V
Figure 54. Output Voltage Ripple
Figure 55. Prebias Start-Up
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9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 1.5 V and 18 V (4.5 V to 25 V
biased). This input supply must be well regulated. Proper bypassing of input supplies and internal regulators is
also critical for noise performance, as is PCB layout and grounding scheme. See the recommendations in the
Layout section.
10 Layout
10.1 Layout Guidelines
Before beginning a design using the TPS53515 device, consider the following:
• Place the power components (including input and output capacitors, the inductor, and the DPA02259 device)
on the solder side of the PCB. To shield and isolate the small signal traces from noisy power lines, insert and
connect at least one inner plane to ground.
• All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE, and RF must be placed
away from high-voltage switching nodes such as SW and VBST to avoid coupling. Use internal layers as
ground planes and shield the feedback trace from power traces and components.
• GND (pin 22) must be connected directly to the thermal pad. Connect the thermal pad to the PGND terminals
and then to the GND plane.
• The GND1 terminal (pin 27) and the GND2 terminal (pin 28) are not actual GND terminals and neither of
these terminals should be used for dedicated ground connection. The recommendation is to connect GND1
terminal (pin 27) and the GND2 terminal (pin 28) to the nearby ground.
• Place the VIN decoupling capacitors as close to the VIN and PGND terminals as possible to minimize the
input AC-current loop.
• Place the feedback resistor near the device to minimize the VFB trace distance.
• Place the frequency-setting resistor (RRF), OCP-setting resistor (RTRIP) and mode-setting resistor (RMODE)
close to the device. Use the common GND via to connect the resistors to the GND plane if applicable.
• Place the VDD and VREG decoupling capacitors as close to the device as possible. Provide GND vias for
each decoupling capacitor and ensure the loop is as small as possible.
• This design defines the PCB trace as a switch node, which connects the SW terminals and high-voltage side
of the inductor. The switch node should be as short and wide as possible.
• Use separated vias or trace to connect SW node to the snubber, bootstrap capacitor, and ripple-injection
resistor. Do not combine these connections.
• Place one more small capacitor (2.2-nF, 0402 size) between the VIN and PGND terminals. This capacitor
must be placed as close to the device as possible.
• TI recommends placing a snubber between the SW shape and GND shape for effective ringing reduction.
The value of snubber design starts at 3 Ω + 470 pF.
• Consider R-C-CC network (ripple injection network) component placement and place the AC coupling
capacitor, CC, close to the device, and R and C close to the power stage. (Application designs with output
capacitance lower than the minimum may require only an R-C-C network. In this case, Bode plot verification
is needed to validate the design).
• See Figure 56 for the layout recommendation.
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10.2 Layout Example
VIN Shape
To inner GND plane
CIN
VIN
VIN
VIN
1
8
1
7
1
6
1
5
2
6
2
7
1
2
3
4
5
6
7
8
9
SW
SW
SW
SW
PGND
NC
PGND
VBST
PGND
EN
PGND
PGOOD
PGND
RF
2
8
GND2
Trace on bottom layer
Trace on inner layer
GND1
2
5
DNC
1
4
NC
1
9
1
3
VDD
2
0
1
2
VREG
2
1
1
1
MODE
2
2
1
0
TRIP
2
3
2
4
VO
GND
To VOUT Shape
FB
Cc
HF cap.
SW Shape
GND Shape
COUT
VOUT Shape
LOUT
To VREG Pin
Cap. Res.
Trace on bottom layer
Trace of top layer
RCC On Bottom layer
Trace of bottom layer
Trace on inner layer
Figure 56. Layout Recommendation
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10.3 Thermal Performance
TA = 23°C, fSW = 500 kHz, VIN = 12 V, VOUT = 1.24 V, IOUT = 8 A, RBOOT= 0 Ω, SNB = 3 Ω + 470 pF
Inductor: LOUT = 1 µH, PIMB103T-1R0MS-63, 10 mm × 11.2 mm × 3 mm, 5.3 mΩ
Figure 57. SP1: 43℃
℃ (TPS53515), SP2: 35.1℃
℃ (Inductor)
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor,
SLVA289
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
D-CAP3, SWIFT, Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS53515RVER
ACTIVE
VQFN-CLIP
RVE
28
3000
RoHS-Exempt
& Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 85
TPS53515
TPS53515RVET
ACTIVE
VQFN-CLIP
RVE
28
250
RoHS-Exempt
& Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 85
TPS53515
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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