TPS54060MDGQTEP

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS54060-EP SLVSCF8 – JULY 2014 TPS54060-EP 0.5-A, 60-V Step-Down DC/DC Converter With Eco-Mode™ 1 Features 2 Applications • • • • 1 • • • • • • • • • • • 3.5- to 60-V Input Voltage Range 200-mΩ High-Side MOSFET High Efficiency at Light Loads With a Pulse Skipping Eco-Mode™ 116-μA Operating Quiescent Current 1.3-μA Shutdown Current 100-kHz to 2.5-MHz Switching Frequency Synchronizes to External Clock Adjustable Slow Start/Sequencing UV and OV Power Good Output Adjustable UVLO Voltage and Hysteresis 0.8-V Internal Voltage Reference MSOP10 Package With PowerPAD™ Supported by SwitcherPro™ Software Tool (http://focus.ti.com/docs/toolsw/folders/print/switch erpro.html) Supports Defense, Aerospace, and Medical Applications – Controlled Baseline – One Assembly and Test Site – One Fabrication Site – Available in Military (–55°C to 125°C) Temperature Range – Extended Product Life Cycle – Extended Product-Change Notification – Product Traceability • 12-V, 24-V, and 48-V Industrial and Commercial Low Power Systems Aftermarket Auto Accessories: Video, GPS, Entertainment 3 Description The TPS54060 device is a 60-V, 0.5-A, step-down regulator with an integrated high-side MOSFET. Current mode control provides simple external compensation and flexible component selection. A low-ripple pulse skip mode reduces the no load, regulated output supply current to 116 μA. Using the enable pin, shutdown supply current is reduced to 1.3 μA when the enable pin is low. Undervoltage lockout is internally set at 2.5 V, but can be increased using the enable pin. The output voltage startup ramp is controlled by the slow start pin that can also be configured for sequencing/tracking. An open-drain power good signal indicates the output is within 93% to 107% of its nominal voltage. A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold back and thermal shutdown protects the part during an overload condition. The TPS54060 is available in a 10-pin thermallyenhanced MSOP10 PowerPAD package. Device Information(1) PACKAGE BODY SIZE (NOM) TPS54060MDGQTEP HVSSOP (10) ORDER NUMBER 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic VIN Efficiency vs Load Current PWRGD 100 TPS54060 90 80 BOOT PH SS /TR RT /CLK COMP 70 Efficiency (%) EN 60 50 40 30 VSENSE VI = 12 V VO = 3.3 V ƒsw = 500 kHz 20 10 GND 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Load Current (A) 0.4 0.45 0.5 C033 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 4 4 4 5 5 7 Absolute Maximum Ratings ..................................... Handling Ratings ...................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. 8.4 Device Functional Modes........................................ 27 9 Application and Implementation ........................ 29 9.1 Application Information............................................ 29 9.2 Typical Application .................................................. 29 10 Power Supply Recommendations ..................... 38 10.1 Power Dissipation Estimate .................................. 38 10.2 Power Supply Considerations............................... 38 11 Layout................................................................... 40 11.1 Layout Guidelines ................................................. 40 11.2 Layout Example .................................................... 41 12 Device and Documentation Support ................. 42 12.1 12.2 12.3 12.4 Detailed Description ............................................ 11 8.1 Overview ................................................................. 11 8.2 Functional Block Diagram ....................................... 12 8.3 Feature Description................................................. 12 Device Support...................................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 42 42 42 42 13 Mechanical, Packaging, and Orderable Information ........................................................... 42 5 Revision History 2 DATE REVISION NOTES July 2014 * Initial release. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 6 Pin Configuration and Functions DGQ Package 10 Pins (Top View) BOOT VIN EN SS/TR RT/CLK 1 10 2 9 3 4 5 Thermal Pad (11) 8 7 6 PH GND COMP VSENSE PWRGD Pin Functions PIN NAME NO. I/O DESCRIPTION BOOT 1 O A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. COMP 8 O Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. EN 3 I Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input undervoltage lockout (UVLO) with two resistors. GND 9 — PH 10 I PowerPAD 11 — GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. PWRGD 6 O An open-drain output, asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or EN shut down. Ground The source of the internal high-side power MOSFET. RT/CLK 5 I Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is reenabled and the mode returns to a resistor set function. SS/TR 4 I Slow-start and tracking. An external capacitor connected to this pin sets the output rise time. Because the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. VIN 2 I Input supply voltage, 3.5 to 60 V. VSENSE 7 I Inverting node of the transconductance (gM) error amplifier. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating temperature range (unless otherwise noted) MIN MAX VIN –0.3 65 EN –0.3 5 BOOT Input voltage 75 VSENSE –0.3 3 COMP –0.3 3 PWRGD –0.3 6 SS/TR –0.3 3 RT/CLK –0.3 3.6 –0.6 65 –2 65 –200 200 BOOT-PH Output voltage Source current PAD to GND mV 100 μA BOOT 100 mA 10 μA VSENSE Current limit A 100 μA RT/CLK VIN Current limit A 100 μA COMP PWRGD SS/TR Operating junction temperature (1) V EN PH Sink current V 8 PH PH, 10-ns transient Voltage difference UNIT –55 10 mA 200 μA 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 Handling Ratings MIN Tstg Storage temperature range V(ESD) (1) Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) (1) (2) MAX UNIT °C –65 150 –1000 1000 –500 500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT TA Ambient temperature –55 125 °C TJ Junction temperature –55 150 °C 3.5 60 V V(VIN) 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 7.4 Thermal Information TPS54060 THERMAL METRIC (1) (2) DGQ (10 PINS) Junction-to-ambient thermal resistance (standard board) 62.5 Junction-to-ambient thermal resistance (custom board) (3) 57 RθJC(top) Junction-to-case (top) thermal resistance 83 RθJB Junction-to-board thermal resistance 28 ψJT Junction-to-top characterization parameter 1.7 ψJB Junction-to-board characterization parameter 20.1 RθJC(bot) Junction-to-case (bottom) thermal resistance 21 RθJA (1) (2) (3) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information. Test boards conditions: (a) 3 inches × 3 inches, 2 layers, thickness: 0.062 inch (b) 2-oz. copper traces located on the top of the PCB (c) 2-oz. copper ground plane, bottom layer (d) 6 thermal vias (13 mil) located under the device package 7.5 Electrical Characteristics TJ = –55°C to 150°C, VIN = 3.5 to 60 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) Operating input voltage 3.5 60 Internal UVLO threshold No voltage hysteresis, rising and falling 2.5 Shutdown supply current V(EN) = 0 V, 3.5 V ≤ V(VIN) ≤ 60 V 1.3 8 Operating: nonswitching supply current V(VSENSE) = 0.83 V, V(VIN) = 12 V 116 150 1.25 1.6 V V μA ENABLE AND UVLO (EN PIN) Enable threshold voltage Input current No voltage hysteresis, rising and falling 0.9 Enable threshold 50 mV –3.8 Enable threshold –50 mV –0.9 Hysteresis current V μA μA –2.9 VOLTAGE REFERENCE Voltage reference TJ = 25°C 0.792 0.8 0.808 0.78 0.8 0.821 V HIGH-SIDE MOSFET On-resistance V(VIN) = 3.5 V, BOOT-PH = 3 V 300 V(VIN) = 12 V, BOOT-PH = 6 V 200 465 mΩ ERROR AMPLIFIER Input current 50 nA Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 97 μMhos Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V, during slow start V(VSENSE) = 0.4 V 26 μMhos Error amplifier dc gain V(VSENSE) = 0.8 V Error amplifier bandwidth Error amplifier source/sink COMP to switch current transconductance Copyright © 2014, Texas Instruments Incorporated V(COMP) = 1 V, 100 mV overdrive 10000 V/V 2700 kHz ±7 μA 1.9 A/V Submit Documentation Feedback 5 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com Electrical Characteristics (continued) TJ = –55°C to 150°C, VIN = 3.5 to 60 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.5 0.94 A 182 °C CURRENT LIMIT Current limit threshold V(VIN) = 12 V THERMAL SHUTDOWN Thermal shutdown TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) ƒSW Switching frequency range using RT mode V(VIN) = 12 V 130 Switching frequency V(VIN) = 12 V, RT = 200 kΩ 440 Switching frequency range using CLK mode V(VIN) = 12 V 300 Minimum CLK input pulse width 581 2500 kHz 740 kHz 2200 kHz 40 RT/CLK high threshold V(VIN) = 12 V RT/CLK low threshold V(VIN) = 12 V 1.9 RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series PLL lock in time Measured at 500 kHz 0.5 ns 2.2 V 0.7 V 60 ns 100 μs 2 μA mV SLOW START AND TRACKING (SS/TR) Charge current V(SS/TR) = 0.4 V SS/TR-to-VSENSE matching V(SS/TR) = 0.4 V 45 SS/TR-to-reference crossover 98% nominal 1.0 V SS/TR discharge current (overload) V(VSENSE) = 0 V, V(SS/TR) = 0.4 V 112 μA SS/TR discharge voltage V(VSENSE) = 0 V 54 mV POWER GOOD (PWRGD PIN) VSENSE falling (fault) V(VSENSE) 6 VSENSE threshold 92% VSENSE rising (good) 94% VSENSE rising (fault) 109% VSENSE falling (good) 107% Hysteresis VSENSE falling Output high leakage V(VSENSE) = VREF, V(PWRGD) = 5.5 V, 25°C 10 On resistance I(PWRGD) = 3 mA, V(VSENSE) < 0.79 V 50 Minimum VIN for defined output V(PWRGD) < 0.5 V, I(PWRGD) = 100 μA 0.95 Submit Documentation Feedback 2% nA Ω 1.5 V Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 500 0.815 400 0.810 Voltage Reference (V) Static Drain-Source On-6WDWH5HVLVWDQFHP  7.6 Typical Characteristics 300 200 100 0.805 0.800 0.795 BOOT-PH = 3 V BOOT-PH = 6 V 0 0.790 ±75 ±55 ±35 ±15 5 25 45 65 85 105 125 145 165 Junction Temperature (ƒC) ±75 ±55 ±35 ±15 VIN = 12 V Figure 1. On Resistance vs Junction Temperature 65 85 105 125 145 165 C002 Figure 2. Voltage Reference vs Junction Temperature Switching Frequency (kHz) Switch Current (A) 45 600 0.9 0.8 0.7 0.6 590 580 570 560 550 0.5 ±75 ±55 ±35 ±15 5 25 45 65 ±75 ±55 ±35 ±15 85 105 125 145 165 Junction Temperature (ƒC) VIN = 12 V 2000 400 Switching Frequency (kHz) 500 1000 500 0 25 VIN = 12 V 50 75 100 125 150 RT/CLK Resistance (kW) 175 200 Figure 5. Switching Frequency vs RT/CLK Resistance High Frequency Range Copyright © 2014, Texas Instruments Incorporated 45 65 85 105 125 145 165 C002 RT = 200 kΩ 300 200 100 0 200 300 400 C005 TJ = 25°C 25 Figure 4. Switching Frequency vs Junction Temperature Figure 3. Switch Current Limit vs Junction Temperature 2500 1500 5 Junction Temperature (ƒC) C002 VIN = 12 V Switching Frequency (kHz) 25 VIN = 12 V 1.0 0 5 Junction Temperature (ƒC) C001 VIN = 12 V 500 600 700 800 900 1000 1100 1200 RT/CLK Resistance (kW) C006 TJ = 25°C Figure 6. Switching Frequency vs RT/CLK Resistance Low Frequency Range Submit Documentation Feedback 7 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com Typical Characteristics (continued) 130 40.000 110 gm (µA/V) gm (µA/V) 30.000 90 20.000 70 50 10.000 ±75 ±55 ±35 ±15 5 25 45 65 ±75 ±55 ±35 ±15 85 105 125 145 165 Junction Temperature (ƒC) 1.250 ±3.65 1.230 ±3.70 1.210 ±3.75 I(EN) (µA) Threshold (V) 45 65 85 105 125 145 165 C002 Figure 8. EA Transconductance vs Junction Temperature Figure 7. EA Transconductance During Slow Start vs Junction Temperature 1.190 1.170 ±3.80 ±3.85 1.150 ±3.90 ±75 ±55 ±35 ±15 5 25 45 65 85 105 125 145 165 Junction Temperature (ƒC) ±75 ±55 ±35 ±15 VIN = 12 V Figure 9. EN Pin Voltage vs Junction Temperature ±0.600 ±2.050 ±0.620 ±2.100 I(SS/TR) (µA) ±2.000 ±0.640 ±2.200 ±0.680 ±2.250 ±75 ±55 ±35 ±15 5 25 45 65 85 105 125 145 165 Junction Temperature (ƒC) Figure 11. EN Pin Current vs Junction Temperature Submit Documentation Feedback 65 85 105 125 145 165 C002 V(EN) = Threshold 50 mV ±2.300 ±75 ±55 ±35 ±15 5 25 45 65 85 105 125 145 165 Junction Temperature (ƒC) C002 V(EN) = Threshold –50 mV 45 ±2.150 ±0.660 ±0.700 25 Figure 10. EN Pin Current vs Junction Temperature ±0.580 VIN = 12 V 5 Junction Temperature (ƒC) C002 VIN = 12 V I(EN) (µA) 25 VIN = 12 V VIN = 12 V 8 5 Junction Temperature (ƒC) C002 C002 VIN = 12 V Figure 12. SS/TR Charge Current vs Junction Temperature Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 115.000 100 110.000 80 % of Nominal fsw I(SS/TR) (µA) Typical Characteristics (continued) 105.000 100.000 60 40 95.000 20 90.000 ±75 ±55 ±35 ±15 5 25 45 65 85 105 125 145 165 Junction Temperature (ƒC) 0 C002 0 VIN = 12 V 0.2 0.4 VSENSE (V) VIN = 12 V Figure 13. SS/TR Discharge Current vs Junction Temperature 0.6 0.8 C014 TJ = 25°C Figure 14. Switching Frequency vs VSENSE 2 1.500 1.5 I(VIN) (μA) I(VIN) (µA) 1.000 0.500 1 0.5 0.000 5 ±75 ±55 ±35 ±15 25 45 65 85 105 125 145 165 Junction Temperature (ƒC) 0 C002 0 10 20 VIN = 12 V 30 40 Input Voltage (V) 50 60 C016 TJ = 25°C Figure 15. Shutdown Supply Current vs Junction Temperature Figure 16. Shutdown Supply Current vs Input Voltage (VIN) 140 130.000 125.000 130 I(VIN) (μA) I(VIN) (µA) 120.000 115.000 110.000 120 110 105.000 100 100.000 ±75 ±55 ±35 ±15 5 25 45 65 85 105 125 145 165 Junction Temperature (ƒC) VIN = 12 V 90 C002 V(VSENSE) = 0.83 V 0 20 TJ = 25°C Figure 17. VIN Supply Current vs Junction Temperature Copyright © 2014, Texas Instruments Incorporated 40 60 Input Voltage (V) C018 V(VSENSE) = 0.83 V Figure 18. VIN Supply Current vs Input Voltage Submit Documentation Feedback 9 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com Typical Characteristics (continued) 120.00 PWRGD Threshold (% of Vref) 80.000 RDSON (Ÿ) 60.000 40.000 20.000 110.00 100.00 90.00 VSENSE Rising (Fault) VSENSE Falling (Good) VSENSE Rising (Good) VSENSE Falling (Fault) 80.00 0.000 ±75 ±55 ±35 ±15 5 25 45 65 ±75 ±55 ±35 ±15 85 105 125 145 165 Junction Temperature (ƒC) 5 25 45 65 85 105 125 145 165 Junction Temperature (ƒC) C002 C002 VIN = 12 V VIN = 12 V Figure 20. PWRGD Threshold vs Junction Temperature Figure 19. PWRGD On Resistance vs Junction Temperature 2.400 2.580 2.560 2.300 2.520 V(VIN) (V) V(BOOT-PH) (V) 2.540 2.200 2.100 2.000 2.500 2.480 2.460 2.440 1.900 2.420 1.800 2.400 ±75 ±55 ±35 ±15 5 25 45 65 85 105 125 145 165 Junction Temperature (ƒC) ±75 ±55 ±35 ±15 25 45 65 85 105 125 145 165 C002 Figure 22. Input Voltage (UVLO) vs Junction Temperature 55.000 400 50.000 Offset (mV) Offset (mV) Figure 21. Boot-PH UVLO vs Junction Temperature 500 300 5 Junction Temperature (ƒC) C002 45.000 40.000 200 35.000 100 30.000 ±75 ±55 ±35 ±15 0 0 100 200 VIN = 12 V 300 400 500 VSENSE (mV) 600 700 800 25 45 65 85 105 125 145 165 VIN = 12 mV C002 V(SS/TR) = 0.2 V TJ = 25°C Figure 23. SS/TR To Vsense Offset vs VSENSE 10 C023 5 Junction Temperature (ƒC) Submit Documentation Feedback Figure 24. SS/TR To VSENSE Offset vs Temperature Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 8 Detailed Description 8.1 Overview The TPS54060 device is a 60-V, 0.5-A, step-down (buck) regulator with an integrated high-side N-channel MOSFET. To improve performance during line and load transients, the device implements a constant frequency, current mode control, which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 100 to 2500 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock. The TPS54060 has a default start-up voltage of approximately 2.5 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage UVLO threshold with two external resistors. In addition, the pullup current provides a default condition. When the EN pin is floating, the device will operate. The operating current is 116 μA when not switching and under no load. When the device is disabled, the supply current is 1.3 μA. The integrated 200-mΩ high-side MOSFET allows for high-efficiency power supply designs capable of delivering 0.5 A of continuous current to a load. The TPS54060 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the boot voltage falls below a preset threshold. The TPS54060 can operate at high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8-V reference. The TPS54060 has a power good comparator (PWRGD), which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open-drain output which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage, allowing the pin to transition high when a pullup resistor is used. The TPS54060 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power good comparator. When the OV comparator is activated, the high-side MOSFET is turned off and masked from turning on until the output voltage is lower than 107%. The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor should be coupled to the pin to adjust the slow start time. A resistor divider can be coupled to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged before the output powers up. This discharging ensures a repeatable restart after an overtemperature fault, UVLO fault, or a disabled condition. The TPS54060, also, discharges the slow-start capacitor during overload conditions with an overload recovery circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage after a fault condition is removed. A frequency foldback circuit reduces the switching frequency during startup and overcurrent fault conditions to help control the inductor current. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 11 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com 8.2 Functional Block Diagram PWRGD 6 EN 3 VIN 2 Shutdown UV Thermal Shutdown Enable Comparator Logic UVLO Shutdown Shutdown Logic OV Enable Threshold Boot Charge Voltage Reference Boot UVLO Minimum Clamp Pulse Skip ERROR AMPLIFIER PWM Comparator VSENSE 7 Current Sense 1 BOOT Logic And PWM Latch SS/TR 4 Shutdown Slope Compensation 10 PH COMP 8 11 POWERPAD Frequency Shift Overload Recovery Maximum Clamp Oscillator with PLL TPS54060 Block Diagram 9 GND 5 RT/CLK 8.3 Feature Description 8.3.1 Fixed Frequency PWM Control The TPS54060 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn-on of the high-side power switch. The error amplifier output is compared to the high-side power switch current. When the power switch current reaches the level set by the COMP voltage, the power switch is turned off. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximum level. Eco-Mode implements with a minimum clamp on the COMP pin. 8.3.2 Slope Compensation Output Current The TPS54060 adds a compensating ramp to the switch current signal. This slope compensation prevents subharmonic oscillations. The available peak inductor current remains constant over the full duty cycle range. 8.3.3 Low-Dropout Operation and Bootstrap Voltage (Boot) The TPS54060 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the low-side diode conducts. The value of this ceramic capacitor should be 0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher because of the stable characteristics overtemperature and voltage. 12 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 Feature Description (continued) To improve dropout, the TPS54060 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.1 V. When the voltage from BOOT to PH drops below 2.1 V, the high-side MOSFET is turned off using an UVLO circuit, which allows the low-side diode to conduct and refresh the charge on the BOOT capacitor. Because the supply current sourced from the BOOT capacitor is low, the high-side MOSFET can remain on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the switching regulator is high. The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the power MOSFET, inductor resistance, low-side diode and printed circuit board resistance. During operating conditions in which the input voltage drops and the regulator is operating in continuous conduction mode (CCM), the high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT to PH voltage falls below 2.1 V. Take care in maximum duty cycle applications which experience extended time periods with light loads or no load. When the voltage across the BOOT capacitor falls below the 2.1-V UVLO threshold, the high-side MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the BOOT capacitor. The high-side MOSFET of the regulator stops switching because the voltage across the BOOT capacitor is less than 2.1 V. The output capacitor then decays until the difference in the input voltage and output voltage is greater than 2.1 V, at which point the BOOT UVLO threshold is exceeded, and the device starts switching again until the desired output voltage is reached. This operating condition persists until the input voltage and/or the load current increases. TI recommends to adjust the VIN stop voltage greater than the BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO feature with resistors on the EN pin. The start and stop voltages for typical 3.3- and 5-V output applications are shown in Figure 25 and Figure 26. The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops switching. 4 5.6 3.8 5.4 3.6 Input Voltage (V) Input Voltage (V) During high duty cycle conditions, the inductor current ripple increases while the BOOT capacitor is being recharged, resulting in an increase in ripple voltage on the output. This increase occurs because the recharge time of the boot capacitor is longer than the typical high-side off time when switching occurs every cycle. Start 3.4 Stop 5.2 Start 5 Stop 4.8 3.2 3 4.6 0 0.05 0.10 Output Current (A) 0.15 VO = 3.3 V Figure 25. 3.3-V Start/Stop Voltage 0.20 0 0.05 C025 0.10 Output Current (A) 0.15 0.20 C026 VO = 5 V Figure 26. 5-V Start/Stop Voltage 8.3.4 Error Amplifier The TPS54060 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 97 μA/V during normal operation. During slow-start operation, the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below 0.8 V and the device is regulating using the SS/TR voltage, the gm is 25 μA/V. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 13 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com The frequency compensation components (capacitor, series resistor, and capacitor) are added to the COMP pin to ground. 8.3.5 Voltage Reference The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output of a temperature stable bandgap circuit. 8.3.6 Adjusting the Output Voltage The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors. Start with a 10 kΩ for the R2 resistor and use the Equation 1 to calculate R1. To improve efficiency at light loads consider using larger value resistors. If the values are too high the regulator will be more susceptible to noise and voltage errors from the VSENSE input current will be noticeable æ Vout - 0.8V ö R1 = R2 ´ ç ÷ 0.8 V è ø (1) 8.3.7 Enable and Adjusting UVLO The TPS54060 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher UVLO, use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using the two external resistors. Though it is not necessary to use the UVLO adjust registers for operation, TI highly recommends to provide consistent power-up behavior. The EN pin has an internal pullup current source, I1, of 0.9 μA that provides the default condition of the TPS54060 device operating when the EN pin floats. After the EN pin voltage exceeds 1.25 V, an additional 2.9 μA of hysteresis, Ihys, is added. This additional current facilitates input voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation 3 to set the input start voltage. TPS54060 VIN Ihys I1 0.9 mA R1 2.9 mA + R2 EN 1.25 V - Figure 27. Adjustable UVLO V - VSTOP R1 = START IHYS R2 = VENA VSTART - VENA + I1 R1 (2) (3) Figure 28 shows another technique to add input voltage hysteresis. Use this method if the resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3 sources additional hysteresis current into the EN pin. 14 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 TPS54060 VIN R1 Ihys I1 0.9 mA 2.9 mA + R2 EN 1.25 V R3 - VOUT Figure 28. Adding Additional Hysteresis R1 = R2 = VSTART - VSTOP V IHYS + OUT R3 (4) VENA VSTART - VENA V + I1 - ENA R1 R3 (5) 8.3.8 Slow Start/Tracking Pin (SS/TR) The TPS54060 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The TPS54060 has an internal pullup current source of 2 μA that charges the external slow start capacitor. Equation 6 shows the calculations for the slow start time (10% to 90%). The voltage reference (VREF) is 0.8 V and the slow start current (ISS) is 2 μA. The slow start capacitor should remain lower than 0.47 μF and greater than 0.47 nF. Tss(ms) ´ Iss(m A) Css(nF) = Vref (V) ´ 0.8 (6) At power up, the TPS54060 does not start switching until the slow-start pin is discharged to less than 40 mV to ensure a proper power up, see Figure 29. Also, during normal operation, the TPS54060 stops switching and the SS/TR must be discharged to 40 mV when either the VIN UVLO is exceeded, EN pin is pulled below 1.25 V, or a thermal shutdown event occurs. The VSENSE voltage follows the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage, the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23). The SS/TR voltage ramps linearly until clamped at 1.7 V. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 15 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com EN SS/TR VSENSE VOUT Figure 29. Operation of SS/TR Pin When Starting 8.3.9 Overload Recovery Circuit The TPS54060 has an overload recovery (OLR) circuit. The OLR circuit slow starts the output from the overload voltage to the nominal regulation voltage after the fault condition is removed. The OLR circuit discharges the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pulldown of 100 μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is removed, the output slow starts from the fault voltage to nominal output voltage. 8.3.10 Sequencing Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins. The sequential method can be implemented using an open-drain output of a power on reset pin of another device. Figure 30 shows the sequential method using two TPS54060 devices. The power good is coupled to the EN pin on the TPS54060, which enables the second power supply after the primary supply reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply provides a 1ms start-up delay. Figure 31 shows the results of Figure 30. 16 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 TPS54060 EN PWRGD EN EN1 SS /TR SS /TR PWRGD1 PWRGD VOUT1 VOUT2 Figure 30. Schematic for Sequential Start-Up Sequence Figure 31. Sequential Startup Using EN and PWRGD TPS54160 TPS54060 3 EN 4 SS/TR 6 PWRGD EN1, EN2 VOUT1 TPS54060 TPS54160 VOUT2 3 EN 4 SS/TR 6 PWRGD Figure 32. Schematic for Ratiometric Start-Up Sequence Figure 33. Ratiometric Startup Using Coupled SS/TR Pins Figure 32 shows a method for ratiometric start-up sequence by connecting the SS/TR pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start time, the pullup current source must be doubled in Equation 6. Figure 33 shows the results of Figure 32. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 17 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com TPS54060 EN VOUT 1 SS/TR PWRGD TPS54060 VOUT 2 EN R1 SS/ TR R2 PWRGD R3 R4 Figure 34. Schematic for Ratiometric and Simultaneous Start-Up Sequence Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 (see Figure 34) to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 7 and Equation 8, the tracking resistors can be calculated to initiate the Vout2 slightly before, after, or at the same time as Vout1. Equation 9 is the voltage difference between Vout1 and Vout2 at the 95% of nominal output regulation. The deltaV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset) in the slow start circuit and the offset created by the pullup current source (Iss) and tracking resistors, the Vssoffset and Iss are included as variables in the equations. To design a ratiometric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 7 through Equation 9 for deltaV. Equation 9 results in a positive number for applications in which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. Because the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO, or thermal shutdown fault, carefully select the tracking resistors to ensure the device will restart after a fault. Make sure the calculated R1 value from Equation 7 is greater than the value calculated in Equation 10 to ensure the device can recover from a fault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage, the Vssoffset becomes larger as the slow start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pin voltage must be greater than 1.3 V for a complete handoff to the internal voltage reference, as shown in Figure 23. Vout2 + deltaV Vssoffset R1 = ´ VREF Iss (7) VREF ´ R1 R2 = Vout2 + deltaV - VREF (8) deltaV = Vout1 - Vout2 (9) R1 > 2800 ´ Vout1 - 180 ´ deltaV (10) 18 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 EN EN VOUT1 VOUT1 VOUT2 Figure 35. Ratiometric Startup With Tracking Resistors VOUT2 Figure 36. Ratiometric Startup With Tracking Resistors EN VOUT1 VOUT2 Figure 37. Simultaneous Startup With Tracking Resistor 8.3.11 Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS54060 is adjustable over a wide range from approximately 100 to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 11 or the curves in Figure 38 or Figure 39. To reduce the solution size, one would typically set the switching frequency as high as possible, but consider tradeoffs of the supply efficiency, maximum input voltage, and minimum controllable on-time. The minimum controllable on-time is typically 130 ns and limits the maximum operating input voltage. The maximum switching frequency is also limited by the frequency shift circuit. More details of the maximum switching frequency follow. 206033 RT (kOhm ) = ¦ sw (kHz )1.0888 (11) Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 19 TPS54060-EP www.ti.com 2500 500 2000 400 Switching Frequency (kHz) Switching Frequency (kHz) SLVSCF8 – JULY 2014 1500 1000 500 0 0 25 VI = 12 V 50 75 100 125 150 RT/CLK Resistance (kW) 175 200 300 200 100 0 200 300 400 C005 TJ = 25°C Figure 38. High Range RT VI = 12 V 500 600 700 800 900 1000 1100 1200 RT/CLK Resistance (kW) C006 TJ = 25°C Figure 39. Low Range RT 8.3.12 Overcurrent Protection and Frequency Shift The TPS54060 implements current mode control, which uses the COMP pin voltage to turn off the high-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and COMP pin voltage are compared. When the peak switch current intersects the COMP voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current limit. To increase the maximum operating switching frequency at high input voltages, the TPS54060 implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Because the device can only divide the switching frequency by 8, there is a maximum input voltage limit in which the device operates and still has frequency-shift protection. During short-circuit events (particularly with high input voltage applications), the control loop has a finite minimum controllable on-time and the output has a low voltage. During the switch on time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on-time. During the switch off time, the inductor would usually not have enough off time and output voltage for the inductor to ramp down by the ramp up amount. The frequency shift effectively increases the off time allowing the current to ramp down. 8.3.13 Selecting the Switching Frequency Select the switching frequency that is the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on-time. Setting the switching frequency above this value will cause the regulator to skip switching pulses. Equation 13 is the maximum switching frequency limit set by the frequency shift protection. To have adequate output short-circuit protection at high input voltages, the switching frequency should be set to be less than the ƒsw(maxshift) frequency. In Equation 13, to calculate the maximum switching frequency one must take into account that the output voltage decreases from the nominal voltage to 0 V, the fdiv integer increases from 1 to 8 corresponding to the frequency shift. In Figure 40, the solid line shows a typical safe operating area regarding frequency shift and assumes the output voltage is 0 V and the resistance of the inductor is 0.130 Ω, FET on-resistance of 0.2 Ω, and the diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these equations in a spreadsheet, other software, or use the SwitcherPro design software to determine the switching frequency. æ 1 ö æ (IL ´ Rdc + VOUT + Vd) ö fSW (max skip ) = ç ÷ ÷ ´ çç ÷ è tON ø è (VIN - IL ´ Rhs + Vd) ø (12) 20 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com fSW (hift ) = SLVSCF8 – JULY 2014 fdiv æ (IL ´ Rdc + VOUTSC + Vd) ö ´ç ÷ t ON çè (VIN - IL x Rhs + Vd ) ÷ø (13) where • IL = Inductor current • Rdc = Inductor resistance • VIN = Maximum input voltage • VOUT = Output voltage • VOUTSC = Output voltage during short • Vd = Diode voltage drop • RDS(on) = Switch on resistance • tON = Controllable on-time • ƒDIV = Frequency divide equals (1, 2, 4, or 8) Switching Frequency (kHz) 2500 2000 Shift 1500 Skip 1000 500 0 10 20 30 40 Input Voltage (V) 50 60 C027 VO = 3.3 V Figure 40. Maximum Switching Frequency vs Input Voltage 8.3.14 How to Interface to RT/CLK Pin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature, connect a square wave to the RT/CLK pin through the circuit network shown in Figure 41. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on-time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range is 300 to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit should be designed so that the device will have the default frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. TI recommends to use a frequency set resistor connected as shown in Figure 41 through a 50-Ω resistor to ground. The resistor should set the switching frequency close to the external CLK frequency. TI recommends to AC couple the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin and a 4-kΩ series resistor. The series resistor reduces PH jitter in heavy-load applications when synchronizing to an external clock and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK threshold, the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Because there is a PLL on the regulator, the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then increases or decreases the switching frequency until the PLL locks onto the CLK frequency within 100 µs. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 21 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com When the device transitions from the PLL to resistor mode, the switching frequency slows down from the CLK frequency to 150 kHz, then reapplies the 0.5-V voltage, and then the resistor sets the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 V on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Figure 42, Figure 43, and Figure 44 show the device synchronized to an external system clock in CCM, discontinuous conduction mode (DCM), and pulse skip mode (PSM). TPS54060 10 pF 4 kW PLL Rfset EXT Clock Source 50 W RT/CLK Figure 41. Synchronizing to a System Clock PH PH EXT EXT IL IL Figure 42. Plot of Synchronizing in CCM 22 Submit Documentation Feedback Figure 43. Plot of Synchronizing in DCM Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 PH EXT IL Figure 44. Plot of Synchronizing in PSM 8.3.15 Power Good (PWRGD Pin) The PWRGD pin is an open-drain output. When the VSENSE pin is between 94% and 107% of the internal voltage reference, the PWRGD pin is de-asserted and the pin floats. TI recommends to use a pullup resistor between the values of 10 and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state after the VIN input voltage is greater than 1.5 V, but with reduced current sinking capability. The PWRGD achieves full current sinking capability as VIN input voltage approaches 3 V. The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulled low. 8.3.16 Overvoltage Transient Protection (OVTP) The TPS54060 incorporates an OVTP circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low-value output capacitance. For example, when the power supply output is overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the error amplifier output to a high voltage, thus requesting the maximum output current. When the condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some applications, the power supply output voltage can respond faster than the error amplifier output can respond, this actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when using a low-value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the highside MOSFET is disabled, preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle. 8.3.17 Thermal Shutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. After the die temperature decreases below 182°C, the device reinitiates the power-up sequence by discharging the SS/TR pin. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 23 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com 8.3.18 Small Signal Model for Loop Response Figure 45 shows an equivalent model for the TPS54060 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA of 97 μA/V. The error amplifier can be modeled using an ideal voltage-controlled current source. The resistor, Ro, and capacitor, Co, model the open-loop gain and frequency response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting 'c' shows the small signal response of the frequency compensation. Plotting 'a' shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing RL with a current source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is only valid for continuous conduction mode designs. PH VO Power Stage gmps 1.9 A/V a R1 RESR RL COMP c 0.8 V R3 C2 CO RO COUT VSENSE gmea 97 mA/V R2 C1 Figure 45. Small Signal Model for Loop Response Schematic 8.3.19 Simple Small Signal Model for Peak Current Mode Control Figure 46 describes a simple small signal model that can be used to understand how to design the frequency compensation. The TPS54060 power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 14 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 45) is the power stage transconductance. The gmPS for the TPS54060 is 1.9 A/V. The low-frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in Equation 15. As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with the load may seem problematic at first glance, but the dominant pole moves with the load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of Figure 46. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high-ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin increases from the ESR zero at the lower frequencies (see Equation 17). 24 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 VO Adc VC RESR fp RL gmps COUT fz Figure 46. Simple Small Signal Model and Frequency Response for Peak Current Mode Control æ s ö ç1 + ÷ 2 p ´ fZ ø VOUT = Adc ´ è VC æ s ö ç1 + ÷ 2p ´ fP ø è Adc = gmps ´ RL (14) (15) 1 fP = COUT ´ RL ´ 2p (16) 1 fZ = COUT ´ RESR ´ 2p (17) 8.3.20 Small Signal Model for Frequency Compensation The TPS54060 uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits. Figure 47 shows compensation circuits Type 2A, Type 2B, and Type 1. Type 2 circuits most likely implemented in high-bandwidth power-supply designs using low-ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or tantalum capacitors. Equation 18 and Equation 19 show how to relate the frequency response of the amplifier to the small signal model in Figure 47. The open-loop gain and bandwidth are modeled using the RO and CO shown in Figure 47. See the application section for a design example using a Type 2A network with a low-ESR output capacitor. Equation 18 through Equation 27 are provided as a reference for those who prefer to compensate using the preferred methods. Those who prefer to use prescribed method use the method outlined in the application section or use switched information. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 25 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com VO R1 VSENSE gmea Type 2A COMP Type 2B Type 1 Vref R2 RO R3 CO C1 C2 R3 C2 C1 Figure 47. Types of Frequency Compensation Aol A0 P1 Z1 P2 A1 BW Figure 48. Frequency Response of the Type 2A and Type 2B Frequency Compensation 26 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 Aol(V/V) gmea gmea = 2p ´ BW (Hz) Ro = CO (18) (19) æ ö s ç1 + ÷ 2p ´ fZ1 ø è EA = A0 ´ æ ö æ ö s s ç1 + ÷ ´ ç1 + ÷ 2 2 p ´ p ´ f f P1 ø è P2 ø è (20) R2 R1 + R2 R2 ´ Ro| | R3 ´ R1 + R2 A0 = gmea ´ Ro ´ A1 = gmea P1 = Z1 = P2 = (21) (22) 1 2p ´ Ro ´ C1 (23) 1 2p ´ R3 ´ C1 (24) 1 2p ´ R3 | | RO ´ (C2 + CO ) type 2a (25) 1 P2 = type 2b 2p ´ R3 | | RO ´ CO P2 = 2p ´ R O (26) 1 type 1 ´ (C2 + C O ) (27) 8.4 Device Functional Modes 8.4.1 Pulse Skip Eco-Mode The TPS54060 operates in a pulse skip Eco-mode at light load currents to improve efficiency by reducing switching and gate drive losses. The TPS54060 is designed so that if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. This current threshold is the current level corresponding to a nominal COMP voltage or 500 mV. When in Eco-mode, the COMP pin voltage is clamped at 500 mV and the high-side MOSFET is inhibited. Further decreases in load current or in output voltage cannot drive the COMP pin below this clamp voltage level. Because the device is not switching, the output voltage begins to decay. As the voltage control loop compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high-side MOSFET is enabled and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The output voltage recharges the regulated value (see Figure 49), then the peak switch current starts to decrease, and eventually falls below the Eco-mode threshold, at which time the device again enters Eco-mode. For Eco-mode operation, the TPS54060 senses peak current, not average or load current, so the load current where the device enters Eco-mode depends on the output inductor value. For example, the circuit in Figure 50 enters Eco-mode at about 20 mA of output current. When the load current is low and the output voltage is within regulation, the device enters a sleep mode and draws only 116-μA input quiescent current. The internal PLL remains operating when in sleep mode. When operating at light load currents in PSM, switching transitions occur synchronously with the external clock signal. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 27 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com Device Functional Modes (continued) VOUT(ac) IL PH Figure 49. PSM Operation 8.4.2 DCM and Eco-Mode Boundary With an input voltage of 34 V, the power supply enters DCM when the output current is less than 60 mA. The power supply enters Eco-mode when the output current is lower than 38 mA. The input current draw at no load is 228 μA. 28 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 9 Application and Implementation 9.1 Application Information The TPS54060 device is a 60-V, 0.5-A, step-down regulator with an integrated high-side MOSFET. 9.2 Typical Application 9.2.1 Design Requirements This example details the design of a high-frequency switching regulator using ceramic output capacitors. A few parameters must be known to start the design process. These parameters are typically determined at the system level. This example starts with the following known parameters: Table 1. Design Parameters DESIGN PARAMETER Output voltage Transient response 0- to 1.5-A load step Maximum output current Input voltage Output voltage ripple EXAMPLE VALUE 3.3 V ΔVout = 4% 0.5 A 34 V nominal 12 to 48 V 1% of Vout Start input voltage (rising VIN) 8.9 V Stop input voltage (falling VIN) 7.9 V 9.2.2 Detailed Design Procedure 9.2.2.1 Selecting the Switching Frequency The first step is to decide on a switching frequency for the regulator. Typically, the user should choose the highest switching frequency possible because this produces the smallest solution size. The high switching frequency allows for lower-valued inductors and smaller-output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that the user can select is limited by the minimum ontime of the internal power switch, the input voltage, and the output voltage and the frequency shift limitation. Equation 12 and Equation 13 must be used to find the maximum switching frequency for the regulator; choose the lower value of the two equations. Switching frequencies higher than these values result in pulse skipping or the lack of overcurrent protection during a short circuit. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 29 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com The typical minimum on-time, tonmin, is 130 ns for the TPS54060. For this example, the output voltage is 3.3 V and the maximum input voltage is 48 V, which allows for a maximum switch frequency up to 616 kHz when including the inductor resistance, on-resistance, and diode voltage in Equation 12. To ensure overcurrent runaway is not a concern during short circuits in your design, use Equation 13 or the solid curve in Figure 40 to determine the maximum switching frequency. With a maximum input voltage of 48 V, assuming a diode voltage of 0.5 V, inductor resistance of 130 mΩ, switch resistance of 400 mΩ, a current limit value of 0.94 A, and a shortcircuit output voltage of 0.1 V. The maximum switching frequency is approximately 923 kHz. Choosing the lower of the two values and adding some margin, a switching frequency of 500 kHz is used. To determine the timing resistance for a given switching frequency, use Equation 11 or the curve in Figure 38. The switching frequency is set by resistor R3 shown in Figure 50. Figure 50. High-Frequency, 3.3-V Output Power Supply Design With Adjusted UVLO 9.2.2.2 Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, the following guidelines may be used. For designs using low-ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used. When using higher-ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is part of the PWM control system, the inductor ripple current should always be greater than 30 mA for dependable operation. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this design example, use KIND = 0.3, and the minimum inductor value is calculated to be 39.7 μH. For this design, a nearest standard value was chosen: 47 μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 30 and Equation 31. For this design, the RMS inductor current is 0.501 A and the peak inductor current is 0.563 A. The chosen inductor is a MSS1048-473ML. It has a saturation current rating of 1.44 A and an RMS current rating of 1.83 A. As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator, but require a larger value of inductance. Selecting higher ripple currents increases the output voltage ripple of the regulator, but allows for a lower inductance value. 30 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. Vinmax - Vout Vout Lo min = ´ Io ´ KIND Vinmax ´ ƒsw (28) IRIPPLE = IL(rms) = VOUT ´ (Vin max - VOUT ) Vin max ´ L O ´ fSW (IO ) + 2 1 æ VOUT ´ (Vinmax - VOUT ) ö ´ç ÷ ÷ 12 çè Vinmax ´ LO ´ fSW ø ILpeak = Iout + (29) 2 (30) Iripple 2 (31) 9.2.2.3 Output Capacitor To select the value of the output capacitor, account for three primary considerations. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulators respond to a large change in load current. The output capacitance must be selected based on the most stringent of these three criteria. The first criterion is the desired response to a large change in the load current. The output capacitor needs to supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. Also, the regulator will temporarily not be able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 32 shows the minimum output capacitance necessary to accomplish this. Where ΔIout is the change in output current, ƒsw is the regulators switching frequency and ΔVout is the allowable change in the output voltage. For this example, the transient load response is specified as a 4% change in Vout for a load step from 0 A (no load) to 0.5 A (full load). For this example, ΔIout = 0.5 – 0 = 0.5 A and ΔVout = 0.04 × 3.3 = 0.132 V. Using these numbers gives a minimum capacitance of 15.2 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into account. The catch diode of the regulator cannot sink current, so any stored energy in the inductor will produce an output voltage overshoot when the load current rapidly decreases (see Figure 51). The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor increases the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 33 is used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L is the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, VF is the final peak output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step is from 0.5 A to 0 A. The output voltage increases during this load transition and the stated maximum in our specification is 4% of the output voltage. This makes Vf = 1.04 × 3.3 = 3.432. Vi is the initial capacitor voltage, which is the nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a minimum capacitance of 13.2 μF. Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where ƒsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. Equation 34 yields 1 μF. Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 35 indicates the ESR should be less than 248 mΩ. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 31 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com The most stringent criterion for the output capacitor is 15.2 μF of capacitance to keep the output voltage in regulation during a load transient. Additional capacitance deratings for aging, temperature, and DC bias should be factored in which will increase this minimum value. For this example, a 47-μF 10-V X5R ceramic capacitor with 5 mΩ of ESR is used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 36 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 36 yields 37.7 mA. 2 ´ DIout Cout > ¦ sw ´ DVout (32) (Ioh (V ¦ 2 Cout > Lo ´ 1 Cout > 8 ´ ¦ sw ´ ) - Vi ) - Iol2 2 2 (33) 1 VORIPPLE IRIPPLE (34) V RESR < ORIPPLE IRIPPLE Icorms = (35) Vout ´ (Vin max - Vout) 12 ´ Vin max ´ Lo ´ ¦ sw (36) 9.2.2.4 Catch Diode The TPS54060 requires an external catch diode between the PH pin and GND. The selected diode must have a reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator. Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage is. Because the design example has an input voltage up to 48 V, a diode with a minimum of 60-V reverse voltage is selected. For the example design, the B160A Schottky diode is selected for its lower forward voltage and it comes in a larger package size which has good thermal characteristics over small devices. The typical forward voltage of the B160A is 0.5 V. The diode must be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, output voltage, and switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies, the AC losses of the diode need to be taken into account. The AC losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery. Equation 37 is used to calculate the total power dissipation, conduction losses plus AC losses, of the diode. The B160A has a junction capacitance of 110 pF. Using Equation 37, the selected diode will dissipate 0.297 W. This power dissipation, depending on mounting techniques, should produce a 5.9°C temperature rise in the diode when the input voltage is 48 V and the load current is 0.5 A. If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode which has a low leakage current and slightly higher forward voltage drop. 2 Pd = 32 (Vin max - Vout) ´ Iout ´ Vƒd Cj ´ ƒsw ´ (Vin + Vƒd) + 2 Vin max Submit Documentation Feedback (37) Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 9.2.2.5 Input Capacitor The TPS54060 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF of effective capacitance, and in some applications, a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54060. The input ripple current can be calculated using Equation 38. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 60-V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V, or 100 V, so a 100-V capacitor should be selected. For this example, two 2.2-μF, 100-V capacitors in parallel are selected. Table 2 shows a selection of high-voltage capacitors. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 39. Using the design example values, Ioutmax = 0.5 A, Cin = 4.4 μF, ƒsw = 500 kHz, yields an input voltage ripple of 57 mV and a rms input ripple current of 0.223 A. Icirms = Iout ´ Vout ´ Vin min (Vin min - Vout ) Vin min (38) Iout max ´ 0.25 ΔVin = Cin ´ ¦ sw (39) Table 2. Capacitor Types VENDOR VALUE (μF) 1.0 to 2.2 Murata 1.0 to 4.7 1.0 1.0 to 2.2 1.0 10 1.8 Vishay 1.0 to 1.2 1.0 to 3.9 1.0 to 1.8 1.0 to 2.2 TDK 1.5 to 6.8 1.0. to 2.2 1.0 to 3.3 1.0 to 4.7 AVX 1.0 1.0 to 4.7 1.0 to 2.2 EIA SIZE 1210 1206 2220 2225 1812 1210 1210 1812 VOLTAGE DIELECTRIC 100 V COMMENTS GRM32 series 50 V 100 V GRM31 series 50 V 50 V 100 V VJ X7R series 50 V 100 V 100 V 50 V 100 V 50 V X7R C series C4532 C series C3225 50 V 100 V 50 V X7R dielectric series 100 V 9.2.2.6 Slow Start Capacitor The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54060 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 33 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss, necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow start current of Issavg. In the example, to charge the 47-μF output capacitor up to 3.3 V while only allowing the average input current to be 0.125 A would require a 1-ms slow start time. After the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the example circuit, the slow start time is not too critical because the output capacitor value is 47 μF which does not require much current to charge to 3.3 V. The example circuit has the slow start time set to an arbitrary value of 3.2 ms, which requires a 0.01-μF capacitor. Cout ´ Vout ´ 0.8 tss > Issavg (40) 9.2.2.7 Bootstrap Capacitor Selection A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. TI recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10 V or higher voltage rating. 9.2.2.8 UVLO Set Point The UVLO can be adjusted using an external voltage divider on the EN pin of the TPS54060. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching after the input voltage increases above 8.9 V (enabled). After the regulator starts switching, it should continue to do so until the input voltage falls below 7.9 V (UVLO stop). The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example application, a 332-kΩ resistor between Vin and EN and a 56.2-kΩ resistor between EN and ground are required to produce the 8.9- and 7.9-V start and stop voltages. 9.2.2.9 Output Voltage and Feedback Resistors Selection For the example design, 10 kΩ was selected for R2. Using Equation 1, R1 is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to current leakage of the VSENSE pin, the current flowing through the feedback network should be greater than 1 μA to maintain the output voltage accuracy. This requirement makes the maximum value of R2 equal to 800 kΩ. Using higher resistor values decreases quiescent current and improves efficiency at low output currents, but may introduce noise immunity problems. 9.2.2.10 Compensation There are several methods used to compensate DC/DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual crossover frequency is usually lower than the crossover frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more accurate design. To get started, the modulator pole, ƒpmod, and the ESR zero, ƒz1 must be calculated using Equation 41 and Equation 42. For Cout, use a derated value of 40 μf. Use equations Equation 43 and Equation 44, to estimate a starting point for the crossover frequency, ƒco, to design the compensation. For the example design, ƒpmod is 603 Hz and ƒzmod is 796 kHz. Equation 43 is the geometric mean of the modulator pole and the ESR zero, and Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 21.9 kHz and Equation 44 gives 12.3 kHz. Use the lower value of Equation 43 or Equation 44 for an initial crossover frequency. For this example, ƒco is 12.3 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole. Ioutmax ¦p mod = 2 × p × Vout × Cout (41) 34 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 ¦ z mod = 1 2 ´ p ´ Resr × Cout (42) fco = f p mod ´ f z mod (43) fco = f f p mod ´ sw 2 (44) To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance, gmps, is 1.9 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V, 0.8 V, and 92 μA/V, respectively. R4 is calculated to be 72.6 kΩ, use the nearest standard value of 73.2 kΩ. Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 3600 pF for compensating capacitor C7, a 3300 pF is used on the board. ö æ 2 ´ p ´ fco ´ Cout ö æ Vout R4 = ç ÷ ÷´ç gmps è ø è Vref ´ gmea ø (45) 1 C7 = 2 ´ p ´ R4 ´ f p m od (46) Use the larger value of Equation 47 and Equation 48 to calculate the C8, to set the compensation pole. Equation 48 yields 8.7 pF so the nearest standard of 10 pF is used. C ´ Re sr C8 = o R4 (47) C8 = 1 R4 ´ f sw ´ p Copyright © 2014, Texas Instruments Incorporated (48) Submit Documentation Feedback 35 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com 9.2.3 Application Curves VIN = 20 V/div (AC Coupled) VOUT = 1 V/div IOUT = 200 mA/div (0.125 to 0.375 A Step) VIN = 20 V/div Time = 5 ms/div Time = 5 ms/div Time = 2 ms/div Time = 2 ms/div Figure 51. Load Transient Figure 52. Startup With VIN VOUT = 10 mV/div (AC Coupled) VOUT = 10 mV/div (AC Coupled) PH = 20 V/div PH = 20 V/div Inductor Current = 100 mA/div Time = 1 μs/div Time = 1 µs/div Time = 5 μs/div Time = 5 µs/div Figure 53. Output Ripple CCM VOUT = 10 mV/div (AC Coupled) Figure 54. Output Ripple, DCM VIN = 20 mV/div (AC Coupled) PH = 20 V/div PH = 20 V/div Time = 50 μs/div Time = 50 µs/div Figure 55. Output Ripple, PSM 36 Submit Documentation Feedback Time = 1 μs/div Time = 1 µs/div Figure 56. Input Ripple CCM Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 100 VIN = 20 V/div (AC Coupled) 90 80 Efficiency (%) 70 PH = 20 V/div VIN = 12 V 60 VIN = 24 V VIN = 18 V VIN = 34 V VIN = 42 V 50 40 30 Inductor Current = 100 mA/div 20 10 0 0 Time = 5 μs/div Time = 5 µs/div 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Output Current (A) C028 VOUT = 3.3 V Figure 58. Efficiency vs Load Current Figure 57. Input Ripple DCM 100 60 90 100 Phase 20 Gain (dB) 60 VIN = 12 V 50 VIN = 24 V VIN = 18 V VIN = 34 V 40 0 0 Gain –50 –20 VIN = 42 V 30 50 Phase (o) 70 Efficiency (%) 150 40 80 –100 20 –40 –150 10 0 0 0.02 0.04 0.06 Output Current (A) –60 100 0.10 0.08 1k C029 10k Frequency (Hz) 100k 1M C030 VOUT = 3.3 V Figure 60. Overall Loop Frequency Response 0.1 0.1 0.08 0.08 0.06 0.06 0.04 0.04 Regulation (%) Regulation (%) Figure 59. Light Load Efficiency 0.02 0 –0.02 0.02 0 –0.02 –0.04 –0.04 –0.06 –0.06 –0.08 –0.08 –0.1 0.00 0.25 0.1 0.15 0.2 0.25 0.3 Load Current (A) 0.35 0.4 0.45 0.5 VI = 34 V Figure 61. Regulation vs Load Current Copyright © 2014, Texas Instruments Incorporated –0.1 10 15 20 C031 25 30 35 40 Input Voltage (V) 45 50 55 60 C032 IO = 0.25 A Figure 62. Regulation vs Input Voltage Submit Documentation Feedback 37 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com 10 Power Supply Recommendations 10.1 Power Dissipation Estimate The following formulas show how to estimate the IC power dissipation under CCM operation. Do not use these equations if the device is working in DCM. The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd), and supply current (Pq). Vout Pcon = Io2 ´ RDS(on) ´ Vin (49) Psw = Vin 2 ´ ¦ sw ´ lo ´ 0.25 ´ 10-9 Pgd = Vin ´ 3 ´ 10 Pq = 116 ´ 10 -6 -9 ´ ¦ sw ´ Vin (50) (51) (52) where: • IOUT is the output current (A). • RDS(on) is the on-resistance of the high-side MOSFET (Ω). • VOUT is the output voltage (V). • VIN is the input voltage (V). • ƒsw is the switching frequency (Hz). So Ptot = Pcon + Psw + Pgd + Pq (53) For given TA, TJ = TA + Rth ´ Ptot (54) For given TJMAX = 150°C TAmax = TJmax - Rth ´ Ptot (55) where • Ptot is the total device power dissipation (W). • TA is the ambient temperature (°C). • TJ is the junction temperature (°C). • Rth is the thermal resistance of the package (°C/W). • TJMAX is maximum junction temperature (°C). • TAMAX is maximum ambient temperature (°C). There will be additional power losses in the regulator circuit due to the inductor AC and DC losses, catch diode, and trace resistance that will impact the overall efficiency of the regulator. 10.2 Power Supply Considerations TPS2105-EP requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. Ceramic capacitors lose capacitance when a DC bias is applied across the capacitor. This capacitance loss is due to the polarization of the ceramic material. The capacitance loss is not permanent; after a large DC bias is applied, reducing the DC bias reduces the degree of polarization and capacitance increases. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. 38 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 Power Supply Considerations (continued) All tantalum capacitors have Tantalum (Ta) particles sintered together to form an anode. The cathode material can either be the traditional MnO2 or a conductive polymer. Because MnO2 is actually a semiconductor, it has a very-high amount of resistance associated with it. A characteristic of this material is that as temperature changes so does its conductivity. So MnO2-based Tantalum capacitors have relatively high ESR and that ESR shifts significantly across the operational temperature range. However, polymer-based cathodes use a highly-conductive polymer material. Because the material is inherently conductive, Tantalum-polymers have a relatively low ESR compared to their MnO2 counterparts in the same voltage and capacitance ranges. All Tantalum capacitors have a voltage derating factor associated with them. Because the Polymer material puts less stress on the Tantalum-Pentoxide dielectric during reflow soldering, more voltage can be applied compared to a MnO2-based Tantalum. For polymer-based capacitors, TI recommends 20% derating whereas the MnO2based tantalum capacitors require 50% or higher derating. Refer to the capacitor vendor data sheet for more details regarding the derating guidelines. Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 39 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com 11 Layout 11.1 Layout Guidelines Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Layout Example for a PCB layout example. The GND pin should be tied directly to the power pad under the IC and the power pad. The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Because the PH connection is the switching node, the catch diode and output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts; however, this layout has been shown to produce good results and is meant as a guideline. 11.1.1 Estimated Circuit Area The estimated printed circuit board area for the components used in the design of Figure 50 is 0.55 inch2. This area does not include test points or connectors. VIN + Cin Cboot Lo BOOT VIN Cd PH GND R1 + GND R2 TPS54060 Co VOUT VSENSE EN COMP SS/TR Rcomp RT/CLK Css RT Czero Cpole Figure 63. Inverting Power Supply from the SLVA317 Application Note 40 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated TPS54060-EP www.ti.com SLVSCF8 – JULY 2014 Layout Guidelines (continued) VOPOS + VIN Copos + Cin Cboot GND PH BOOT VIN Lo Cd R1 GND + Coneg R2 TPS54060 VONEG VSENSE EN COMP SS/TR Rcomp RT/CLK Css Czero RT Cpole Figure 64. Split Rail Power Supply Based on the SLVA369 Application Note 11.2 Layout Example Vout Output Capacitor Topside Ground Area Output Inductor Route Boot Capacitor Trace on another layer to provide wide path for topside ground Input Bypass Capacitor Vin UVLO Adjust Resistors Slow Start Capacitor BOOT Catch Diode PH VIN GND EN COMP SS/TR VSENSE RT/CLK PWRGD Frequency Set Resistor Compensation Network Resistor Divider Thermal VIA Signal VIA Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 41 TPS54060-EP SLVSCF8 – JULY 2014 www.ti.com 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Trademarks Eco-Mode, PowerPAD, SwitcherPro are trademarks of Texas Instruments. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 42 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS54060MDGQTEP ACTIVE HVSSOP DGQ 10 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -55 to 125 546M V62/14617-01XE ACTIVE HVSSOP DGQ 10 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -55 to 125 546M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of