TPS54218RTER

Product Folder Order Now Support & Community Tools & Software Technical Documents Reference Design TPS54218 SLVS974F – SEPTEMBER 2009 – REVISED MAY 2020 TPS54218 2.95-V to 6-V Input, 2-A Output, 2-MHz, Synchronous Step-Down SWIFT™ Converter 1 Features 3 Description • TheTPS54218 device is a full-featured, 6-V, 2-A, synchronous, step-down current-mode converter with two integrated MOSFETs. 1 • • • • • • • • • • • Two, 30-mΩ (typical) MOSFETs for high-efficiency at 2-A loads Switching frequency: 200 kHz to 2 MHz Voltage reference over temperature: 0.8 V ±1% Synchronizes to external clock Adjustable soft start/sequencing UV and OV power-good output Low operating and shutdown quiescent current Safe start-up into prebiased output Cycle-by-cycle current limit, thermal and frequency foldback protection Operating junction temperature range: –40°C to 150°C Thermally-enhanced 3-mm × 3-mm 16-pin WQFN package Create a custom design using the TPS54218 with the WEBENCH® Power Designer 2 Applications • • • Factory automation Broadband fixed line access Wireless infrastructure The TPS54218 device enables small designs by integrating the MOSFETs, implementing current mode control to reduce external component count, reducing inductor size by enabling up to 2-MHz switching frequency, and minimizing the device footprint with a small, 3-mm × 3-mm, thermallyenhanced QFN package. The TPS54218 device provides accurate regulation for a variety of loads with an accurate ±1% voltage reference (VREF) over temperature. Efficiency is maximized through the integrated 30-mΩ MOSFETs and a 350-μA typical supply current. Using the EN pin, shutdown supply current is reduced to 2 μA by entering a shutdown mode. Undervoltage lockout is internally set at 2.6 V, but can be increased by programming the threshold with a resistor network on the enable pin. The output voltage startup ramp is controlled by the soft-start pin. An open-drain power-good signal indicates the output is within 93% to 107% of its nominal voltage. Frequency foldback and thermal shutdown protects the device during an overcurrent condition. For more SWIFT™ documentation, see the TI website at www.ti.com/swift. Device Information(1) PART NUMBER TPS54218 PACKAGE WQFN (16) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VIN Efficiency versus Output Current TPS54218 100 BOOT EN PH PWRGD VSENSE SS RT/CLK COMP 90 VOUT 85 80 75 70 65 GND AGND PowerPad 95 Efficiency (%) VIN 60 VIN = 5 V 55 VOUT = 1.8 V fSW = 1 MHz 50 0 0.25 0.5 0.75 1 1.25 Output Current (A) 1.5 1.75 2 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS54218 SLVS974F – SEPTEMBER 2009 – REVISED MAY 2020 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 6 7 9 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 13 7.1 Overview ................................................................. 13 7.2 Functional Block Diagram ....................................... 14 7.3 Feature Description................................................. 14 7.4 Device Functional Modes........................................ 19 8 Application and Implementation ........................ 23 8.1 Application Information............................................ 23 8.2 Typical Application .................................................. 23 9 Power Supply Recommendations...................... 34 10 Layout................................................................... 34 10.1 Layout Guidelines ................................................. 34 10.2 Layout Example .................................................... 35 11 Device and Documentation Support ................. 36 11.1 11.2 11.3 11.4 11.5 11.6 Device Support .................................................... Receiving Notification of Documentation Updates Support Resources ............................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 36 36 36 36 36 36 12 Mechanical, Packaging, and Orderable Information ........................................................... 36 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (September 2018) to Revision F • Page Changed axis names of Figure 13 ...................................................................................................................................... 10 Changes from Revision D (April 2018) to Revision E Page • Changed charge current from 1.8 μA to 2.07 μA.................................................................................................................... 8 • Changed SS discharge voltage (overload) units from μA to mV............................................................................................ 8 • Changed SS charge current graph....................................................................................................................................... 11 • Updated content of Soft-Start Pin, including Equation 4 ...................................................................................................... 16 • Changed "ISS is 2 μA..." to "ISS is 2.07 μA." ......................................................................................................................... 26 • Deleted "VREF is 0.8 V" ......................................................................................................................................................... 26 • Changed "...which requires a 10 µF capacitor' to "...which requires a 9.2-nF capacitor. The nearest standard value of 10 nF is used resulting in a calculated soft-start time of 4.3 msec. " ............................................................................... 26 • Deleted reference to obsolete SwitcherPro software .......................................................................................................... 28 • Changed Figure 45 .............................................................................................................................................................. 31 • Added Figure 46 ................................................................................................................................................................... 31 Changes from Revision C (December 2014) to Revision D • update title; add top navigator icon for TI reference design ................................................................................................... 1 Changes from Revision B (June 2013) to Revision C • 2 Page Page Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1 Submit Documentation Feedback Copyright © 2009–2020, Texas Instruments Incorporated Product Folder Links: TPS54218 TPS54218 www.ti.com SLVS974F – SEPTEMBER 2009 – REVISED MAY 2020 Changes from Revision A (August 2012) to Revision B Page • Added Figure 22 to Typical Characteristics section ............................................................................................................. 11 • Added clarity to Fixed Frequency PWM Control section ...................................................................................................... 14 • Added clarity to Soft-Start Pin section.................................................................................................................................. 16 • Added Soft-Start Pin section ................................................................................................................................................ 16 • Added clarity to Synchronize Using the RT/CLK Pin section ............................................................................................... 18 • Added Step Five: Minimum Load DC COMP Voltage section ............................................................................................. 26 • Added clarity to the Step Six: Choose the Soft-Start Capacitor section .............................................................................. 26 Changes from Original (September 2009) to Revision A • Page Added "Instantaneous peak current" specification to the Current Limit section in the Electrical Characteristics table ......... 7 Submit Documentation Feedback Copyright © 2009–2020, Texas Instruments Incorporated Product Folder Links: TPS54218 3 TPS54218 SLVS974F – SEPTEMBER 2009 – REVISED MAY 2020 www.ti.com 5 Pin Configuration and Functions VIN EN PWRGD BOOT RTE Package 16 Pin WQFN (TOP VIEW) 16 15 14 13 VIN 1 12 PH VIN 2 11 PH Thermal Pad GND 3 10 PH GND 4 5 6 7 8 AGND VSENSE COMP RT/CLK 9 SS Pin Functions PIN I/O (1) DESCRIPTION NAME NO. AGND 5 G Analog ground must be electrically connected to GND close to the device. BOOT 13 I A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed. COMP 7 O Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. EN 15 I Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. Can be used to set the on/off threshold (adjust UVLO) with two additional resistors. G Power ground. This pin must be electrically connected directly to the power pad under the device. O The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous) rectifier MOSFET 3 GND 4 10 PH 11 12 PWRGD 14 O An open-drain output asserts low if output voltage is low due to thermal shutdown, overcurrent, overvoltage or undervoltage, or EN shut down. RT/CLK 8 I/O Resistor Timing or External Clock input pin SS 9 I/O Slow start. An external capacitor connected to this pin sets the output voltage rise time. 1 VIN 2 I Input supply voltage, 2.95 V to 6 V I Inverting node of the transconductance (gm) error amplifier G GND pin must be connected to the exposed power pad for proper operation. This power pad must be connected to any internal PCB ground plane using multiple vias for good thermal performance. 16 VSENSE Thermal Pad (1) 4 6 I = Input, O = Output, G = Ground Submit Documentation Feedback Copyright © 2009–2020, Texas Instruments Incorporated Product Folder Links: TPS54218 TPS54218 www.ti.com SLVS974F – SEPTEMBER 2009 – REVISED MAY 2020 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Input voltage MIN MAX EN, PWRGD, VIN –0.3 7 RT/CLK –0.3 6 COMP, SS, VSENSE –0.3 3 BOOT 8 PH PH (10 ns transient) Source current Sink current V VPH+ 8 V BOOT-PH Output voltage UNIT –0.6 7 –2 7 V EN, RT/CLK 100 COMP, SS 100 µA µA PWRGD 10 mA Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins V(ESD) (1) (2) Electrostatic discharge (1) VALUE UNIT ±2000 V ±500 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VVIN Input voltage TJ Operating junction temperature MAX UNIT 3 6 V –40 150 °C Submit Documentation Feedback Copyright © 2009–2020, Texas Instruments Incorporated Product Folder Links: TPS54218 5 TPS54218 SLVS974F – SEPTEMBER 2009 – REVISED MAY 2020 www.ti.com 6.4 Thermal Information (1) TPS54218 THERMAL METRIC (2) RTE (WQFN) UNIT 16 PINS RθJA Junction-to-ambient thermal resistance (3) 50 °C/W RθJA Junction-to-ambient thermal resistance 37 °C/W RθJC(top) Junction-to-case (top) thermal resistance 59.1 °C/W RθJB Junction-to-board thermal resistance 23.1 °C/W ψJT Junction-to-top characterization parameter 1.4 °C/W ψJB Junction-to-board characterization parameter 23.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.9 °C/W (1) (2) (3) 6 Unless otherwise specified, metrics listed in this table refer to JEDEC high-K board measurements For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Test Board Conditions: (a) 2 inches × 2 inches, 4 layers, thickness: 0.062 inch (b) 2 oz. copper traces located on the top of the PCB (c) 2 oz. copper ground planes located on the two internal layers and bottom layer (d) 4 thermal vias (10 mil) located under the device package Submit Documentation Feedback Copyright © 2009–2020, Texas Instruments Incorporated Product Folder Links: TPS54218 TPS54218 www.ti.com SLVS974F – SEPTEMBER 2009 – REVISED MAY 2020 6.5 Electrical Characteristics –40°C ≤ TJ ≤ 150°C, 2.95 V ≤ VVIN ≤ 6 V (unless otherwise noted) over operating free-air temperature range PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN) VVIN Operating input voltage VUVLO Internal under voltage lockout threshold No voltage hysteresis, rising and falling IQ(vin) Shutdown supply current VEN = 0 V, TA = 25°C, 2.95 V ≤ VVIN ≤ 6 V Quiescent current VVSENSE = 0.9 V, VVIN = 5 V, 25°C, RT = 400 kΩ Iq 2.95 6 V 2.6 2.8 V 2 5 μA 350 500 μA 1.25 1.37 ENABLE AND UVLO (EN) VTH(en) Enable threshold IEN Input current Rising 1.16 Falling 1.18 Enable rising threshold + 50 mV –3.2 Enable falling threshold – 50 mV –0.65 V μA VOLTAGE REFERENCE (VSENSE) VREF Voltage reference 2.95 V ≤ VVIN ≤ 6 V, –40°C