TPS54229E
SLVSAZ7A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
4.5V to 18V Input, 2-A Synchronous Step-Down Converter with Eco-Mode™
Check for Samples: TPS54229E
FEATURES
DESCRIPTION
1
•
23
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Mode Enables Fast Transient
Response
Low Output Ripple and Allows Ceramic Output
Capacitor
Wide VIN Input Voltage Range: 4.5 V to 18 V
Output Voltage Range: 0.76 V to 7.0 V
Highly Efficient Integrated FETs Optimized
for Lower Duty Cycle Applications
– 160 mΩ (High Side) and 110 mΩ (Low Side)
High Efficiency, less than 10 μA at shutdown
High Initial Bandgap Reference Accuracy
Adjustable Soft Start
Pre-Biased Soft Start
650-kHz Switching Frequency (fSW)
Cycle By Cycle Over Current Limit
Auto-Skip Eco-mode™ for High Efficiency at
Light Load
APPLICATIONS
•
The TPS54229E is an adaptive on-time D-CAP2™
mode synchronous buck converter. The TPS54229E
enables system designers to complete the suite of
various end-equipment power bus regulators with a
cost effective, low component count, low standby
current solution. The main control loop for the
TPS54229E uses the D-CAP2™ mode control that
provides a fast transient response with no external
compensation components. The adaptive on-time
control supports seamless transition between PWM
mode at higher load conditions and Eco-mode™
operation at light loads. Eco-mode™ allows the
TPS54229E to maintain high efficiency during lighter
load conditions. The TPS54229E also has a
proprietary circuit that enables the device to adopt to
both low equivalent series resistance (ESR) output
capacitors, such as POSCAP or SP-CAP, and ultralow ESR ceramic capacitors. The device operates
from 4.5-V to 18-V VIN input. The output voltage can
be programmed between 0.76 V and 7 V. The device
also features an adjustable soft start time. The
TPS54229E is available in the 8-pin DDA package,
and designed to operate from –40°C to 85°C.
Wide Range of Applications for Low Voltage
System
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminal
– Digital Set Top Box (STB)
Vout = 50 mV/div
TPS54229EDDA
Iout = 1 A/div
t - Time - 10 ms
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP2, Eco-mode are trademarks of Texas Instruments.
Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS54229E
SLVSAZ7A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 85°C
(1)
(2)
(3)
(3)
ORDERABLE PART NUMBER
TPS54229EDDA
DDA
TRANSPORT
MEDIA
PIN
Tube
8
TPS54229EDDAR
Tape and Reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
All package options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
Input voltage range
Output voltage range
MAX
VIN, EN
–0.3
20
VBST
–0.3
26
VBST (10 ns transient)
–0.3
28
VBST (vs SW)
–0.3
6.5
VFB, SS
–0.3
6.5
SW
–2
20
SW (10 ns transient)
–3
22
VREG5
–0.3
6.5
GND
–0.3
0.3
–0.2
0.2
V
2
kV
500
V
Voltage from GND to thermal pad, Vdiff
Electrostatic discharge
Human Body Model (HBM)
Charged Device Model (CDM)
Operating junction temperature, TJ
–40
150
Storage temperature, Tstg
–55
150
(1)
UNIT
MIN
V
V
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC (1)
TPS54229E
DDA (8 PINS)
θJA
Junction-to-ambient thermal resistance
45.3
θJCtop
Junction-to-case (top) thermal resistance
54.8
θJB
Junction-to-board thermal resistance
16.2
ψJT
Junction-to-top characterization parameter
6.6
ψJB
Junction-to-board characterization parameter
16.0
θJCbot
Junction-to-case (bottom) thermal resistance
8.5
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range, (unless otherwise noted)
VIN
Supply input voltage range
VI
Input voltage range
MIN
MAX
4.5
18
VBST
–0.1
24
VBST (10 ns transient)
–0.1
27
VBST(vs SW)
–0.1
5.7
5.7
SS
–0.1
EN
–0.1
18
VFB
–0.1
5.5
SW
–1.8
18
SW (10 ns transient)
UNIT
V
V
–3
21
GND
–0.1
0.1
–0.1
5.7
V
0
10
mA
VO
Output voltage range
VREG5
IO
Output Current range
IVREG5
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVIN
Operating - non-switching supply current
VIN current, TA = 25°C, EN = 5 V,
VFB = 0.8 V
800
1200
μA
IVINSDN
Shutdown supply current
VIN current, TA = 25°C, EN = 0 V
5.8
10
μA
0.6
V
LOGIC THRESHOLD
VEN
EN high-level input voltage
EN
EN low-level input voltage
EN
1.6
V
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH
VFB threshold voltage
IVFB
VFB input current
TA = 25°C, VO = 1.05 V, IO = 10 mA, Ecomode™ operation
TA = 25°C, VO = 1.05 V, continuous mode
operation
770
749
VFB = 0.8 V, TA = 25°C
mV
765
781
mV
0
±0.1
μA
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 6.0 V < VIN < 18 V,
0 < IVREG5 < 5 mA
5.5
V
IVREG5
Output current
VIN = 6 V, VREG5 = 4.0 V, TA = 25°C (1)
60
mA
High side switch resistance
25°C, VBST - SW = 5.5 V (1)
160
mΩ
Low side switch resistance
25°C (1)
110
mΩ
MOSFET
RDS(on)
CURRENT LIMIT
Iocl
(1)
Current limit
L out = 2.2 μH (1)
2.5
3.3
4.7
A
Not production tested.
3
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL SHUTDOWN
TSDN
Thermal shutdown threshold
Shutdown temperature
Hysteresis
(2)
165
(2)
°C
35
ON-TIME TIMER CONTROL
tON
On time
VIN = 12 V, VO = 1.05 V
155
ns
tOFF(MIN)
Minimum off time
TA = 25°C, VFB = 0.7 V (2)
260
ns
SOFT START
ISS
SS charge current
VSS = 1.0 V
4.2
6
SS discharge current
VSS = 0.5 V
0.1
0.2
7.8
μA
mA
UVLO
UVLO
(2)
UVLO threshold
Wake up VREG5 voltage
3.75
Hysteresis VREG5 voltage
0.32
V
Not production tested.
4
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DEVICE INFORMATION
DDA PACKAGE
(TOP VIEW)
1
VBST
2
VIN
SS
8
EN
7
VREG5
6
VFB
5
TPS54229E
DDA
(HSOP8)
3
SW
4
GND
Power PAD
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NO.
VBST
1
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW
pins. An internal diode is connected between VREG5 and VBST.
VIN
2
Input voltage supply pin.
SW
3
Switch node connection between high-side NFET and low-side NFET.
GND
4
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at
a single point.
VFB
5
Converter feedback input. Connect to output voltage with feedback resistor divider.
VREG5
6
5.5 V power supply output. A capacitor (typical 0.47 µF) should be connected to GND. VREG5 is not
active when EN is low.
EN
7
Enable input control. EN is active high and must be pulled up to enable the device.
SS
8
Soft-start control. An external capacitor should be connected to GND.
Exposed Thermal
Pad
Back side
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to
GND.
5
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FUNCTIONAL BLOCK DIAGRAM
EN
7
EN
VIN
Logic
VIN
2
VREG5
Control Logic
Ref
+
SS
+ PWM
1
1 shot
VFB
SW
VO
3
-
5
VBST
XCON
ON
VREG5
VREG5
Ceramic
Capacitor
6
SGND
SS
SS
8
4
Softstart
PGND
SGND
+
ZC
-
PGND
+
OCP
-
PGND
GND
SW
SW
VIN
UVLO
VREG5
UVLO
REF
TSD
Protection
Logic
Ref
6
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TPS54229E
SLVSAZ7A – SEPTEMBER 2011 – REVISED MARCH 2012
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OVERVIEW
The TPS54229E is a 2-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS54229E is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.
PWM Frequency and Adaptive On-Time Control
TPS54229E uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54229E runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
Auto-Skip Eco-Mode™ Control
The TPS54229E is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1
(VIN - VOUT )×VOUT
1
I OUT ( LL ) =
×
2 × L × fsw
VIN
(1)
Soft Start and Pre-Biased Soft Start
The soft start function is adjustable. When the EN pin becomes high, 6 μA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
6 μA.
t
SS
(ms) =
CSS (nF) x VREF ´1.1
I (mA)
SS
=
CSS (nF) x 0.765 ´1.1
6
(2)
The TPS54229E contains a unique circuit to prevent current from being pulled from the output during startup if
the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft
start becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by
starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and
ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to
normal mode operation.
7
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Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. The TPS54229E constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of over-current protection. The load current one half of the
peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the
output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output voltage to fall. When the over current condition is removed, the output
voltage returns to the regulated value. This protection is non-latching.
UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54229E is shut off. This protection is non-latching.
Thermal Shutdown
TPS54229E monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.
8
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TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25°C (unless otherwise noted).
12
1200
VI = 12 V
10
Ivccsdn - Shutdown Current - mA
ICC - Supply Current - mA
1000
800
600
400
200
0
-50
0
50
100
VI = 12 V
8
6
4
2
0
-50
150
0
50
TJ - Junction Temperature - °C
100
150
TJ - Junction Temperature - °C
Figure 1. VIN CURRENT vs JUNCTION TEMPERATURE
Figure 2. VIN SHUTDOWN CURRENT vs
JUNCTION TEMPERATURE
1.1
50
45
40
VO - Output Voltage - V
EN Input Current - mA
1.075
VI = 18 V
35
30
25
20
15
VI = 18 V
VI = 12 V
1.05
VI = 5 V
1.025
10
5
1
0
0
5
10
EN Input Voltage - V
15
20
Figure 3. EN CURRENT vs EN VOLTAGE
0
0.5
1
IO - Output Current - A
1.5
2
Figure 4. 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT
1.07
IO = 10 mA
Vout = 50 mV/div
VO - Output Voltage - V
1.06
IO = 1 A
1.05
Iout = 1 A/div
1.04
1.03
0
5
10
VI - Input Voltage - V
15
20
Figure 5. 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE
t - Time - 10 ms
Figure 6. 1.05-V, LOAD TRANSIENT RESPONSE
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TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25°C (unless otherwise noted).
100
VO = 3.3 V
EN = 10 V/div
90
Efficiency - %
80
VREG5 = 5 V/div
VO = 0.5 V/div
VO = 2.5 V
VO = 1.8 V
70
60
50
40
t - Time - 1 ms
0
0.5
Figure 7. START-UP WAVE FORM
1
IO - Output Current - A
1.5
2
Figure 8. EFFICIENCY vs OUTPUT CURRENT
900
100
VO = 3.3 V
90
850
VO = 2.5 V
fsw - Switching Frequency - kHz
80
Efficiency - %
70
60
VO = 1.8 V
50
40
30
20
10
800
VO = 5 V
750
VO = 3.3 V
700
650
VO = 2.5 V
600
VO = 1.8 V
550
VO = 1.2 V
500
VO = 1.05 V
VO = 1.5 V
450
0
0.01
10
400
0
IO - Output Current - A
Figure 9. LIGHT LOAD EFFICIENCY vs OUTPUT CURRENT
5
10
VI - Input Voltage - V
15
20
Figure 10. SWITCHING FREQUENCY vs INPUT VOLTAGE
800
VI = 12 V
VO = 1.05 V
VO = 1.8 V
fsw - Switching Frequency - kHz
700
VO = 10 mV/div
600
VO = 1.05 V
500
SW = 5 V/div
400
VO = 3.3 V
300
200
100
0
0.01
0.1
1
IO - Output Current - A
10
Figure 11. SWITCHING FREQUENCY vs OUTPUT
CURRENT
t - Time - 400 ns
Figure 12. VOLTAGE RIPPLE AT OUTPUT (IO = 2 A)
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TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25°C (unless otherwise noted).
0.78
VO = 1.05 V
VIN = 12 V
IO = 1 A
0.775
VFB Voltage (V)
VI = 50 mV/div
SW = 5 V/div
0.77
0.765
0.76
0.755
0.75
−40
−20
0
20
40
60
Temperature (°C)
80
100
120
G000
t - Time - 400 ns
Figure 13. VOLTAGE RIPPLE AT INPUT (IO = 2 A)
Figure 14. VFB VOLTAGE vs JUNCTION TEMPERATURE
11
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DESIGN GUIDE
Step-By-Step Design Procedure
To
•
•
•
•
•
begin the design process, the user must know a few application parameters:
Input voltage range
Output voltage
Output current
Output voltage ripple
Input voltage ripple
U1
TPS54229EDDA
Figure 15. Shows the schematic diagram for this design example.
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.
To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VFB input current are more noticeable.
æ
ö
R1÷
V
= 0.765 x çç1 +
÷
OUT
çè
R2 ø÷
(3)
Output Filter Selection
The output filter used with the TPS54229E is an LC circuit. This LC filter has double pole at:
F =
P
2p L
1
OUT
x COUT
(4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54229E. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain
rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero
that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1
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Table 1. Recommended Component Values
C4 (pF) (1)
Output Voltage (V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
C8 + C9 + C10 (µF)
1
6.81
22.1
2.2
20 - 68
1.05
8.25
22.1
2.2
20 - 68
1.2
12.7
22.1
2.2
20 - 68
1.5
21.5
22.1
2.2
20 - 68
1.8
30.1
22.1
5 - 22
3.3
20 - 68
2.5
49.9
22.1
5 - 22
3.3
20 - 68
3.3
73.2
22.1
5 - 22
3.3
20 - 68
5
124
22.1
5 - 22
4.7
20 - 68
6.5
165
22.1
5 - 22
4.7
20 - 68
(1)
Optional
Since the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by
adding a feed forward capacitor (C4) in parallel with R1
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
fSW.
Use 700 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS
current of Equation 7.
V
- VOUT
V
OUT x IN(max)
I
=
IPP
V
L x f
IN(max)
O
SW
I
=I +
Ipeak
O
(5)
I
lpp
(6)
2
1
2
2
= I
I
+
I
Lo(RMS)
O
12 IPP
(7)
For this design example, the calculated peak current is 2.335 A and the calculated RMS current is 2.009 A. The
inductor used is a TDK CLF7045T-2R2N with a peak current rating of 5.5 A and an RMS current rating of 4.3 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54229E is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20µF to 68µF. Use Equation 8
to determine the required RMS current rating for the output capacitor.
I
Co(RMS)
=
VOUT x (VIN - VOUT )
12 x VIN x LO x fSW
(8)
For this design three TDK C3216X5R0J106M 10µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.19 A and each output capacitor is rated for 4A.
Input Capacitor Selection
The TPS54229E requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor (C3) is required to provide additional high frequency filtering and insure accurate current limit operation.
This capacitor must be placed as close to the IC pins 2 (VIN) and 4 (GND) as possible. The capacitor voltage
rating needs to be greater than the maximum input voltage.
Bootstrap Capacitor Selection
A 0.1 µF. ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.
13
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TPS54229E
SLVSAZ7A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
VREG5 Capacitor Selection
A 0.47 µF. ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor.
THERMAL INFORMATION
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external
heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
Figure 16. Thermal Pad Dimensions
14
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Product Folder Link(s) :TPS54229E
TPS54229E
SLVSAZ7A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
LAYOUT CONSIDERATIONS
1. Keep the input switching current loop as small as possible.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the analog ground to power ground.
5. Do not allow switching current to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected to PGND.
9. Output capacitor should be connected to a broad pattern of the PGND.
10. Voltage feedback loop should be as short as possible, and preferably with ground shield.
11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to analog ground
trace.
12. Providing sufficient via is preferable for VIN, SW and PGND connection.
13. VIN input bypass capacitor and VIN high frequency bypass capacitor must be placed as near as possible to
the device.
14. Performance based on four layer printed circuit board.
15
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s) :TPS54229E
TPS54229E
SLVSAZ7A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
VIA to Power Ground Plane
VIN
VIN
INPUT
BYPASS
CAPACITOR
VIA to SW Copper Pour on Bottom
or Internal Layer
VIN
HIGH FREQENCY
BYPASS
CAPACITOR
ANALOG
GROUND
TRACE
BOOST
CAPACITOR
VBST
SS
VIN
EN
SW
VREG5
TO ENABLE
CONTROL
VFB
GND
BIAS
CAP
EXPOSED
THERMAL PAD
AREA
FEEDBACK
RESISTORS
POWER
GROUND
SW node copper pour
area on internal or
bottom layer
OUTPUT
INDUCTOR
POWER
GROUND
VOUT
SLOW
START
CAP
Connection to
POWER GROUND
on internal or
bottom layer
OUTPUT
FILTER
CAPACITOR
Figure 17. PCB Layout
16
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s) :TPS54229E
TPS54229E
SLVSAZ7A – SEPTEMBER 2011 – REVISED MARCH 2012
www.ti.com
REVISION HISTORY
Changes from Original (September 2011) to Revision A
•
Page
Removed SWIFT™ from the data sheet title ........................................................................................................................ 1
•
Deleted from the ELECTRICAL CHARACTERISTICS table, VLN5 and VLD5, VREG5 MIN and MAX values .......................... 3
•
Added in ELECTRICAL CHARACTERISTICS table, IVREG5 and RDS(on) footnote references ............................................... 3
•
Added in ELECTRICAL CHARACTERISTICS table, tOFF(MIN) footnote reference and deleted MAX value .......................... 4
•
Deleted from ELECTRICAL CHARACTERISTICS, UVLO MIN and MAX values ................................................................ 4
•
Added TYPICAL CHARACTERISTICS Condition ................................................................................................................ 9
17
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s) :TPS54229E
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54229EDDA
ACTIVE SO PowerPAD
DDA
8
75
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 85
54229E
TPS54229EDDAR
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 85
54229E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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