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TPS54295
SLVSB01D – OCTOBER 2011 – REVISED AUGUST 2016
TPS54295 2-A Dual Channel Synchronous Step-Down Switcher With Integrated FET
1 Features
3 Description
•
The TPS54295 is a dual, adaptive on-time D-CAP2
mode synchronous buck converter. The TPS54295
enables system designers to complete the suite of
various end-equipment power bus regulators with a
cost effective, low component count, and low standby
current solution. The main control loops of the
TPS54295 use the D-CAP2 mode control which
provides a very fast transient response with no
external compensation components. The adaptive ontime control supports seamless transition between
PWM mode at higher load conditions and Eco-mode
operation at light loads. Eco-mode allows the
TPS54295 to maintain high efficiency during lighter
load conditions. The TPS54295 is able to adapt to
both low equivalent series resistance (ESR) output
capacitors such as POSCAP or SP-CAP, and ultralow ESR ceramic capacitors. The device provides
convenient and efficient operation with input voltages
from 4.5 V to 18 V.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
D-CAP2™ Control Mode
– Fast Transient Response
– No External Parts Required For Loop
Compensation
– Compatible With Ceramic Output Capacitors
Wide Input Voltage Range : 4.5 V to 18 V
Output Voltage Range : 0.76 V to 7 V
Highly Efficient Integrated FETs Optimized for
Low Duty Cycle Applications
– 150 mΩ (High-Side) and 100 mΩ (Low-Side)
High Initial Reference Accuracy
Low-Side rDS(ON) Lossless Current Sensing
Adjustable Soft Start
Non-Sinking Prebiased Soft Start
700-kHz Switching Frequency
Cycle-by-Cycle Overcurrent Limit Control
OCL, OVP, UVP, UVLO, and TSD Protections
Adaptive Gate Drivers With Integrated Boost
PMOS Switch
OCP Constant Due to Thermally Compensated
rDS(ON) With 4000 ppm/℃
16-Pin HTSSOP, 16-pin VQFN
Auto-Skip Eco-mode™ for High Efficiency at Light
Load
2 Applications
•
Point-of-Load Regulation in Low Power Systems
for Wide Range of Applications
– Digital TV Power Supplies
– Networking Home Terminals
– Digital Set Top Boxes (STB)
– DVD Players and Recorders
– Gaming Consoles and Other
The TPS54295 is available in a 4.4 mm × 5 mm 16pin HTSSOP (PWP) package and 4 mm x 4 mm 16pin VQFN (RSA) package, designed to operate at an
ambient temperature range from –40°C to 85°C.
Device Information(1)
PART NUMBER
TPS54295
PACKAGE
BODY SIZE (NOM)
HTSSOP (16)
5.00 mm × 4.40 mm
VQFN (16)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Load Transient Response
VO2 = 1.5 V (50 mV/div)
Iout (1 A/div)
t - Time - 100 ms/div
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54295
SLVSB01D – OCTOBER 2011 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
6
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
12
13
14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 20
10.3 Thermal Considerations ........................................ 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D
Page
•
Added Device Information table, Specifications section, ESD Ratings table, Detailed Description section, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
•
Deleted Operating ambient temperature from Absolute Maximum Ratings table .................................................................. 5
•
Deleted Operating ambient temperature from Recommended Operating Conditions table................................................... 5
•
Changed Operating junction temperature maximum value from 150 to 125 in Recommended Operating Conditions table 5
Changes from Revision B (December 2011) to Revision C
Page
•
Added the RSA-16 Pin package to the Ordering Information table........................................................................................ 1
•
Changed the Description text to include the RSA package ................................................................................................... 1
•
Added the RSA-16 Pin package pin out................................................................................................................................. 4
•
Added Figure 26 ................................................................................................................................................................... 21
Changes from Revision A (October 2011) to Revision B
Page
•
Deleted MIN and MAX values from VVREG5 specification........................................................................................................ 6
•
Deleted Line and Load regulation specs from VREG5 specification......................................................................................... 6
•
Added "Ensured by design. Not production tested" annotation to specifications for MOSFETs, ON-TIME TIMER
CONTROl, and SOFT START................................................................................................................................................ 6
•
Deleted MIN and MAX values from VUVREG5 specification...................................................................................................... 6
•
Added "VIN = 12 V, TA = 25°C (unless otherwise noted)" to Typical Characteristics conditions statement. ......................... 8
2
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SLVSB01D – OCTOBER 2011 – REVISED AUGUST 2016
Changes from Original (October 2011) to Revision A
Page
•
Added indication for not production tested parameters.......................................................................................................... 6
•
Added Over/Under Voltage Protection Description .............................................................................................................. 14
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TPS54295
SLVSB01D – OCTOBER 2011 – REVISED AUGUST 2016
www.ti.com
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
VBST2
SW1
3
14
SW2
PGND1
4
13
PGND2
VBST2
1
VIN2
2
SS2
15
13
2
EN2
VBST1
14
VIN2
PGND2
16
15
1
SW2
VIN1
16
RSA Package
16-Pin VQFN
Top View
12
VFB2
11
VREG5
Thermal Pad
VFB1
7
10
VFB2
GND
8
9
VIN1
3
10
GND
VBST1
4
9
VFB1
8
SS2
SS1
11
7
6
EN1
SS1
Thermal Pad
6
EN2
PGND1
12
5
5
SW1
EN1
VREG5
Not to scale
Not to scale
Pin Functions
PIN
NAME
HTSSOP
VQFN
EN1
5
7
EN2
12
14
GND
8
10
PGND1
4
6
PGND2
13
15
SS1
6
8
SS2
11
13
SW1
3
5
SW2
14
16
VBST1
2
14
VBST2
15
1
I/O
I
DESCRIPTION
Enable. Pull high to enable the corresponding (1 or 2) converter.
I/O
Signal GND. Connect sensitive SSx and VFBx returns to GND at a single point.
I/O
Ground returns for low-side MOSFETs. Input of current comparator.
O
Soft-start programming pin. Connect capacitor from SSx pin to GND to program soft-start time.
I/O
Switch node connections for both the high-side NFETs and low-side NFETs. Input of current
comparator.
I
Supply input for high-side NFET gate drive circuit. Connect a 0.1-µF ceramic capacitor between
VBSTx and SWx pins. An internal diode is connected between VREG5 and VBSTx.
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
I
Power inputs and connects to both high-side NFET drains. Supply Input for 5.5-V linear
regulator.
VFB1
7
9
VFB2
10
12
VIN1
1
3
VIN2
16
2
VREG5
9
11
O
Output of 5.5-V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least
1 µF. VREG5 is active when VIN1 is added.
Thermal
Pad
—
—
—
Thermal pad of the package. Must be soldered to ground to achieve appropriate dissipation.
Must be connected to GND.
4
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SLVSB01D – OCTOBER 2011 – REVISED AUGUST 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Input voltage
MIN
MAX
VIN1, VIN2, EN1, EN2
–0.3
20
VBST1, VBST2
–0.3
26
VBST1, VBST2 (10-ns transient)
–0.3
28
VBST1 – SW1 , VBST2 – SW2
–0.3
6.5
VFB1, VFB2
UNIT
V
–0.3
6.5
SW1, SW2
–2
20
SW1, SW2 (10-ns transient)
–3
22
VREG5, SS1, SS2
–0.3
6.5
PGND1, PGND2
–0.3
0.3
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
Output voltage
(1)
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to IC GND terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
UNIT
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply input voltage
Input voltage
Output voltage
TJ
MIN
MAX
4.5
18
VBST1, VBST2
–0.1
24
VBST1, VBST2 (10-ns transient)
–0.1
27
VBST1 – SW1, VBST2 – SW2
–0.1
5.7
VFB1, VFB2
–0.1
5.7
EN1, EN2
–0.1
18
SW1, SW2
–1
18
SW1, SW2 (10-ns transient)
–3
21
VREG5, SS1, SS2
–0.1
5.7
PGND1, PGND2
–0.1
0.1
VO1, VO2
0.76
7
–40
125
VIN1, VIN2
Operating Junction Temperature
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UNIT
V
V
V
°C
5
TPS54295
SLVSB01D – OCTOBER 2011 – REVISED AUGUST 2016
www.ti.com
6.4 Thermal Information
TPS54295
THERMAL METRIC (1)
PWP (HTSSOP)
RSA (VQFN)
16 PINS
16 PINS
UNIT
34.9
°C/W
RθJA
Junction-to-ambient thermal resistance
47.5
RθJC(top)
Junction-to-case (top) thermal resistance
27.1
40
°C/W
RθJB
Junction-to-board thermal resistance
20.8
11.8
°C/W
ψJT
Junction-to-top characterization parameter
1
0.7
°C/W
ψJB
Junction-to-board characterization parameter
20.6
11.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.7
3.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1300
2000
µA
80
150
µA
765
773
mV
115
ppm/℃
0.35
µA
SUPPLY CURRENT
IIN
VINx supply current
TA = 25°C, VEN1 = VEN2 = 5 V, VVFB1 = VVFB2 = 0.8 V
IVINSDN
VINx shutdown current
TA = 25°C, VEN1 = VEN2 = 0 V
FEEDBACK VOLTAGE
VVFBTHLx
VFBx threshold voltage
TA = 25°C, VCH1 = 3.3 V, VCH2 = 1.5 V
TCVFBx
Temperature coefficient
On the basis of 25°C (1)
–115
758
IVFBx
VFBx Input Current
VVFBx = 0.8 V, TA = 25°C
–0.35
0.2
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 6 V < VIN1 < 18 V, IVREG5 = 5 mA
5.5
V
IVREG5
Output current
VIN1 = 6 V, VVREG5 = 4 V, TA = 25°C (1)
75
mA
High-side switch resistance
TA = 25℃, VVBSTx – VSWx = 5.5 V
150
mΩ
100
mΩ
MOSFETs
rDS(ON)H
rDS(ON)L
Low-side switch resistance
TA = 25℃
(1)
(1)
ON-TIME TIMER CONTROL
TON1
SW1 ON time
VSW1 = 12 V, VOUT1 = 1.2 V
165
ns
TON2
SW2 ON time
VSW2 = 12 V, VOUT2 = 1.2 V
165
ns
TOFF1
SW1 minimum OFF time
TA = 25℃, VVFB1 = 0.7 V (1)
220
ns
TOFF2
SW2 minimum OFF time
TA = 25℃, VVFB2 = 0.7 V (1)
220
ns
SOFT START
ISSC
SSx charge current
TCISSC
ISSC temperature coefficient
ISSD
SSx discharge current
VSSx = 0.5 V, TA = 25℃
–8.4
–8
–7.6
On the basis of 25°C (1) (PWP)
–4
3
On the basis of 25°C (1) (RSA)
–4
5
VSSx = 0.5 V
3
7
10
µA
nA/°C
mA
UVLO
VUVREG5
VREG5 UVLO threshold
VREG5 rising
3.83
Hysteresis
V
0.6
LOGIC THRESHOLDS
VENxH
ENx H-level threshold voltage
VENxL
ENx L-level threshold voltage
RENx_IN
ENx input resistance
2
V
0.4
V
VENx = 12 V
225
450
900
kΩ
LOUT = 2.2 µH (1)
2.7
3.9
4.5
A
CURRENT LIMITS
IOCL
(1)
6
Current limit
Ensured by design. Not production tested.
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Electrical Characteristics (continued)
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
115%
120%
125%
3
10
68%
73%
UNIT
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION (UVP, OVP)
VOVP
Output OVP trip threshold
TOVPDEL
Output OVP prop delay
VUVP
Output UVP trip threshold
TUVPDEL
Output UVP delay time
TUVPEN
Output UVP enable delay
measured on VFBx
measured on VFBx
63%
1.5
UVP enable delay and soft-start time
× 1.4
× 1.7
µs
ms
×2
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
Shutdown temperature (1)
Hysteresis (1)
155
25
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7
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SLVSB01D – OCTOBER 2011 – REVISED AUGUST 2016
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6.6 Typical Characteristics
One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted).
200
VIN1 = VIN2 = 12V
EN1 = EN2 = ON
Ivccsdn - Shutdown Current - mA
180
160
140
120
100
80
60
40
20
0
-50
0
50
100
150
TJ - Junction Temperature - °C
Figure 1. Input Current vs Junction Temperature
Figure 2. Input Shutdown Current vs Junction Temperature
90
3.38
80
3.36
VO - Output Voltage - V
3.4
EN Input Current - mA
100
70
60
50
40
30
3.34
VI = 12 V
3.32
3.3
3.28
3.26
VI = 5 V
3.24
20
3.22
10
3.2
0
0
5
10
EN Input Voltage - V
15
0
20
0.4
0.6
0.8
1
1.2
1.4
IO - Output Current - A
1.6
1.8
2
Figure 4. Output Voltage vs Output Current
Figure 3. EN Current vs EN Voltage
1.55
3.4
1.54
3.38
1.53
3.36
VI = 18 V
VI = 12 V
1.52
VO - Output Voltage - V
VO - Output Voltage - V
0.2
VOUT1 = 3.3 V
VENx = 12 V
1.51
1.5
1.49
VI = 5 V
1.48
3.34
Io1 = 1 A
3.32
3.3
3.28
Io1 = 10 mA
3.26
1.47
3.24
1.46
3.22
3.2
1.45
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0
2
4
IO - Output Current - A
6
8
10
12
VI - Input Voltage - V
14
16
18
20
VOUT1 = 3.3 V
VOUT2 = 1.5 V
Figure 5. Output Voltage vs Output Current
8
VI = 18 V
Figure 6. Output Voltage vs Input Voltage
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Typical Characteristics (continued)
One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted).
1.55
100
1.54
90
Io2 = 1 A
1.52
VI = 12 V
80
Efficiency - %
VO - Output Voltage - V
1.53
1.51
1.5
Io2 = 10 m A
1.49
VI = 18 V
VI = 5 V
70
60
1.48
1.47
50
1.46
1.45
40
0
2
4
6
8
10
12
VI - Input Voltage - V
14
16
18
20
0
VOUT2 = 1.5 V
0.5
1
IO - Output Current - A
1.5
2
VOUT1 = 3.3 V
Figure 7. Output Voltage vs Input Voltage
Figure 8. Efficiency vs Output Current
100
100
VI = 18 V
90
VI = 12 V
90
80
VI = 5 V
70
Efficiency - %
Efficiency - %
80
60
50
40
VI = 12 V
VI = 18 V
VI = 5 V
70
60
30
20
50
10
40
0
0.001
0.01
IO - Output Current - A
0.1
0
VOUT1 = 3.3 V
0.5
2
Figure 10. Efficiency vs Output Current
900
100
90
850
fsw - Switching Frequency - kHz
VI = 18 V
80
VI = 12 V
70
Efficiency - %
1.5
VOUT1 = 1.5 V
Figure 9. Efficiency vs Output Current
60
1
IO - Output Current - A
VI = 5 V
50
40
30
20
10
IO1=1 A
800
750
700
650
600
550
500
450
400
0
0.001
0.01
IO - Output Current - A
0.1
0
5
10
VI - Input Voltage - V
15
20
VOUT1 = 3.3 V
VOUT2 = 1.5 V
Figure 11. Efficiency vs Output Current
Figure 12. Switching Frequency vs Input Voltage
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Typical Characteristics (continued)
900
1000
850
900
800
800
fsw - Switching Frequency - kHz
fsw - Switching Frequency - kHz
One output is enabled unless otherwise noted. VI = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted).
750
700
IO2 = 1 A
650
600
550
500
450
VI = 12 V
700
600
500
400
300
200
100
400
0
5
10
VI - Input Voltage - V
15
20
VOUT2 = 1.5 V
0
0.01
0.1
1
IO - Output Current - A
10
VOUT1 = 3.3 V
Figure 13. Switching Frequency vs Input Voltage
Figure 14. Switching Frequency vs Output Current
800
VI = 12 V
fsw - Switching Frequency - kHz
700
600
500
400
300
200
100
0
0.01
0.1
1
IO - Output Current - A
10
VOUT2 = 1.5 V
Figure 15. Switching Frequency vs Output Current
10
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7 Detailed Description
7.1 Overview
The TPS54295 is a 2-A and 2-A, dual synchronous step-down (buck) converter with two integrated N-channel
MOSFETs for each channel. It operates using D-CAP2 control mode. The fast transient response of D-CAP2
control reduces the required output capacitance to meet a specific level of performance. Proprietary internal
circuitry allows the use of low ESR output capacitors including ceramic and special polymer types.
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7.2 Functional Block Diagram
VIN1
VIN1
-32%
VREG5
UV1
UV
VBST1
Control Logic
0.1uF
OV1
OV
+20%
Ref1
SW1
PGND1
Err
Comp
SS1
VO1
PGND1
VFB1
Ref_OCL
PGND1
SW1
EN1
PGND
SW1
OCP1
EN
Logic
EN2
ZC1
EN Logic
VIN1
GND
VREG5
CH1 Min-off timer
5 VREG
1.0uF
CH2 Min-off timer
SS1
Ref1
Ref2
SS1
SS2
REF
SoftStart
SS2
CSS1
CSS2
UV1
UV2
OV1
OV2
UVLO
TSD
-32%
UV
UV2
UVLO
Protection
Logic
VIN2
VIN2
VREG5
VBST2
Control Logic
0.1uF
+20
OV
VO2
OV2
SW2
PGND
Ref2
SS2
PGND2
Err
Comp
PGND2
VFB2
PGND2
Ref_OCL
SW2
SW2
OCP2
ZC2
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7.3 Feature Description
7.3.1 PWM Operation
The main control loop of the TPS54295 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 control mode. D-CAP2 control combines constant on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both low
ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off when the internal
timer expires. This timer is set by the converter’s input voltage (VINx) and the output voltage (VOUTx) to maintain a
pseudo-fixed frequency over the input voltage range hence it is called adaptive on-time control. The timer is reset
and the high-side MOSFET is turned on again when the feedback voltage falls below the nominal output voltage.
An internal ramp is added to the reference voltage to simulate output voltage ripple, eliminating the need for ESR
induced output ripple from D-CAP control.
7.3.2 PWM Frequency and Adaptive On-Time Control
TPS54295 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54295 runs with a pseudo-fixed frequency of 700 kHz by using the input voltage and output voltage to set
the on-time timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage,
therefore, when the duty ratio is VOUTx / VINx, the frequency is constant.
7.3.3 Auto-Skip Eco-Mode Control
The TPS54295 is designed with auto-skip Eco-mode to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current also reduces and eventually comes to the point where
its ripple valley touches the zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when zero inductor current is detected. As the load
current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost half
as it was in the continuous conduction mode because it takes longer to discharge the output capacitor with
smaller load current to the nominal output voltage. The transition point to the light load operation current
(IOUT(LL)x) can be estimated with Equation 1 with 700 kHz used as fSW.
(VIN x - VOUT x ) ´ VOUT x
1
´
IOUT(LL) x =
2 ´ L1x ´ fSW
VIN x
(1)
7.3.4 Soft Start and Prebiased Soft Start
The soft-start time is adjustable. When the ENx pin becomes high, 8-µA current begins charging the capacitor
which is connected from the SSx pin to GND. Smooth control of the output voltage is maintained during start-up.
Calculate the slow-start time with Equation 2. VFBx voltage is 0.765 V and SSx pin source current is 8 µA.
C4x(nF) ´ VFBx(V)
C4x(nF) ´ 0.765 V
TSS (ms) =
=
ISS (m A)
8 mA
(2)
The TPS54295 contains a unique circuit to prevent current from being pulled from the output during start-up if the
output is prebiased. When the soft start commands a voltage higher than the prebias level (internal soft start
becomes greater than internal feedback voltage), the controller slowly activates synchronous rectification by
starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by 1 – D, where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the prebiased output, and ensures that the output voltage starts and
ramps up smoothly into regulation from prebiased start-up to normal mode operation.
7.3.5 Overcurrent Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detection control circuit.
The switch current is monitored by measuring the low-side FET switch voltage between the SWx and PGNDx
pins. This voltage is proportional to the switch current and the on-resistance of the FET. To improve the
measurement accuracy, the voltage sensing is temperature compensated.
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Feature Description (continued)
During the ON time of the high-side FET switch, the switch current increases at a linear rate determined by VINx,
VOUTx, the ON time, and the output inductor value. During the ON time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current (IOUTx). If the sensed voltage on
the low-side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on
until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle
begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is
monitored in the same manner.
Following are some important considerations for this type of overcurrent protection. The load current is one half
of the peak-to-peak inductor current higher than the overcurrent threshold. Also when the current is being limited,
the output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. When the overcurrent condition is removed, the output voltage returns to the regulated value. This
protection is non-latching.
7.3.6 Overvoltage and Undervoltage Protection
TPS54295 monitors the resistor divided feedback voltage to detect overvoltage and undervoltage. If the feedback
voltage is higher than 120% of the reference voltage, the OVP comparator output goes high and the circuit
latches both the high-side MOSFET driver and the low-side MOSFET driver off. When the feedback voltage is
lower than 68% of the reference voltage, the UVP comparator output goes high and an internal UVP delay
counter begins counting. After 1.5 ms, TPS54295 latches OFF both the high-side MOSFET and the low-side
MOSFET drivers. This function is enabled approximately 1.7 times the soft-start time after power on. The OVP
and UVP latch off is reset when EN is toggled.
7.3.7 UVLO Protection
Undervoltage lockout protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is
lower than the UVLO threshold, the TPS54295 shuts down. As soon as the voltage increases above the UVLO
threshold, the converter starts again.
7.3.8 Thermal Shutdown
TPS54295 monitors its temperature. If the temperature exceeds the threshold value (typically 155°C), the device
shuts down. When the temperature falls below the threshold, the IC starts again.
When VIN1 starts up and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is
lower than 155°C. As long as VIN1 rises, TJ must be kept below 110°C.
7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS54295 can operate in the normal switching modes. Normal continuous conduction mode (CCM) occurs when
the minimum switch current is above 0 A. In CCM, the TPS54295 operates at a quasi-fixed frequency of 700 kHz
while VOUT1 = VOUT2 = 3.3 V.
7.4.2 Eco-Mode Operation
When the TPS54295 is in the normal CCM operating mode and the switch current falls to 0 A, the TPS54295
begins operating in pulse skipping Eco-mode. Each switching cycle is followed by a period of energy saving
sleep time. The sleep time ends when the VFB voltage falls below the Eco-mode threshold voltage. As the output
current decreases, the perceived time between switching pulses increases.
7.4.3 Standby Operation
When the TPS54295 is operating in either normal CCM or Eco-mode, it may be placed in standby mode by
asserting the EN pin low.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54295 is a typical step-down DC-DC converter. The device typically is used to convert a higher DC
voltage to a lower DC voltage with a maximum output current of 2 A.
8.2 Typical Application
VINx
12V ± 10%
C11
10 mF
VO1
1.05 V
L11
1.5 mH
C31
0.1 mF
C21
22 mF
x2
1
VIN1
2
VBST1
3
4
PGND
VIN2
VBST2 15
SW1
PGND1
16
TPS54295
HTSSOP16
VO2
1.8 V
C22
22 mF
x2
PGND2 13
PGND
5
EN1
EN2
12
6
SS1
SS2
11
7
VFB1
VFB2
10
C42
SGND
R21
22.1 kW
C12
10 mF
SW2 14
C41
R11
8.25 kW
L12
1.5 mH
C32
0.1 mF
SGND
C5 1uF
8
GND
VREG5
R12
30.1 kW
R22
22.1 kW
9
PGND
SGND
SGND
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Figure 16. Schematic Diagram for the Design Example
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage
4.5 V to 18 V
Output voltage
1.05 V and 1.8 V
Transient response (1.5-A load step)
ΔVOUT = ±5%
Input ripple voltage
400 mV
Output ripple voltage
30 mV
Output current rating
2A
Operating frequency
700 kHz
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8.2.2 Detailed Design Procedure
This section presents a simplified design process and guidelines for component selection. Alternatively the
WEBENCH® software may be used to generate a complete design. WEBENCH uses an iterative design
procedure and accesses a comprehensive database of components when generating a design.
To
•
•
•
begin the design process, determine the following application parameters:
Input voltage
Output voltage
Output current
In all formulas x is used to indicate that they are valid for both converters. For the calculations the estimated
switching frequency of 700 kHz is used.
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFBx pin. TI recommends 1%
tolerance or better divider resistors. Start by using Equation 3 to calculate VOUTx.
To improve the efficiency at very light loads consider using larger value resistors, but resistance values that are
too high make the device susceptible to noise and voltage errors due to the VFBx input current being more
noticeable.
æ R1x ö
VOUT x = 0.765 V ´ ç 1+
÷
è R2x ø
(3)
8.2.2.2 Output Filter Selection
The output filter used with the TPS54295 is an LC circuit. This LC filter has a double pole at:
1
FP =
2p L1x ´ C1x
(4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS545295. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain
rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided by the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 2.
Table 2. Recommended Component Values
OUTPUT VOLTAGE (V)
R1x (kΩ)
R2x (kΩ)
CFFx (pF) (1)
L1x (µH)
C2x (µF)
1
6.81
22.1
—
1 to 1.5
22 to 68
1.05
8.25
22.1
—
1 to 1.5
22 to 68
1.2
12.7
22.1
—
1 to 1.5
22 to 68
1.5
21.5
22.1
—
1.5
22 to 68
1.8
30.1
22.1
5 to 22
1.5
22 to 68
2.5
49.9
22.1
5 to 22
2.2
22 to 68
3.3
73.2
22.1
5 to 22
2.2
22 to 68
5
124
22.1
5 to 22
3.3
22 to 68
(1)
Optional
For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (CFF) in parallel with R1.
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6, and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
16
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For the calculations, use 700 kHz as the switching frequency (fSW). Make sure the chosen inductor is rated for
the peak current of Equation 6 and the RMS current of Equation 7.
VIN(MAX) x - VOUT x
VOUT x
´
ΔIL1x =
VIN(MAX) x
L1x ´ fSW
(5)
ΔI
IL1xpeak = IOUT x + L1x
(6)
2
IL1x(RMS) =
IOUT x 2 +
1
DIL1x 2
12
(7)
For this design example, the calculated peak current is 2.46 A and the calculated RMS current is 2.02 A for
VOUT1. The inductor used has a rated current of 7.3 A based on the inductance change and of 4.9 A based on
the temperature rise.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54295 is intended for use
with ceramic or other low ESR capacitors. TI recommends a value from 22 µF to 68 µF. Use Equation 8 to
determine the required RMS current rating for the output capacitors.
VOUT x ´ (VIN x - VOUT x )
IC2x(RMS) =
12 ´ VIN x ´ L1x ´ fSW
(8)
For this design two 22-µF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS
current is 0.19 A and each output capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
The TPS54295 requires an input decoupling capacitor and a bulk capacitor may be required depending on the
application. TI recommends a ceramic capacitor of at least 10 µF for the decoupling capacitor. Additionally, TI
recommends 0.1-µF ceramic capacitors from VIN1 and VIN2 to ground to improve the stability and reduce the
SWx node overshoots. The capacitors' voltage rating must be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBSTx and SWx pins for proper operation. TI
recommends ceramic capacitors with a dielectric of X5R or better.
8.2.2.5 VREG5 Capacitor Selection
A 1-µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. TI
recommends a ceramic capacitor with a dielectric of X5R or better.
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8.2.3 Application Curves
Vo1(50 mV/div)
Vo2(50 mV/div)
IO1(1 A/div)
IO2(1 A/div)
t - Time - 100 ms/div
t - Time - 100 ms/div
VOUT1 = 3.3 V
VOUT2 = 1.5 V
Figure 17. 0-A to 2-A Load Transient Response
Figure 18. 0-A to 2-A Load Transient Response
EN2 (10 V/div)
EN1 (10 V/div)
VO1(1 V/div)
VO2(0.5 V/div)
SS1 (2 V/div)
SS2 (2 V/div)
CSS2 = 0.01µF
CSSx = 0.01µF
t - Time - 400 ms/div
t - Time - 400 ms/div
VOUT2 = 1.5 V
VOUT1 = 3.3 V
Figure 20. Soft Start
Figure 19. Soft Start
Vo1 = 3.3 V (10 mV/div)
Vo2 = 1.5 V (10 mV/div)
SW2 (5 V/div)
SW1 (5 V/div)
t - Time - 400 ns/div
VOUT1 = 3.3 V
t - Time - 400 ns/div
IOUT1 = 2 A
VOUT2 = 1.5 V
Figure 21. VOUT1 Ripple Voltage
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IOUT2 = 2 A
Figure 22. VOUT2 Ripple Voltage
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VIN1 = 12 V (50 mV/div)
VIN2 = 12 V (50 mV/div)
SW2 (5 V/div)
SW1 (5 V/div)
t - Time - 400 ns/div
t - Time - 400 ns/div
IOUT1 = 2 A
IOUT2 = 2 A
Figure 23. VIN1 Input Voltage Ripple
Figure 24. VIN2 Input Voltage Ripple
9 Power Supply Recommendations
The TPS54295 is designed to operate with an input voltage supply from 4.5 V to 18 V. This input power supply
must be well regulated. Bulk capacitance may be required in addition to the ceramic bypass capacitors if the
input supply is placed more than a few inches from the device. A 47-µF electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal
pad.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching currents to flow under the device.
6. Keep the pattern lines for VINx and PGNDx broad.
7. Exposed pad of device must be soldered to PGND.
8. VREG5 capacitor must be placed near the device, and connected to GND.
9. Output capacitors must be connected with a broad pattern to the PGND.
10. Voltage feedback loops must be as short as possible, and preferably with ground shields.
11. Kelvin connections must be brought from the output to the feedback pin of the device.
12. Providing sufficient vias is preferable for VIN, SW, and PGND connections.
13. PCB pattern for VIN, SW, and PGND must be as broad as possible.
14. VIN capacitor must be placed as near as possible to the device.
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10.2 Layout Example
VIN2
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
～0.1µF
VIN1
1
16
VIN2
VBST 1
2
15
VBST2
SW 1
3
14
SW2
4
13
PGND 2
EN1
5
12
EN2
SS1
6
11
SS2
VFB1
7
10
VFB2
GND
8
9
PGND 1
Symmetrical Layout
for CH1 and CH2
VIN INPUT
BYPASS
CAPACITOR
10µF x2
Switching noise
flows through IC
and CIN . It avoids
the thermal Pad.
OUTPUT
FILTER
CAPACITOR
VO2
OUTPUT
INDUCTOR
Recommend to keep
distance more than 3-4mm.
(to avoid noise scattering,
especially GND plane.)
TO ENABLE
CONTROL
Keep
distance more
than 1 inch
VREG 5
POWER GND
To feedback
resisters
Feedback
resisters
BIAS
CAP
GND
PLANE
2,3 or bottom
layer
Via to GND Plane
- Blue parts can be placed on the bottom side
- Connect the SWx pins through another layer with the indcutor
(yellow line)
Figure 25. TPS54295 PWP Package Layout
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Layout Example (continued)
VOUT2
KEEP
VIAS > 3-4 mm
FROM OUTPUT
CAPACITORS
OUTPUT2
FILTER
CAPACITORS
POWER
GROUND
OUTPUT2
INDUCTOR
KEEP OUTPUT
VIAS > 25 mm
FROM INPUT VIAS
TO ENABLE
CONTROL
VIN INPUT
BYPASS
CAPACITORS
SS2
16
15
14
13
SLOW
START
CAP 2
FEEDBACK
RESISTORS
EXPOSED THERMAL
PAD AREA
2
11
VREG5
VIN1
3
10
GND
VBST1
4
9
VFB1
BOOST
CAPACITOR
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
5
6
7
FEEDBACK
RESISTORS
8
SLOW
START
CAP 1
KEEP
VIAS > 3-4 mm
FROM INPUT
CAPACITORS
VIA to Internal or
Bottom Layer Ground Plane
VIN INPUT
BYPASS
CAPACITORS
TO ENABLE
CONTROL
VIA to internal or
Bottom Layer Etch
OUTPUT1
INDUCTOR
Etch or Copper Fill
on Top Layer
Internal or Bottom
Layer Ground Plane
Etch on Bottom Layer,
Internal Layer or
Under Component
NOTE: IT IS POSSIBLE TO PLACE
SOME COMPONENTS SUCH AS
BOOST CAPACITOR AND FEEDBACK
RESISTORS ON BOTTOM LAYER
BIAS ANALOG
CAP GROUND
TRACE
SS1
VIN2
EN 1
VFB2
1
PGND1
12
VBST2
SW1
VIN
EN2
BOOST
CAPACITOR
PGND2
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
SW2
KEEP
VIAS > 3-4 mm
FROM INPUT
CAPACITORS
KEEP OUTPUT
VIAS > 25 mm
FROM INPUT VIAS
POWER
GROUND
OUTPUT1
FILTER
CAPACITORS
VOUT1
KEEP
VIAS > 3-4 mm
FROM OUTPUT
CAPACITORS
INTERNAL OR
BOTTOM LAYER
GROUND PLANE
Figure 26. TPS54295 RSA Package Layout
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10.3 Thermal Considerations
This 16-pin PWP package incorporates an exposed thermal pad. The thermal pad must be soldered directly to
the printed-circuit board (PCB). After soldering, the PCB is used as a heat sink. In addition, through the use of
thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical
schematic for the device, or alternatively, can be attached to a special heat sink structure designed into the PCB.
This design optimizes the heat transfer from the integrated circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see PowerPAD Thermally Enhanced Package and PowerPAD Made Easy.
The exposed thermal pad dimensions for this package are shown in Figure 27.
Figure 27. Thermal Pad Dimensions
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
WEBENCH tools http://www.ti.com/lsds/ti/analog/webench/overview.page
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• PowerPAD Thermally Enhanced Package (SLMA002)
• PowerPAD Made Easy (SLMA004)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
D-CAP2, Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54295PWP
ACTIVE
HTSSOP
PWP
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54295
TPS54295PWPR
ACTIVE
HTSSOP
PWP
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PS54295
TPS54295RSAR
ACTIVE
QFN
RSA
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
54295
TPS54295RSAT
ACTIVE
QFN
RSA
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
54295
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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