Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
具有 Eco-mode™ 的 TPS54340 42V 输入、3.5A 降压直流/直
直流转换器
1 特性
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3 说明
4.5V 到 42V（绝对最大值为 45V）输入范围
3.5A 持续电流，4.5A 最小峰值电感器电流限值
电流模式控制直流到直流转换器
92mΩ 高侧金属氧化物半导体场效应晶体管
(MOSFET)
轻负载条件下使用脉冲跳跃实现的高效率 Ecomode。™
轻负载条件下使用集成型引导 (BOOT) 再充电场效
应晶体管 (FET) 实现的低压降
146μA 工作静态电流
1μA 关断电流
100kHz 至 2.5MHz 的固定开关频率
同步至外部时钟
可调欠压闭锁 (UVLO) 电压和滞后
内部软启动
精确逐周期电流限制
过热、过压和频率折返保护
0.8V 1% 内部电压基准
8 引脚 HSOP，带有 PowerPAD™封装
TJ 运行范围为 -40°C 至 150°C
使用 TPS54340 并借助 WEBENCH 电源设计器创
建定制设计方案
TPS54340 是一款 42V，3.5A，降压稳压器，此稳压
器具有一个集成的高侧 MOSFET。按照 ISO 7637 标
准，此器件能够耐受高达 45V 的抛负载脉冲。电流模
式控制提供了简单的外部补偿和灵活的组件选择。一个
低纹波脉冲跳跃模式将无负载时的电源电流减小至
146μA。当启用引脚被拉至低电平时，关断电源电流被
减少至 1μA。
欠压闭锁在内部设定为 4.3V，但可用使能引脚将之提
高。输出电压启动斜升由内部控制以提供一个受控的启
动并且消除过冲。
宽开关频率范围可实现对效率或者外部组件尺寸的优
化。频率折返和热关断在过载条件下保护内部和外部组
件。
TPS54340 可提供 8 引脚热增强型 HSOP
PowerPAD™ 封装。
器件信息
订货编号
封装
封装尺寸
TPS54340DDA
HSOP (8)
4.89mm x 3.9mm
空白
2 应用
12V，24V 工业、汽车和通信电源系统
简化电路原理图
效率与负载电流间的关系
100
VIN
VIN
90
80
TPS54340
VOUT = 5V
EN
RT/CLK
BOOT
VOUT
SW
R1
COMP
Efficiency - %
70
VOUT = 3.3V
60
50
40
30
20
VIN = 12V
fsw = 600 kHz
10
FB
0
R3
GND
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IO - Output Current - A
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSBK0
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
5
6
7
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 22
8
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Applications ................................................ 23
8.3 WEBENCH Power Designer ................................... 36
9 Power Supply Recommendations...................... 36
10 Layout................................................................... 37
10.1 Layout Guidelines ................................................. 37
10.2 Layout Example .................................................... 37
11 器件和文档支持 ..................................................... 38
11.1
11.2
11.3
11.4
11.5
文档支持................................................................
商标 .......................................................................
社区资源................................................................
静电放电警告.........................................................
Glossary ................................................................
38
38
38
38
38
12 机械、封装和可订购信息 ....................................... 39
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (June 2016) to Revision D
Page
•
Changed VIN MIN Value From: 4.5 V To: VO + VDO, and added Note 1 in the Recommended Operating Conditions .......... 5
•
Updated text and added Equation 1 in the Low Dropout Operation and Bootstrap Voltage (BOOT) ................................. 13
•
Deleted text: "The start and stop voltage for a typical 5 V..." and Figure: "5V Start/Stop Voltage" from the Low
Dropout Operation and Bootstrap Voltage (BOOT) section ................................................................................................. 13
•
Added new section: Minimum VIN ......................................................................................................................................... 29
•
Deleted 2 graphs named "Low Dropout Operation" from the Application Curves section ................................................... 32
Changes from Revision B (March 2014) to Revision C
Page
•
将特性部分及整个数据表中的 HSOIC 封装更改为 HSOP 封装 .............................................................................................. 1
•
Moved Storage temperature to the Absolute Maximum Ratings (1) table ............................................................................... 5
•
Changed the Handling Ratings table to the ESD Ratings table ............................................................................................. 5
•
Changed Output current MAX value From: 5 A To: 3.5 A in the Recommended Operating Conditions table ...................... 5
•
Changed Error amplifier transconductance units from µMhos to µS in the Electrical Characteristics table .......................... 6
•
Changed Equation 7 and Equation 8 .................................................................................................................................. 15
•
Changed Equation 27 .......................................................................................................................................................... 24
Changes from Revision A (February 2013) to Revision B
Page
•
将数据表更改为全新 TI 版面布局............................................................................................................................................ 1
•
已将应用范围列表从：12V，24V 和 48V 工业改为：12V，24V 工业.................................................................................... 1
•
已添加器件信息表 ................................................................................................................................................................... 1
•
Added the Handling Ratings table .......................................................................................................................................... 5
•
Added the Recommended Operating Conditions table .......................................................................................................... 5
•
Added the Thermal Information table inside the document ................................................................................................... 5
•
Changed the Operating: nonswitching supply current TEST CONDITIONS From: FB = 0.83 V To: FB = 0.9 V ................. 6
2
版权 © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
•
Changed RT/CLK high threshold MAX value From: 1.7 V To: 2 V ....................................................................................... 6
•
Changed Figure 6 title From: HIGH FREQUENCY RANGE To: LOW FREQUENCY RANGE ............................................. 7
•
Changed Figure 7 title From: LOW FREQUENCY RANGE To: HIGH FREQUENCY RANGE ............................................. 7
•
Added the Power Supply Recommendations section .......................................................................................................... 36
Changes from Original (October 2012) to Revision A
Page
•
Changed Figure 11 From: IEN (µV) To: IEN (µA) ..................................................................................................................... 8
•
Changed Figure 12 From: IEN (µV) To: IEN (µA) ..................................................................................................................... 8
Copyright © 2012–2017, Texas Instruments Incorporated
3
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
5 Pin Configuration and Functions
DDA Package
8-Pin (HSOP)
(Top View)
BOOT
1
VIN
2
8
SW
7
GND
PowerPAD
9
EN
3
6
COMP
RT/CLK
4
5
FB
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BOOT
1
O
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high side MOSFET, the output is switched off until the capacitor is
refreshed.
VIN
2
I
Input supply voltage with 4.5 V to 42 V operating range.
EN
3
I
Enable terminal, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the
input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
RT/CLK
4
I
Resistor Timing and External Clock. An internal amplifier holds this terminal at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the terminal is pulled above the PLL upper
threshold, a mode change occurs and the terminal becomes a synchronization input. The internal amplifier is
disabled and the terminal is a high impedance clock input to the internal PLL. If clocking edges stop, the
internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
FB
5
I
Inverting input of the transconductance (gm) error amplifier.
COMP
6
O
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this terminal.
GND
7
–
Ground
SW
8
I
The source of the internal high-side power MOSFET and switching node of the converter.
Thermal Pad
9
–
GND terminal must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
4
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
–0.3
45
EN
–0.3
8.4
BOOT
Input voltage
UNIT
53
V
FB
–0.3
3
COMP
–0.3
3
RT/CLK
–0.3
3.6
–0.6
45
–2
45
Operating junction temperature
–40
150
°C
Storage temperature, TSTG
–65
150
°C
BOOT-SW
Output voltage
8
SW
SW, 10-ns Transient
(1)
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
(1)
VESD
(1)
(2)
(3)
Human Body Model (HBM) ESD Stress Voltage
(2)
Charged Device Model (HBM) ESD Stress Voltage
UNIT
±2000
(3)
V
±500
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
into the device.
Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe
manufacturing with a standard ESD control process. terminals listed as 1000V may actually have higher performance.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe
manufacturing with a standard ESD control process. terminals listed as 250V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VO + VDO
42
V
Output voltage
0.8
41.1
V
IO
Output current
0
3.5
A
TJ
Junction Temperature
–40
150
°C
VIN
Supply input voltage
VO
(1)
(1)
UNIT
See Equation 1
6.4 Thermal Information
THERMAL METRIC (1) (2)
TPS54340
DDA (8 PINS)
UNIT
θJA
Junction-to-ambient thermal resistance (standard board)
42.0
°C/W
ψJT
Junction-to-top characterization parameter
5.9
°C/W
ψJB
Junction-to-board characterization parameter
23.4
°C/W
θJCtop
Junction-to-case(top) thermal resistance
45.8
°C/W
θJCbot
Junction-to-case(bottom) thermal resistance
3.6
°C/W
θJB
Junction-to-board thermal resistance
23.4
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.
Copyright © 2012–2017, Texas Instruments Incorporated
5
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
42
V
4.3
4.48
V
SUPPLY VOLTAGE (VIN TERMINAL)
Operating input voltage
Internal undervoltage lockout threshold
4.5
Rising
4.1
Internal undervoltage lockout threshold
hysteresis
325
mV
Shutdown supply current
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V
1.3
3.5
Operating: nonswitching supply current
FB = 0.9 V, TA = 25°C
146
175
1.2
1.3
μA
ENABLE AND UVLO (EN TERMINAL)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling
1.1
Enable threshold +50 mV
–4.6
Enable threshold –50 mV
Hysteresis current
V
μA
–0.58
–1.2
-1.8
–2.2
–3.4
-4.5
μA
0.792
0.8
0.808
V
92
190
VOLTAGE REFERENCE
Voltage reference
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, BOOT-SW = 6 V
mΩ
ERROR AMPLIFIER
Input current
Error amplifier transconductance (gM)
–2 μA < ICOMP < 2 μA, VCOMP = 1 V
Error amplifier transconductance (gM) during
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V
soft-start
Error amplifier dc gain
VFB = 0.8 V
Min unity gain bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100 mV overdrive
COMP to SW current transconductance
50
nA
350
μS
77
μS
10,000
V/V
2500
kHz
±30
μA
12
A/V
CURRENT LIMIT
Current limit threshold
All VIN and temperatures, Open Loop (1)
4.5
5.5
6.8
All temperatures, VIN = 12 V, Open Loop (1)
4.5
5.5
6.25
VIN = 12 V, TA = 25°C, Open Loop (1)
5.2
5.5
5.85
A
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
176
°C
12
°C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL)
Switching frequency range using RT mode
fSW
Switching frequency
Switching frequency range using CLK mode
100
RT = 200 kΩ
450
160
RT/CLK high threshold
RT/CLK low threshold
(1)
6
500
1.55
0.5
2500
kHz
550
kHz
2300
kHz
2
1.2
V
V
Open Loop current limit measured directly at the SW terminal and is independent of the inductor value and slope compensation.
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
6.6 Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE AND UVLO (EN TERMINAL)
Enable to COMP active
VIN = 12 V , TA = 25°C
540
µs
INTERNAL SOFT-START TIME
Soft-Start Time
fSW = 500 kHz, 10% to 90%
2.1
ms
Soft-Start Time
fSW = 2.5 MHz, 10% to 90%
0.42
ms
VIN = 12 V, TA = 25°C
135
ns
60
ns
15
ns
HIGH-SIDE MOSFET
Minimum controllable on time
CURRENT LIMIT
Current limit threshold delay
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK TERMINAL)
Minimum CLK input pulse width
RT/CLK falling edge to SW rising edge
delay
Measured at 500 kHz with RT resistor in series
55
ns
PLL lock in time
Measured at 500 kHz
78
μs
6.7 Typical Characteristics
0.25
0.814
VFB - Voltage Referance ( V)
RDS(ON) − On-State Resistance (Ω)
BOOT-SW = 3 V
BOOT-SW = 6 V
0.2
0.15
0.1
0.05
0
−50
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
0.809
0.804
0.799
0.794
0.789
0.784
150
±50
0
25
50
75
100
125
150
TJ - Junction Temperature (ƒC)
VIN = 12V
C026
VIN = 12 V
Figure 1. On Resistance vs Junction Temperature
Figure 2. Voltage Reference vs Junction Temperature
6.5
6.5
6.3
6.3
High-Side Switch Current (A)
High Side Switch Current (A)
±25
G001
6.1
5.9
5.7
5.5
5.3
5.1
4.9
TJ = −40°C
TJ = 25°C
TJ = 150°C
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.7
4.5
4.5
±50
±25
0
25
50
75
100
TJ - Junction Temperature (ƒC)
125
150
VIN = 12 V
Figure 3. Switch Current Limit vs Junction Temperature
Copyright © 2012–2017, Texas Instruments Incorporated
0
5
C027
10
15
20
25
30
VIN − Input Voltage (V)
35
40
45
G004
VIN = 12V
Figure 4. Switch Current Limit vs Input Voltage
7
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
550
500
540
450
FSW - Switching Frequency (kHz)
FS - Switching Frequency (kHz)
Typical Characteristics (continued)
530
520
510
500
490
480
470
460
450
350
300
250
200
150
100
50
0
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
VIN = 12 V
150
200
300
400
500
600
700
800
900
RT/CLK - Resistance (k )
C029
1000
C030
ƒsw (kHz) = 92417 x RT (kΩ) -0.991
RT (kΩ) = 101756 x ƒsw (kHz) -1.008
RT = 200 kΩ
Figure 6. Switching Frequency vs RT/CLK Resistance
Low Frequency Range
2500
500
450
2000
400
1500
gm (µA/V)
ƒSW − Switching Frequency (kHz)
Figure 5. Switching Frequency vs Junction Temperature
1000
250
0
50
100
150
RT/CLK − Resistance (kΩ)
200
200
±50
25
50
75
100
125
TJ - Junction Temperature (ƒC)
150
C032
Figure 8. EA Transconductance vs Junction Temperature
120
110
EN - Threshold (V)
100
90
80
70
60
50
40
30
20
±25
0
VIN = 12 V
Figure 7. Switching Frequency vs RT/CLK Resistance
High Frequency Range
±50
±25
G007
VIN = 12V
gm (µA/V)
350
300
500
0
0
25
50
75
100
TJ - Junction Temperature (ƒC)
125
150
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.2
1.19
1.18
1.17
1.16
1.15
±50
±25
Figure 9. EA Transconductance During Soft-Start vs
Junction Temperature
0
25
50
75
100
TJ - Junction Temperature (ƒC)
C033
VIN = 12 V
8
400
125
150
C034
VIN = 12 V
Figure 10. EN Terminal Voltage vs Junction Temperature
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
±0.5
−4
±0.7
−4.1
±0.9
−4.2
±1.1
−4.3
±1.3
−4.4
IEN (µA)
IEN (µA)
Typical Characteristics (continued)
±1.5
±1.7
−4.5
−4.6
±1.9
−4.7
±2.1
−4.8
±2.3
−4.9
−5
−50
±2.5
±50
±25
0
25
50
75
100
125
150
TJ - Junction Temperature (ƒC)
VIN = 5 V
IEN = Threshold +50 mV
125
150
G012
IEN = Threshold +50 mV
Figure 12. EN Terminal Current vs Junction Temperature
100
±2.5
VFB Falling
VFB Rising
% of Nominal Switching Frequency
±2.7
±2.9
IEN - Hysteresis (µA)
0
25
50
75
100
Tj − Junction Temperature (°C)
VIN = 12 V
Figure 11. EN Terminal Current vs Junction Temperature
±3.1
±3.3
±3.5
±3.7
±3.9
±4.1
±4.3
75
50
25
0
±4.5
±50
±25
0
25
50
75
100
125
150
TJ - Junction Temperature (ƒC)
0
0.1
0.2
0.3
C037
0.4
VFB (V)
0.5
0.6
0.7
0.8
G013
VIN = 12V
VIN = 12 V
Figure 14. Switching Frequency vs FB
Figure 13. EN Terminal Current Hysteresis vs Junction
Temperature
3
3
2.5
2.5
2
2
IVIN (µA)
IVIN (µA)
−25
C036
1.5
1.5
1
1
0.5
0.5
0
0
±50
±25
0
25
50
75
100
125
150
TJ - Junction Temperature (ƒC)
VIN = 12 V
Figure 15. Shutdown Supply Current vs Junction
Temperature
Copyright © 2012–2017, Texas Instruments Incorporated
0
10
20
30
40
VIN - Input Voltage (V)
C039
50
60
C040
TJ = 25°C
Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
9
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
Typical Characteristics (continued)
210
190
190
VIN − Supply Current (µA)
210
IVIN (µA)
170
150
130
110
170
150
130
110
90
90
70
70
±50
±25
0
25
50
75
100
125
150
TJ - Junction Temperature (ƒC)
2.6
35
40
45
G018
4.5
BOOT-SW UVLO Falling
BOOT-SW UVLO Rising
4.4
2.4
4.3
Input Voltage (V)
VIN − (BOOT−SW) (dB)
15
20
25
30
VIN − Input Voltage (V)
Figure 18. VIN Supply Current vs Input Voltage
Figure 17. VIN Supply Current vs Junction Temperature
2.3
2.2
2.1
4.2
4.1
4
2
3.9
1.9
3.8
1.8
−50
10
TJ = 25°C
VIN = 12 V
2.5
5
0
C041
−25
0
25
50
75
100
TJ − Junction Temperature (°C)
125
UVLO Start Switching
UVLO Stop Switching
3.7
−50
150
−25
G018
Figure 19. BOOT-SW UVLO vs Junction Temperature
0
25
50
75
100
Tj − Junction Temperature (°C)
125
150
G019
Figure 20. Input Voltage UVLO vs Junction Temperature
10
9
Soft-Start Time (ms)
8
7
6
5
4
3
2
1
0
2500
2300
VIN = 12 V
2100
1900
1700
1500
1300
1100
900
700
500
300
100
Switching Frequency (kHz)
C045
TJ = 25°C
Figure 21. Soft-Start Time vs Switching Frequency
10
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
7 Detailed Description
7.1 Overview
The TPS54340 is a 42 V, 3.5 A, step-down (buck) regulator with an integrated high side n-channel MOSFET.
The device implements constant frequency, current mode control which reduces output capacitance and
simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows
either efficiency or size optimization when selecting the output filter components. The switching frequency is
adjusted using a resistor to ground connected to the RT/CLK terminal. The device has an internal phase-locked
loop (PLL) connected to the RT/CLK terminal that will synchronize the power switch turn on to a falling edge of
an external clock signal.
The TPS54340 has a default input start-up voltage of approximately 4.3 V. The EN terminal can be used to
adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pull up
current source enables operation when the EN terminal is floating. The operating current is 146 μA under no load
condition (not switching). When the device is disabled, the supply current is 1 μA.
The integrated 92mΩ high side MOSFET supports high efficiency power supply designs capable of delivering 3.5
amperes of continuous current to a load. The gate drive bias voltage for the integrated high side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW terminals. The TPS54340 reduces the
external component count by integrating the bootstrap recharge diode. The BOOT terminal capacitor voltage is
monitored by a UVLO circuit which turns off the high side MOSFET when the BOOT to SW voltage falls below a
preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54340 to operate at high duty
cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of
the application. The minimum output voltage is the internal 0.8 V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Transient Protection (OVP) comparator. When
the OVP comparator is activated, the high side MOSFET is turned off and remains off until the output voltage is
less than 106% of the desired output voltage.
The TPS54340 includes an internal soft-start circuit that slows the output rise time during start-up to reduce inrush current and output voltage overshoot. Output overload conditions reset the soft-start timer. When the
overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal
regulation voltage. A frequency foldback circuit reduces the switching frequency during start-up and overcurrent
fault conditions to help maintain control of the inductor current.
Copyright © 2012–2017, Texas Instruments Incorporated
11
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
7.2 Functional Block Diagram
EN
VIN
Thermal
Shutdown
UVLO
Enable
Comparator
OV
Shutdown
Shutdown
Logic
Enable
Threshold
Boot
Charge
Voltage
Reference
Boot
UVLO
Minimum
Clamp
Pulse
Skip
Error
Amplifier
Current
Sense
PWM
Comparator
FB
BOOT
Logic
Shutdown
6
Slope
Compensation
SW
COMP
Frequency
Foldback
Reference
DAC for
Soft- Start
Maximum
Clamp
Oscillator
with PLL
8/8/ 2012 A 0192789
GND
POWERPAD
RT/ CLK
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54340 uses fixed frequency, peak current mode control with adjustable switching frequency. The output
voltage is compared through external resistors connected to the FB terminal to an internal voltage reference by
an error amplifier. An internal oscillator initiates the turn on of the high side power switch. The error amplifier
output at the COMP terminal controls the high side power switch current. When the high side MOSFET switch
current reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP terminal
voltage will increase and decrease as the output current increases and decreases. The device implements
current limiting by clamping the COMP terminal voltage to a maximum level. The pulse skipping Eco-mode is
implemented with a minimum voltage clamp on the COMP terminal.
7.3.2 Slope Compensation Output Current
The TPS54340 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high side switch is not affected by the slope compensation and remains constant over the full duty cycle range.
12
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
Feature Description (continued)
7.3.3 Pulse Skip Eco-mode
The TPS54340 operates in a pulse skipping Eco-mode at light load currents to improve efficiency by reducing
switching and gate drive losses. If the output voltage is within regulation and the peak switch current at the end
of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The pulse
skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of 600 mV.
When in Eco-mode, the COMP terminal voltage is clamped at 600 mV and the high side MOSFET is inhibited.
Since the device is not switching, the output voltage begins to decay. The voltage control loop responds to the
falling output voltage by increasing the COMP terminal voltage. The high side MOSFET is enabled and switching
resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to
the regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light
load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54340 senses and controls peak switch current, not the average load
current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor
value. The circuit in Figure 32 enters Eco-mode at about 31.4 mA output current. As the load current approaches
zero, the device enters a pulse skip mode during which it draws only 146 μA input quiescent current.
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54340 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW
terminals provides the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the
high side MOSFET is off and the external low side diode conducts. The recommended value of the BOOT
capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or
higher is recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high side MOSFET of the TPS54340 will
operate at 100% duty cycle as long as the BOOT to SW terminal voltage is greater than 2.1V. When the voltage
from BOOT to SW drops below 2.1V, the high side MOSFET is turned off and an integrated low side MOSFET
pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low side MOSFET at high
output voltages, it is disabled at 24 V output and re-enabled when the output reaches 21.5 V.
Since the gate drive current sourced from the BOOT capacitor is small, the high side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout
is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode
voltage and the printed circuit board resistance.
Equation 1 calculates the minimum input voltage required to regulate the output voltage and ensure normal
operation of the device. This calculation must include tolerance of the component specifications and the variation
of these specifications at their maximum operating temperature in the application
VOUT VF Rdc u IOUT
VIN min
RDS on u IOUT VF
0.99
where
•
•
•
VF = Schottky diode forward voltage
Rdc = DC resistance of inductor and PCB
RDS(on) = High-side MOSFET RDS(on)
Copyright © 2012–2017, Texas Instruments Incorporated
(1)
13
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
Feature Description (continued)
At heavy loads, the minimum input voltage must be increased to ensure a monotonic startup. Equation 2 can be
used to calculate the minimum input voltage for this condition.
V OUT(max) = D (max) x (V IN(min) - I OUT(max) x R DS(on) + V F ) - V F + I OUT(max) x R dc
where
•
•
•
•
•
•
D(max) ≥ 0.9
IB2SW = 100 µA
TSW = 1 / Fsw
VB2SW = VBOOT + VF
VBOOT = (1.41 x VIN - 0.554 - VF / TSW - 1.847 x 103 x IB2SW) / (1.41 + 1 / Tsw)
RDS(on) = 1 / (-0.3 x VB2SW2 + 3.577 x VB2SW - 4.246)
(2)
7.3.5 Error Amplifier
The TPS54340 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier
compares the FB terminal voltage to the lower of the internal soft-start voltage or the internal 0.8 V voltage
reference. The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During softstart operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal
soft-start voltage.
The frequency compensation components (capacitor, series resistor and capacitor) are connected between the
error amplifier output COMP terminal and GND terminal.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8 V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB terminal. It is recommended to use 1% tolerance or better divider
resistors. Select the low side resistor RLS for the desired divider current and use Equation 3 to calculate RHS. To
improve efficiency at light loads consider using larger value resistors. However, if the values are too high, the
regulator will be more susceptible to noise and voltage errors from the FB input current may become noticeable.
æ Vout - 0.8V ö
RHS = RLS ´ ç
÷
0.8 V
è
ø
(3)
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54340 is enabled when the VIN terminal voltage rises above 4.3 V and the EN terminal voltage exceeds
the enable threshold of 1.2 V. The TPS54340 is disabled when the VIN terminal voltage falls below 4 V or when
the EN terminal voltage is below 1.2 V. The EN terminal has an internal pull-up current source, I1, of 1.2 μA that
enables operation of the TPS54340 when the EN terminal floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 22 to
adjust the input voltage UVLO with two external resistors. When the EN terminal voltage exceeds 1.2 V, an
additional 3.4 μA of hysteresis current, Ihys, is sourced out of the EN terminal. When the EN terminal is pulled
below 1.2 V, the 3.4 μA Ihys current is removed. This addional current facilitates adjustable input voltage UVLO
hysteresis. Use Equation 4 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 5 to
calculate RUVLO2 for the desired VIN start voltage.
In applications designed to start at relatively low input voltages (e.g., 4.5 V) and withstand high input voltages
(e.g., 40 V), the EN terminal may experience a voltage greater than the absolute maximum voltage of 8.4 V
during the high input voltage condition. It is recommended to use a zener diode to clamp the terminal voltage
below the absolute maximum rating.
14
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
Feature Description (continued)
VIN
TPS54340
i1
ihys
RUVLO1
EN
Optional
VEN
RUVLO2
Figure 22. Adjustable Undervoltage Lockout (UVLO)
- VSTOP
V
RUVLO1 = START
IHYS
RUVLO2 =
VENA
VSTART - VENA
+ I1
RUVLO1
(4)
(5)
7.3.8 Internal Soft-Start
The TPS54340 has an internal digital soft-start that ramps the reference voltage from zero volts to its final value
in 1024 switching cycles. The internal soft-start time (10% to 90%) is calculated using Equation 6.
1024
tSS (ms) =
fSW (kHz)
(6)
If the EN terminal is pulled below the stop threshold of 1.2 V, switching stops and the internal soft-start resets.
The soft-start also resets in thermal shutdown.
7.3.9 Constant Switching Frequency and Timing Resistor (RT/CLK) Terminal)
The switching frequency of the TPS54340 is adjustable over a wide range from 100 kHz to 2500 kHz by placing
a resistor between the RT/CLK terminal and GND terminal. The RT/CLK terminal voltage is typically 0.5 V and
must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given
switching frequency, use Equation 7 or Equation 8 or the curves in Figure 5 and Figure 6. To reduce the solution
size one would typically set the switching frequency as high as possible, but tradeoffs of the conversion
efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum
controllable on time is typically 135 ns which limits the maximum operating frequency in applications with high
input to output step down ratios. The maximum switching frequency is also limited by the frequency foldback
circuit. A more detailed discussion of the maximum switching frequency is provided in the next section.
101756
RT (kW) =
f sw (kHz)1.008
(7)
f sw (kHz) =
92417
RT (kW)0.991
Copyright © 2012–2017, Texas Instruments Incorporated
(8)
15
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
Feature Description (continued)
7.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
The TPS54340 implements peak current mode control in which the COMP terminal voltage controls the peak
current of the high side MOSFET. A signal proportional to the high side switch current and the COMP terminal
voltage are compared each cycle. When the peak switch current intersects the COMP control voltage, the high
side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier
increases switch current by driving the COMP terminal high. The error amplifier output is clamped internally at a
level which sets the peak switch current limit. The TPS54340 provides an accurate current limit threshold with a
typical current limit delay of 60 ns. With smaller inductor values, the delay will result in a higher peak inductor
current. The relationship between the inductor value and the peak inductor current is shown in Figure 23.
Inductor Current (A)
Peak Inductor Current
ΔCLPeak
Open Loop Current Limit
ΔCLPeak = VIN/L x tCLdelay
tCLdelay
tON
Figure 23. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54340
implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB terminal voltage
falls from 0.8 V to 0 V. The TPS54340 uses a digital frequency foldback to enable synchronization to an external
clock during normal start-up and fault conditions. During short-circuit events, the inductor current can exceed the
peak current limit because of the high input voltage and the minimum controllable on time. When the output
voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The
frequency foldback effectively increases the off time by increasing the period of the switching cycle providing
more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. Equation 10 calculates the maximum switching frequency at
which the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating
frequency should not exceed the calculated value.
Equation 9 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required at maximum input voltage.
fSW (max skip ) =
16
1
tON
æ I ´R + V
dc
OUT + Vd
´ç O
ç VIN - IO ´ RDS(on ) + Vd
è
ö
÷
÷
ø
(9)
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
Feature Description (continued)
fSW(shift) =
fDIV æç ICL ´ Rdc + VOUT(sc ) + Vd
´
tON ç VIN - ICL ´ RDS(on ) + Vd
è
ö
÷
÷
ø
IO
Output current
ICL
Current limit
Rdc
inductor resistance
VIN
maximum input voltage
VOUT
output voltage
VOUTSC
output voltage during short
Vd
diode voltage drop
RDS(on)
switch on resistance
tON
controllable on time
ƒDIV
frequency divide equals (1, 2, 4, or 8)
(10)
7.3.11 Synchronization to RT/CLKTerminal
The RT/CLK terminal can receive a frequency synchronization signal from an external system clock. To
implement this synchronization feature connect a square wave to the RT/CLK terminal through either circuit
network shown in Figure 24. The square wave applied to the RT/CLK terminal must switch lower than 0.5 V and
higher than 1.7 V and have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 kHz to
2300 kHz. The rising edge of the SW will be synchronized to the falling edge of RT/CLK terminal signal. The
external synchronization circuit should be designed such that the default frequency set resistor is connected from
the RT/CLK terminal to ground when the synchronization signal is off. When using a low impedance signal
source, the frequency set resistor is connected in parallel with an ac coupling capacitor to a termination resistor
(e.g., 50 Ω) as shown in Figure 24. The two resistors in series provide the default frequency setting resistance
when the signal source is turned off. The sum of the resistance should set the switching frequency close to the
external CLK frequency. It is recommended to ac couple the synchronization signal through a 10 pF ceramic
capacitor to RT/CLK terminal.
The first time the RT/CLK is pulled above the PLL threshold the TPS54340 switches from the RT resistor freerunning frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and the
RT/CLK terminal becomes high impedance as the PLL starts to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and locks onto the external clock frequency within 78 microseconds. During
the transition from the PLL mode to the resistor programmed mode, the switching frequency will fall to 150 kHz
and then increase or decrease to the resistor programmed frequency when the 0.5 V bias voltage is reapplied to
the RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB terminal voltage ramps from 0 to 0.8 volts. The
device implements a digital frequency foldback to enable synchronizing to an external clock during normal startup and fault conditions. Figure 25, Figure 26 and Figure 27 show the device synchronized to an external system
clock in continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).
TPS54340
TPS54340
RT/CLK
RT/CLK
PLL
PLL
RT
Clock
Source
Hi-Z
Clock
Source
RT
Figure 24. Synchronizing to a System Clock
Copyright © 2012–2017, Texas Instruments Incorporated
17
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
Feature Description (continued)
SW
SW
EXT
EXT
IL
IL
Figure 25. Plot of Synchronizing in CCM
Figure 26. Plot of Synchronizing in DCM
SW
EXT
IL
Figure 27. Plot of Synchronizing in Eco-Mode
7.3.12 Overvoltage Protection
The TPS54340 incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot when
recovering from output fault conditions or strong unload transients in designs with low output capacitance. For
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the internal reference voltage. If the FB terminal voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier will increase to a maximum voltage corresponding to the peak
current limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier
output transitions to the normal operating level. In some applications, the power supply output voltage can
increase faster than the response of the error amplifier output resulting in an output overshoot.
18
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
Feature Description (continued)
The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB
terminal voltage to the rising OVP threshold which is nominally 109% of the internal voltage reference. If the FB
terminal voltage is greater than the rising OVP threshold, the high side MOSFET is immediately disabled to
minimize output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106%
of the internal voltage reference, the high side MOSFET resumes normal operation.
7.3.13 Thermal Shutdown
The TPS54340 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 176°C. The high side MOSFET stops switching when the junction temperature exceeds the thermal trip
threshold. Once the die temperature falls below 164°C, the device reinitiates the power up sequence controlled
by the internal soft-start circuitry.
7.3.14 Small Signal Model for Loop Response
Figure 28 shows an equivalent model for the TPS54340 control loop which can be simulated to check the
frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gmEA
of 3350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor
Ro and capacitor Co model the open loop gain and frequency response of the amplifier. The 1mV ac voltage
source between the nodes a and b effectively breaks the control loop for the frequency response measurements.
Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small
signal response of the overall loop. The dynamic loop response can be evaluated by replacing RL with a current
source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is
only valid for continuous conduction mode (CCM) operation.
SW
VO
Power Stage
gmps 12 A/V
a
b
R1
RESR
RL
COMP
c
0.8 V
R3
CO
C2
RO
FB
COUT
gmea
R2
350 mA/V
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Small Signal Model for Loop Response
7.3.15 Simple Small Signal Model for Peak Current Mode Control
Figure 29 describes a simple small signal model that can be used to design the frequency compensation. The
TPS54340 power stage can be approximated by a voltage-controlled current source (duty cycle modulator)
supplying current to the output capacitor and load resistor. The control to output transfer function is shown in
Equation 11 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in
switch current and the change in COMP terminal voltage (node c in Figure 28) is the power stage
transconductance, gmPS. The gmPS for the TPS54340 is 12 A/V. The low-frequency gain of the power stage is
the product of the transconductance and the load resistance as shown in Equation 12.
Copyright © 2012–2017, Texas Instruments Incorporated
19
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
Feature Description (continued)
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 13). The combined effect is highlighted by the dashed line in the right half of
Figure 29. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same with varying load conditions. The type of output capacitor chosen determines
whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum
electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the
overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 14).
VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 29. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
æ
s
ç1 +
2
p
´ fZ
VOUT
= Adc ´ è
VC
æ
s
ç1 +
2p ´ fP
è
Adc = gmps ´ RL
fP =
ö
÷
ø
ö
÷
ø
1
COUT ´ RL ´ 2p
1
fZ =
COUT ´ RESR ´ 2p
(11)
(12)
(13)
(14)
7.3.16 Small Signal Model for Frequency Compensation
The TPS54340 uses a transconductance amplifier for the error amplifier and supports three of the commonlyused frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in
Figure 30. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR
output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or
tantalum capacitors. Equation 15 and Equation 16 relate the frequency response of the amplifier to the small
signal model in Figure 30. The open-loop gain and bandwidth are modeled using the RO and CO shown in
Figure 30. See the application section for a design example using a Type 2A network with a low ESR output
capacitor.
Equation 15 through Equation 24 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power supply requirements.
20
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
Feature Description (continued)
VO
R1
FB
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
RO
R3
CO
C1
C2
R3
C2
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 30. Types of Frequency Compensation
Aol
A0
P1
Z1
P2
A1
BW
Figure 31. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Aol(V/V)
gmea
gmea
=
2p ´ BW (Hz)
Ro =
CO
æ
ö
s
ç1 +
÷
2p ´ fZ1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2p ´ fP1 ø è
2p ´ fP2 ø
è
A0 = gmea
A1 = gmea
P1 =
R2
´ Ro ´
R1 + R2
R2
´ Ro| | R3 ´
R1 + R2
1
2p ´ Ro ´ C1
Copyright © 2012–2017, Texas Instruments Incorporated
(15)
(16)
(17)
(18)
(19)
(20)
21
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
Feature Description (continued)
Z1 =
P2 =
1
2p ´ R3 ´ C1
1
type 2a
2p ´ R3 | | RO ´ (C2 + CO )
1
P2 =
type 2b
2p ´ R3 | | RO ´ CO
P2 =
2p ´ R O
1
type 1
´ (C2 + C O )
(21)
(22)
(23)
(24)
7.4 Device Functional Modes
7.4.1 Operation with VIN < 4.5 V (Minimum VIN)
The device is recommended to operate with input voltages above 4.5 V. The typical VIN UVLO threshold is 4.3 V
and the device may operate at input voltages down to the UVLO voltage. At input voltages below the actual
UVLO voltage, the device will not switch. If EN is externally pulled up to VIN or left floating, when VIN passes the
UVLO threshold the device will become active. Switching is enabled the soft start sequence is initiated. The
TPS54340 will start at the soft start time determined by the internal soft start time.
7.4.2 Operation with EN Control
The enable threshold voltage is 1.2 V typical. With EN held below that voltage the device is disabled and
switching is inhibited even if VIN is above its UVLO threshold. The IC quiescent current is reduced in this state. If
the EN voltage is increased above the threshold while VIN is above its UVLO threshold, the device becomes
active. Switching is enabled, and the soft start sequence is initiated. The TPS54340 will start at the soft start time
determined by the internal soft start time.
22
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS54340 is a 42 V, 3.5 A, step down regulator with an integrated high side MOSFET. Idea applications
are: 12 V, 24 V Industrial, Automotive and Communications Power Systems.
8.2 Typical Applications
8.2.1 Buck Converter
L1
5.6uH
3.3V, 3.5A VOUT
C4 0.1uF
U1
TPS54340DDA
VIN
6V to 42V
2
3
C1
C2
2.2uF
2.2uF
R1
365k
4
SW
BOOT
VIN
GND
EN
COMP
RT/CLK
PWRPD
1
9
GND
R2
86.6k
R3
162k
FB
C6
D1
8
100uF
B560C
R5
31.6k
7
6
5
GND
FB
R4
11.5k
C8
R6
10.2k
47pF
GND
FB
C5
5600pF
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 32. 3.3 V Output TPS54340 Design Example
8.2.1.1 Design Requirements
This guide illustrates the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These requirements are typically determined at
the system level. For this example, we will start with the following known parameters:
Table 1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
Output Voltage
3.3 V
Transient Response 0.875 A to 2.625 A load step
ΔVOUT = 4 %
Maximum Output Current
3.5 A
Input Voltage
12 V nom. 6 V to 42 V
Output Voltage Ripple
0.5% of VOUT
Start Input Voltage (rising VIN)
5.75 V
Stop Input Voltage (falling VIN)
4.5 V
Copyright © 2012–2017, Texas Instruments Incorporated
23
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
8.2.1.2 Detailed Design Procedures
8.2.1.2.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the TPS54340 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
– Run electrical simulations to see important waveforms and circuit performance,
– Run thermal simulations to understand the thermal performance of your board,
– Export your customized schematic and layout into popular CAD formats,
– Print PDF reports for the design, and share your design with colleagues.
5. Get more information about WEBENCH tools at www.ti.com/webench.
8.2.1.2.2 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible since this produces the smallest solution size. High switching frequency allows for
lower value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage and the frequency foldback protection.
Equation 9 and Equation 10 should be used to calculate the upper limit of the switching frequency for the
regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values
results in pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54340. For this example, the output voltage is 3.3 V
and the maximum input voltage is 42 V, which allows for a maximum switch frequency up to 712 kHz to avoid
pulse skipping from Equation 9. To ensure overcurrent runaway is not a concern during short circuits use
Equation 10 to determine the maximum switching frequency for frequency foldback protection. With a maximum
input voltage of 42 V, assuming a diode voltage of 0.7 V, inductor resistance of 21 mΩ, switch resistance of 92
mΩ, a current limit value of 4.7 A and short circuit output voltage of 0.1 V, the maximum switching frequency is
1260 kHz.
For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 7 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 32. For 600 kHz operation, the closest
standard value resistor is 162 kΩ.
1
æ 3.5 A x 21 mW + 3.3 V + 0.7 V ö
fSW(max skip) =
´ ç
÷ = 712 kHz
135ns
è 42 V - 3.5 A x 92 mW + 0.7 V ø
(25)
8
æ 4.7 A x 21 mW + 0.1 V + 0.7 V ö
´ ç
÷ = 1260 kHz
135 ns
è 42 V - 4.7 A x 92 mW + 0.7 V ø
101756
RT (kW) =
= 161 kW
600 (kHz)1.008
fSW(shift) =
(26)
(27)
8.2.1.2.3 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 28.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to
or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer,
however, the following guidelines may be used.
24
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA
for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple
current. This provides sufficient ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the minimum inductor value is calculated to be 4.8 μH. The nearest
standard value is 5.6 μH. It is important that the RMS current and saturation current ratings of the inductor not be
exceeded. The RMS and peak inductor current can be found from Equation 30 and Equation 31. For this design,
the RMS inductor current is 3.5 A and the peak inductor current is 3.95 A. The chosen inductor is a WE
7443552560, which has a saturation current rating of 7.5 A and an RMS current rating of 6.7 A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54340 which is nominally 5.5 A.
LO(min ) =
VIN(max ) - VOUT
IOUT ´ KIND
´
VOUT
42 V - 3.3 V
3.3 V
=
´
= 4.8 mH
VIN(max ) ´ fSW
3.5 A x 0.3
42 V ´ 600 kHz
(28)
spacer
IRIPPLE =
VOUT ´ (VIN(max ) - VOUT )
VIN(max ) ´ LO ´ fSW
=
3.3 V x (42 V - 3.3 V)
= 0.905 A
42 V x 5.6 mH x 600 kHz
(29)
spacer
(
æ
1 ç VOUT ´ VIN(max ) - VOUT
2
´ç
IL(rms ) = (IOUT ) +
12 ç
VIN(max ) ´ LO ´ fSW
è
)÷ö
2
÷ =
÷
ø
2
(3.5 A )2 +
æ 3.3 V ´ (42 V - 3.3 V ) ö
1
´ ç
÷ = 3.5 A
ç 42 V ´ 5.6 mH ´ 600 kHz ÷
12
è
ø
(30)
spacer
IL(peak ) = IOUT +
IRIPPLE
0.905 A
= 3.5 A +
= 3.95 A
2
2
(31)
8.2.1.2.4 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.
Equation 32 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw
is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this example,
the transient load response is specified as a 4% change in VOUT for a load step from 0.875 A to 2.625 A.
Therefore, ΔIOUT is 2.625 A - 0.875 A = 1.75 A and ΔVOUT = 0.04 × 3.3 = 0.13 V. Using these numbers gives a
minimum capacitance of 44.9 μF. This value does not take the ESR of the output capacitor into account in the
output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum
electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations.
Copyright © 2012–2017, Texas Instruments Incorporated
25
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response is
shown in Figure Figure 33. The excess energy absorbed in the output capacitor will increase the voltage on the
capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods.
Equation 33 calculates the minimum capacitance required to keep the output voltage overshoot to a desired
value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under
light load, Vf is the peak output voltage, and VI is the initial voltage. For this example, the worst case load step
will be from 2.625 A to 0.875 A. The output voltage increases during this load transition and the stated maximum
in our specification is 4 % of the output voltage. This makes Vf = 1.04 × 3.3 = 3.432. Vi is the initial capacitor
voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a minimum
capacitance of 38.6 μF.
Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 34 yields 11.4 μF.
Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 35 indicates the ESR should be less than 18 mΩ.
The most stringent criteria for the output capacitor is 44.9 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, 100
μF ceramic capacitors with 5 mΩ of ESR is used. The derated capacitance is 70 µF, well above the minimum
required capacitance of 44.9 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. Equation 36 can be used to calculate the RMS ripple current that the output capacitor must support. For
this example, Equation 36 yields 261 mA.
2 ´ DIOUT
2 ´ 1.75 A
=
= 44.9 mF
COUT >
fSW ´ DVOUT 600 kHz x 0.13 V
(32)
((I ) - (I ) ) = 5.6 mH x (2.625 A - 0.875 A ) = 38.6 mF
x
(3.432 V - 3.3 V )
((V ) - (V ) )
2
OH
COUT > LO
2
2
2
OL
2
f
2
2
2
I
1
1
1
1
´
=
= 11.4 mF
COUT >
x
8 ´ fSW æ VORIPPLE ö 8 x 600 kHz
æ 16.5 mV ö
ç 0.905 A ÷
ç
÷
è
ø
è IRIPPLE ø
V
16.5 mV
= 18 mW
RESR < ORIPPLE =
IRIPPLE
0.905 A
ICOUT(rms) =
(
VOUT ´ VIN(max ) - VOUT
)=
12 ´ VIN(max ) ´ LO ´ fSW
3.3 V ´
(42 V
- 3.3 V )
12 ´ 42 V ´ 5.6 mH ´ 600 kHz
(33)
(34)
(35)
= 261 mA
(36)
8.2.1.2.5 Catch Diode
The TPS54340 requires an external catch diode between the SW terminal and GND. The selected diode must
have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be
greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due
to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of
42 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54340.
For the example design, the B560C-13-F Schottky diode is selected for its lower forward voltage and good
thermal characteristics compared to smaller devices. The typical forward voltage of the B560C-13-F is 0.70 volts
at 5 A.
26
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 37 is
used to calculate the total power dissipation, including conduction losses and ac losses of the diode.
The B560C-13-F diode has a junction capacitance of 300 pF. Using Equation 37, the total loss in the diode is
2.42 Watts.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
PD =
(V
IN(max ) - VOUT
)´ I
OUT
+
VIN(max )
(42 V
2
´ Vf d
- 3.3 V ) ´ 3.5 A x 0.7 V
42 V
C j ´ fSW ´ (VIN + Vf d)
=
2
+
300 pF x 600 kHz x (42 V + 0.7 V)2
= 2.42 W
2
(37)
8.2.1.2.6 Input Capacitor
The TPS54340 requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3 μF of
effective capacitance. Some applications will benefit from additional bulk capacitance. The effective capacitance
includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor must be greater
than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum
input current ripple of the TPS54340. The input ripple current can be calculated using Equation 38.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 42 V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V or 100 V. For this example, two 2.2 μF, 100 V capacitors in parallel are used. Table 2 shows several
choices of high voltage capacitors.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 39. Using the design example values, IOUT = 3.5 A, CIN = 4.4 μF, ƒsw = 600 kHz,
yields an input voltage ripple of 331 mV and a rms input ripple current of 1.74 A.
ICI(rms ) = IOUT x
VOUT
x
VIN(min )
(V
IN(min ) - VOUT
VIN(min )
) = 3.5 A
´ 0.25
I
3.5 A ´ 0.25
DVIN = OUT
=
= 331 mV
CIN ´ fSW
4.4 mF ´ 600 kHz
Copyright © 2012–2017, Texas Instruments Incorporated
3.3 V
´
6V
(6 V
- 3.3 V )
6V
= 1.74 A
(38)
(39)
27
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
Table 2. Capacitor Types
VALUE (μF)
1 to 2.2
1 to 4.7
1
1 to 2.2
1 to 1.8
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
1
1 to 4.7
1 to 2.2
EIA Size
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE
DIALECTRIC
100 V
COMMENTS
GRM32 series
50 V
100 V
GRM31 series
50 V
50 V
100 V
VJ X7R series
50 V
100 V
100 V
X7R
C series C4532
50 V
100 V
C series C3225
50 V
50 V
100 V
X7R dielectric series
50 V
100 V
8.2.1.2.7 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW terminals for proper operation. A
ceramic capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10 V or
higher voltage rating.
8.2.1.2.8 Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN terminal of the
TPS54340. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it
should continue to do so until the input voltage falls below 4.5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between Vin and
ground connected to the EN terminal. Equation 4 and Equation 5 calculate the resistance values necessary. For
the example application, a 365 kΩ between Vin and EN (RUVLO1) and a 86.6 kΩ between EN and ground
(RUVLO2) are required to produce the 8 V and 6.25 V start and stop voltages.
V
- VSTOP
5.75 V - 4.5 V
=
= 368 kW
RUVLO1 = START
IHYS
3.4 mA
(40)
RUVLO2 =
VENA
1.2 V
=
= 87.8 kW
VSTART - VENA
5.75 V - 1.2 V
+
1.2
m
A
+ I1
365 kW
RUVLO1
(41)
8.2.1.2.9 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 3, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input
current of the FB terminal, the current flowing through the feedback network should be greater than 1 μA to
maintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ.
Choosing higher resistor values decreases quiescent current and improves efficiency at low output currents but
may also introduce noise immunity problems.
V
- 0.8 V
æ 3.3 V - 0.8 V ö
= 10.2 kW x ç
RHS = RLS x OUT
÷ = 31.9 kW
0.8 V
0.8 V
è
ø
(42)
28
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
8.2.1.2.10 Minimum VIN
To ensure proper operation of the device and to keep the output voltage in regulation, the input voltage at the
device must be above the value calculated with Equation 43. Using the typical values for the RHS, RDC and VF in
this application example, the minimum input voltage is 5.56 V. The BOOT-SW = 3 V curve in Figure 1 was used
for RDS(on) = 0.12 Ω because the device operates with low drop out. When operating with low dropout, the BOOTSW voltage is regulated at a lower voltage because the BOOT-SW capacitor is not refreshed every switching
cycle. In the final application, the values of RDS(on), Rdc and VF used in this equation must include tolerance of the
component specifications and the variation of these specifications at their maximum operating temperature in the
application. In this application example the calculated minimum input voltage is near the input voltage UVLO for
the TPS54340 so the device may turn off before going into drop out.
VOUT VF Rdc u IOUT
VIN min
RDS on u IOUT VF
0.99
3.3 V 0.5 V 0.0206 : u 3.5 A
VIN min
0.12 : u 3.5 A 0.5 V 3.83 V
0.99
(43)
8.2.1.2.11 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 44 and
Equation 45. For COUT, use a derated value of 70 μF. Use equations Equation 46 and Equation 47 to estimate a
starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 2411 Hz and ƒz(mod) is 455 kHz.
Equation 45 is the geometric mean of the modulator pole and the ESR zero and Equation 47 is the mean of
modulator pole and the switching frequency. Equation 46 yields 33.1 kHz and Equation 47 gives 26.9 kHz. Use
the lower value of Equation 46 or Equation 47 for an initial crossover frequency. For this example, the target ƒco
is 26.9 kHz.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IOUT(max )
3.5 A
fP(mod) =
=
= 2411 Hz
2 ´ p ´ VOUT ´ COUT 2 ´ p ´ 3.3 V ´ 70 mF
(44)
f Z(mod) =
1
2 ´ p ´ RESR ´ COUT
fco =
fp(mod) x f z(mod) =
fco =
fp(mod) x
fSW
2
=
=
1
= 455 kHz
2 ´ p ´ 5 mW ´ 70 mF
2411 Hz x 455 kHz
2411 Hz x
600 kHz
2
= 33.1 kHz
= 26.9 kHz
(45)
(46)
(47)
To determine the compensation resistor, R4, use Equation 48. Assume the power stage transconductance,
gmps, is 12 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5
V, 0.8 V and 350 μA/V, respectively. R4 is calculated to be 11.6 kΩ and a standard value of 11.5 kΩ is selected.
Use Equation 49 to set the compensation zero to the modulator pole frequency. Equation 49 yields 5740 pF for
compensating capacitor C5. 5600 pF is used for this design.
ö
VOUT
æ 2 ´ p ´ fco ´ COUT ö æ
ö
3.3 V
æ 2 ´ p ´ 26.9 kHz ´ 70 mF ö æ
R4 = ç
÷ = ç
÷ x ç
÷ x ç 0.8 V x 350 mA / V ÷ = 11.6 kW
gmps
V
x
gmea
12
A
/
V
è
ø è
ø
è
ø è REF
ø
(48)
1
1
=
= 5740 pF
C5 =
2 ´ p ´ R4 x fp(mod)
2 ´ p ´ 11.5 kW x 2411 Hz
Copyright © 2012–2017, Texas Instruments Incorporated
(49)
29
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 50 and Equation 51 for C8 to set the
compensation pole. The selected value of C8 is 47 pF for this design example.
C
x RESR
70 mF x 5 mW
=
= 30.4 pF
C8 = OUT
R4
11.5 kW
(50)
1
1
=
= 46.1 pF
C8 =
R4 x f sw x p
11.5 kW x 600 kHz x p
(51)
8.2.1.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 342 mA. The power supply enters Eco-mode when the output current is lower than 31.4 mA. The
input current draw is 237 μA with no load.
8.2.1.2.13 Power Dissipation
The following formulas show how to estimate the TPS54340 power dissipation under continuous conduction
mode (CCM) operation. These equations should not be used if the device is operating in discontinuous
conduction mode (DCM).
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD) and
supply current (PQ). Example calculations are shown with the 12 V typical input voltage of the design example.
æV
ö
3.3 V
2
PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷ = 3.5 A 2 ´ 92 mW ´
= 0.31 W
12 V
è VIN ø
(52)
spacer
PSW = VIN ´ fSW ´ IOUT ´ trise = 12 V ´ 600 kHz ´ 3.5 A ´ 4.9 ns = 0.123 W
(53)
spacer
PGD = VIN ´ QG ´ fSW = 12 V ´ 3nC ´ 600 kHz = 0.022 W
(54)
spacer
PQ = VIN ´ IQ = 12 V ´ 146 mA = 0.0018 W
(55)
Where:
IOUT
is the output current (A).
RDS(on)
is the on-resistance of the high-side MOSFET (Ω).
VOUT
is the output voltage (V).
VIN
is the input voltage (V).
ƒsw
is the switching frequency (Hz).
trise
is the SW terminal voltage rise time and can be estimated by trise = VIN x 0.16ns/V + 3.0ns.
QG
is the total gate charge of the internal MOSFET.
IQ
is the operating nonswitching supply current.
30
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
Therefore,
PTOT = PCOND + PSW + PGD + PQ = 0.31 W + 0.123 W + 0.022 W + 0.0018 W = 0.457 W
(56)
For given TA,
TJ = TA + RTH ´ PTOT
(57)
For given TJMAX = 150°C
TA (max ) = TJ(max ) - RTH ´ PTOT
(58)
Where:
Ptot
is the total device power dissipation (W),
TA
is the ambient temperature (°C).
TJ
is the junction temperature (°C).
RTH
is the thermal resistance of the package (°C/W).
TJMAX
is maximum junction temperature (°C)
TAMAX
is maximum ambient temperature (°C).
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and PCB trace resistance impacting the overall efficiency of the regulator.
Copyright © 2012–2017, Texas Instruments Incorporated
31
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
10 V/div
1 A/div
8.2.1.3 Application Curves
C4: IOUT
VIN
C3
C3: VOUT ac coupled
20 mV/div
100 mV/div
C4
VOUT
Time = 4 ms/div
Figure 34. Line Transient (8 V to 40 V)
5 V/div
5 V/div
Time = 100 ms/div
Figure 33. Load Transient
C1: VIN
-3.3 V offset
C1: VIN
C3: EN
C3
C2: VOUT
2 V/div
C1
2 V/div
2 V/div
2 V/div
C1
C2
C3: EN
C3
C2: VOUT
C2
Time = 2 ms/div
Figure 35. Start-up With VIN
500 mA/div
C4: IL
C2: VOUT ac coupled
10 mV/div
20 mV/div
10 V/div
C1
1 A/div
10 V/div
C1: SW
Time = 2 ms/div
Figure 36. Start-up With EN
C2
C4
C1: SW
C1
C4: IL
C4
C2
C2: VOUT ac coupled
Time = 2 ms/div
IOUT = 3.5 A
Figure 37. Output Ripple CCM
32
Time = 2 ms/div
IOUT = 100 mA
Figure 38. Output Ripple DCM
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
10 V/div
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
C1: SW
C1
C1: SW
C1
1 A/div
C4: IL
C4: IL
C4
C2: VOUT ac coupled
C3: VIN ac coupled
C2
200 mV/div
20 mV/div
200 mA/div
10 V/div
www.ti.com.cn
C2
C4
Time = 2 ms/div
Time = 2 ms/div
No Load
IOUT = 3.5 A
Figure 40. Input Ripple CCM
C1: SW
2 V/div
C1: SW
C1
200 mA/div
C4: IL
C4
C3: VIN ac coupled
20 mV/div
50 mV/div
500 mA/div
10 V/div
Figure 39. Output Ripple PSM
C3
C4
C4: IL
C3
C3: VOUT ac coupled
Time = 2 ms/div
IOUT = 100 mA
VIN = 12V
VIN = 5.5 V
VOUT = 5 V
Figure 42. Low Dropout Operation
100
100
90
90
80
80
70
70
Efficiency - %
Efficiency - %
Figure 41. Input Ripple DCM
Time = 20 ms/div
No Load
EN Floating
60
50
40
30
20
60
50
40
30
20
6Vin
12Vin
24Vin
10
36Vin
42Vin
0
0
0.5
1.0
1.5
2.0
2.5
3.0
6Vin
12Vin
24Vin
10
3.5
0
0.001
0.01
IO - Output Current - A
VOUT = 3.3 V
ƒsw = 600 kHz
Figure 43. Efficiency vs Load Current
Copyright © 2012–2017, Texas Instruments Incorporated
36Vin
42Vin
0.1
1
IO - Output Current - A
VOUT = 3.3 V
ƒsw = 600 kHz
Figure 44. Light Load Efficiency
33
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
90
80
80
70
70
Efficiency - %
100
90
Efficiency - %
100
60
50
40
30
20
60
50
40
30
20
6Vin
12Vin
24Vin
10
36Vin
42Vin
0
0
0.5
1.0
1.5
2.5
2.0
3.0
3.5
6Vin
12Vin
24Vin
10
0
0.001
4.0
VOUT = 5 V
ƒsw = 600 kHz
VOUT = 5 V
180
1
0.8
40
Phase - degree
120
60
20
Gain - dB
Output Voltage Deviation - %
Phase
Gain
0
0
-20
-60
-40
-120
-180
-60
VIN = 12 V
1000
ƒsw = 600 kHz
Figure 46. Light Load Efficiency
60
100
1
IO - Output Current - A
Figure 45. Efficiency vs Load Current
10
0.1
0.01
IO - Output Current - A
36Vin
42Vin
10000
100000
0.6
0.4
0.2
0
-0.2
0.4
-0.6
-0.8
-1
0
1000000
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IO - Output Current - A
Frequency - Hz
VOUT = 3.3 V
IOUT = 3.5 A
VIN = 12 V
Figure 47. Overall Loop Frequency Response
VOUT = 3.3 V
ƒsw = 600 kHz
Figure 48. Regulation vs Load Current
Output Voltage Deviation - %
0.3
0.2
0.1
0
-0.1
0.2
-0.3
5
10
15
20
25
30
35
40
45
VIN - Input Voltage - V
VOUT = 3.3 V
IOUT = 3.5 A
ƒsw = 600 kHz
Figure 49. Regulation vs Input Voltage
34
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
8.2.2 Inverting Power
The TPS54340 can be used to convert a positive input voltage to a negative output voltage. Idea applications are
amplifiers requiring a negative power supply. For a more detailed example see SLVA317.
VIN
+
Cin
Cboot
Lo
Cd
VIN
BOOT
GND
SW
R1
+
GND
TPS54340
R2
FB
Co
VOUT
EN
COMP
Rcomp
RT/CLK
RT
Czero
Cpole
Copyright © 2016, Texas Instruments Incorporated
Figure 50. TPS54340 Inverting Power Supply
Copyright © 2012–2017, Texas Instruments Incorporated
35
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
8.2.3 Split Rail Power Supply
The TPS54340 can be used to convert a positive input voltage to a split rail positive and negative output voltage
by using a coupled inductor. Idea applications are amplifiers requiring a split rail positive and negative voltage
power supply. For a more detailed example see SLVA369.
VOPOS
+
VIN
Copos
+
Cin
Cboot
BOOT
VIN
GND
SW
Lo
Cd
R1
GND
+
Coneg
R2
TPS54340
VONEG
FB
EN
COMP
Rcomp
RT/CLK
RT
Czero
Cpole
Copyright © 2016, Texas Instruments Incorporated
Figure 51. TPS54340 Split Rail Power Supply
8.3 WEBENCH Power Designer
TPS54340 with WEBENCH Power Designer
9 Power Supply Recommendations
The device are designed to operate from an input voltage supply range between 4.5 V and 42 V. If the input
supply is located more than a few inches from the TPS54340 converter additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 100 μF is a typical
choice.
36
Copyright © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance
• To reduce parasitic effects, the VIN terminal should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric.
• Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN
terminal, and the anode of the catch diode.
• The GND terminal should be tied directly to the power pad under the IC and the PowerPAD™.
• The PowerPAD™ should be connected to internal PCB ground planes using multiple vias directly under the
IC.
• The SW terminal should be routed to the cathode of the catch diode and to the output inductor.
• Since the SW connection is the switching node, the catch diode and output inductor should be located close
to the SW terminals, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
• For operation at full rated load, the top side ground area must provide adequate heat dissipating area.
• The RT/CLK terminal is sensitive to noise so the RT resistor should be located as close as possible to the IC
and routed with minimal lengths of trace.
• The additional external components can be placed approximately as shown.
• It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has
been shown to produce good results and is meant as a guideline.
10.2 Layout Example
Vout
Output
Capacitor
Topside
Ground
Area
Output
Inductor
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
Vin
UVLO
Adjust
Resistors
BOOT
Catch
Diode
SW
VIN
GND
EN
COMP
RT/CLK
Frequency
Set Resistor
FB
Compensation
Network
Resistor
Divider
Thermal VIA
Signal VIA
Figure 52. PCB Layout Example
10.2.1 Estimated Circuit Area
Boxing in the components in the design of Figure 32 the estimated printed circuit board area is 1.025 in2 (661
mm2). This area does not include test points or connectors.
版权 © 2012–2017, Texas Instruments Incorporated
37
TPS54340
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 使用 WEBENCH 工具定制设计方案
请单击此处，借助 WEBENCH®电源设计器并使用 TPS54340 器件创建定制设计方案。
1. 首先，输入您的输入电压、输出电压和输出电流要求。
2. 使用优化器拨盘优化效率、封装和成本等关键设计参数并将您的设计与德州仪器 (TI) 的其他可行解决方案进行
比较。
3. WEBENCH 电源设计器提供一份定制原理图以及罗列实时价格和组件供货情况的物料清单。
4. 在多数情况下，您还可以：
– 运行电气仿真，观察重要波形以及电路性能，
– 运行热性能仿真，了解电路板热性能,
– 将定制原理图和布局方案导出至常用 CAD 格式,
– 打印设计方案的 PDF 报告并与同事共享。
5. 请访问 www.ti.com/webench，获取有关 WEBENCH 工具的详细信息。
11.1.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.1.3 相关文档
相关文档如下：
• 《用降压稳压器创建反向电源》，SLVA317
TPS5430：https://webench.ti.com/wb5/WBTablet/PartDesigner/quickview.jsp?base_pn=TPS54340
11.2 商标
Eco-mode。, PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
38
版权 © 2012–2017, Texas Instruments Incorporated
TPS54340
www.ti.com.cn
ZHCSAC5D – OCTOBER 2012 – REVISED MARCH 2017
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2012–2017, Texas Instruments Incorporated
39
PACKAGE OPTION ADDENDUM
www.ti.com
17-Oct-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS54340DDA
ACTIVE SO PowerPAD
DDA
8
75
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
54340
Samples
TPS54340DDAR
ACTIVE SO PowerPAD
DDA
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
54340
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
